AD7804BN

a +3.3 V to +5 V Quad/Octal 10-Bit DACs AD7804/AD7805/AD7808/AD7809 FUNCTIONAL BLOCK DIAGRAMS FEATURES Four 10-Bit DACs in One Package Serial and Parallel Loading Facilities Available AD7804 Quad 10-Bit Serial Loading AD7805 Quad 10-Bit Parallel Loading AD7808 Octal 10-Bit Serial Loading AD7809 Octal 10-Bit Parallel Loading +3.3 V to +5 V Operation Power-Down Mode Power-On Reset Standby Mode (All DACs/Individual DACs) Low Power All CMOS Construction 10-Bit Resolution Double Buffered DAC Registers Dual External Reference Capability AVDD DVDD REFOUT 1.23V REF AGND DGND VOUTF* POWER ON RESET AD7804/ AD7808 REFIN AVDD DIVIDER MUX VBIAS DAC D COMP CHANNEL D CONTROL REG DATA REGISTER MUX CHANNEL C CONTROL REG CHANNEL B CONTROL REG VBIAS DAC C DATA REGISTER PD** CHANNEL A CONTROL REG DAC B DATA REGISTER DAC REGISTER VBIAS DAC A The AD7804/AD7808 are quad/octal 10-bit digital-to-analog converters, with serial load capabilities, while the AD7805/AD7809 are quad/octal 10-bit digital-to-analog converters with parallel load capabilities. These parts operate from a +3.3 V to +5 V (±10%) power supply and incorporates an on-chip reference. These DACs provide output signals in the form of VBIAS ± VSWING. VSWING is derived internally from VBIAS. On-chip control registers include a system control register and channel control registers. The system control register has control over all DACs in the package. The channel control registers allow individual control of DACs. The complete transfer function of each individual DAC can be shifted around the VBIAS point using an on-chip Sub DAC. All DACs contain double buffered data inputs, which allow all analog outputs to be simultaneously updated using the asynchronous LDAC input. FSIN CLKIN SDIN Channels Controlled Main DAC Sub DAC Hardware Clear System Control Power Down1 System Standby2 System Clear Input Coding Channel Control Channel Standby2 Channel Clear VBIAS All 兹 兹 All All All All 兹 兹 兹 兹 兹 兹 Selective Selective Selective 兹 兹 兹 兹 兹 VOUTA VOUTH* VOUTG* INPUT SHIFT REGISTER & CONTROL LOGIC CLR LDAC **ONLY AD7804 SHOWN FOR CLARITY **SHOWS ADDITIONAL CHANNELS ON THE AD7808 **PIN ON THE AD7808 ONLY AVDD DVDD REFOUT 1.23V REF AGND DGND VOUTF* POWER ON RESET AD7805/ AD7809 REFIN AVDD DIVIDER MUX VBIAS DAC D VOUTE* VOUTD COMP CHANNEL D CONTROL REG DATA REGISTER MUX CHANNEL C CONTROL REG DAC REGISTER VBIAS DAC C DATA REGISTER CHANNEL B CONTROL REG DAC B DATA REGISTER VOUTC DAC REGISTER VBIAS MUX Control Features VOUTB DAC REGISTER DATA REGISTER SYSTEM CONTROL REG GENERAL DESCRIPTION VOUTC DAC REGISTER MUX MUX VOUTD DAC REGISTER VBIAS APPLICATIONS Optical Disk Drives Instrumentation and Communication Systems Process Control and Voltage Setpoint Control Trim Potentiometer Replacement Automatic Calibration VOUTE* VOUTB DAC REGISTER VBIAS PD** CHANNEL A CONTROL REG MUX DAC A DATA REGISTER DAC REGISTER SYSTEM CONTROL REG CS WR CONTROL LOGIC VOUTA VOUTH* INPUT REGISTER VOUTG* 兹 NOTES 1 Power-down function powers down all internal circuitry including the reference. 2 Standby functions power down all circuitry except for the reference. MODE A0 A1 A2** DB9 DB2 DB1 DB0 CLR LDAC **ONLY AD7805 SHOWN FOR CLARITY **SHOWS ADDITIONAL CHANNELS ON THE AD7809 **PIN ON THE AD7809 ONLY REV. A Index on Page 26. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 AD7804/AD7805/AD7808/AD7809 AD7804/AD7805–SPECIFICATIONS (AVDD and DV DD = 3.3 V ⴞ 10% to 5 V ⴞ 10%; AGND = DGND = 0 V; Reference = Internal Reference; CL = 100 pF; RL = 2 k⍀ to GND. Sub DAC at Midscale. All specifications TMIN to TMAX unless otherwise noted.) B Grade1 C Grade1 Units Comments 10 ±3 ±3 –80/+40 –V BIAS / +40 16 9 2 10 ±3 ±3 –80/+40 –V BIAS / +40 16 10 2 Bits LSB max % FSR max mV max mV max DAC Code = 0.5 Full Scale DAC Code = 000H for Offset Binary 8 ± 0.125 ± 0.5 8 ± 0.125 ± 0.5 Bits LSB typ LSB max VBIAS ± 15/16 × VBIAS VBIAS /16 to 31/16 × VBIAS 4 2.5 1 0.5 0.5 ± 0.2 2 0.002 VBIAS ± 15/16 × VBIAS VBIAS/16 to 31/16 × VBIAS 4 2.5 1 0.5 0.5 ± 0.2 2 0.002 V V µs max V/µs typ nV-s typ nV-s typ nV-s typ LSB typ Ω typ %/% typ DAC REFERENCE INPUTS REF IN Range REF IN Input Leakage 1.0 to VDD/2 ±1 1.0 to VDD/2 ±1 V min to V max µA max DIGITAL INPUTS Input High Voltage, VIH @ VDD = 5 V Input High Voltage, VIH @ VDD = 3.3 V Input Low Voltage, VIL @ VDD = 5 V Input Low Voltage, VIL @ VDD = 3.3 V Input Leakage Current Input Capacitance Input Coding 2.4 2.1 0.8 0.6 ± 10 10 Twos Comp/Binary 2.4 2.1 0.8 0.6 µA max 10 Twos Comp/Binary V min V min V max V max REFERENCE OUTPUT REF OUT Output Voltage REF OUT Error REF OUT Temperature Coefficient REF OUT Output Impedance 1.23 ±8 –100 5 1.23 ±8 –100 5 V nom % max ppm/°C typ kΩ nom 3/5.5 3/5.5 V min to V max 12 250 12 250 mA max µA 0.8 1.5 0.8 1.5 µA max µA max 66 1.38 66 1.38 mW max mW max 4.4 8.25 4.4 8.25 µW max µW max Parameter STATIC PERFORMANCE MAIN DAC Resolution Relative Accuracy Gain Error Bias Offset Error2 Zero-Scale Error3 Monotonicity Minimum Load Resistance SUB DAC Resolution Differential Nonlinearity OUTPUT CHARACTERISTICS Output Voltage Range3 Voltage Output Settling Time to 10 Bits Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough Digital Crosstalk Analog Crosstalk DC Output Impedance Power Supply Rejection Ratio POWER REQUIREMENTS VDD (AVDD and DVDD) IDD (AIDD Plus DIDD) Normal Mode System Standby (SSTBY) Mode Power-Down (PD) Mode @ +25°C TMIN–TMAX Power Dissipation Normal Mode System Standby (SSTBY) Mode Power-Down (PD) Mode @ +25°C TMIN–TMAX Bits kΩ min and 200H for Twos Complement Coding Refers to an LSB of the Main DAC Twos Complement Coding Offset Binary Coding Typically 1.5 µs 1 LSB Change Around the Major Carry ∆VDD ± 10% Typically ± 1 nA pF max Excluding Load Currents VIH = V DD, V IL = DGND VIH = V DD, V IL = DGND VIH = V DD, V IL = DGND Excluding Power Dissipated in Load NOTES 1 Temperature range is – 40°C to +85°C. 2 Can be minimized using the Sub DAC. 3 VBIAS is the center of the output voltage swing and can be V DD/2, Internal Reference or REFIN as determined by MX1 and MX0 in the channel control register. Specifications subject to change without notice. –2– REV. A AD7804/AD7805/AD7808/AD7809 AD7808/AD7809–SPECIFICATIONS (AVDD and DV DD = 3.3 V ⴞ 10% to 5 V ⴞ 10%; AGND = DGND = 0 V; Reference = Internal Reference; CL = 100 pF; RL = 2 k⍀ to GND. Sub DAC at Midscale. All specifications TMIN to TMAX unless otherwise noted.) B Grade1 Units Comments 10 ±4 ±3 ± 60 ± 35 9 2 Bits LSB max % FSR max mV max mV max Bits kΩ min DAC Code = 0.5 Full Scale DAC Code = 000H for Offset Binary and 200H for Twos Complement Coding 8 ± 0.125 ± 0.5 Bits LSB typ LSB max VBIAS ± 15/16 × VBIAS VBIAS /16 to 31/16 × VBIAS 4 2.5 1 0.5 0.5 ± 0.2 2 0.002 V V µs max V/µs typ nV-s typ nV-s typ nV-s typ LSB typ Ω typ %/% typ DAC REFERENCE INPUTS REF IN Range REF IN Input Leakage 1.0 to VDD/2 ±1 V min to V max µA max DIGITAL INPUTS Input High Voltage, VIH @ VDD = 5 V Input High Voltage, VIH @ VDD = 3.3 V Input Low Voltage, VIL @ VDD = 5 V Input Low Voltage, VIL @ VDD = 3.3 V Input Leakage Current Input Capacitance Input Coding 2.4 2.1 0.8 0.6 ± 10 8 Twos Comp/Binary V min V min V max V max µA max pF max REFERENCE OUTPUT REF OUT Output Voltage REF OUT Error REF OUT Temperature Coefficient REF OUT Output Impedance 1.23 ±8 –100 5 V nom % max ppm/°C typ kΩ nom 3/5.5 V min to V max 18 250 mA max µA max 1 3 µA max µA max 99 1.38 mW max mW max 5.5 16.5 µW max µW max Parameter STATIC PERFORMANCE MAIN DAC Resolution Relative Accuracy Gain Error Bias Offset Error2 Zero-Scale Error Monotonicity Minimum Load Resistance SUB DAC Resolution Differential Nonlinearity OUTPUT CHARACTERISTICS Output Voltage Range3 Voltage Output Settling Time to 10 Bits Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough Digital Crosstalk Analog Crosstalk DC Output Impedance Power Supply Rejection Ratio POWER REQUIREMENTS VDD (AVDD and DVDD) IDD (AIDD Plus DIDD) Normal Mode System Standby (SSTBY) Mode Power-Down (PD) Mode @ +25°C TMIN–TMAX Power Dissipation Normal Mode System Standby (SSTBY) Mode Power-Down (PD) Mode @ +25°C TMIN–TMAX Refers to an LSB of the Main DAC Twos Complement Coding Offset Binary Coding Typically 1.5 µs 1 LSB Change Around the Major Carry ∆VDD ± 10% Typically ± 1 nA Excluding Load Currents VIH = V DD, V IL = DGND VIH = VDD , VIL = DGND VIH = V DD, V IL = DGND Excluding Power Dissipated in Load NOTES 1 Temperature range is – 40°C to +85°C. 2 Can be minimized using the Sub DAC. 3 VBIAS is the center of the output voltage swing and can be V DD/2, Internal Reference or REFIN as determined by MX1 and MX0 in the channel control register. Specifications subject to change without notice. REV. A –3– AD7804/AD7805/AD7808/AD7809 AD7804/AD7808 TIMING CHARACTERISTICS1(V DD = 3.3 V ⴞ 10% to 5 V ⴞ 10%; AGND = DGND = 0 V; Reference = Internal Reference. All specifications TMIN to TMAX unless otherwise noted.) Parameter t1 t2 t3 t4 t5 t6 t6A t7 t8 t9 Limit at TMIN, T MAX All Versions Units Description 100 40 40 30 30 5 6 90 20 40 100 ns min ns min ns min ns min ns min ns min ns min ns max ns min ns min ns min CLKIN Cycle Time CLKIN High Time CLKIN Low Time FSIN Setup Time Data Setup Time Data Hold Time LDAC Hold Time FSIN Hold Time LDAC, CLR Pulsewidth LDAC Setup Time NOTES 1 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and timed from a voltage of (V IL + VIH)/2. Specifications subject to change without notice. t1 CLKIN(I) t2 t3 t4 t7 FSIN(I) t5 t6 SDIN(I) DB15 DB0 t 6A t5 LDAC1 t9 LDAC2 t8 t8 CLR 1TIMING 2TIMING REQUIREMENTS FOR SYNCHRONOUS LDAC UPDATE OR LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED. REQUIREMENTS FOR ASYNCHRONOUS LDAC UPDATE. Figure 1. Timing Diagram for AD7804 and AD7808 –4– REV. A AD7804/AD7805/AD7808/AD7809 AD7805/AD7809 TIMING CHARACTERISTICS1 (VDD = 3.3 V ⴞ 10% to 5 V ⴞ 10%; AGND = DGND = 0 V; Reference = Internal Reference. All specifications TMIN to TMAX unless otherwise noted.) Parameter Limit at TMIN, T MAX All Versions Unit Description t1 t2 t3 t4 t5 t6 t6A t7 t8 t9 t10 t11 t12 25 4.5 25 4.5 25 4.5 6 40 0 40 100 40 100 ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min Mode Valid to Write Setup Time Mode Valid to Write Hold Time Address Valid to Write Setup Time Address Valid to Write Hold Time Data Setup Time Data Hold Time LDAC Valid to Write Hold Time Chip Select to Write Setup Time Chip Select to Write Hold Time Write Pulsewidth Time Between Successive Writes LDAC, CLR Pulsewidth Write to LDAC Setup Time NOTE 1 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and timed from a voltage of (V IL + VIH)/2. Specifications subject to change without notice. t1 t2 MODE t3 t4 A0, A1, A2 t8 t7 CS t10 t9 WR t5 t6 DATA t 6A LDAC 1 t12 t11 LDAC 2 t11 CLR 1TIMING 2TIMING REQUIREMENTS FOR SYNCHRONOUS LDAC UPDATE OR LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED. REQUIREMENTS FOR ASYNCHRONOUS LDAC UPDATE. Figure 2. Timing Diagram for AD7805/AD7809 Parallel Write REV. A –5– AD7804/AD7805/AD7808/AD7809 ABSOLUTE MAXIMUM RATINGS 1 PDIP (N-24) Package, Power Dissipation . . . . . . . . . 670 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C SOIC (R-28) Package, Power Dissipation . . . . . . . . . 875 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 70°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C PDIP (N-28) Package, Power Dissipation . . . . . . . . . 875 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C SSOP (RS-28) Package, Power Dissipation . . . . . . . . 875 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C TQFP (SU-44) Package, Power Dissipation . . . . . . 450 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 116°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C (TA = +25°C unless otherwise noted) DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V + 0.3 V Digital Input Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 V Analog Input Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V COMP to AGND . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V REF OUT to AGND . . . . . . . . . . . . . . . . . . –0.3 V to + AVDD REF IN to AGND . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V VOUT to AGND2 . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V Input Current to Any Pin Except Supplies3 . . . . . . . . ± 10 mA Operating Temperature Range AD7804/AD7805 Commercial Plastic (B, C Versions) . . . . . . . . . . . . . . . . . . . . –40°C to +85°C AD7808/AD7809 Commercial Plastic (B, C Versions) . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C SOIC (R-16) Package, Power Dissipation . . . . . . . . . 450 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C PDIP (N-16) Package, Power Dissipation . . . . . . . . . 670 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 116°C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C SOIC (R-24) Package, Power Dissipation . . . . . . . . . 450 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 The outputs may be shorted to voltages in this range provided the power dissipation of the package is not exceeded. 3 Transient currents of up to 100 mA will not cause SCR latch-up. ORDERING GUIDE Model AD7804BN AD7804BR AD7805BN AD7805BR AD7805BRS AD7805CR AD7808BN AD7808BR AD7809BST Supply Voltage 3.3 V to 5 V 3.3 V to 5 V 3.3 V to 5 V 3.3 V to 5 V 3.3 V to 5 V 3.3 V to 5 V 3.3 V to 5 V 3.3 V to 5 V 3.3 V to 5 V Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Relative Accuracy ± 3 LSB ± 3 LSB ± 3 LSB ± 3 LSB ± 3 LSB ± 3 LSB ± 4 LSB ± 4 LSB ± 4 LSB Package Descriptions 16-Lead Plastic DIP 16-Lead Small Outline IC 28-Lead Plastic DIP 28 Lead Small Outline IC 28-Lead Shrink Small Outline Package 28-Lead Small Outline IC 24-Lead Plastic DIP 24 Lead Small Outline IC 44-Lead Thin Plastic Quad Flatpack (TQFP) CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although these devices feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –6– Package Options N-16 R-16 N-28 R-28 RS-28 R-28 N-24 R-24 SU-44 WARNING! ESD SENSITIVE DEVICE REV. A AD7804/AD7805/AD7808/AD7809 AD7804/AD7808 PIN FUNCTION DESCRIPTION AD7804 Pin No. AD7808 Pin No. Mnemonic Description 1 2, 3 4 1, 6 2, 3 4 5 AGND VOUTB, VOUTA REFOUT PD 5 7, 8 9 VOUTF, VOUTE FSIN 6 10 LDAC 7 11 SDIN 8 9 10 12 13 14 DGND DVDD CLKIN 11 15 CLR 12 16 17, 18 20 NC VOUTH, VOUTG REFIN 13 21 COMP 14, 15 16 22, 23 19, 24 VOUTD, V OUTC AVDD Ground reference point for analog circuitry. Analog output voltage from the DACs. Reference Output. This is a bandgap reference and is typically 1.23 V. Active low input used to put the part into low power mode reducing current consumption to 1 µA. Analog output voltages from the DACs. Level-triggered control input (active low). This is the frame synchronization signal for the input data. When FSIN goes low, it enables the input shift register and data is transferred on the falling edges of CLKIN. LDAC Input. When this digital input is taken low, all DAC registers are simultaneously updated with the contents of the data registers. If LDAC is tied permanently low, or is low on the sixteenth falling clock edge with timing similar to that of SDIN, an automatic update will take place. Serial Data Input. These devices accept a 16-bit word. Data is clocked into the input shift register on the falling edge of CLKIN. Ground reference point for digital circuitry. Digital Power Supply. Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN. Duty Cycle should be between 40% and 60%. Asynchronous CLR Input. When this input is taken low, all Main DAC outputs are cleared either to VBIAS or to V BIAS/16 volts. All Sub DACs are also cleared and thus the transfer function of the Main DAC will remain centered around the VBIAS point. No Connect. This pin should be left open circuit. Analog output voltages from the DACs. This is an external reference input for the DACs. When this reference is selected for a DAC in the control register, the analog output from the selected DAC swings around this point. Compensation Pin. This pin provides an output from the internal VDD/2 divider and is provided for ac bypass purposes only. This pin should be decoupled with 1 nF capacitors to both AVDD and AGND. This pin can be overdriven with an external reference, thus giving the facility for two external references on the part. Analog output voltage from the DACs. Analog Power Supply. +3.3 V to +5 V. AD7808 PIN CONFIGURATION AD7804 PIN CONFIGURATION AGND 1 VOUT B 2 VOUT A 3 16 15 14 AVDD VOUT C VOUT D AD7804 13 COMP TOP VIEW FSIN 5 (Not to Scale) 12 REFIN REFOUT 4 LDAC 6 11 CLR SDIN 7 10 CLKIN DGND 8 9 DVDD AGND 1 24 AVDD VOUT B 2 23 VOUT C VOUT A 3 22 VOUT D REFOUT 4 21 COMP PD 5 AGND 6 VOUT F 7 VOUT E 8 17 VOUT H FSIN 9 16 NC LDAC 10 15 CLR SDIN 11 14 CLKIN DGND 12 13 DVDD AD7808 20 REFIN 19 AVDD TOP VIEW (Not to Scale) 18 V OUT G NC = NO CONNECT REV. A –7– AD7804/AD7805/AD7808/AD7809 AD7805/AD7809 PIN FUNCTION DESCRIPTIONS AD7805 Pin No. AD7809 Pin No. 1 2, 3 4 5–10, 12, 13 19, 20 1, 11, 13, 20, 33 2, 5, 39, 40 41, 42 43 3, 4, 6, 7, 9, 10, 15, 23 24, 26 11 8, 12 14 VOUTF, VOUTE LDAC 14 15 16 16 17 18 DGND DVDD WR 17 18 21 19 CS CLR 21, 22 22, 25 27, 29, 30 VOUTH, VOUTG A2, A1, A0 23 31 MODE 24 32 REFIN 25 34 COMP 26, 27 28 35, 36 28, 37, 38 44 VOUTD, V OUTC AVDD PD Mnemonic Description NC No Connect. These pins should be left open circuit. AGND VOUTB, VOUTA REFOUT DB9–DB2 Ground reference point for analog circuitry. Analog output voltages from the DACs. Reference Output. This is a bandgap reference and is typically 1.23 V. Data Inputs. DB9 to DB2 are the 8 MSBs of the data word. DB1, DB0 DB1 and DB0 function as the 2 LSBs of the 10-bit word in 10-bit parallel mode but have other functions when BYTE loading structure is used. Analog output voltages from the DACs. LDAC Input. When this digital input is taken low, all DAC registers are simultaneously updated with the contents of the DAC data registers. If LDAC is permanently tied low, or is low during the rising edge of WR similar to data inputs, an automatic update will take place. Ground reference point for digital circuitry. Digital Power Supply. Write Input WR is an active low logic input which is used in conjunction with CS and the address pins to write data to the relevant registers. Chip Select. Active low logic input. Asynchronous CLR Input. When this input is taken low, all Main DAC outputs are cleared either to VBIAS or to V BIAS/16 volts. All Sub DACs are also cleared and thus the transfer function of the MAIN DAC will remain centered around the VBIAS point. Analog output voltages from the DACs. DAC Address Inputs. These digital inputs are used in conjunction with CS and WR to determine which DAC channel control register or DAC data register is loaded from the input register. These address bits are don’t cares when writing to the system control register. Logic Input. Logic high enables writing to the DAC data registers, a logic low enables writing to the control registers. This is an external reference input for the DAC. When this reference is selected for the DAC in the control register, the analog output from the selected DAC swings around this point. Compensation Pin. This pin provides an output from the internal VDD/2 divider and is provided for ac bypass purposes only. This pin should be decoupled with 1 nF capacitors to both AVDD and AGND. This pin can be overdriven with an external reference, thus giving the facility for two external references on the part. Analog output voltages from the DACs. Analog Power Supply. Active low input used to put the part into low power mode reducing current consumption to 1 µA. VOUT C VOUT A 3 26 VOUT D REFOUT 4 25 COMP DB9 5 24 REFIN NC 1 AGND 2 23 MODE 22 A0 TOP VIEW DB6 8 (Not to Scale) 21 A1 DB4 10 19 DB1 LDAC 11 18 CLR DB3 12 17 CS DB2 13 16 WR DGND 14 15 DVDD MODE 30 A0 A1 28 AVDD 29 AD7809 DB7 6 TOP VIEW (Not to Scale) DB6 7 VOUTF 8 27 26 A2 DB0 DB5 9 25 VOUTG DB4 10 24 DB1 NC 11 23 DB2 12 13 14 15 16 17 18 19 20 21 22 NC = NO CONNECT –8– CS VOUT H DB0 31 DB8 4 AGND 5 WR CLR NC 20 DB9 3 DVDD DB5 9 NC REFIN DGND AD7805 32 33 PIN 1 IDENTIFIER LDAC DB3 DB7 7 44 43 42 41 40 39 38 37 36 35 34 VOUT E NC DB8 6 COMP AVDD 27 AVDD VOUT C VOUT D 28 AGND AVDD AGND 1 VOUT B 2 VOUT A VOUT B AGND AD7809 PIN CONFIGURATION PD REFOUT AD7805 PIN CONFIGURATION REV. A AD7804/AD7805/AD7808/AD7809 TERMINOLOGY Relative Accuracy Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the digital inputs change state with the DAC selected and the LDAC used to update the DAC. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition. Regardless of whether offset binary or twos complement coding is used, the major carry transition occurs at the analog output voltage change of VBIAS to VBIAS – 1 LSB or vice versa. For the DACs, relative accuracy or endpoint nonlinearity is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Figures 32 and 33 show the linearity at 3 V and 5 V respectively. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of a DAC from the digital inputs of the same DAC but is measured when the DAC is not updated. It is specified in nV secs and is measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa. Bias Offset Error If the DACs are ideal, the output voltage of any DAC with midscale code loaded will be equal to VBIAS where VBIAS is selected by MX1 and MX0 in the control register. The DAC bias offset error is the difference between the actual output voltage and VBIAS, expressed in mV. Digital Crosstalk Digital crosstalk is the glitch impulse transferred to the output of one converter due to a digital code change to another DAC. It is specified in nV-s. Gain Error The difference between the actual and ideal analog output range, expressed as a percent of full-scale range. It is the deviation in slope of the DAC transfer characteristic from ideal. Analog Crosstalk Analog crosstalk is a change in output of any DAC in response to a change in the output of one or more of the other DACs. It is measured in LSBs. Zero-Scale Error The zero-scale error is the actual output minus the ideal output from any DAC when zero code is loaded to the DAC. If offset binary coding is used, the code loaded is 000Hex, and if twos complement coding is used, a code of 200HEX is loaded to the DAC to calculate the zero-scale error. Zero-scale error is expressed in mV. Power Supply Rejection Ratio (PSRR) This specification indicates how the output of the DAC is affected by changes in the power supply voltage. Power-supply rejection ratio is quoted in terms of % change in output per % change in VDD for full-scale output of the DAC. VDD is varied ± 10%. AD7804/AD7808 INTERFACE SECTION sequence for the channel control register write, and Figures 6 and 7 show the sequence for loading data to the Main and Sub DAC data registers. Figure 3 shows the internal registers associated with the AD7804/AD7808 serial interface DACs. Only one DAC structure is shown for clarity. The AD7804 and AD7808 are serial input devices. Three lines control the serial interface, FSIN, CLKIN and SDIN. The timing diagram is shown in Figure 1. Two mode bits (MD1 and MD0) which are DB13 and DB14 of the serial word written to the AD7804/AD7808 are used to determine whether writing is to the DAC data registers or the control registers of the device. These parts contain a system control register for controlling the operation of all DACs in the package as well as a channel control register for controlling the operation of each individual DAC. Table I shows how to access these registers. FSIN CLKIN SDIN 16-BIT INPUT SHIFT REGISTER DECODER SYSTEM CONTROL REGISTER Table I. Register Selection Table for the AD7804/AD7808 MD1 MD0 Function 0 0 1 0 1 X Write enable to system control register. Write enable to channel control register. Write enable to DAC data registers. TO ALL CHANNELS SINGLE CHANNEL INTERNAL VREF VDD/2 DATA REGISTER DATA REGISTER 10 8 DAC REGISTER DAC REGISTER 10 10-BIT DAC (MAIN DAC) VOUT When the FSIN input goes low, data appearing on the SDIN line is clocked into the input register on each falling edge of CLKIN. Data to be transferred to the AD7804/AD7808 is loaded MSB first. Figure 4 shows the loading sequence for the AD7804/AD7808 system control register, Figure 5 shows the REV. A CHANNEL CONTROL REGISTER 8 8-BIT DAC (SUB DAC) VBIAS MUX REFIN Figure 3. AD7804/AD7808 Internal Registers –9– AD7804/AD7805/AD7808/AD7809 MSB X LSB MD0 = 0 MD1 = 0 X X X X X 0 PD BIN/COMP SSTBY SCLR 0 X X X = Don’t Care Figure 4. AD7804/AD7808 System Control Register Loading Sequence DB15 (MSB) X DB0 (LSB) MD0 = 1 MD1 = 0 A2* A1 A0 MX1 MX0 X X STBY X CLR 0 X X X = Don’t Care *Applicable to the AD7808 Only, and Are Don’t Care Conditions when Operating the AD7804 . Figure 5. AD7804/AD7808 Channel Control Register Loading Sequence DB15 (MSB) MAIN/SUB DB0 (LSB) MD0 = X MD1 = 1 A2* A1 A0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X = Don’t Care *Applicable to the AD7808 Only, and Are Don’t Care Conditions when Operating the AD7804 . Figure 6. AD7804/AD7808 Main DAC Data Register Loading Sequence (MAIN /SUB = 0) DB15 (MSB) MAIN/SUB DB0 (LSB) MD0 = X MD1 = 1 A2* A1 A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X X = Don’t Care *Applicable to the AD7808 Only, and Are Don’t Care Conditions when Operating the AD7804. Figure 7. AD7804/AD7808 Sub DAC Data Register Loading Sequence (MAIN /SUB = 1) When the system control register is selected by writing zeros to the mode bits, MD1 and MD0 the address bits are ignored as the system control register controls all DACs in the package. When MD1 = 0 and MD0 = 1, writing is to the channel control register. Only the DAC selected by the address bits will be affected by writing to this register. Each individual DAC has a channel control register. AD7804/AD7808 SYSTEM CONTROL REGISTER (MD1 = 0, MD0 = 0) The DACs data registers are addressed by writing a one to MD1 (DB13); the condition of MD0 (DB14) does not matter when writing to the data registers. DB15 determines whether writing is to the Main DAC data register or to the Sub DAC data register. The Main DAC is 10 bits wide and the Sub DAC is 8 bits wide. Thus when writing to the Sub DAC DB1 and DB0 become don’t cares. The Sub DAC is used to offset the complete transfer function of the Main DAC around its VBIAS point. The Sub DAC has 1/8 LSB resolution and will enable the transfer function of the Main DAC to be offset by ± VBIAS/32. This bit in the control register is used to shut down the complete device. With a 0 in this position, the reference and all DACs are put into low power mode. Writing a 1 to this bit puts the part in the normal operating mode. When in power-down mode, the contents of all registers are retained and are valid when the device is put back into normal operation. The bits in this register allow control over all DACs in the package. The control bits include power down (PD), DAC input coding select (BIN/COMP), system standby (SSTBY) and a system clear (SCLR). The function of these bits is as follows: Power Down (PD) When the LDAC line goes low, all DAC registers in the device are simultaneously loaded with the contents of their respective DAC data registers, and the outputs change accordingly. Bringing the CLR line low resets the DAC data and DAC registers. This hardware clear affects both the Main and Sub DACs. This operation sets the analog output of the Main DAC to VBIAS/ 16 when offset binary coding is selected and the output is set to VBIAS when twos complement coding is used. VBIAS is the output of the internal multiplexer as shown in Figure 3. The output of the Sub DAC is used to shift the transfer function of the Main DAC around the VBIAS point and the contribution from the Sub DAC is zero following an external hardware clear. Software clears affect the Main DACs only. Coding (BIN/COMP) This bit in the system control register allows the user to select one of two input coding schemes. The available schemes are Twos complement coding and offset binary coding. All DACs will be configured with the same input coding scheme. Writing a zero to the control register selects twos complement coding, while writing a 1 to this bit in the control register selects offset binary coding. With twos complement coding selected the output voltage from the Main DAC is of the form : VOUT = VBIAS ± VSWING where VSWING is 15 × VBIAS 16 With Offset Binary coding selected the output voltage from the Main DAC ranges from: VOUT = –10– VBIAS to VOUT = 31 × VBIAS 16 16 REV. A AD7804/AD7805/AD7808/AD7809 VBIAS can be the internal bandgap reference, the internal VDD/2 reference or the external REFIN as determined by MX1 and MX0 in the channel control register. A second external reference can be used if required by overdriving the VDD/2 reference which appears at the COMP pin. Standby (STBY) This bit allows the selected DAC in the package to be put into low power mode. Writing a zero to the STBY bit in the channel control register puts the selected DAC into standby mode. On writing a zero to this bit all linear circuitry is switched off and the DAC output is connected through a high impedance to ground. The DAC is returned to normal operation by writing a one to the STBY bit. System Standby (SSTBY) This bit allows all the DACs in the package to be put into low power mode simultaneously but the reference is not affected. Writing a one to the SSTBY bit in the system control register puts all DACs into standby mode. On writing a one to this bit all linear circuitry is switched off and the DAC outputs are connected through a high impedance to ground. The DACs come out of standby mode when a 0 is written to the SSTBY bit. Software Clear Function (CLR) System Clear Function (SCLR) This function allows the user to clear the contents of all data and DAC registers in software. Writing a one to the SCLR bit in the control register clears the DAC’s outputs. A zero in this bit position puts the DAC in normal operating mode. The output of the Main DACs are cleared to one of two voltages depending on the input coding used. If twos complement coding is selected, then issuing a software clear will reset the output of the Main DAC to midscale (VBIAS). If offset binary coding is selected, the Main DAC output will be reset to VBIAS /16 following the execution of a software clear. This system clear function does not affect the Sub DAC; the Sub DAC data register retains its value during a system software clear (SCLR). This function allows the user to clear the contents of the selected DAC’s data in software. Writing a one to the CLR bit in the control register clears the DAC’s output. A zero in the CLR bit position puts the DAC in normal operating mode. This software CLR operation clears only the Main DAC, the contents of the Sub DAC is unaffected by a CLR operation. The output of the Main DAC can be cleared to one of two places depending on the input coding used. An LDAC pulse is required to activate the channel clear function and must be applied after the bit in the channel control register is set or reset. If twos complement coding is selected, then issuing a software clear will reset the output of the Main DAC to midscale (VBIAS). If offset binary coding is selected, the Main DAC output will be reset to VBIAS/16 following the execution of a software clear. Multiplexer Selection (MX1, MX0) These two bits are used to select the reference input for the selected DAC. Table III shows the options available. Table III. Multiplexer Output Selection AD7804/AD7808 CHANNEL CONTROL REGISTER (MD1 = 0, MD0 = 1) This register allows the user to have control over individual DACs in the package. The control bits in this register include the address bits for the selected DAC, standby (STBY), individual DAC clear (CLR) and multiplexer output selection (MX1 and MX0). The function of these bits follows. MX1 MX0 VBIAS 0 0 1 1 0 1 0 1 VDD/2 INTERNAL VREF REFIN Undetermined DAC Selection (A2, A1, A0) Bits A2, A1 and A0 in the input registers are used to address a specific DAC. Table IIa shows the selection table for the DACs of the AD7804. Table IIb shows the selection table for the DACs of the AD7808. Table IIa. DAC Selection Table for the AD7804 A2 A1 A0 Function X X X X 0 0 1 1 0 1 0 1 DAC A Selected DAC B Selected DAC C Selected DAC D Selected Table IIb. DAC Selection Table for the AD7808 REV. A A2 A1 A0 Function 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 DAC A Selected DAC B Selected DAC C Selected DAC D Selected DAC E Selected DAC F Selected DAC G Selected DAC H Selected AD7804/AD7808 SUB DAC DATA REGISTER Figure 7 shows the loading sequence for writing to the data registers of the DACs. DB15 determines whether writing is to the Main or Sub DAC’s data register. A one in this position selects the addressed Sub DAC’s data register. The Sub DAC is 8 bits wide and thus DB1 and DB0 of the 16-bit input word are don’t cares when writing to the Sub DAC. This Sub DAC allows the complete transfer function of each individual DAC to be offset around the VBIAS point. This is achieved by either adding or subtracting to the output of the Main DAC. This Sub DAC has a span of ± VBIAS/32 with 1/8-bit resolution. The coding scheme for the Sub DAC is the same as that for the Main DAC. With offset binary coding the transfer function for the Sub DAC is VBIAS (NB – 128) × 16 256 where NB is the digital code written to the Sub DAC and varies from 0 to 255. With twos complement coding the transfer function for the Sub DAC is V BIAS × NB 16 256 where NB is the digital code written to the Sub DAC and varies from –128 to 127. VBIAS can be either the internal bandgap reference, the internal VDD/2 reference or the external REFIN as ( ) –11– AD7804/AD7805/AD7808/AD7809 determined by MX1 and MX0 in the channel control register as shown in Table III. The internal VDD/2 reference is provided at the COMP pin. This internal reference can be overdriven with an external reference thus providing the facility for two external references. POWER-UP SYSTEM CONFIGURATION WRITE TO SYSTEM CONTROL REGISTER WRITE TO CHANNEL CONTROL REGISTER CHANNEL CONFIGURATION AD7804/AD7808 POWER-UP CONDITIONS When power is applied to the device, the device will come up in standby mode where all the linear circuitry excluding the reference are switched off. Figure 8 shows the relevant default values for the system control register. Since a write to the system control register is required to remove the standby condition the only bits for which default conditions are applicable are PD and SSTBY. Figure 9 details the relevant default conditions for the Channel Control Register. PD SSTBY 1 1 ALL CHANNELS CONFIGURED N Y WRITE TO SELECTED MAIN OR SUB DAC DATA REGISTERS DATA LOADING COMPLETE DATA WRITE N Y Figure 8. Default Conditions for System Control Register on Power-Up STBY CLR MX1 MX0 1 1 0 0 Y N Y Figure 9. Default Conditions for Channel Control Register on Power-Up After power has been applied to the device the following procedure should be followed to communicate and set up the device. First, a write to the system control register is required to clear the SSTBY bit and change the input coding scheme if required. For example, to remove standby and set up offset binary input coding 0060Hex should be written to the input register, if twos complement coding is required 0020Hex should be written to the input register. MD1 and MD0 are decoded in the input register and this allows the data to be written to the system control register. Step two requires writing to the channel control register, which allows individual control over each DAC in the package and allows the VBIAS for the DAC to be selected as well as individual DAC standby and clear functions. For example, if channel A is to be configured for normal operation with internal reference selected then 4110Hex should be written to the input register. In the input register, the MD1 and MD0 bits are decoded in association with the address bits to give access to the required channel control register. The third and final step is to write data to the selected DAC. To write half scale to channel A Main DAC, 2200Hex should be written to the input register, the MSB in the sixteen bit stream selects the Main DAC and the next three bits address the DAC and the final 10 bits contain the data. To write half scale to channel A Sub DAC, then A200 should be written to the input register. The flowchart in Figure 10 shows in graphic form the steps required in communicating with the AD7804/AD7808. CHANGE CHANNEL CONFIGURATION CHANGE SYSTEM CONFIGURATION N END Figure 10. Flowchart for Controlling the DAC Following Power-Up AD7805/AD7809 INTERFACE SECTION The AD7805 and AD7809 are parallel data input devices and contain both control registers and data registers. The system control register has global control over all DACs in the package while the channel control register allows control over individual DACs in the package. Two data registers are also available, one for the 10-bit Main DAC and the second for the 8-bit Sub DAC. In the parallel mode, CS and WR, in association with the address pins, control the loading of data. Data is transferred from the data register to the DAC register under the control of the LDAC signal. Only data contained in the DAC register determines the analog output of any DAC. The timing diagram for 10-bit parallel loading is shown in Figure 2. The MODE pin on the device determines whether writing is to the data registers or to the control registers. When MODE is at a logic one, writing is to the data registers. In the next write to the data registers a bit in the channel control register determines whether the Main DAC or the Sub DAC is addressed. This means that to address either the Main or the Sub DAC the Main/Sub bit in the control register has to be set appropriately before the data register write. A logic zero on the mode pin enables writing to the control register. Bit MD0 determines whether writing is to the system control register or to the addressed channel control register. Bringing the CLR line low resets the DAC registers to one of two known conditions depending on the coding scheme selected. The hardware clear affects both the Main and Sub DAC registers. With offset binary coding a clear sets the output –12– REV. A AD7804/AD7805/AD7808/AD7809 of the Main DAC to the bottom of the transfer function, VBIAS/16. With twos complement coding the output of the DAC is cleared to midscale which is VBIAS. A hardware clear always clears the output of the Sub DAC to midscale thus the output of the Sub DAC makes zero contribution to the output of the channel. MODE ADDR CS WR LDAC CONTROL LOGIC DECODER CHANNEL CONTROL REGISTER DATA REGISTER SINGLE CHANNEL 10 8 DAC REGISTER 10 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VBIAS X X X X X X X DB1 DB0 DB1 DB0 0 MAIN/SUB 1 MAIN/SUB X = Don’t Care Figure 15. AD7805/AD7809 Main DAC Data Register Configuration (MODE = 1, 10 /8 = 1, MAIN /SUB = 0) Figure 11. AD7805/AD7809 Internal Registers Figure 16 shows the bit allocations for writing to the Sub DAC. AD7805/AD7809 CONTROL REGISTERS Access to the control registers of the AD7805/AD7809 is achieved by taking the mode pin to a logic low. The control register of these DACs are configured as in Figures 12 and 13. There are two control registers associated with the part. System control register which looks after the input coding, data format, power down, system clear and system standby. The channel control register contains bits that affect the operation of the selected DAC. The external address bits are used to select the DACs. These registers are eight bits wide and the last two bits are control bits. The mode pin must be low to have access to the control registers. DB9 DB2 DB1 PD SSTBY SCLR 0 X DB0 MD0 = 0 X = Don’t Care Figure 12. AD7805/AD7809 System Control Register Configuration, (MODE = 0) DB9 MX1 MX0 MAIN/SUB X DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 MUX X X 10/8 BIN/COMP X X = Don’t Care DB9 8 REFIN DB2 X STBY CLR 0 DB1 X DB9 MD0 = 1 Figure 13. AD7805/AD7809 Channel Control Register Configuration (MODE = 0) The external mode pin must be taken high to allow data to be written to the DAC data registers. Figure 14 shows the bit allocations when 10-bit parallel operation is selected in the system control register. DB2 DB1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB0 X MAIN/SUB X = Don’t Care Figure 16. AD7805/AD7809 Sub DAC Data Register Configuration (MODE = 1, MAIN /SUB = 1) Each DAC has a separate channel control register. The following is a brief discussion on the bits in each of the control registers. DAC Selection (A2, A1, A0) The external address pins in conjunction with CS, WR and MODE are used to address the various DAC data and control registers. Table IVa shows how these DAC registers can be addressed on the AD7805. Table IVb shows how these registers are addressed on the AD7809. Refer to Figures 12 to 16 for information on the registers. Table IVa. AD7805 DAC Data/Control Register Selection Table DB0 X = Don’t Care REV. A DB0 8-BIT DAC (SUB DAC) 10-BIT DAC (MAIN DAC) VOUT INTERNAL VREF VDD/2 DATA REGISTER DAC REGISTER DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 Figure 15 shows the bit allocations when 8-bit parallel operation is selected in the system control register. DB9 to DB2 are retained as data bits. DB1 acts as a high byte or low byte enable. When DB1 is low, the eight MSBs of the data word are loaded to the input register. When DB1 is high, the low byte consisting of the two LSBs are loaded to the input register. DB0 is used to select either the Main or Sub DAC when in the byte mode. SYSTEM CONTROL REGISTER TO ALL CHANNELS DB0 Figure 14. AD7805/AD7809 Main DAC Data Register (Top) and Sub DAC Data Register (Bottom) Configuration (MODE = 1, 10/8 = 0) D9 D2 D1 D0 INPUT REGISTER DB9 MODE A1 A0 Function Selected 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 DAC A Control Registers DAC B Control Registers DAC C Control Registers DAC D Control Registers DAC A Data Registers DAC B Data Registers DAC C Data Registers DAC D Data Registers –13– AD7804/AD7805/AD7808/AD7809 Table IVb. AD7809 DAC Data/Control Register Selection Table MODE A2 A1 A0 Function Selected 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 DAC A Control Register DAC B Control Register DAC C Control Register DAC D Control Register DAC E Control Register DAC F Control Register DAC G Control Register DAC H Control Register 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 DAC A Data Register DAC B Data Register DAC C Data Register DAC D Data Register DAC E Data Register DAC F Data Register DAC G Data Register DAC H Data Register System Clear SCLR 0 Normal operation. 1 All DACs in the package are cleared to a known state depending on the coding scheme selected. The SCLR bit clears the Main DACs only; the Sub DACs are unaffected by the system clear function. The main DAC is cleared to different levels depending on the coding scheme. With offset binary coding the Main DAC output is cleared to the bottom of the transfer function VBIAS/16. With twos complement coding the Main DAC output is cleared to midscale VBIAS. The channel output will be the sum of the Main DAC and Sub DAC contributions. AD7805/AD7809 CHANNEL CONTROL REGISTER This register allows the user to have control over individual DACs in the package. The control bits in this register include multiplexer output selection (MX1 and MX0), Main or Sub DAC selection (MAIN/SUB), standby (STBY) and individual DAC clear (CLR). The function of these bits is as follows. Multiplexer Selection (MX1, MX0) Table V shows the VBIAS selection using MX1 and MX0 bits in the channel control register. AD7805/AD7809 SYSTEM OR CHANNEL CONTROL REGISTER SELECTION Table V. VBIAS Selection Table MD0 0 1 This enables writing to the system control register. The contents of this are shown in Figure 12. Mode must be low to access this control register. This enables writing to the channel control register. The contents of this are shown in Figure 13. Mode must also be low to access this control register. MX1 MX0 VBIAS 0 0 1 1 0 1 0 1 VDD/2 (Default on Power-Up) INTERNAL VREF REFIN Undetermined Main DAC or Sub DAC Selection AD7805/AD7809 SYSTEM CONTROL REGISTER 0 10-bit parallel loading structure. MAIN/SUB 0 Writing a 0 to this bit means that the data in the next data register write is transferred to the selected Main DAC. 1 Writing a 1 to this bit means that the data in the next data register write is transferred to the selected Sub DAC. This applies to the 10-bit parallel load feature. In byte load mode, (Figure 15) DB0 selects the Main or Sub DAC data registers. 1 Byte loading structure. (8+2 loading). Standby The bits in this register allow control over all DACs in the package. The control bits include data format (10/8), power down (PD), DAC input coding select (BIN/COMP), system standby (SSTBY) and a system clear (SCLR). The function of these bits is as follows: Data Format 10/8 Input Coding BIN/COMP 0 Twos complement coding. 1 Offset Binary Coding. Power Down PD 0 Complete power-down of device. 1 Normal operation (default on power-up). STBY 0 1 Clear CLR 0 1 System Standby SSTBY 0 Normal operation. 1 All DACs in the package put in standby mode (default on power-up). Places the selected DAC and its associated linear circuitry in Standby Mode. Normal operation (default on power-up). –14– Normal operation. Clears the output of the selected Main DAC to one of two conditions depending on the input coding selected. With offset binary coding the Main DAC output is cleared to the bottom of the transfer function, VBIAS/16 and with twos complement coding the Main DAC output is cleared to midscale VBIAS. The Sub DAC is unaffected by a clear operation. An LDAC signal has to be applied to the DAC for a channel clear to be implemented. REV. A AD7804/AD7805/AD7808/AD7809 POWER-UP CONDITIONS (POWER-ON RESET) START When power is applied to the AD7805/AD7809 the device powers up in a known condition. The device powers up in system standby (SSTBY) mode where all DACs in the package are in low power mode, the reference is active and the outputs of the DACs are connected internally through a high impedance to ground. Figure 17 show the default conditions for the system control register. Since a write to the system control register is required to remove the standby condition, relevant default conditions are only applicable for PD and SSTBY in the system control register. The following are the bits in the channel control register for which default conditions are applicable, STBY, CLR, MX1 and MX0. Figure 18 shows the default conditions for the channel control register. PD SSTBY 1 1 WRITE TO SYSTEM CONTROL REGISTER Y WRITE TO CHANNEL CONTROL REGISTER N WRITE TO SUB DAC WRITE TO MAIN DAC DATA REGISTER N WRITING COMPLETE Y Y Y WRITE TO CHANNEL CONTROL REGISTER WRITE TO SUB DAC DATA REGISTER RECONFIGURE SYSTEM N N END STBY CLR MX1 MX0 1 1 0 0 WRITING COMPLETE Y Figure 17. Default Conditions for the AD7805/AD7809 System Control Register on Power-Up Figure 19. Flowchart for Controlling the AD7805/AD7809 DACs in 10-Bit Parallel Mode Following Power-Up mode as the selection can be made using the hardware bit DB0 and this will reduce the software overheads when accessing the DACs. CLEAR FUNCTIONS Figure 18. Default Conditions for the AD7805/AD7809 Channel Control Register on Power-Up The flowchart in Figure 19 shows the steps necessary to control the AD7805/AD7809 following power-on. This flowchart details the necessary steps when using the AD7805/AD7809 in its 10-bit parallel mode. The first step is to write to the system control register to clear the SSTBY bit and to configure the part for 10-bit parallel mode and select the required coding scheme. The next step is to determine whether writing is to the Main or Sub DAC. This is achieved by writing to the channel control register. Other bits that need to be configured in the channel control register are MX1 and MX0 which determine the source of the VBIAS for the selected DAC and the channel STBY and channel CLR bits need to be configured as desired. Once writing to the channel control register is complete, data can now be written to the selected Main or Sub DAC. Parallel data can also be written to the device in 8+2 format to allow interface to 8-bit processors. Eight-bit mode is invoked by writing a one to the 10/8 bit in the system control register. When in the 8-bit mode the two unused data bits (DB1 and DB0) are used as hardware control bits and have the same timing characteristics as the address inputs. DB1 is a don’t care bit when writing to both the system and channel control registers; DB0 acts as the mode select bit and must be low to enable writing to the system control register and when high enables access to the channel control register. There are three methods of clearing the output of the Main DAC in these devices. The first is the external hardware clear. An active low logic signal applied to this pin clears all the DACs in the package. The voltage to which the output is cleared will depend on the input coding selected. The Main DAC outputs are cleared to midscale (VBIAS) in twos complement format and to the bottom of the transfer function (VBIAS/16) in offset binary format. The second way of clearing the main DACs is a software clear by asserting the SCLR bit in the system control register of the part. Writing a one to this bit clears all DACs in the package. The third method of clearing a DAC is to write a one to the CLR bit in the channel control register. This differs from that of the system control register in that only the selected DACs output is cleared. The channel clear requires an LDAC pulse to activate it. There is only one way of clearing the output of the Sub DAC and that is to use the external hardware clear. The output of the Sub DAC is cleared to midscale (0 V) regardless of the input coding being used. Figure 20 shows a simplified diagram of the implementation of the clear functions for a single DAC in the package. When in the 8-bit data write mode, DB1 acts as a low byte and high byte enable, when low data is written to the 8 MSBs of the DAC and when high data is written to the two LSBs. DB0 acts as a bit to select writing to the Main or Sub DAC. When DB0 is low, writing is to the Main DAC, and when high, writing is to the Sub DAC data register. In the 8+2 mode the channel control register does not have to be accessed to switch between writing to the Main and Sub DACs as in the 10-bit parallel REV. A WRITE TO MAIN DAC –15– EXT CLR SYSTEM CLR CLR SUB DAC CHANNEL CLR LDAC CLR A2 A1 ADDR DECODER MAIN DAC A0 ALL OTHER CIRCUITRY OMITTED FOR CLARITY Figure 20. CLR Functions for Main and Sub DACs AD7804/AD7805/AD7808/AD7809 POWER-DOWN AND STANDBY FUNCTIONS ANALOG OUTPUTS There are two distinct low power modes on the device, powerdown mode and standby mode. When in power-down mode all circuitry including the reference are put into low power mode and power dissipation from the package is at its minimum. The AD7804 and AD7805 DACs contain four independent voltage output Main DACs with 10-bit resolution. The AD7808 and AD7809 contain eight independent voltage output main DACs with 10-bit resolution. Each Main DAC has an associated Sub DAC with 8-bit resolution which can be used to offset the complete transfer function of the Main DAC around the VBIAS point. These DACs produce an output voltage in the form of VBIAS ± VSWING where VSWING is 15/16 of V BIAS. SYSTEM PD STANDBY INT REFERENCE CHANNEL STBY The digital input code to these DACs can be in twos complement or offset binary form. All DACs will be configured with the same input coding scheme which is programmed through the system control register. The default condition on power-up is for offset binary coding. STANDBY A2 A1 ADDR DECODER MAIN & SUB DAC A0 ONLY ONE DAC SHOWN FOR CLARITY Figure 21. Implementation of Power-Down and Standby Functions TWOS COMPLEMENT CODING Table VI shows the twos complement transfer function for the Main DAC. The standby functions allow either the selected DAC or all DACs in the package to be put into low power mode. The reference is not switched off when any of the standby functions are invoked. Table VI. Twos Complement Code Table for Main DAC The PD bit in the system control register is used to shut down the complete device. With a 0 in this position the reference and all DACs are put into low power mode. Writing a 1 to this bit puts the part in the normal operating mode. When in power-down mode the contents of all registers are retained and are valid when the device is taken out of power down. The SSTBY bit which resides in the system control register can be used to put all DACs and their associated linear circuitry into standby mode, the SSTBY function does not power down the reference. The STBY bit in the channel control register can be used to put a selected DAC and its associated linear circuitry into standby mode. Figure 18 shows a simplified diagram of how the power-down and standby functions are implemented for a single DAC in the package. LDAC FUNCTION LDAC input is a logic input that allows all DAC registers to be simultaneously updated with the contents of the DAC data registers. LDAC input has two operating modes, a synchronous mode and an asynchronous mode. The LDAC input condition is sampled on the sixteenth falling edge on the AD7804/AD7808 and is sampled on the rising edge of write on the AD7805/AD7809. If LDAC is low on the sixteenth falling clock edge or on the rising edge of WR, an automatic or synchronous update will take place. LDAC input can be tied permanently low or have timing similar to that of the data inputs to operate in the synchronous mode. Digital Input MSB . . . LSB Analog Output 0111111111 0111111110 VBIAS(1+1.875 × 511/1024) VBIAS(1+1.875 × 510/1024) 0000000001 0000000000 VBIAS(1+1.875 × 1/1024) VBIAS 1111111111 VBIAS(1–1.875 × 1/1024) 1000000001 1000000000 VBIAS(1–1.875 × 511/1024) VBIAS(1–1.875 × 512/1024) Figure 22 shows the Main DAC transfer function for twos complement coding. Any Main DAC output voltage can be expressed as: VOUT' = VBIAS + 1.875 × VBIAS × NA/1024 where NA is the decimal equivalent of the twos complement input code. NA ranges from –512 to +511. 31 16 VBIAS DAC OUTPUT VOLTAGE SYSTEM STBY If LDAC is high during the sample period, the AD7804/AD7805/ AD7808/AD7809 assumes an asynchronous update. When in the asynchronous mode, an LDAC setup time has to be allowed following the sixteenth falling clock edge or the rising edge of WR before the LDAC can be activated. VBIAS VBIAS 16 DAC INPUT CODE 200 201 3FF 000 001 1FE 1FF Figure 22. Main DAC Output Voltage vs. DAC Input Codes (HEX) for Twos Complement Coding –16– REV. A AD7804/AD7805/AD7808/AD7809 Configuring the AD7805/AD7809 for Twos Complement Coding Table VII shows the twos complement transfer function for the Sub DAC. Figure 23 shows the Sub DAC transfer function for twos complement coding. Any Sub DAC output voltage can be expressed as: Figure 24 shows a typical configuration for the AD7805/AD7809. The circuit can be used for either 3.3 V or 5 V operation and uses the internal VDD /2 as the reference for the part and 10-bit parallel interfacing is used. The following are the steps required to operate the Main DACs in this part. VOUT" = VBIAS/16 × (NB/256) where NB is the decimal equivalent of the twos complement input code. NB ranges from –128 to +127. +3.3V/+5V Table VII. Twos Complement Code Table for Sub DAC Digital Input MSB . . . LSB Analog Input 0.01mF AVDD DVDD COMP (VBIAS/16) × (127/256) (VBIAS/16) × (126/256) (VBIAS/16) × (1/256) 0 (–VBIAS/16) × (1/256) (–VBIAS/16) × (127/256) (–VBIAS/16) × (128/256) 01111111 01111111 00000001 00000000 11111111 10000001 10000000 0.1mF 0.1mF 10mF REFIN 0.01mF REFOUT A2* A0 AD7805/ AD7809 A1 VOUTA D9 DIGITAL INTERFACE VOUTB D0 MODE VOUTC CS 127 3VBIAS 256 16 WR VOUTD CLR DVDD DAC OUTPUT VOLTAGE LDAC DGND AGND *USED ON THE AD7809 ONLY 0 Figure 24. Typical Configuration for AD7805/AD7809 System Control Register Write: MODE = 0, address inputs (A2, A1, A0) are don’t cares. 128 3VBIAS 256 16 DAC INPUT CODE 80 Write 020 Hex 81 FF 00 01 7E Channel Control Register Write: 7F MODE = 0, address inputs (A2, A1, A0) select desired channel. Figure 23. Sub DAC Output Voltage vs. DAC Input Codes (HEX) for Twos Complement Coding Write 011 Hex The total output for a single channel when using twos complement coding is the sum of the voltage from the Main DAC and the Sub DAC. Internal VDD/2 selected as VBIAS for DAC, and any DAC data writes that follow are to the Main DAC. DAC Data Register Write: VOUT = VOUT' + VOUT" = VBIAS + 1.875 × VBIAS × (NA/1024) + VBIAS/16 × (NB/256) = VBIAS × (1 + 1.875 × NA/1024 + NB/4096) where NA ranges from –512 to +511 and NB ranges from –128 to +127. Figure 28 shows a pictorial view of the transfer function for any DAC. REV. A Configure part for 10-bit parallel, twos complement coding, normal operation –17– MODE = 1, address inputs (A2, A1, A0) select desired channel. Write XXX Hex With MODE = 1 all data writes are to the selected DAC. XXX is the required data. 200 Hex will give zero scale and 1FF Hex will give full scale from the DAC. AD7804/AD7805/AD7808/AD7809 Table VI and Figure 22 show the analog outputs available for the above configuration. The following is the procedure required if the complete transfer function needs to be offset around the VBIAS point. Table VII and Figure 23 show the analog output variations available from the Sub DAC. OFFSET BINARY CODING System Control Register Write: Digital Inputs MSB . . . LSB Analog Output 1111111111 1111111110 1000000001 1000000000 0111111111 0000000001 0000000000 VBIAS+1.875 × VBIAS(1023–512)/1024 VBIAS+1.875 × VBIAS(1022–512)/1024 VBIAS+1.875 × VBIAS/1024 VBIAS VBIAS+1.875 × VBIAS(511–512)/1024 VBIAS+1.875 × VBIAS(1–512)/1024 VBIAS/16 Table VIII shows the offset binary transfer function for the Main DAC. Table VIII. Offset Binary Code Table for Main DAC MODE = 0, address inputs (A2, A1, A0) are don’t cares. Write 020 Hex Configure part for 10-bit parallel, twos complement coding, normal operation Channel Control Register Write: MODE = 0, address inputs (A2, A1, A0) select desired channel. Write 091 Hex Internal VDD/2 selected as VBIAS for DAC, and any DAC data writes that follow are to the Sub DAC. NOTE: The span range is (30/16) × VBIAS = 1.875 × VBIAS DAC Data Register Write: 31 16 VBIAS MODE = 1, address inputs (A2, A1, A0) select desired channel. With MODE = 1 all data writes are to the selected DACs Sub DAC. XX is the required data. 7F Hex will give zero scale and 80 Hex will give full scale from the Sub DAC. DAC OUTPUT VOLTAGE Write XX Hex Channel Control Register Write: MODE = 0, address inputs (A2, A1, A0) select desired channel. Write 011 Hex Internal VDD/2 selected as VBIAS for DAC, and any DAC data writes that follow are to the Main DAC. VBIAS VBIAS 16 DAC Data Register Write: DAC INPUT CODE 000 001 1FF 200 201 3FE 3FF MODE = 1, address inputs (A2, A1, A0) select desired channel. Write XXX Hex With MODE = 1 all data writes are to the selected Main DAC. XXX is the required data. 1FF Hex will give zero scale and 200 Hex will give full scale from the DAC. Figure 25. Main DAC Output Voltage vs. DAC Input Codes (HEX) for Offset Binary Coding Figure 25 shows the Main DAC transfer function when offset binary coding is used. With offset binary coding selected the output voltage can be calculated as follows: VOUT' = VBIAS + 1.875 × VBIAS × ((NA-512)/1024) where NA is the decimal equivalent of the offset binary input code. NA ranges from 0 to 1023. Table IX shows the offset binary transfer function for the Sub DAC. Figure 26 shows the Sub DAC transfer function for offset binary coding. Any Sub DAC output voltage can be expressed as: VOUT" = VBIAS/16 × [(NB-128)/256] where NB is the decimal equivalent of the offset binary input code. NB ranges from 0 to 255. –18– REV. A AD7804/AD7805/AD7808/AD7809 Table IX. Offset Binary Code Table for Sub DAC Digital Input MSB . . . LSB Analog Output 11111111 11111110 10000001 10000000 01111111 00000001 00000000 VBIAS/16 × 127/256 VBIAS/16 × 126/256 VBIAS/16 × 1/256 0 –VBIAS/16 × 1/256 –VBIAS/16 × 127/256 –VBIAS/32 +3.3V/+5V 10mF 0.1mF 0.1mF 6.8kV 0.01mF AVDD DVDD COMP REFIN 0.01mF AD589 AD7804/ AD7808 FSIN SERIAL INTERFACE REFOUT SDIN VOUTA CLKIN VOUTB VOUTC 127 3 VBIAS 128 32 DVDD CLR VOUTD LDAC DAC OUTPUT VOLTAGE DGND 0 AGND Figure 27. Typical Configuration for AD7804/AD7808 Using an AD589 1.23 V Reference for the AD7804/AD7808 System Control Register Serial Write: Write 0060 Hex Mode bits select system control register and configure system for offset binary coding and normal operation. VBIAS 32 DAC INPUT CODE 00 01 7F 80 81 FE FF Channel Control Register Serial Write: Write 4210 Hex Figure 26. Sub DAC Output Voltage vs. DAC Input Codes (HEX) for Offset Binary Coding Configuring the AD7804/AD7808 for Offset Binary Coding Figure 27 shows a typical configuration for the AD7804/AD7808. This circuit can be used for both 3.3 V or 5 V operation and uses an external AD589 as the reference for the part and serial interfacing with offset binary coding is used. The MX1 and MX0 bits in the system control register have to be set to enable selection of the AD589 as the reference. The following are the steps required to operate the DACs in this part. Figures 4 to 7 show the contents of the registers on the AD7804/AD7808. Mode bits select channel control register, channel A is configured for operation with external reference. Main DAC Data Register Serial Write: Write 23FF Hex This 16-bit write selects writing to channel A and writes full scale to the Main DAC. Sub DAC Data Register Serial Write: Write A3FF Hex This 16-bit write selects writing to channel A Sub DAC and writes full scale to the Sub DAC. Table VIII and Figure 25 show the analog outputs available for the above configuration when writing to the Main DAC only while Table IX and Figure 26 show the contributions from the Sub DAC to the overall transfer function. The total output for a single channel when using offset binary coding is the sum of that from the Main DAC and the Sub DAC. VOUT = VOUT' + VOUT" = VBIAS + 1.875 × VBIAS × ((NA-512)/1024) + VBIAS/16 = × [(NB-128)/256] = VBIAS × (1 + 1.875 × ((NA-512)/1024) + (NB-128)/ 4096) where NA ranges from 0 to +1023 and NB ranges from 0 to +255. Figure 28 shows a pictorial view of the transfer function for any DAC channel. REV. A –19– AD7804/AD7805/AD7808/AD7809 MAIN DAC RANGE 2 1 32 32 32 VBIAS 3 VBIAS V 32 BIAS 31 32 VBIAS 32 62 VBIAS 33 32 VBIAS 61 32 VBIAS 32 VBIAS 63 32 VBIAS SUB DAC RANGE CHANNEL RANGE MIN CODE LOADED TO SUB DAC CHANNEL RANGE CENTER CODE LOADED TO SUB DAC CHANNEL RANGE MAX CODE LOADED TO SUB DAC Figure 28. Pictorial View of Transfer Function for Any DAC Channel Grounding and Layout Techniques To obtain optimum performance from the AD7804/AD7805/ AD7808/AD7809 care should be taken with the layout. Causes for concern would be feedthrough from the interface bus onto the analog circuitry particularly the reference pins and ground loops. The board should be designed such that the analog and digital sections are separated as much as possible. Ground planing and shielding should be used as much as possible. Digital and analog ground planes should only be joined in one place to avoid ground loops. The ideal place to join the ground planes is at the analog and digital ground pins of the DAC. Alternatively a star ground should be established on the board to which all other grounds are returned. Good decoupling is important in achieving optimum performance. All supplies, analog or digital, should be decoupled with 10 µF tantalum and 0.1 µF ceramic capacitors to their respective grounds, and should be as close as possible to the pins of the device. The main aim of the bypassing element is to maximize the charge stored in the bypass loop while simultaneously minimizing the inductance of this loop. Inductance in the loop acts as an impedance to high frequency transients and results in power supply spiking. By keeping the decoupling as close as possible to the device, the loop area is kept to a minimum thus reducing the possibility of power supply spikes. On the AD7805 the REFOUT pin of the device is located next to the DB9 of the data bus, to reduce the risk of digital feedthrough and noise being coupled from the digital section onto the reference, the REFOUT pin and any trace connected to it should be shielded with analog ground. To reduce the noise on this reference it should be decoupled with a 0.01 µF capacitor to analog ground, keeping the capacitor as close as possible to the device. The comp pin which is the output from the internal VDD/2 reference is located next to VOUTD on the DAC and is sensitive to noise pickup and feedthrough from the DAC output and thus should be shielded with analog ground to keep this reference point as quiet as possible. The comp pin should be decoupled both to AVDD and AGND with 1–10 nF ceramic capacitors. The external REFIN pin should also be shielded with analog ground from the digital pins located next to it. The same precautions should be taken with the reference pins on the AD7804/AD7808 to reduce the risk of noise pickup and feedthrough. Reference Settling Time With the REFOUT on the AD7804/AD7805/AD7808/AD7809 decoupled with a 0.01 µF capacitor to AGND it takes the REFOUT approximately 2 ms to fully settle after taking the device out of power down. When this capacitor is reduced to 1 nF the settling time reduces to 150 µs. The size of the capacitor required on the REFOUT depends to a large extent on the layout, if the REFOUT is well shielded with AGND the size of the capacitor can be reduced thus reducing the settling time for the reference. The internal VDD /2 reference provided at the comp pin when decoupled with a 1 nF capacitor to both AVDD and AGND has very fast settling time, typically less than 500 ns. –20– REV. A Typical Performance Characteristics–AD7804/AD7805/AD7808/AD7809 0.150000 2.0 0.125000 INTEGRAL LINEARITY – LSBs MAIN DAC = ZERO SCALE SUB DAC = MID SCALE VBIAS = VDD /2 TA = +258C 0.100000 VOUT – V VDD = 5.5V 0.075000 VDD = 3V 0.050000 0.025000 1.5 AVDD = DVDD = 5V VBIAS = VDD /2 1.0 TA = +258C SUB DAC LOADED WITH 1/2 SCALE 0.5 0.0 –0.5 –1.0 –1.5 SOURCE CURRENT 0.000000 –0.5 –0.4 –0.3 –0.2 SINK CURRENT –0.1 0.0 0.1 CURRENT – mA 0.2 0.3 0.4 –2.0 0.5 Figure 29. Sink and Source Current with Zero Scale Loaded to DAC. VDD = 5 V and VDD = 3 V 100 200 300 400 500 600 700 DAC CODE 800 900 1023 Figure 32. Integral Linearity with 5 V Operation 5.200000 2.0 VDD = 5.5V MAIN DAC = FULL SCALE SUB DAC = MID SCALE VBIAS = VDD /2 TA = +258C INTEGRAL LINEARITY – LSBs 5.180000 0 RL = VOUT – V 5.160000 RL = 2kV 5.140000 5.120000 1.5 AVDD = DVDD = 3V VBIAS = VDD /2 1.0 TA = +258C SUB DAC LOADED WITH 1/2 SCALE 0.5 0.0 –0.5 –1.0 –1.5 SOURCE CURRENT SINK CURRENT 5.100000 –6.0 –4.0 –2.0 0.0 2.0 CURRENT – mA 4.0 –2.0 6.0 Figure 30. Sink and Source Current at Full Scale with VDD = 5 V 200 300 400 500 600 700 DAC CODE 800 900 1023 1.225 VDD = 3V MAIN DAC = FULL SCALE SUB DAC = MID SCALE VBIAS = VDD /2 TA = +258C VDD = 3V RL = 2kV||100pF CODE CHANGE 011111 1111 TO 100000 0000 TA = +258C 1.224 1.223 DAC OUTPUT RL = VOUT – V 100 Figure 33. Integral Linearity with 3 V Operation 2.850000 2.830000 0 2.810000 RL = 2kV 2.790000 1.222 1.221 1.220 1.219 1.218 2.770000 SOURCE CURRENT 2.750000 –6.0 –4.0 –2.0 1.217 SINK CURRENT 0.0 2.0 CURRENT – mA 4.0 1.216 6.0 Figure 31. Sink and Source Current at Full Scale with VDD = 3 V REV. A 0 20 40 60 80 100 ns 120 140 160 180 200 Figure 34. Digital-to-Analog Glitch Impulse –21– AD7804/AD7805/AD7808/AD7809 MICROPROCESSOR INTERFACING AD7804/AD7808–ADSP-2101/ADSP-2103 Interface Figure 35 shows a serial interface between the AD7804/AD7808 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP2103 should be set up to operate in the SPORT Transmit Alternate Framing Mode. The ADSP-2101/ADSP-2103 SPORT is programmed through the SPORT control register and should be configured as follows: Internal Clock Operation, Active Low Framing, 16-bit Word Length. Transmission is initiated by writing a word to the TX register after the SPORT has been enabled. The data is clocked out on each rising edge of the serial clock and clocked into the AD7804/AD7808 on the falling edge of the SCLK. ADSP-2101/ ADSP-2103* +5V AD7804*/ AD7808 CLR FO LDAC TFS FSIN DT SDIN SCLK AD7804*/ AD7808 68HC11/68L11* CLKIN *ADDITIONAL PINS OMITTED FOR CLARITY Figure 35. ADSP-2101/ADSP-2103 Interface AD7804/AD7808–68HC11/68L11 Interface Figure 36 shows a serial interface between the AD7804/AD7808 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/ 68L11 drives the CLKIN of the AD7804/AD7808, while the MOSI output drives the serial data line of the DAC. The FSIN signal is derived from a port line (PC7). The setup conditions for correct operation of this interface are as follows: the 68HC11/68L11 should be configured so that its CPOL bit is a 0 and its CPHA bit is a 1. When data is being transmitted to the DAC the FSIN line is taken low (PC7). When the 68HC11/ 68L11 is configured as above, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. In order to load data to the AD7804/AD7808, PC7 is left low after the first eight bits are transferred and a second serial write operation is performed to the DAC and then PC7 is taken high at the end of this procedure. In the diagram shown LDAC and CLR are also controlled from the bit programmable lines of the 68HC11/68L11. The user can bring LDAC low after every two bytes have been transmitted to update that particular DAC which has been programmed or alternatively it is possible to wait until all the input registers have been loaded before updating takes place. PC5 CLR PC6 LDAC PC7 FSIN SCK CLKIN MOSI SDIN *ADDITIONAL PINS OMITTED FOR CLARITY Figure 36. AD7804/AD7808–68HC11/68L11 Interface AD7804/AD7808–80C51/80L51 Interface Figure 37 shows a serial interface between the AD7804/AD7808 and the 80C51/80L51 microcontroller. The setup for the interface is as follows, TXD of the 80C51/80L51 drives CLKIN of the AD7804/AD7808 while RXD drives the serial data line of the part. The FSIN signal is again derived from a bit programmable pin on the port in this case port line P3.3 is used. When data is to be transmitted to the part, P3.3 is taken low. Data on RXD is valid on the falling edge of TXD. The 80C51/80L51 transmits data in eight bit bytes thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted and a second write cycle is initiated to transmit the second byte of data, P3.3 is taken high following the completion of this cycle. The 80C51/80L51 outputs the serial data in a format which has the LSB first. The AD7804/AD7808 requires its data with the MSB as the first bit received. The 80C51/80L51 transmit routine should take this into account. In the diagram shown LDAC and CLR are also controlled from the bit programmable lines of the 80C51/80L51 port. The user can bring LDAC low after every two bytes have been transmitted to update that particular DAC which has been programmed or alternatively it is possible to wait until all the input registers have been loaded before updating takes place. –22– AD7804*/ AD7808 80C51/80L51* P3.5 CLR P3.4 LDAC P3.3 FSIN TXD SCLK RXD SDIN *ADDITIONAL PINS OMITTED FOR CLARITY Figure 37. AD7804/AD7808–80C51/80L51 Interface REV. A AD7804/AD7805/AD7808/AD7809 AD7805/AD7809–ADSP-2101 Interface Figure 38 shows a parallel interface between the AD7805/AD7809 and the ADSP-2101/ADSP-2103 digital signal processor. Fast interface timing allows the AD7805/AD7809 interface directly to the DSP. In this interface an external timer is used to update the DACs. TIMER DMA14 ADDRESS BUS DMA0 ADDR DECODE DMS EN A0 A1 LDAC A2** OUT DAC, D. DAC = Decoded DAC Address. D = Data Memory Address. Certain applications may require that the updating of the DAC latch be controlled by the microprocessor rather than the external timer. One option as shown in the TMS32020 interface is to decode the LDAC from the address bus so that a write operation to the DAC latch (at a separate address to the input latch) updates the output. MODE AD7805/AD7809–8051/8088 Interface CS AD7805*/ AD7809 ADSP-2101*/ ADSP-2103* Again fast interface timing allows the AD7805/AD7809 interface directly to the processor. Data is loaded to the AD7805/ AD7809 input latch using the following instruction: Figure 40 shows a parallel interface between the AD7805/ AD7809 and the 8051/8088 processors. WR WR DB9 A15 ADDRESS BUS DB0 A8 DMD15 ADDR DECODE DATA BUS DMD0 PSEN OR DEN **ADDITIONAL PINS OMITTED FOR CLARITY **A2 CONTAINED ON THE AD7809 ONLY WR Figure 38. AD7805/AD7809–ADSP-2101/ADSP-2103 Interface ALE AD7805*/ AD7809 OCTAL LATCH DB9 AD7 AD0 MR0 = ADSP-2101 MR0 Register. Figure 40. AD7805/AD7809–8051/8088 Interface AD7805/AD7809–TMS32020 Interface Figure 39 shows a parallel interface between the AD7805/AD7809 and the TMS32020 processor. A15 ADDRESS BUS A0 ADDR DECODE EN A0 A1 A2** CS AD7805*/ AD7809 TMS32020 LDAC STRB R/W ADDRESS/DATA BUS **ADDITIONAL PINS OMITTED FOR CLARITY **A2 CONTAINED ON THE AD7809 ONLY DAC = Decoded DAC Address. WR DB9 DB0 DATA BUS D0 **ADDITIONAL PINS OMITTED FOR CLARITY **A2 CONTAINED ON THE AD7809 ONLY Figure 39. AD7805/AD7809–TMS32020 Interface REV. A MODE LDAC DB0 DM(DAC) = MR0, D15 A1 A2** WR 8051/8088 Data is loaded to the AD7805/AD7809 input register using the following instruction: IS EN A0 CS –23– AD7804/AD7805/AD7808/AD7809 APPLICATIONS Opto-Isolated Interface for Process Control Applications AD7808 CLKIN FSIN The AD7804/AD7808 has a versatile serial three-wire serial interface making it ideal for generating accurate voltages in process control and industrial applications. Due to noise, safety requirements, or distance, it may be necessary to isolate the AD7804/AD7808 from the controller. This can easily be achieved by using opto-isolators which will provide isolation in excess of 3 kV. The serial loading structure of the AD7804/ AD7808 makes it ideally suited for use in opto-isolated applications. Figure 41 shows an opto-isolated interface to the AD7804/AD7808 where SDIN, CLKIN and FSIN are driven from optocouplers. LDAC is hardwired low to reduce the number of interface lines and this ensures that each DAC is updated following the sixteenth serial clock of a write cycle. SDIN SDIN VDD CLKIN LDAC VCC 1Y0 AD7808 1G ENABLE FSIN 1Y1 1A SDIN 1Y2 CODED ADDRESS CLKIN 1B LDAC 1Y3 74HC139 AD7808 DGND FSIN SDIN POWER CLKIN +5V REGULATOR 10mF AD7808 VDD FSIN AVDD 10kV CLKIN VDD DVDD SDIN REFOUT CLKIN CLKIN AD7804/ AD7808 10kV FSIN REFIN Figure 42. Decoding Multiple AD7808s Using the FSIN Pin VOUTA AD7805 As a Digitally Programmable Window Detector VOUTB VDD 10kV A digitally programmable upper/lower limit detector using two DACs in the AD7805 is shown in Figure 43. The upper and lower limits for the test are loaded to DACs A and B that in turn set the limits on the CMP04. If a signal at the VIN input is not within the programmed window an LED will indicate the fail condition. Only one limit detector is shown below but can easily be adapted for a dual channel system by using the extra DACs on the AD7805 and the two unused comparators on the CMP04. VOUTC SDIN VDD1 VOUTD CLR LDAC DGND LDAC 1 TO 10nF FSIN DATA LDAC 0.1mF AGND Figure 41. AD7804/AD7808 Opto-Isolated Interface +5V 10mF 0.1mF Decoding Multiple AD7808s The FSIN pin on the AD7808s can be used in applications to decode a number of DACs. In this application all DACs in the system receive the same serial clock and serial data, but only the FSIN to one of the DACs will be active at any one time allowing access to eight channels in this thirty-two channel system. The 74HC139 is used as a 2- to 4-line decoder to address any of the DACs in the system. To prevent timing errors from occurring the enable input should be brought to its inactive state while the coded address inputs are changing state. Figure 42 shows a system decoding multiple AD7808s in a multichannel system. 0.01mF AVDD DVDD COMP 1kV PASS 1/2 CMP04 VOUTA 0.01mF PASS/ FAIL AD7805 D9 DVDD 1kV FAIL VIN D0 VOUTB MODE CS WR VOUTC 1/6 74HC05 VOUTD CLR LDAC DGND AGND Figure 43. Digitally Programmable Window Detector –24– REV. A AD7804/AD7805/AD7808/AD7809 Low Cost, Two-Channel Mixer Using AD7805, SSM2164 and OP275 Dual External Reference Input Capability It is possible to operate the AD7804/AD7805/AD7808/AD7809 with two externally applied references. Figure 45 shows the connections for the AD7804. Reference one, the AD589, is connected to the REFIN pin of the part; the second reference, the AD780, is used to overdrive the internal VDD/2 reference which is provided at the COMP pin of the device. With the circuit shown in Figure 45 it is possible to configure two of the channels for operation with the AD780 2.5 V reference and the other two with the AD589 1.23 V reference. The channel control register allows the user to select the reference for the individual channels. The SSM2164 is a quad voltage controlled amplifier (VCA) with 120 dB of gain control range. Each VCA in the package is a current in, current out device with a –33 mV/dB voltage control input port. Figure 44 shows a basic application circuit which can be used to implement a low cost stereo, two channel mixer. A 30 kΩ resistor converts the input voltage to an input current for the VCA. The 500 Ω resistor and 560 pF capacitor on the input are added to ensure stable operation of the SSM2164. The IOUT pin of the SSM2164 should be maintained at virtual ground and thus the OP275 is operated in its inverting mode. Its wide bandwidth, high slew rate and low power make it ideal for a current to voltage converter. A 30 kΩ feedback resistor is chosen to match the input resistor and thus give unity gain for a zero volt control voltage input. The 100 pF capacitors reduce high frequency noise and can be increased to reduce the low pass cutoff frequency for further noise reduction. The AD7805 in the circuit is used to control the attenuation of the VCA, this application circuit only gives attenuation. The voltage output from the AD7805 provides a low impedance drive to the SSM2164 so attenuation can be controlled accurately. With a 5 V VDD and a VBIAS of VDD/2 the AD7805 has an LSB size of approximately 4.5 mV. Therefore, the attenuation can be controlled with a resolution of 0.136 dB/bit and thus 750 codes are required to provide the full 100 dB of attenuation. +5V 10mF 0.1mF 0.1mF 6.8kV VIN VO AD780 GND AVDD DVDD COMP REFIN 0.01mF AD589 AD7804 FSIN SERIAL INTERFACE SDIN CLKIN DVDD REFOUT VOUTA VOUTB CLR VOUTC LDAC VOUTD DGND AGND Figure 45. Two Externally Applied References +5V VIN2 10mF 0.1mF 30kV VIN1 30kV 100pF 0.01mF AVDD DVDD COMP 560pF 560pF 0.01mF MODE DVDD 100pF VC3 30kV IN4 +15V 1/2 OP275 VC4 VOUT D AGND –15V IN3 CLR DGND VOUT A VC2 VOUT B VOUTC LDAC SSM2164 500V 500V 560pF 560pF 30kV –15V 30kV Figure 44. Low Cost, Two-Channel Mixer –25– VOUT B –V VIN3 VIN4 REV. A 1/2 OP275 IN2 CS WR +15V VC1 VOUT A D0 +V 30kV IN1 AD7805 D9 +15V 500V 500V –15V AD7804/AD7805/AD7808/AD7809 PAGE INDEX (AD7804/AD7808 SERIAL INTERFACE PART) PAGE INDEX (AD7805/AD7809 PARALLEL INTERFACE PART) Topic Page No. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3 Timing Information Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . 6 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Terminology Relative Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Differential Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bias Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Zero-Scale Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Digital-to-Analog Glitch Impulse . . . . . . . . . . . . . . . . . . . . 9 Digital Feedthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Digital Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Analog Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power Supply Rejection Ratio . . . . . . . . . . . . . . . . . . . . . . 9 Interface Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Channel Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 11 SUB DAC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power-Up Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Clear Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power-Down and Standby Functions . . . . . . . . . . . . . . . . . 16 LDAC Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Transfer Functions Pictorial View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Twos Complement (Main DAC) . . . . . . . . . . . . . . . . . . . 16 Twos Complement (Sub DAC) . . . . . . . . . . . . . . . . . . . . 17 Complete Channel Transfer Function . . . . . . . . . . . . . . . 17 Offset Binary (Main DAC) . . . . . . . . . . . . . . . . . . . . . . . . 18 Offset Binary (Sub DAC) . . . . . . . . . . . . . . . . . . . . . . . . . 19 Grounding and Layout Techniques . . . . . . . . . . . . . . . . . . . 20 Reference Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . 21 Microprocessor Interfacing ADSP-2101/ADSP-2103 . . . . . . . . . . . . . . . . . . . . . . . . . 22 68HC11/68L11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 80C51/80L51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Applications Opto-Isolated Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Decoding Multiple ICs . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27, 28 Topic Page No. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3 Timing Information Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . 6 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Terminology Relative Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Differential Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bias Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Zero-Scale Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Digital-to-Analog Glitch Impulse . . . . . . . . . . . . . . . . . . . 9 Digital Feedthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Digital Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Analog Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power Supply Rejection Ratio . . . . . . . . . . . . . . . . . . . . . 9 Interface Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . 14 Channel Control Register . . . . . . . . . . . . . . . . . . . . . . . . 14 Power-Up Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Clear Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power-Down and Standby Functions . . . . . . . . . . . . . . . . 16 LDAC Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Transfer Functions Pictorial View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Twos Complement (Main DAC) . . . . . . . . . . . . . . . . . . 16 Twos Complement (Sub DAC) . . . . . . . . . . . . . . . . . . . 17 Complete Channel Transfer Function . . . . . . . . . . . . . . 17 Offset Binary (Main DAC) . . . . . . . . . . . . . . . . . . . . . . . 18 Offset Binary (Sub DAC) . . . . . . . . . . . . . . . . . . . . . . . . 19 Grounding and Layout Techniques . . . . . . . . . . . . . . . . . . 20 Reference Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Typical Performance Characteristics . . . . . . . . . . . . . . . . . 21 Microprocessor Interfacing ADSP-2101/ADSP-2103 . . . . . . . . . . . . . . . . . . . . . . . . 23 TMS32020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8051/8088 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Applications Programmable Window Detector . . . . . . . . . . . . . . . . . . 24 Low Cost Two-Channel Mixer . . . . . . . . . . . . . . . . . . . 25 Dual External Reference Input Capability . . . . . . . . . . . 25 Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 27, 28 –26– REV. A AD7804/AD7805/AD7808/AD7809 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic DIP (N-28) Plastic DIP (N-16) 28 0.840 (21.33) 0.745 (18.93) 15 0.580 (14.73) 0.485 (12.32) PIN 1 1 14 1.565 (39.70) 1.380 (35.10) 9 1 8 0.210 (5.33) MAX 0.150 (3.81) MIN 0.200 (5.05) 0.125 (3.18) 0.100 (2.54) BSC 0.070 (1.77) MAX 0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) PIN 1 0.060 (1.52) 0.015 (0.38) 0.250 (6.35) MAX 0.022 (0.558) 0.014 (0.356) 16 0.130 (3.30) MIN 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) SEATING PLANE 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.070 (1.77) SEATING 0.045 (1.15) PLANE 0.100 (2.54) BSC 0.625 (15.87) 0.600 (15.24) 0.195 (4.95) 0.125 (3.18) SOIC (R-16) 0.015 (0.381) 0.008 (0.204) 28 14 1 0.1043 (2.65) 0.0926 (2.35) 0.7125 (18.10) 0.6969 (17.70) 8 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) BSC 0.0125 (0.32) 0.0091 (0.23) 0.0118 (0.30) 0.0040 (0.10) 0.0500 (1.27) BSC 0.0291 (0.74) x 45 ° 0.0098 (0.25) 8° 0° 0.0500 (1.27) 0.0157 (0.40) SSOP (RS-28) 28 15 0.212 (5.38) 0.205 (5.207) 0.311 (7.9) 0.301 (7.64) PIN 1 1 14 0.407 (10.34) 0.397 (10.08) REV. A 1 PIN 1 0.4193 (10.65) 0.3937 (10.00) PIN 1 0.008 (0.203) 0.002 (0.050) 9 15 0.2992 (7.60) 0.2914 (7.40) 0.0118 (0.30) 0.0040 (0.10) 16 0.07 (1.78) 0.066 (1.67) 8° 0° 0.009 (0.229) 0.005 (0.127) 1. LEAD NO. 1 IDENTIFIED BY A DOT. 2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS 0.0256 (0.65) BSC 0.015 (0.38) 0.010 (0.25) 0.03 (0.762) 0.022 (0.558) –27– 0.4193 (10.65) 0.3937 (10.00) SOIC (R-28) 0.2992 (7.60) 0.2914 (7.40) 0.4133 (10.50) 0.3977 (10.00) 0.1043 (2.65) 0.0926 (2.35) 0.0291 (0.74) x 45° 0.0098 (0.25) 8° 0.0192 (0.49) 0° SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) AD7804/AD7805/AD7808/AD7809 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). TQFP (SU-44) 0.047 (1.20) MAX 13 24 0.018 (0.45) 12 1 0.472 (12.00) SQ 0.030 (0.75) 0.280 (7.11) 0.240 (6.10) PIN 1 33 23 34 1.275 (32.30) 1.125 (28.60) 0.015 (0.38) MIN 0.210 (5.33) MAX 22 SEATING PLANE 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.160 (4.06) 0.115 (2.92) 0.022 (0.558) 0.014 (0.356) 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) BSC 0.394 (10.0) SQ TOP VIEW (PINS DOWN) 0.130 (3.30) MIN 0.015 (0.381) 0.008 (0.203) SEATING PLANE 44 C2107A–1–12/98 Plastic DIP (N-24) 12 1 11 0.006 (0.15) 0.002 (0.05) 0.04134 (1.05) 0.0374 (0.95) 0.031 (0.80) BSC 0.018 (0.45) 0.012 (0.30) SOIC (R-24) 0.614 (15.6) 0.598 (15.2) 24 13 0.299 (7.6) 0.419 (10.65) 0.291 (7.4) 0.394 (10.00) 1 12 0.012 (0.3) 0.004 (0.1) 0.0500 (1.27) BSC 0.104 (2.65) 0.093 (2.35) 0.03 (0.75) 0.01 (0.25) 88 0.019 (0.49) SEATING 0.013 (0.32) 08 0.014 (0.35) PLANE 0.009 (0.25) 0.0500 (1.27) 0.0157 (0.40) PRINTED IN U.S.A. PIN 1 –28– REV. A