AD7837ANQ

a FEATURES Two 12-Bit MDACs with Output Amplifiers 4-Quadrant Multiplication Space-Saving 0.3" 24-Lead DIP and 24-Terminal , SOIC Package Parallel Loading Structure: AD7847 (8 + 4) Loading Structure: AD7837 APPLICATIONS Automatic Test Equipment Function Generation Waveform Reconstruction Programmable Power Supplies Synchro Applications LC2MOS Complete, Dual 12-Bit MDACs AD7837/AD7847 FUNCTIONAL BLOCK DIAGRAMS VDD MS INPUT LATCH LS INPUT LATCH 8 12 RFBA VOUTA AGNDA RFBB AD7837 4 DAC LATCH A VREFA VREFB DB0 DB7 LDAC CS WR A0 CONTROL LOGIC 4 DAC A DAC B 12 DAC LATCH B 8 LS INPUT LATCH MS INPUT LATCH VOUTB AGNDB GENERAL DESCRIPTION A1 The AD7837/AD7847 is a complete, dual, 12-bit multiplying digital-to-analog converter with output amplifiers on a monolithic CMOS chip. No external user trims are required to achieve full specified performance. Both parts are microprocessor compatible, with high speed data latches and interface logic. The AD7847 accepts 12-bit parallel data which is loaded into the respective DAC latch using the WR input and a separate Chip Select input for each DAC. The AD7837 has a double-buffered 8-bit bus interface structure with data loaded to the respective input latch in two write operations. An asynchronous LDAC signal on the AD7837 updates the DAC latches and analog outputs. The output amplifiers are capable of developing ± 10 V across a 2 kΩ load. They are internally compensated with low input offset voltage due to laser trimming at wafer level. The amplifier feedback resistors are internally connected to VOUT on the AD7847. The AD7837/AD7847 is fabricated in Linear Compatible CMOS (LC2MOS), an advanced, mixed technology process that combines precision bipolar circuits with low power CMOS logic. A novel low leakage configuration (U.S. Patent No. 4,590,456) ensures low offset errors over the specified temperature range. DGND VSS VDD AD7847 VREFA VREFB DB0 DB11 WR CSA CSB CONTROL LOGIC DAC LATCH A DAC A VOUTA AGNDA DAC B VOUTB AGNDB DAC LATCH B DGND VSS PRODUCT HIGHLIGHTS 1. The AD7837/AD7847 is a dual, 12-bit, voltage-out MDAC on a single chip. This single chip design offers considerable space saving and increased reliability over multichip designs. 2. The AD7837 and the AD7847 provide a fast versatile interface to 8-bit or 16-bit data bus structures. R EV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 (V = V 5%, V AD7837/AD7847–SPECIFICATIONS1D7837]. +15specifications T= –15 TV = O V. V = V = +10 V, R = 2 k , C = 100 pF [V connected to R A All to DD SS REFA REFB L L OUT FB MIN 5%, AGNDA = AGNDB = DGND MAX unless otherwise noted.) Parameter STATIC PERFORMANCE Resolution Relative Accuracy2 Differential Nonlinearity2 Zero Code Offset Error2 @ +25°C TMIN to TMAX Gain Error2 @ +25°C TMIN to TMAX REFERENCE INPUTS VREF Input Resistance VREFA, VREFB Resistance Matching DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current Input Capacitance3 ANALOG OUTPUTS DC Output Impedance Short Circuit Current POWER REQUIREMENTS4 VDD Range VSS Range Power Supply Rejection ∆Gain/∆VDD ∆Gain/∆VSS IDD ISS AC CHARACTERISTICS2, 3 Voltage Output Settling Time A Version B Version S Version Units Test Conditions/Comments 12 ±1 ±1 ±2 ±4 ±4 ±5 12 ± 1/2 ±1 ±2 ±3 ±2 ±3 12 ±1 ±1 ±2 ±4 ±4 ±5 Bits LSB max LSB max mV max mV max LSB max LSB max Guaranteed Monotonic DAC Latch Loaded with All 0s Temperature Coefficient = ± 5 µV/°C typ DAC Latch Loaded with All 1s Temperature Coefficient = ± 2 ppm of FSR/°C typ Typical Input Resistance = 10 kΩ Typically ± 0.25% 8/13 ±2 2.4 0.8 ±1 8 8/13 ±2 2.4 0.8 ±1 8 8/13 ±2 2.4 0.8 ±1 8 kΩ min/max % max V min V max µA max pF max Ω typ mA typ Digital Inputs at 0 V and VDD 0.2 11 0.2 11 0.2 11 VOUT Connected to AGND 14.25/15.75 –14.25/–15.75 ± 0.01 ± 0.01 8 6 14.25/15.75 14.25/15.75 –14.25/–15.75 –14.25/–15.75 ± 0.01 ± 0.01 8 6 ± 0.01 ± 0.01 8 6 V min/max V min/max % per % max % per % max mA max mA max VDD = 15 V ± 5%, VREF = –10 V VSS = –15 V ± 5%, VREF = +10 V Outputs Unloaded. Inputs at Thresholds. Typically 5 mA Outputs Unloaded. Inputs at Thresholds. Typically 3 mA Settling Time to Within ± 1/2 LSB of Final Value. DAC Latch Alternately Loaded with All 0s and All 1s 1 LSB Change Around Major Carry VREFA = 20 V p-p, 10 kHz Sine Wave. DAC Latches Loaded with All 0s VREFB = 20 V p-p, 10 kHz Sine Wave. DAC Latches Loaded with All 0s VREF = 20 V p-p, 10 kHz Sine Wave. DAC Latch Loaded with All 0s VREF = 100 mV p-p Sine Wave. DAC Latch Loaded with All 1s VREF = 20 V p-p Sine Wave. DAC Latch Loaded with All 1s VREF = 6 V rms, 1 kHz. DAC Latch Loaded with All 1s Code Transition from All 0s to All 1s and Vice Versa See Typical Performance Graphs Amplifier Noise and Johnson Noise of RFB 3 5 11 10 –95 –95 –90 750 175 –88 1 3 5 11 10 –95 –95 –90 750 175 –88 1 3 5 11 10 –95 –95 –90 750 175 –88 1 µs typ µs max V/µs typ nV secs typ dB typ dB typ dB typ kHz typ kHz typ dB typ nV secs typ Slew Rate Digital-to-Analog Glitch Impulse Channel-to-Channel Isolation VREFA to VOUTB VREFB to VOUTA Multiplying Feedthrough Error Unity Gain Small Signal BW Full Power BW Total Harmonic Distortion Digital Crosstalk Output Noise Voltage @ +25°C (0.1 Hz to 10 Hz) Digital Feedthrough 2 1 2 1 2 1 µV rms typ nV secs typ NOTES 1 Temperature ranges are as follows: A, B Versions, –40 °C to +85°C; S Version, –55°C to +125°C. 2 See Terminology. 3 Guaranteed by design and characterization, not production tested. 4 The Devices are functional with V DD/VSS = ± 12 V (See typical performance graphs.). Specifications subject to change without notice. –2– REV. C AD7837/AD7847 TIMING CHARACTERISTICS1, 2, 3 Parameter t1 t2 t3 t4 t5 t6 4 t7 4 t8 4 0 0 30 80 0 0 0 50 (VDD = +15 V 5%, VSS = –15 V Unit ns min ns min ns min ns min ns min ns min ns min ns min 5%, AGNDA = AGNDB = DGND = O V) Conditions/Comments CS to WR Setup Time CS to WR Hold Time WR Pulsewidth Data Valid to WR Setup Time Data Valid to WR Hold Time Address to WR Setup Time Address to WR Hold Time LDAC Pulsewidth Limit at TMIN, TMAX (All Versions) NOTES 1 All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 See Figures 3 and 5. 3 Guaranteed by design and characterization, not production tested. 4 AD7837 only. ABSOLUTE MAXIMUM RATINGS * (TA = +25°C unless otherwise noted) ORDERING GUIDE VDD to DGND, AGNDA, AGNDB . . . . . . . –0.3 V to +17 V VSS1 to DGND, AGNDA, AGNDB . . . . . . . +0.3 V to –17 V VREFA, VREFB to AGNDA, AGNDB . . . . . . . . . . . . . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V AGNDA, AGNDB to DGND . . . . . . . –0.3 V to VDD + 0.3 V VOUTA2, VOUTB2 to AGNDA, AGNDB . . . . . . . . . . . . . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V RFBA3, RFBB3 to AGNDA, AGNDB . . . . . . . . . . . . . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V Digital Inputs to DGND . . . . . . . . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range Commercial/Industrial (A, B Versions) . . . –40°C to +85°C Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300°C Power Dissipation (Any Package) to +75°C . . . . . . 1000 mW Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C NOTES 1 If VSS is open circuited with V DD and either AGND applied, the V SS pin will float positive, exceeding the Absolute Maximum Ratings. If this possibility exists, a Schottky diode connected between V SS and AGND (cathode to AGND) ensures the Maximum Ratings will be observed. 2 The outputs may be shorted to voltages in this range provided the power dissipation of the package is not exceeded. 3 AD7837 only. *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one Absolute Maximum Rating may be applied at any one time. Model1 AD7837AN AD7837BN AD7837AR AD7837BR AD7837AQ AD7837BQ AD7837SQ AD7847AN AD7847BN AD7847AR AD7847BR AD7847AQ AD7847BQ AD7847SQ Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –55°C to +125°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –55°C to +125°C Relative Accuracy ± 1 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1 LSB ± 1 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1 LSB Package Option2 N-24 N-24 R-24 R-24 Q-24 Q-24 Q-24 N-24 N-24 R-24 R-24 Q-24 Q-24 Q-24 NOTES 1 To order MIL-STD-883, Class B processed parts, add /883B to part number. 2 N = Plastic DIP; Q = Cerdip; R = SOIC. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although these devices feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. C –3– AD7837/AD7847 TERMINOLOGY Relative Accuracy (Linearity) Channel-to-Channel Isolation Relative accuracy, or endpoint linearity, is a measure of the maximum deviation of the DAC transfer function from a straight line passing through the endpoints. It is measured after allowing for zero and full-scale errors and is expressed in LSBs or as a percentage of full-scale reading. Differential Nonlinearity This is an ac error due to capacitive feedthrough from the VREF input on one DAC to VOUT on the other DAC. It is measured with the DAC latches loaded with all 0s. Digital Feedthrough Digital feedthrough is the glitch impulse injected from the digital inputs to the analog output when the data inputs change state, but the data in the DAC latches is not changed. For the AD7837, it is measured with LDAC held high. For the AD7847, it is measured with CSA and CSB held high. Digital Crosstalk Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB or less over the operating temperature range ensures monotonicity. Zero Code Offset Error Zero code offset error is the error in output voltage from VOUTA or VOUTB with all 0s loaded into the DAC latches. It is due to a combination of the DAC leakage current and offset errors in the output amplifier. Gain Error Digital crosstalk is the glitch impulse transferred to the output of one converter due to a change in digital code on the DAC latch of the other converter. It is specified in nV secs. Digital-to-Analog Glitch Impulse Gain error is a measure of the output error between an ideal DAC and the actual device output with all 1s loaded. It does not include offset error. Total Harmonic Distortion This is the voltage spike that appears at the output of the DAC when the digital code changes, before the output settles to its final value. The energy in the glitch is specified in nV secs and is measured for a 1 LSB change around the major carry transition (0111 1111 1111 to 1000 0000 0000 and vice versa). Unity Gain Small Signal Bandwidth This is the ratio of the root-mean-square (rms) sum of the harmonics to the fundamental, expressed in dBs. Multiplying Feedthrough Error This is the frequency at which the small signal voltage output from the output amplifier is 3 dB below its dc level. It is measured with the DAC latch loaded with all 1s. Full Power Bandwidth This is an ac error due to capacitive feedthrough from the VREF input to VOUT of the same DAC when the DAC latch is loaded with all 0s. This is the maximum frequency for which a sinusoidal input signal will produce full output at rated load with a distortion less than 3%. It is measured with the DAC latch loaded with all 1s. AD7837 PIN FUNCTION DESCRIPTION (DIP AND SOIC PIN NUMBERS) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17–20 21–24 Mnemonic CS RFBA VREFA VOUTA AGNDA VDD VSS AGNDB VOUTB VREFB DGND RFBB WR LDAC A1 A0 DB7–DB4 DB3–DB0 Description Chip Select. Active low logic input. The device is selected when this input is active. Amplifier Feedback Resistor for DAC A. Reference Input Voltage for DAC A. This may be an ac or dc signal. Analog Output Voltage from DAC A. Analog Ground for DAC A. Positive Power Supply. Negative Power Supply. Analog Ground for DAC B. Analog Output Voltage from DAC B. Reference Input Voltage for DAC B. This may be an ac or dc signal. Digital Ground. Ground reference for digital circuitry. Amplifier Feedback Resistor for DAC B. Write Input. WR is an active low logic input which is used in conjunction with CS, A0 and A1 to write data to the input latches. DAC Update Logic Input. Data is transferred from the input latches to the DAC latches when LDAC is taken low. Address Input. Most significant address input for input latches (see Table II). Address Input. Least significant address input for input latches (see Table II). Data Bit 7 to Data Bit 4. Data Bit 3 to Data Bit 0 (LSB) or Data Bit 11 (MSB) to Data Bit 8. –4– REV. C AD7837/AD7847 AD7847 PIN FUNCTION DESCRIPTION (DIP AND SOIC PIN NUMBERS) Pin 11 12 13 14 15 16 17 18 19 10 11 12 13 14–24 Mnemonic CSA CSB VREFA VOUTA AGNDA VDD VSS AGNDB VOUTB VREFB DGND DB11 WR DB10–DB0 Description Chip Select Input for DAC A. Active low logic input. DAC A is selected when this input is low. Chip Select Input for DAC B. Active low logic input. DAC B is selected when this input is low. Reference Input Voltage for DAC A. This may be an ac or dc signal. Analog Output Voltage from DAC A. Analog Ground for DAC A. Positive Power Supply. Negative Power Supply. Analog Ground for DAC B. Analog Output Voltage from DAC B. Reference Input Voltage for DAC B. This may be an ac or dc signal. Digital Ground. Data Bit 11 (MSB). Write Input. WR is a positive edge triggered input which is used in conjunction with CSA and CSB to write data to the DAC latches. Data Bit 10 to Data Bit 0 (LSB). AD7837 PIN CONFIGURATION DIP AND SOIC AD7847 PIN CONFIGURATION DIP AND SOIC CS RFBA VREFA VOUTA AGNDA VDD VSS AGNDB VOUTB 1 2 3 4 5 6 24 DB0 23 DB1 22 DB2 21 DB3 CSA CSB VREFA VOUTA AGNDA VDD VSS AGNDB VOUTB 1 2 3 4 5 6 24 DB0 23 DB1 22 DB2 21 DB3 AD7837 TOP VIEW 20 DB4 19 DB5 AD7847 TOP VIEW 20 DB4 19 DB5 7 (Not to Scale) 18 DB6 8 9 17 DB7 16 A0 15 A1 14 LDAC 13 WR 7 (Not to Scale) 18 DB6 8 9 17 DB7 16 DB8 15 DB9 14 DB10 13 WR VREFB 10 DGND 11 RFBB 12 VREFB 10 DGND 11 DB11 12 REV. C –5– AD7837/AD7847–Typical Performance Graphs 10 25 0.6 0.4 0.2 VDD = +15V VSS = –15V DAC A 20 0 VOUT – Volts p–p 0 ERROR – LSB –0.2 –0.4 –0.6 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 DAC B GAIN – dB 15 –10 VDD = +15V VSS = –15V VREF = +20Vp–p DAC CODE = 111...111 10 VDD = +15V VSS = –15V VREF = +20Vp–p @ 1kHz DAC CODE = 111...111 –20 5 –30 104 106 105 FREQUENCY – Hz 107 0 10 100 1k LOAD RESISTANCE – 10k 0 2048 CODE 4095 Figure 1. Frequency Response Figure 2. Output Voltage Swing vs. Resistive Load 400 Figure 3. DAC-to-DAC Linearity Matching –40 0.5 NOISE SPECTRAL DENSITY – nV/ Hz 0.4 ERROR – LSB VREF = 7.5V –50 300 THD – dB 0.3 200 VDD = +15V VSS = –15V VREF = 0V DAC CODE = 111...111 –60 –70 VDD = +15V VSS = –15V VREF = 6V rms DAC CODE = 111...111 0.2 INL –80 0.1 DNL 0.0 0 11 13 15 VDD /VSS – Volts 17 100 –90 0 0.01 0.1 10 1 FREQUENCY – Hz 100 –100 0.1 1 10 FREQUENCY – kHz 100 Figure 4. Linearity vs. Power Supply Figure 5. Noise Spectral Density vs. Frequency Figure 6. THD vs. Frequency –50 A1 –0.01V –60 VDD = +15V VSS = –15V VREF = 20V p-p DAC CODE = 000...000 FEEDTHROUGH – dB –70 FULL SCALE –80 VOUT –90 ZERO SCALE –100 0.1 200mV 50mV B w L 2s 1 100 10 FREQUENCY – kHz 1000 HORIZ 2 s /DIV VERT 2V/DIV Figure 7. Multiplying Feedthrough Error vs. Frequency Figure 8. Large Signal Pulse Response Figure 9. Small Signal Pulse Response –6– REV. C AD7837/AD7847 CIRCUIT INFORMATION D/A SECTION Table I. AD7847 Truth Table A simplified circuit diagram for one of the D/A converters and output amplifier is shown in Figure 10. A segmented scheme is used whereby the 2 MSBs of the 12-bit data word are decoded to drive the three switches A-C. The remaining 10 bits drive the switches (S0–S9) in a standard R-2R ladder configuration. Each of the switches A–C steers 1/4 of the total reference current with the remaining 1/4 passing through the R-2R section. The output amplifier and feedback resistor perform the current to voltage conversion giving VOUT = – D × VREF where D is the fractional representation of the digital word. (D can be set from 0 to 4095/4096.) The output amplifier can maintain ± 10 V across a 2 kΩ load. It is internally compensated and settles to 0.01% FSR (1/2 LSB) in less than 5 µs. Note that on the AD7837, VOUT must be connected externally to RFB. R VREF 2R C 2R B 2R A 2R S9 2R S8 2R S0 2R R /2 R R CSA X 1 0 1 0 g 1 g CSB X 1 1 0 0 1 g g WR 1 X g g g 0 0 0 Function No Data Transfer No Data Transfer Data Latched to DAC A Data Latched to DAC B Data Latched to Both DACs Data Latched to DAC A Data Latched to DAC B Data Latched to Both DACs X = Don’t Care. g = Rising Edge Triggered. CSA, CSB t1 WR t3 t2 t4 DATA VALID DATA t5 Figure 12. AD7847 Write Cycle Timing Diagram INTERFACE LOGIC INFORMATION—AD7837 VOUT SHOWN FOR ALL 1s ON DAC AGND Figure 10. D/A Simplified Circuit Diagram INTERFACE LOGIC INFORMATION—AD7847 The input control logic for the AD7847 is shown in Figure 11. The part contains a 12-bit latch for each DAC. It can be treated as two independent DACs, each with its own CS input and a common WR input. CSA and WR control the loading of data to the DAC A latch, while CSB and WR control the loading of the DAC B latch. The latches are edge triggered so that input data is latched to the respective latch on the rising edge of WR. If CSA and CSB are both low and WR is taken high, the same data will be latched to both DAC latches. The control logic truth table is shown in Table I, while the write cycle timing diagram for the part is shown in Figure 12. CSA WR The input loading structure on the AD7837 is configured for interfacing to microprocessors with an 8-bit-wide data bus. The part contains two 12-bit latches per DAC—an input latch and a DAC latch. Each input latch is further subdivided into a leastsignificant 8-bit latch and a most-significant 4-bit latch. Only the data held in the DAC latches determines the outputs from the part. The input control logic for the AD7837 is shown in Figure 13, while the write cycle timing diagram is shown in Figure 14. LDAC CS WR 4 DAC A LATCH 12 DAC B LATCH 12 A0 DAC A MS INPUT LATCH 8 DAC A LS INPUT LATCH A1 4 DAC B LS INPUT LATCH DAC A LATCH 8 DAC B LS INPUT LATCH CSB DAC B LATCH 8 DB7 DB0 Figure 11. AD7847 Input Control Logic Figure 13. AD7837 Input Control Logic REV. C –7– AD7837/AD7847 UNIPOLAR BINARY OPERATION A0/A1 ADDRESS DATA t6 CS t7 t1 t3 WR t2 Figure 15 shows DAC A on the AD7837/AD7847 connected for unipolar binary operation. Similar connections apply for DAC B. When VIN is an ac signal, the circuit performs 2-quadrant multiplication. The code table for this circuit is shown in Table III. Note that on the AD7847 the feedback resistor RFB is internally connected to VOUT. VDD t4 DATA VALID DATA t5 AD7837 AD7847 t8 VREFA VIN DAC A DGND VDD RFBA VOUTA * VOUT *INTERNALLY CONNECTED ON AD7847 LDAC AGNDA VSS VSS Figure 14. AD7837 Write Cycle Timing Diagram CS, WR, A0 and A1 control the loading of data to the input latches. The eight data inputs accept right-justified data. Data can be loaded to the input latches in any sequence. Provided that LDAC is held high, there is no analog output change as a result of loading data to the input latches. Address lines A0 and A1 determine which latch data is loaded to when CS and WR are low. The control logic truth table for the part is shown in Table II. Table II. AD7837 Truth Table Figure 15. Unipolar Binary Operation Table III. Unipolar Code Table DAC Latch Contents MSB LSB Analog Output, VOUT 1111 1111 1111 CS WR A1 A0 LDAC Function 1 X 0 0 0 0 1 X 1 0 0 0 0 1 X X 0 0 1 1 X X X 0 1 0 1 X 1 1 1 1 1 1 0 No Data Transfer No Data Transfer DAC A LS Input Latch Transparent DAC A MS Input Latch Transparent DAC B LS Input Latch Transparent DAC B MS Input Latch Transparent DAC A and DAC B DAC Latches Updated Simultaneously from the Respective Input Latches  4095  –VIN ×    4096   2048  –V IN ×   = – 1/ 2 VIN  4096  1 –V IN ×    4096  0V . 1000 0000 0000 0000 0000 0001 0000 0000 0000 Note 1 LSB = V IN 4096 X = Don’t Care. The LDAC input controls the transfer of 12-bit data from the input latches to the DAC latches. When LDAC is taken low, both DAC latches, and hence both analog outputs, are updated at the same time. The data in the DAC latches is held on the rising edge of LDAC. The LDAC input is asynchronous and independent of WR. This is useful in many applications especially in the simultaneous updating of multiple AD7837s. However, care must be taken while exercising LDAC during a write cycle. If an LDAC operation overlaps a CS and WR operation, there is a possibility of invalid data being latched to the output. To avoid this, LDAC must remain low after CS or WR return high for a period equal to or greater than t8, the minimum LDAC pulsewidth. –8– REV. C AD7837/AD7847 BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) APPLICATIONS PROGRAMMABLE GAIN AMPLIFIER (PGA) The dual DAC/amplifier combination along with access to RFB make the AD7837 ideal as a programmable gain amplifier. In this application, the DAC functions as a programmable resistor in the amplifier feedback loop. This type of configuration is shown in Figure 17 and is suitable for ac gain control. The circuit consists of two PGAs in series. Use of a dual configuration provides greater accuracy over a wider dynamic range than a single PGA solution. The overall system gain is the product of the individual gain stages. The effective gains for each stage are controlled by the DAC codes. As the code decreases, the effective DAC resistance increases, and so the gain also increases. VREFA Figure 16 shows the AD7837/AD7847 connected for bipolar operation. The coding is offset binary as shown in Table IV. When VIN is an ac signal, the circuit performs 4-quadrant multiplication. To maintain the gain error specifications, resistors R1, R2 and R3 should be ratio matched to 0.01%. Note that on the AD7847 the feedback resistor RFB is internally connected to VOUT. R2 20k R1 20k VDD AD711 RFBA VOUTA VOUT AD7837 AD7847 VREFA VIN DAC A VDD * R3 10k VIN RFBA DAC A VOUTA AGNDA VREFB DGND AGNDA VSS VSS *INTERNALLY CONNECTED ON AD7847 AD7837 DAC B RFBB AGNDB Figure 16. Bipolar Offset Binary Operation Table IV. Bipolar Code Table VOUT VOUTB DAC Latch Contents MSB LSB Figure 17. Dual PGA Circuit Analog Output, VOUT  2047  +V IN ×    2048  +V IN 1 ×   2048  The transfer function is given by 1111 1111 1111 VOUT REQA REQB = × V IN RFBA RFBB (1) 1000 0000 0001 1000 0000 0000 0111 1111 1111 where REQA, REQB are the effective DAC resistances controlled by the digital input code: REQ = 212 RIN N (2) 0V 1 –V IN ×    2048   2048  –V IN ×   = –V IN  2048  . where RIN is the DAC input resistance and is equal to RFB and N = DAC input code in decimal. The transfer function in (1) thus simplifies to 0000 0000 0000 Note 1 LSB = V IN 2048 212 212 VOUT = × V IN N A NB (3) where NA = DAC A input code in decimal and NB = DAC B input code in decimal. NA, NB may be programmed between 1 and (212–1). The zero code is not allowed as it results in an open loop amplifier response. To minimize errors, the digital codes NA and NB should be chosen to be equal to or as close as possible to each other to achieve the required gain. REV. C –9– AD7837/AD7847 ANALOG PANNING CIRCUIT TOTAL POWER VARIATION – dB 0.6 In audio applications it is often necessary to digitally “pan” or split a single signal source into a two-channel signal while maintaining the total power delivered to both channels constant. This may be done very simply by feeding the signal into the VREF input of both DACs. The digital codes are chosen such that the code applied to DAC B is the two's complement of that applied to DAC A. In this way the signal may be panned between both channels as the digital code is changed. The total power variation with this arrangement is 3 dB. For applications which require more precise power control the circuit shown in Figure 18 may be used. This circuit requires the AD7837/AD7847, an AD712 dual op amp and eight equal value resistors. Again both channels are driven with two's complementary data. The maximum power variation using this circuit is only 0.5 dBs. R R 0.5 0.4 0.3 0.2 0.1 0.0 1 512 1024 1536 2048 2560 3072 DIGITAL INPUT CODE NA 3584 4095 Figure 19. Power Variation for Circuit in Figure 9 APPLYING THE AD7837/AD7847 General Ground Management 1/2 AD712 R R VIN R R VREFA AD7837/ AD7847 VOUTA VOUTB 1/2 AD712 R R VOUTA RLA RLB VREFB AC or transient voltages between the analog and digital grounds i.e., between AGNDA/AGNDB and DGND can cause noise injection into the analog output. The best method of ensuring that both AGNDs and DGND are equal is to connect them together at the AD7837/AD7847 on the circuit board. In more complex systems where the AGND and DGND intertie is on the backplane, it is recommended that two diodes be connected in inverse parallel between the AGND and DGND pins (1N914 or equivalent). Power Supply Decoupling VOUTB In order to minimize noise it is recommended that the VDD and the VSS lines on the AD7837/AD7847 be decoupled to DGND using a 10 µF in parallel with a 0.1 µF ceramic capacitor. Operation with Reduced Power Supply Voltages Figure 18. Analog Panning Circuit The voltage output expressions for the two channels are as follows: N  VOUTA = –V IN  12 A   2 + NA  N  VOUT B = –V IN  12 B  2 + NB   where NA = DAC A input code in decimal (1 ≤ NA ≤ 4095) and NB = DAC B input code in decimal (1 ≤ NB ≤ 4095) with NB = 2s complement of NA. The two's complement relationship between NA and NB causes NB to increase as NA decreases and vice versa. Hence NA + NB = 4096. With NA = 2048, then NB = 2048 also; this gives the balanced condition where the power is split equally between both channels. The total power variation as the signal is fully panned from Channel B to Channel A is shown in Figure 19. The AD7837/AD7847 is specified for operation with VDD/VSS = ± 15 V ± 5%. The part may be operated down to VDD/VSS = ± 10 V without significant linearity degradation. See typical performance graphs. The output amplifier however requires approximately 3 V of headroom so the VREF input should not approach within 3 V of either power supply voltages in order to maintain accuracy. MICROPROCESSOR INTERFACING–AD7847 Figures 20 to 22 show interfaces between the AD7847 and three popular 16-bit microprocessor systems, the 8086, MC68000 and the TMS320C10. In all interfaces, the AD7847 is memorymapped with a separate memory address for each DAC latch. AD7847–8086 Interface Figure 20 shows an interface between the AD7847 and the 8086 microprocessor. A single MOV instruction loads the 12-bit word into the selected DAC latch and the output responds on the rising edge of WR. –10– REV. C AD7837/AD7847 ADDRESS BUS 8086 16 BIT LATCH ADDRESS DECODE CSA CSB MICROPROCESSOR INTERFACING–AD7837 ALE WR AD7847* WR DB11 DB0 AD15 AD0 ADDRESS/DATA BUS *ADDITIONAL PINS OMITTED FOR CLARITY Figure 20. AD7847 to 8086 Interface AD7847–MC68000 Interface Figure 21 shows an interface between the AD7847 and the MC68000. Once again a single MOVE instruction loads the 12-bit word into the selected DAC latch. CSA and CSB are AND-gated to provide a DTACK signal when either DAC latch is selected. A23 A1 MC68000 AS DTACK LDS R/W ADDRESS BUS Figures 23 to 25 show the AD7837 configured for interfacing to microprocessors with 8-bit data bus systems. In all cases, data is right-justified and the AD7837 is memory-mapped with the two lowest address lines of the microprocessor address bus driving the A0 and A1 inputs of the AD7837. Five separate memory addresses are required, one for the each MS latch and one for each LS latch and one for the common LDAC input. Data is written to the respective input latch in two write operations. Either high byte or low byte data can be written first to the input latch. A write to the AD7837 LDAC address transfers the data from the input latches to the respective DAC latches and updates both analog outputs. Alternatively, the LDAC input can be asynchronous and can be common to several AD7837s for simultaneous updating of a number of voltage channels. AD7837–8051/8088 Interface Figure 23 shows the connection diagram for interfacing the AD7837 to both the 8051 and the 8088. On the 8051, the signal PSEN is used to enable the address decoder while DEN is used on the 8088. A15 A8 8051/8088 PSEN OR DEN ADDRESS DECODE EN CSA CSB ADDRESS BUS A0 A1 CS LDAC AD7847* WR DB11 DB0 ADDRESS DECODE EN OCTAL LATCH ALE WR AD7837* WR DB7 DB0 D15 D0 DATA BUS *ADDITIONAL PINS OMITTED FOR CLARITY AD7 Figure 21. AD7847 to MC68000 Interface AD7847–TMS320C10 Interface AD0 ADDRESS/DATA BUS *ADDITIONAL PINS OMITTED FOR CLARITY Figure 22 shows an interface between the AD7847 and the TMS320C10 DSP processor. A single OUT instruction loads the 12-bit word into the selected DAC latch. A11 A0 TMS320C10 MEN WE ADDRESS BUS Figure 23. AD7837 to 8051/8088 Interface AD7837–MC68008 Interface An interface between the AD7837 and the MC68008 is shown in Figure 24. In the diagram shown, the LDAC signal is derived from an asynchronous timer but this can be derived from the address decoder as in the previous interface diagram. TIMER A19 A0 MC68008 AS ADDRESS BUS A0 A1 CS LDAC ADDRESS DECODE EN CSA CSB AD7847* WR DB11 DB0 ADDRESS DECODE EN D15 D0 DATA BUS *ADDITIONAL PINS OMITTED FOR CLARITY DTACK DS R/W AD7837* WR DB7 DB0 Figure 22. AD7847 to TMS320C10 Interface D7 D0 DATA BUS *ADDITIONAL PINS OMITTED FOR CLARITY Figure 24. AD7837 to 68008 Interface REV. C –11– AD7837/AD7847 AD7837–6502/6809 Interface Figure 25 shows an interface between the AD7837 and the 6502 or 6809 microprocessor. For the 6502 microprocessor, the φ2 clock is used to generate the WR, while for the 6809 the E signal is used. A15 A0 6502/6809 R/W 2 OR E ADDRESS BUS A0 A1 ADDRESS DECODE EN CS LDAC AD7837* WR DB7 DB0 D7 D0 *ADDITIONAL PINS OMITTED FOR CLARITY DATA BUS Figure 25. AD7837 to 6502/6809 Interface OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead Plastic DIP (N-24) 1.228 (31.19) 1.226 (31.14) 24 1 13 12 24-Lead Cerdip (Q-24) 24 13 0.261 (6.61 0.001 0.03) PIN 1 0.32 (8.128) 0.30 (7.62) 1 12 0.295 (7.493) MAX 0.070 (1.778) 0.020 (0.508) 0.320 (8.128) 0.290 (7.366) 0.180 (4.572) MAX PIN 1 0.130 (3.30) 0.128 (3.25) 1.290 (32.77) MAX 0.225 (5.715) MAX SEATING PLANE 0.011 (0.28) 0.11 (2.79) 0.07 (1.78) 15° 0.009 (0.23) 0.02 (0.5) 0° 0.09 (2.28) 0.05 (1.27) 0.016 (0.41) 1. LEAD NO. 1 IDENTIFIED BY A DOT OR NOTCH. 2. PLASTIC LEADS WILL EITHER BE SOLDER DIPPED OR TIN LEAD PLATED. IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS. 0.125 (3.175) MIN SEATING 0.012 (0.305) 0.021 (0.533) 0.110 (2.794) 0.065 (1.651) PLANE 15° 0.008 (0.203) 0° 0.015 (0.381) 0.090 (2.286) 0.055 (1.397) TYP TYP TYP 1. LEAD NO. 1 IDENTIFIED BY A DOT OR NOTCH. 2. CERDIP LEADS WILL EITHER BE TIN PLATED OR SOLDER DIPPED. IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS 24-Lead SOIC (R-24) 0.608 (15.45) 0.596 (15.13) 24 13 0.299 (7.6) 0.291 (7.39) 1 12 0.414 (10.52) 0.398 (10.10) PIN 1 0.096 (2.44) 0.089 (2.26) 0.03 (0.76) 0.02 (0.51) 0.01 (0.254) 0.05 0.006 (0.15) (1.27) 6 0 SEATING 0.042 (1.067) 0.013 (0.32) PLANE 0.018 (0.457) 0.009 (0.23) 1. LEAD NO. 1 IDENTIFIED BY A DOT. 2. SOIC LEADS WILL EITHER BE TIN PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS. 0.019 (0.49) 0.014 (0.35) –12– REV. C PRINTED IN U.S.A. C01007a–0–8/00 (rev. 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