AD7839ASZ

a Octal 13-Bit, Parallel Input, Voltage-Output DAC AD7839 FEATURES Eight 13-Bit DACs in One Package Voltage Outputs Offset Adjust for Each DAC Pair Reference Range of ⴞ5 V Maximum Output Voltage Range of ⴞ10 V Clear Function to User-Defined Voltage 44-Lead MQFP Package GENERAL DESCRIPTION The AD7839 contains eight 13-bit DACs on one monolithic chip. It has output voltages with a full-scale range of ± 10 V from reference voltages of ± 5 V. The AD7839 accepts 13-bit parallel loaded data from the external bus into one of the input registers under the control of the WR, CS and DAC channel address pins, A0–A2. The DAC outputs are updated on reception of new data into the DAC registers. All the outputs may be updated simultaneously by taking the LDAC input low. APPLICATIONS Automatic Test Equipment Process Control General Purpose Instrumentation Each DAC output is buffered with a gain-of-two amplifier into which an external DAC offset voltage can be inserted via the DUTGNDx pins. The AD7839 is available in a 44-lead MQFP package. FUNCTIONAL BLOCK DIAGRAM VCC VSS VDD VREF(+) VREF(–) AB AB DUTGND CD AD7839 13 DUTGND AB R INPUT 13 REG A DAC REG A DAC A VOUTA R DB12 13 INPUT 13 REG B DAC REG B DAC B VOUTB R 13 INPUT 13 REG C DAC REG C R 13 DAC C VOUTC WR R 13 ADDRESS DECODE CS A1 R 13 DB0 A0 R 13 13 A2 INPUT 13 REG D DAC REG D 13 INPUT 13 REG E DAC REG E 13 INPUT 13 REG F DAC REG F 13 INPUT 13 REG G DAC REG G 13 INPUT 13 REG H DAC REG H 13 R DAC D VOUTD DAC E VOUTE LDAC 13 R R R R R R R R DAC F VOUTF 13 DAC G VOUTG 13 DAC H VOUTH GND VREF(+) VREF(–) GH GH VREF(+) VREF(–) CDEF CDEF CLR DUTGND EF DUTGND GH REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 (VCC = +5 V ⴞ 5%; VDD = +15 V ⴞ 5%; VSS = –15 V ⴞ 5%; GND = DUTGND = 0 V; 1 L L A = TMIN to TMAX, unless otherwise noted.) AD7839–SPECIFICATIONS R = 5 k⍀ and C = 50 pF to GND, T Parameter A Version Units 13 ±2 ± 0.9 ±4 ±4 ±1 0.5 10 120 Bits LSB max LSB max LSB max LSB max LSB typ ppm FSR/°C typ ppm FSR/°C max µV max REFERENCE INPUTS2 DC Input Impedance Input Current VREF(+) Range VREF(–) Range [VREF(+) – VREF(–)] 100 ±1 0/+5 –5/0 +2/+10 MΩ typ µA max V min/max V min/max V min/max DUTGND INPUTS2 DC Input Impedance Max Input Current Input Range 60 ± 0.3 –2/+2 kΩ typ mA typ V min/max OUTPUT CHARACTERISTICS2 Output Voltage Swing Short Circuit Current Resistive Load Capacitive Load DC Output Impedance ± 10 15 5 50 0.5 V min mA max kΩ min pF max Ω max 2.4 0.8 V min V max 1 ± 10 10 µA max µA max pF max ACCURACY Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale Error Gain Error Gain Temperature Coefficient2 DC Crosstalk2 DIGITAL INPUTS2 VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current @ +25°C TMIN to TMAX CIN, Input Capacitance POWER REQUIREMENTS3 VCC VDD VSS Power Supply Sensitivity2 ␣␣ ∆Full Scale/∆VDD ␣␣ ∆Full Scale/∆VSS ICC IDD ISS Test Conditions/Comments Typically ± 0.5 LSB Guaranteed Monotonic Over Temperature VREF(+) = +5 V, VREF(–) = –5 V. Typically within ± 1 LSB VREF(+) = +5 V, VREF(–) = –5 V. Typically within ± 1 LSB VREF(+) = +5 V, VREF(–) = –5 V See Terminology. Typically 75 µV Per Input. Typically ± 0.03 µA For Specified Performance. Can Go as Low as 0 V, but Performance Not Guaranteed Per Input 2 × (VREF(–) + [VREF(+) – VREF(–)] × D) – VDUTGND To 0 V To 0 V Total for All Pins +4.75/+5.25 V min/max +14.25/+15.75 V min/max –14.25/–15.75 V min/max For Specified Performance For Specified Performance For Specified Performance 90 90 0.5 10 10 VINH = VCC, VINL = GND. Dynamic Current Outputs Unloaded. Typically 8 mA Outputs Unloaded. Typically 8 mA dB typ dB typ mA max mA max mA max NOTES 1 Temperature range for A Version: –40°C to +85°C 2 Guaranteed by characterization. Not production tested. 3 The AD7839 is functional with power supplies of ± 12 V ± 10% with reduced output range. At 12 V it is recommended to restrict reference range to ± 4 V due to output amplifier headroom limitations Specifications subject to change without notice. –2– REV. 0 AD7839 (These characteristics are included for Design Guidance and are not subject AC PERFORMANCE CHARACTERISTICS to production testing.) Parameter A Units Test Conditions/Comments µs typ µs max V/µs typ nV-s typ Full-Scale Change to ± 1/2 LSB. DAC Latch Contents Alternately Loaded with All 0s and All 1s Slew Rate Digital-to-Analog Glitch Impulse 30 40 0.7 230 Channel-to-Channel Isolation DAC-to-DAC Crosstalk Digital Crosstalk 99 40 0.2 dB typ nV-s typ nV-s typ Digital Feedthrough Output Noise Spectral Density ␣␣ @ 1 kHz 0.1 nV-s typ Measured with VREF(+) = +5 V, VREF(–) = –5 V. DAC Latch Alternately Loaded with 0FFF Hex and 1000 Hex. Not Dependent on Load Conditions See Terminology See Terminology Feedthrough to DAC Output Under Test Due to Change in Digital Input Code to Another Converter Effect of Input Bus Activity on DAC Output Under Test 200 nV/√Hz typ All 1s Loaded to DAC. VREF(+) = VREF(–) = 0 V DYNAMIC PERFORMANCE Output Voltage Settling Time Specifications subject to change without notice. TIMING SPECIFICATIONS1, 2 (V = +5 V ⴞ 5%; VDD = +15 V ⴞ 5%; VSS = –15 V ⴞ 5%; GND = DUTGND = 0 V) CC Parameter Limit at TMIN, TMAX Units Description t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 15 0 50 50 0 0 20 0 30 300 50 ns min ns min ns min ns min ns min ns min ns min ns min µs typ ns max ns min Address to WR Setup Time Address to WR Hold Time CS Pulsewidth Low WR Pulsewidth Low CS to WR Setup Time WR to CS Hold Time Data Setup Time Data Hold Time Settling Time CLR Pulse Activation Time LDAC Pulsewidth Low NOTES 1 All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 Rise and fall times should be no longer than 50 ns. Specifications subject to change without notice. t1 t2 A0, A1, A2 t6 t5 CS t3 t4 WR t8 t7 DATA t9 VOUT t10 CLR VOUT t11 LDAC Figure 1. Timing Diagram REV. 0 –3– AD7839 ABSOLUTE MAXIMUM RATINGS 1, 2 Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4000 V (TA = +25°C unless otherwise noted) VCC to GND3 . . . . . . . . . . . . . . .–0.3 V, +7 V or VDD + 0.3 V (Whichever Is Lower) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –17 V Digital Inputs to GND . . . . . . . . . . . . . . –0.3 V, VCC + 0.3 V VREF(+) to VREF(–) . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18 V VREF(+) to GND . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V VREF(–) to GND . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V DUTGND to GND . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V VOUT (A–H) to GND . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . +150°C MQFP Package Power Dissipation . . . . . . . . . . . . . . . . . . (TJ max – TA)/θJA θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95°C/W NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up. 3 V CC must not exceed V DD by more than 0.3 V. If it is possible for this to happen during power supply sequencing, the following diode protection scheme will ensure protection. V V DD IN4148 CC HP5082-2811 VDD VCC AD7839 ORDERING GUIDE Model Temperature Range Linearity Error (LSBs) DNL (LSBs) Package Option* AD7839AS –40°C to +85°C ±2 ±1 S-44 *S = Plastic Quad Flatpack (MQFP). VOUTF VOUTG 39 DUTGND_EF 40 VREF(+)CDEF VOUTD 41 VDD 42 VREF(–)CDEF VOUTC 43 VOUTE 44 DUTGND_CD VOUTB PIN CONFIGURATION 38 37 36 35 34 DUTGND_AB 1 VOUTA 33 PIN 1 IDENTIFIER DUTGND_GH 32 VOUTH VREF(–)AB 3 31 VREF(–)GH VREF(+)AB 4 30 VREF(+)GH 2 VDD 5 VSS 6 LDAC 7 A2 8 A1 DB9 CS 11 23 DB8 12 13 14 15 16 17 18 19 20 21 22 DB7 24 DB6 DB10 A0 10 DB5 25 DB4 DB11 9 DB3 DB12 26 DB2 27 DB1 CLR DB0 28 GND VSS TOP VIEW (Not to Scale) WR 29 VCC AD7839 –4– REV. 0 AD7839 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 DUTGND_AB 2, 44, 43, 41, 37, 35, 34, 32 4, 3 5 6 7 VOUTA . . VOUTH Device Sense Ground for DACs A and B. VOUTA and VOUTB are referenced to the voltage applied to this pin. DAC Outputs. 10, 9, 8 A0, A1, A2 11 12 CS WR 13 14 15–27 VCC GND DB0␣ .␣ .␣ DB12 28 CLR 30, 31 33 VREF(+)GH, VREF(–)GH DUTGND_GH 36 DUTGND_EF 39 40 42 VREF(+)CDEF VREF(–)CDEF DUTGND_CD REV. 0 VREF(+)AB, VREF(–)AB VDD VSS LDAC Reference Inputs for DACs A and B. These reference voltages are referred to GND. Positive Analog Power Supply; +15 V ± 5%. Negative Analog Power Supply; –15 V ± 5%. Load DAC Logic Input (active low). When this logic input is taken low the contents of the input registers are transferred to their respective DAC registers. LDAC can be tied permanently low enabling the outputs to be updated on the rising edge of WR. Address inputs. A0, A1 and A2 are decoded to select one of the eight input registers for a data transfer. Level-Triggered Chip Select Input (active low). The device is selected when this input is low. Level-Triggered Write Input (active low), used in conjunction with CS to write data to the AD7839 input registers. Data is latched into the selected input register on the rising edge of WR. Logic Power Supply; +5 V ± 5%. Ground. Parallel Data Inputs. The AD7839 can accept a straight 13-bit parallel word on DB0 to DB12 where DB12 is the MSB and DB0 is the LSB. Asynchronous Clear Input (level sensitive, active low). When this input is low, all analog outputs are switched to the externally set potential on the relevant DUTGND pin. The contents of input registers and DAC registers A to H are not affected when the CLR pin is taken low. When CLR is brought back high, the DAC outputs revert to their original outputs as determined by the data in their DAC registers. Reference Inputs for DACs G and H. These reference voltages are referred to GND. Device Sense Ground for DACs G and H. VOUTG and VOUTH are referenced to the voltage applied to this pin. Device Sense Ground for DACs E and F. VOUTE and VOUTF are referenced to the voltage applied to this pin. Reference Inputs for DACs C, D, E and F. These reference voltages are referred to GND. Device Sense Ground for DACs C and D. VOUTC and VOUTD are referenced to the voltage applied to this pin. –5– AD7839 TERMINOLOGY Relative Accuracy Full-Scale Error This is the error in DAC output voltage when all 1s are loaded into the DAC latch. Ideally the output voltage, with all 1s loaded into the DAC latch, should be 2 VREF(+) – 1 LSB. Relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error and is normally expressed in Least Significant Bits. Zero-Scale Error Zero-scale error is the error in the DAC output voltage when all 0s are loaded into the DAC latch. Ideally the output voltage, with all 0s in the DAC latch should be equal to 2 VREF(–). Zeroscale error is mainly due to offsets in the output amplifier. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. Gain Error Gain Error is defined as (Full-Scale Error) – (Zero-Scale Error). DC Crosstalk GENERAL DESCRIPTION DAC Architecture—General Although the common input reference voltage signals are internally buffered, small IR drops in the individual DAC reference inputs across the die can mean that an update to one channel can produce a dc output change in one or another of the channel outputs. Each channel consists of a straight 13-bit R-2R voltage-mode DAC. The full-scale output voltage range is equal to twice the reference span of VREF(+) – VREF(–). The DAC coding is straight binary; all 0s produces an output of 2 VREF(–); all 1s produces an output of 2 VREF(+) – 1 LSB. The eight DAC outputs are buffered by op amps that share common VDD and VSS power supplies. If the dc load current changes in one channel (due to an update), this can result in a further dc change in one or another of the channel outputs. This effect is most obvious at high load currents and reduces as the load currents are reduced. With high impedance loads the effect is virtually unmeasurable. The analog output voltage of each DAC channel reflects the contents of its own DAC register. Data is transferred from the external bus to the input register of each DAC on a per channel basis. Bringing the CLR line low switches all the signal outputs, VOUTA to VOUTH, to the voltage level on the DUTGND pin. When the CLR signal is brought back high, the output voltages from the DACs will reflect the data stored in the relevant DAC registers. Output Voltage Settling Time This is the amount of time it takes for the output to settle to a specified level for a full-scale input change. Data Loading to the AD7839 Data is loaded into the AD7839 in straight parallel 13-bit wide words. Digital-to-Analog Glitch Impulse This is the amount of charge injected into the analog output when the inputs change state. It is specified as the area of the glitch in nV-secs. It is measured with VREF(+) = +5 V and VREF(–) = –5 V and the digital inputs toggled between 0FFFH and 1000H. The DAC output voltages, VOUTA – VOUTH are updated to reflect new data in the DAC registers. The actual input register being written to is determined by the logic levels present on the device’s address lines, as shown in Table I. Channel-to-Channel Isolation Channel-to-channel isolation refers to the proportion of input signal from one DAC’s reference input that appears at the output of another DAC. It is expressed in dBs. Table I. Address Line Truth Table DAC-to-DAC Crosstalk A2 A1 A0 DAC Selected DAC-to-DAC crosstalk is defined as the glitch impulse that appears at the output of one converter due to both the digital change and subsequent analog O/P change at another converter. It is specified in nV-secs. 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 INPUT REG A (DAC A) INPUT REG B (DAC B) INPUT REG C (DAC C) INPUT REG D (DAC D) INPUT REG E (DAC E) INPUT REG F (DAC F) INPUT REG G (DAC G) INPUT REG H (DAC H) Digital Crosstalk The glitch impulse transferred to the output of one converter due to a change in digital input code to the other converter is defined as the digital crosstalk and is specified in nV-secs. Digital Feedthrough When the device is not selected, high frequency logic activity on the device’s digital inputs can be capacitively coupled both across and through the device to show up as noise on the VOUT pins. This noise is digital feedthrough. DC Output Impedance This is the effective output source resistance. It is dominated by package lead resistance. –6– REV. 0 Typical Performance Characteristics– AD7839 1.0 0.25 0.0 –0.25 1.0 0.25 0.0 VDD = +15V VSS = –15V VREF(+) = +5V VREF(–) = –5V TA = +258C –0.25 –0.50 –0.75 –1.0 2048 4096 CODE 6144 8191 0 Figure 2. Typical INL Plot 2.0 1.5 1.0 0.0 –0.5 0.25 0 –0.25 4096 CODE 6144 8192 –2.0 –40 –0.75 –1.5 80 100 VCC = +5V VDD = +15V VSS = –15V 5 FULL-SCALE ERROR 4 0 –1.0 0 20 40 60 TEMPERATURE – 8C 6 –0.5 MIN DNL –20 Figure 4. Typical INL Error vs. Temperature 0.5 –0.50 MIN INL –1.5 ICC – mA MAX DNL ERROR – LSBs DNL ERROR – LSBs 0.50 VDD = +15V VSS = –15V VREF(+) = +5V VREF(–) = –5V MAX INL 0.5 Figure 3. Typical DNL Plot 1.0 VDD = +15V VSS = –15V VREF(+) = +5V VREF(–) = –5V 2048 VDD = +15V VSS = –15V VREF(+) = +5V VREF(–) = –5V –1.0 –0.50 0 0.75 INL ERROR – LSBs 0.50 1.5 DNL ERROR – LSBs 0.75 INL ERROR – LSBs 2.0 0.50 VDD = +15V VSS = –15V VREF(+) = +5V VREF(–) = –5V TA = +258C 3 DIGITAL INPUTS @ THRESHOLDS 2 1 ZERO-SCALE ERROR DIGITAL INPUTS @ SUPPLIES –1.0 –40 –20 0 20 40 60 TEMPERATURE – 8C 80 –2.0 –40 100 Figure 5. Typical DNL Error vs. Temperature 0 –20 0 20 40 60 TEMPERATURE – 8C 80 –1 –40 100 0 20 40 60 TEMPERATURE – 8C 100 10 0.5 VDD = +15V VSS = –15V VCC = +5V 10.19 VOUT – Volts 0.3 0.2 0.1 IDD/ISS – mA 0.4 VOLTS 80 Figure 7. ICC vs. Temperature Figure 6. Zero-Scale and Full-Scale Error vs. Temperature 0.6 –20 10.18 10.17 IDD 8 ISS 6 0 20.1 10.16 20.2 0 50 150 200 250 300 350 400 450 500 550 Figure 8. Typical Digital-to-Analog Glitch Impulse REV. 0 27 28 29 30 31 SETTLING TIME – ms 32 Figure 9. Settling Time (+) –7– 33 4 –40 –20 0 20 40 60 TEMPERATURE – °C 80 100 Figure 10. IDD, ISS vs. Temperature AD7839 When bipolar-zero and full-scale adjustment are not needed, R2 and R3 can be omitted. Pin 12 on the AD588 should be connected to Pin 11 and Pin 5 should be left floating. Unipolar Configuration Figure 11 shows the AD7839 in the unipolar binary circuit configuration. The VREF(+) input of the DAC is driven by the AD586, a +5 V reference. VREF(–) is tied to ground. Table II gives the code table for unipolar operation of the AD7839. Other suitable references include the REF02, a precision +5 V reference, and the REF195, a low dropout, micropower precision +5 V reference. +15V 2 8 AD586 C1 1mF 5 C1 1mF VOUT (0 TO +10V) VOUT AD7839* VREF(–) 9 AD588 +5V VDD VCC 14 15 16 AD7839* DUTGND VREF(–) VSS 12 VOUT (–10V TO +10V) VREF(+) 1 GND 8 13 SIGNAL GND –15V GND VSS SIGNAL GND +15V VOUT 3 10 11 R3 100kV DUTGND 4 6 2 5 R2 100kV VCC VREF(+) R1 10kV 4 7 +5V VDD 6 R1 39kV *ADDITIONAL PINS OMITTED FOR CLARITY Figure 12. Bipolar ± 10 V Operation SIGNAL GND –15V Table III. Code Table for Bipolar Operation *ADDITIONAL PINS OMITTED FOR CLARITY Figure 11. Unipolar +10 V Operation Offset and gain may be adjusted in Figure 11 as follows: To adjust offset, disconnect the VREF(–) input from 0 V, load the DAC with all 0s and adjust the VREF(–) voltage until VOUT = 0 V. For gain adjustment, the AD7839 should be loaded with all 1s and R1 adjusted until VOUT = 2 VREF(+) – 1 LSB = 10 V(8191/ 8192) = 9.99878 V. Many circuits will not require these offset and gain adjustments. In these circuits R1 can be omitted. Pin 5 of the AD586 may be left open circuit and Pin 2 (VREF(–)) of the AD7839 tied to 0 V. 1 1 0 0 0 1111 0000 1111 0000 0000 1111 0000 1111 0000 0000 1111 0000 1111 0001 0000 Analog Output (VOUT) 1 1 1 0 0 0 2[VREF(–) + VREF (8191/8192)] V 2[VREF(–) + VREF (4097/8192)] V 2[VREF(–) + VREF (4096/8192)] V 2[VREF(–) + VREF (4095/8192)] V 2[VREF(–) + VREF (1/8192)] V 2[VREF(–)] V 1111 0000 0000 1111 0000 0000 1111 0000 0000 1111 0000 0000 1111 0001 0000 1111 0001 0000 NOTES VREF = (VREF(+) – VREF(–)). For VREF(+) = +5 V, and VREF(–) = –5 V, VREF = 10 V, 1 LSB = 2 V REF V/213 = 20 V/8192 = 2.44 mV. Table II. Code Table for Unipolar Operation Binary Number in DAC Register MSB␣ ␣ ␣ ␣ ␣ ␣ ␣ ␣ LSB Binary Number in DAC Register MSB LSB Analog Output (VOUT) CONTROLLED POWER-ON OF THE OUTPUT STAGE 2 VREF (8191/8192) V 2 VREF (4096/8192) V 2 VREF (4095/8192) V 2 VREF (1/8192) V 0V A block diagram of the output stage of the AD7839 is shown in Figure 13. It is capable of driving a load of 5 kΩ in parallel with 50 pF. G1 to G6 are transmission gates used to control the power on voltage present at VOUT. On power up G1 and G2 are also used in conjunction with the CLR input to set VOUT to the user defined voltage present at the DUTGND pin. When CLR is taken back high, the DAC outputs reflect the data in the DAC registers. NOTES VREF = VREF(+); VREF(–) = 0 V for unipolar operation. For VREF(+) = +5 V, 1 LSB = +10 V/2 13 = +10 V/8192 = 1.22 mV. Bipolar Configuration G1 Figure 12 shows the AD7839 set up for ± 10 V operation. The AD588 provides precision ± 5 V tracking outputs that are fed to the VREF(+) and VREF(–) inputs of the AD7839. The code table for bipolar operation of the AD7839 is shown in Table III. G6 DAC VOUT G3 G2 In Figure 12, full-scale and bipolar zero adjustments are provided by varying the gain and balance on the AD588. R2 varies the gain on the AD588 while R3 adjusts the offset of both the +5 V and –5 V outputs together with respect to ground. G4 R For bipolar-zero adjustment, the DAC is loaded with 1000␣ .␣ .␣ .␣ 0000 and R3 is adjusted until VOUT = 0 V. Full scale is adjusted by loading the DAC with all 1s and adjusting R2 until VOUT = 10(4095/4096) V = 9.997559 V. R = 60kV G5 14kV DUTGND Figure 13. Block Diagram of AD7839 Output Stage –8– REV. 0 AD7839 Power-On with CLR Low G1 The output stage of the AD7839 has been designed to allow output stability during power-on. If CLR is kept low during power-on, then just after power is applied to the AD7839, the situation is as depicted in Figure 14. G1, G4 and G6 are open while G2, G3 and G5 are closed. G6 DAC VOUT G3 G2 G4 R G1 R G5 14kV G6 DAC VOUT G3 G2 G4 R DUTGND Figure 16. Output Stage After CLR Is Taken High Power-On with CLR High R G5 If CLR is high on the application of power to the device, the output stages of the AD7839 are configured as in Figure 17 while VDD is less than 7 V and VSS is more positive than –3 V. G1 is closed and G2 is open, thereby connecting the output of the DAC to the input of its output amplifier. G3 and G5 are closed while G4 and G6 are open, thus connecting the output amplifier as a unity gain buffer. VOUT is connected to DUTGND via G5 through a 14 kΩ resistor until VDD exceeds 7 V and VSS is more negative than –3 V. 14kV DUTGND Figure 14. Output Stage with VDD < 7 V or VSS > –3 V; CLR Low VOUT is kept within a few hundred millivolts of DUTGND via G5 and a 14 kΩ resistor. This thin-film resistor is connected in parallel with the gain resistors of the output amplifier. The output amplifier is connected as a unity gain buffer via G3, and the DUTGND voltage is applied to the buffer input via G2. The amplifier’s output is thus at the same voltage as the DUTGND pin. The output stage remains configured as in Figure 14 until the voltage at VDD exceeds 7 V and VSS is more negative than –3 V. By now the output amplifier has enough headroom to handle signals at its input and has also had time to settle. The internal power-on circuitry opens G3 and G5 and closes G4 and G6. This situation is shown in Figure 15. Now the output amplifier is configured in its noise gain configuration via G4 and G6. The DUTGND voltage is still connected to the noninverting input via G2 and this voltage appears at VOUT. G1 VOUT G3 G2 R G5 14kV DUTGND Figure 17. Output Stage Powering Up with CLR High While VDD < 7 V or VSS > –3 V When the difference between the supply voltages reaches +10 V, the internal power-on circuitry opens G3 and G5 and closes G4 and G6 configuring the output stage as shown in Figure 18. G6 VOUT G3 G2 G4 R G1 DAC G6 DAC G1 G4 R G6 DAC VOUT R G5 G3 14kV G2 G4 R DUTGND Figure 15.␣ Output Stage with VDD > 7 V and VSS < –3 V; CLR Low R VOUT has been disconnected from the DUTGND pin by the opening of G5, but will track the voltage present at DUTGND via the configuration shown in Figure 15. 14kV DUTGND Figure 18.␣ Output Stage Powering Up with CLR High; VDD > 7 V and VSS < –3 V When CLR is taken back high, the output stage is configured as shown in Figure 16. The internal control logic closes G1 and opens G2. The output amplifier is connected in a noninverting gain-of-two configuration. The voltage that appears on the VOUT pins is determined by the data present in the DAC registers. REV. 0 G5 –9– AD7839 DUTGND Voltage Range During power-on, the VOUT pins of the AD7839 are connected to the relevant DUTGND pins via G5 and the 14 kΩ thin-film resistor. The DUTGND potential must obey the max ratings at all times. Thus, the voltage at DUTGND must always be within the range VSS – 0.3 V, VDD + 0.3 V. However, in order that the voltages at the VOUT pins of the AD7839 stay within ± 2 V of the relevant DUTGND potential during power-on, the voltage applied to DUTGND should also be kept within the range GND – 2␣ V, GND + 2 V. Once the AD7839 has powered on and the on-chip amplifiers have settled, any voltage that is now applied to the DUTGND pin is subtracted from the DAC output, which has been gained up by a factor of two. Thus, for specified operation, the maximum voltage that can be applied to the DUTGND pin increases to the maximum allowable 2 VREF(+) voltage, and the minimum voltage that can be applied to DUTGND is the minimum 2 VREF(–) voltage. After the AD7839 has fully powered on, the outputs can track any DUTGND voltage within this minimum/maximum range. Power Supply Sequencing When operating the AD7839, it is important that ground be connected at all times to avoid high current states. The recommended power-up sequence is VDD/VSS followed by VCC. If VCC can exceed VDD on power-up, the diode scheme shown in the absolute max ratings will ensure protection. The reference inputs and digital inputs should be powered up last. Should the references exceed VDD/VSS on power-up, current limiting resistors should be inserted in series with the reference inputs to limit the current to 20 mA. Logic inputs should not be applied before VCC. Current limiting resistors (470 Ω), in series with the logic inputs, should be inserted if these inputs come up before VCC. MICROPROCESSOR INTERFACING Interfacing the AD7839—16-Bit Interface The AD7839 can be interfaced to a variety of 16-bit microcontrollers or DSP processors. Figure 19 shows the AD7839 interfaced to a generic 16-bit microcontroller/DSP processor. The lower address lines from the processor are connected to A0, A1 and A2 on the AD7839 as shown. The upper address lines are decoded to provide a chip select signal or an LDAC signal for the AD7839. The fast interface timing of the AD7839 allows direct interface to a wide variety of microcontrollers and DSPs as shown in Figure 19. APPLICATIONS Power Supply Bypassing and Grounding In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD7839 is mounted should be designed such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should be joined at only one place. The GND pin of the AD7839 should be connected to the AGND of the system. If the AD7839 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only, a star ground point that should be established as close as possible to the AD7839. Digital lines running under the device should be avoided as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7839 to avoid noise coupling. The power supply lines of the AD7839 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but not always possible with a double sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. The AD7839 should have ample supply bypassing located as close to the package as possible, ideally right up against the device. Figure 20 shows the recommended capacitor values of 10 µF in parallel with 0.1 µF on each of the supplies. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor should have low Effective Series Resistance (ESR) and Effective Series Inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. VCC 0.1mF mCONTROLLER/ DSP PROCESSOR* VDD 10mF 10mF 0.1mF 10mF 0.1mF AD7839 AD7839 VSS D12 D12 D0 D0 DATA BUS UPPER BITS OF ADDRESS BUS A2 A1 A0 R/W ADDRESS DECODE Figure 20. Recommended Decoupling Scheme for AD7839 CS LDAC A2 A1 A0 WR *ADDITIONAL PINS OMITTED FOR CLARITY Figure 19. AD7839 Parallel Interface –10– REV. 0 AD7839 Automated Test Equipment The AD7839 is particularly suited for use in an automated test environment. Figure 21 shows the AD7839 providing the necessary voltages for the pin driver and the window comparator in a typical ATE pin electronics configuration. AD588s are used to provide reference voltages for the AD7839. In the configuration shown, the AD588s are configured so that the voltage at Pin 1 is 5 V greater than the voltage at Pin 9 and the voltage at Pin 15 is 5 V less than the voltage at Pin 9. VOFFSET +15V –15V 16 2 4 3 6 1 8 13 10 11 12 AD588 +15V VREF(+)AB 15 VREF(–)AB 14 VOUTA PIN DRIVER VOUTB 9 –15V AD7839* 7 1mF DUTGND GH +15V –15V 2 3 6 1 8 15 AD588 VOUTG VREF(+)GH VREF(–)GH 14 9 7 1mF VOUT 16 4 13 10 11 12 DEVICE GND DEVICE GND VOUTH GND DEVICE GND The AD7839 is particularly suited for use in an automated test environment. The reference input for the AD7839 octal 13-bit DAC requires three differential references for the eight DACs. Programmable references may be a requirement in some ATE applications as the offset and gain errors at the output of a DAC can be adjusted by varying the voltages on the reference pins of the DAC. To trim offset errors, the DAC is loaded with the digital code 000␣ .␣ .␣ .␣ 000 and the voltage on the VREF(–) pin is adjusted until the desired negative output voltage is obtained. To trim out gain errors, first the offset error is trimmed. Then the DAC is loaded with the code 111␣ .␣ .␣ .␣ 111 and the voltage on the VREF(+) pin is adjusted until the desired full-scale voltage minus one LSB is obtained. It is not uncommon in ATE design, to have other circuitry at the output of the AD7839 that can have offset and gain errors of up to say ± 300 mV. These offset and gain errors can be easily removed by adjusting the reference voltages of the AD7839. The AD7839 uses nominal reference values of ± 5 V to achieve an output span of ± 10 V. Since the AD7839 has a gain of two from the reference inputs to the DAC output, adjusting the reference voltages by ± 150 mV will adjust the DAC offset and gain by ± 300 mV. DUTGND AB 0.1mF Programmable Reference Generation for the AD7839 in an ATE Application WINDOW COMPARATOR TO TESTER *ADDITIONAL PINS OMITTED FOR CLARITY Figure 21. ATE Application One of the AD588s is used as a reference for DACs A and B. These DACs are used to provide high and low levels for the pin driver. The pin driver may have an associated offset. This can be nulled by applying an offset voltage to Pin 9 of the AD588. First, the code 1000␣ .␣ .␣ .␣ 0000 is loaded into the DACA latch and the pin driver output is set to the DACA output. The VOFFSET voltage is adjusted until 0 V appears between the pin driver output and DUT GND. This causes both VREF(+) and VREF(–) to be offset with respect to GND by an amount equal to VOFFSET. However, the output of the pin driver will vary from –10 V to +10 V with respect to DUTGND as the DAC input code varies from 000␣ .␣ .␣ .␣ 000 to 111␣ .␣ .␣ .␣ 111. The VOFFSET voltage is also applied to the DUTGND pins. When a clear is performed on the AD7839, the output of the pin driver will be 0 V with respect to DUTGND. The other AD588 is used to provide a reference voltage for DACs G and H. These provide the reference voltages for the window comparator shown in the diagram. Note that Pin 9 of this AD588 is connected to Device GND. This causes VREF(+)GH and VREF(–)GH to be referenced to Device GND. As DAC G and DAC H input codes vary from 000␣ .␣ .␣ .␣ 000 to 111␣ .␣ .␣ .␣ 111, VOUTG and VOUTH vary from –10 V to +10 V with respect to Device GND. Device GND is also connected to DUTGND. When the AD7839 is cleared, VOUTG and VOUTH are cleared to 0 V with respect to Device GND. There are a number of suitable 8- and 10-bit DACs available that would be suitable to drive the reference inputs of the AD7839, such as the AD7804, a quad 10-bit digital-to-analog converter with serial load capabilities. The voltage output from this DAC is in the form of VBIAS ± VSWING and rail-to-rail operation is achievable. The voltage reference for this DAC can be internally generated or provided externally. This DAC also contains an 8-bit SUB DAC which can be used to shift the complete transfer function of each DAC around the VBIAS point. This can be used as a fine trim on the output voltage. In this application two AD7804s are required to provide programmable reference capability for all eight DACs. One AD7804 is used to drive the VREF(+) pins and the second package used to drive the VREF(–) pins. Another suitable DAC for providing programmable reference capability is the AD8803. This is an octal 8-bit trimDAC® and provides independent control of both the top and bottom ends of the trimDAC. This is helpful in maximizing the resolution of devices with a limited allowable voltage control range. The AD8803 has an output voltage range of GND to VDD (0 V to +5 V). To trim the VREF(+) input, the appropriate trim range on the AD8803 DAC can be set using the VREFL and VREFH pins allowing 8 bits of resolution between the two points. This will allow the VREF(+) pin to be adjusted to remove gain errors. To trim the VREF(–) voltage, some method of providing a trim voltage in the required negative voltage range is required. Neither the AD7804 or the AD8803 can provide this range in normal operation as their output range is 0 V to +5 V. There are two methods of producing this negative voltage. One method is to provide a positive output voltage and then to level shift that analog voltage to the required negative range. Alternatively TrimDAC is a registered trademark of Analog Devices, Inc. REV. 0 –11– AD7839 digital signals driving the DACs need to be level-shifted from the 0 V to +5 V range to the –5 V to 0 V range. Figure 22 shows a typical application circuit to provide programmable reference capabilities for the AD7839. these DACs can be operated with supplies of 0 V and –5 V, with the VDD pin connected to 0 V and the GND pin connected to –5 V. Now these can be used to provide the negative reference voltages for the VREF(–) inputs on the AD7839. However, the C3168–2–4/99 ADDR BUS +5V ADDR DECODER FSIN/CS 8/10-BIT DAC VDD A0, A1, A2 0V TO +5V D IN SDATA VREF(+)AB SCLK SCLK VOUTA VOUTA GND CONTROLLER AD7839* LOGIC LEVEL SHIFT FSIN/CS 8/10-BIT DAC VDD 0V TO ⴚ5V D IN VREF(ⴚ)AB VOUTB SCLK VOUTB GND ⴚ5V DATA BUS DATA BUS GND *ADDITIONAL PINS OMITTED FOR CLARITY Figure 22. Programmable Reference Generation for the AD7839 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead MQFP (S-44) 0.548 (13.925) 0.546 (13.875) 0.398 (10.11) 0.390 (9.91) 0.096 (2.44) MAX 0.037 (0.94) 0.025 (0.64) 8° 0.8° 33 23 34 22 PRINTED IN U.S.A. SEATING PLANE TOP VIEW (PINS DOWN) 12 44 0.040 (1.02) 0.032 (0.81) 0.040 (1.02) 0.032 (0.81) 0.083 (2.11) 0.077 (1.96) 1 11 0.033 (0.84) 0.029 (0.74) –12– 0.016 (0.41) 0.012 (0.30) REV. 0