a
FEATURES
Specified for V DD of 3 V to 5.5 V
AD7858—200 kSPS; AD7858L—100 kSPS
System and Self-Calibration with Autocalibration on
Power-Up
Eight Single-Ended or Four Pseudo-Differential Inputs
Low Power
AD7858: 12 mW (VDD = 3 V)
AD7858L: 4.5 mW (V DD = 3 V)
Automatic Power-Down After Conversion (25 W)
Flexible Serial Interface:
8051/SPI™/QSPI™/P Compatible
24-Lead DIP, SOIC, and SSOP Packages
APPLICATIONS
Battery-Powered Systems (Personal Digital Assistants,
Medical Instruments, Mobile Communications)
Pen Computers
Instrumentation and Control Systems
High-Speed Modems
GENERAL DESCRIPTION
The AD7858/AD7858L are high-speed, low-power, 12-bit
ADCs that operate from a single 3 V or 5 V power supply, the
AD7858 being optimized for speed and the AD7858L for low
power. The ADC powers up with a set of default conditions at
which time it can be operated as a read-only ADC. The ADC
contains self-calibration and system calibration options to ensure accurate operation over time and temperature and have a
number of power-down options for low-power applications.
The part powers up with a set of default conditions and can
operate as a read-only ADC.
The AD7858 is capable of 200 kHz throughput rate while the
AD7858L is capable of 100 kHz throughput rate. The input
track-and-hold acquires a signal in 500 ns and features a
pseudo-differential sampling scheme. The AD7858/AD7858L
voltage range is 0 to VREF with straight binary output coding.
Input signal range is to the supply and the part is capable of converting full power signals to 100 kHz.
CMOS construction ensures low power dissipation of typically
4.5 mW for normal operation and 1.15 mW in power-down
mode with a throughput rate of 10 kSPS (VDD = 3 V). The part
is available in 24-lead, 0.3 inch-wide dual-in-line package
(DIP), 24-lead small outline (SOIC), and 24-lead small shrink
outline (SSOP) packages.
3 V to 5 V Single Supply, 200 kSPS
8-Channel, 12-Bit Sampling ADC
AD7858/AD7858L
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
AIN1
I/P
MUX
AD7858/
AD7858L
T/H
AIN8
DVDD
2.5V
REFERENCE
COMP
REFIN /REF OUT
DGND
BUF
CREF1
CHARGE
REDISTRIBUTION
DAC
CLKIN
CREF2
CAL
SAR AND ADC
CONTROL
CALIBRATION
MEMORY AND
CONTROLLER
CONVST
BUSY
SLEEP
SERIAL INTERFACE/CONTROL REGISTER
SYNC
DIN
DOUT
SCLK
PRODUCT HIGHLIGHTS
1. Specified for 3 V and 5 V supplies.
2. Automatic calibration on power-up.
3. Flexible power management options including automatic
power-down after conversion.
4. Operates with reference voltages from 1.2 V to VDD.
5. Analog input range from 0 V to VDD.
6. Eight single-ended or four pseudo-differential input channels.
7. System and self-calibration.
8. Versatile serial I/O port (SPI/QSPI/8051/µP).
9. Lower power version AD7858L.
See page 31 for data sheet index.
SPI and QSPI are trademarks of Motorola, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1, 2
(AV = DV = +3.0 V to +5.5 V, REF /REF = 2.5 V External
AD7858/AD7858L–SPECIFICATIONS
Reference unless otherwise noted, f
= 4 MHz (1.8 MHz B Grade (0ⴗC to +70ⴗC), 1 MHz A and B Grades (–40ⴗC to +85ⴗC) for L Version); f
=
DD
DD
IN
OUT
CLKIN
SAMPLE
200 kHz (AD7858), 100 kHz (AD7858L); SLEEP = Logic High; TA = TMIN to TMAX, unless otherwise noted.) Specifications in ( ) apply to the AD7858L.
Parameter
DYNAMIC PERFORMANCE
Signal to Noise + Distortion Ratio3
(SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)
Second Order Terms
Third Order Terms
Channel-to-Channel Isolation
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Total Unadjusted Error
Unipolar Offset Error
Unipolar Offset Error Match
Positive Full-Scale Error
Positive Full-Scale Error Match
ANALOG INPUT
Input Voltage Ranges
Leakage Current
Input Capacitance
REFERENCE INPUT/OUTPUT
REFIN Input Voltage Range
Input Impedance
REFOUT Output Voltage
REFOUT Tempco
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN4
A Version1 B Version1
Units
Test Conditions/Comments
70
71
dB min
–78
–78
–78
–78
dB max
dB max
Typically SNR is 72 dB
VIN = 10 kHz Sine Wave, fSAMPLE = 200 kHz (100 kHz)
VIN = 10 kHz Sine Wave, fSAMPLE = 200 kHz (100 kHz)
VIN = 10 kHz Sine Wave, fSAMPLE = 200 kHz (100 kHz)
–78
–78
–90
–80
–80
–90
dB typ
dB typ
dB typ
fa = 9.983 kHz, fb = 10.05 kHz, fSAMPLE = 200 kHz (100 kHz)
fa = 9.983 kHz, fb = 10.05 kHz, fSAMPLE = 200 kHz (100 kHz)
VIN = 25 kHz
12
±1
±1
12
±1
± 0.5
(± 1)
Any Channel
(± 1)
±1
±1
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
±1
±5
± 2.5
(± 3)
(± 1.5)
1.5
±4
± 1.5
1
±1
±5
± 2.5
(± 3)
(± 1.5)
1.5
±4
± 1.5
1
LSB typ
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
0 to VREF
0 to VREF
Volts
±1
20
±1
20
µA max
pF typ
2.3/VDD
150
2.3/2.7
20
2.3/VDD
150
2.3/2.7
20
V min/max
kΩ typ
V min/max
ppm/°C typ
Functional from 1.2 V
2.4
2.1
0.8
0.6
± 10
10
2.4
2.1
0.8
0.6
± 10
10
V min
V min
V max
V max
µA max
pF max
AVDD = DVDD = 4.5 V to 5.5 V
AVDD = DVDD = 3.0 V to 3.6 V
AVDD = DVDD = 4.5 V to 5.5 V
AVDD = DVDD = 3.0 V to 3.6 V
Typically 10 nA, VIN = 0 V or VDD
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance4
Output Coding
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
4
4
2.4
2.4
0.4
0.4
± 10
± 10
10
10
Straight (Natural) Binary
V min
V min
V max
µA max
pF max
4.6 (18)
µs max
µs max
µs min
0.4 (1)
4.6
(10)
0.4 (1)
–2–
2.5 V External Reference VDD = 3 V, VDD = 5 V (B Grade Only)
5 V External Reference VDD = 5 V
(L Version, 5 V External Reference, VDD = 5 V)
(L Version)
Guaranteed No Missed Codes to 12 Bits. 2.5 V External
Reference VDD = 3 V, 5 V External Reference, VDD = 5 V
Typically ± 2 LSBs
5 V External Reference, VDD = 5 V
(L Version)
(L Version, 5 V External Reference, VDD = 5 V)
5 V External Reference, VDD = 5 V
i.e., AIN(+) – AIN(–) = 0 to VREF, AIN(–) can be biased
up but AIN(+) cannot go below AIN(–)
ISOURCE = 200 µA
AVDD = DVDD = 4.5 V to 5.5 V
AVDD = DVDD = 3.0 V to 3.6 V
ISINK = 0.8 mA
(L Versions Only, –40°C to +85°C, 1 MHz CLKIN)
(L Versions Only, 0°C to +70°C, 1.8 MHz CLKIN)
(L Versions Only)
REV. B
AD7858/AD7858L
Parameter
DYNAMIC PERFORMANCE
AVDD, DVDD
IDD
Normal Mode5
Sleep Mode6
With External Clock On
With External Clock Off
Normal-Mode Power Dissipation
Sleep Mode Power Dissipation
With External Clock On
With External Clock Off
SYSTEM CALIBRATION
Offset Calibration Span7
Gain Calibration Span7
A Version1
B Version1
Units
+3.0/+5.5
+3.0/+5.5
V min/max
6 (1.9)
5.5 (1.9)
6 (1.9)
5.5 (1.9)
mA max
mA max
AVDD = DVDD = 4.5 V to 5.5 V. Typically 4.5 mA (1.5)
AVDD = DVDD = 3.0 V to 3.6 V. Typically 4.0 mA (1.5 mA)
10
10
µA typ
400
400
µA typ
5
5
µA max
200
200
µA typ
33 (10.5)
20 (6.85)
33 (10.5)
20 (6.85)
mW max
mW max
Full Power-Down. Power Management Bits in Control
Register Set as PMGT1 = 1, PMGT0 = 0
Partial Power-Down. Power Management Bits in
Control Register Set as PMGT1 = 1, PMGT0 = 1
Typically 1 µA. Full Power-Down. Power Management Bits
in Control
Register Set as PMGT1 = 1, PMGT0 = 0
Partial Power-Down. Power Management Bits in Control
Register Set as PMGT1 = 1, PMGT0 = 1
VDD = 5.5 V. Typically 25 mW (8); SLEEP = VDD
VDD = 3.6 V. Typically 15 mW (5.4); SLEEP = VDD
55
36
27.5
18
55
36
27.5
18
µW typ
µW typ
µW max
µW max
VDD = 5.5 V. SLEEP = 0 V
VDD = 3.6 V. SLEEP = 0 V
VDD = 5.5 V. Typically 5.5 µW; SLEEP = 0 V
VDD = 3.6 V. Typically 3.6 µW; SLEEP = 0 V
V max/min
V max/min
Allowable Offset Voltage Span for Calibration
Allowable Full-Scale Voltage Span for Calibration
+0.05 × VREF/–0.05 × VREF
+1.025 × VREF/–0.975 × VREF
Test Conditions/Comments
NOTES
1
Temperature ranges as follows: A, B Versions: –40°C to +85°C. For L Versions, A and B Versions f CLKIN = 1 MHz over –40°C to +85°C temperature range,
B Version f CLKIN = 1.8 MHz over 0°C to +70°C temperature range.
2
Specifications apply after calibration.
3
SNR calculation includes distortion and noise components.
4
Sample tested @ +25°C to ensure compliance.
5
All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital outputs. Analog inputs @ AGND.
6
CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital
outputs. Analog inputs @ AGND.
7
The Offset and Gain Calibration Spans are defined as the range of offset and gain errors that the AD7858/AD7858L can calibrate. Note also that these are voltage
spans and are not absolute voltages ( i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–)
± 0.05 × VREF, and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be
VREF ± 0.025 × VREF). This is explained in more detail in the Calibration section of the data sheet.
Specifications subject to change without notice.
REV. B
–3–
AD7858/AD7858L
(AVDD = DVDD = +3.0 V to +5.5 V; fCLKIN = 4 MHz for AD7858 and 1.8/1 MHz for AD7858L;
A
MIN to TMAX , unless otherwise noted)
TIMING SPECIFICATIONS1 T = T
Limit at TMIN, TMAX
(A, B Versions)
5V
3V
Units
Description
500
4
1.8
1
4
100
90
4.6
10 (18)
–0.4 tSCLK
⫿0.4 tSCLK
90
90
115
60
30
0.4 tSCLK
0.4 tSCLK
50
50/0.4 tSCLK
50
130
90
2.5 tCLKIN
2.5 tCLKIN
31.25
kHz min
MHz max
MHz max
MHz max
MHz max
ns min
ns max
µs max
µs max
ns min
ns min/max
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min/max
ns max
ns max
ns max
ns max
ns max
ms typ
Master Clock Frequency
t125
t13
t146
t15
t16
tCAL7
500
4
1.8
1
4
100
50
4.6
10 (18)
–0.4 tSCLK
⫿0.4 tSCLK
50
50
75
40
20
0.4 tSCLK
0.4 tSCLK
30
30/0.4 tSCLK
50
90
50
2.5 tCLKIN
2.5 tCLKIN
31.25
tCAL17
27.78
27.78
ms typ
tCAL27
3.47
3.47
ms typ
Parameter
fCLKIN
2
fSCLK
t1 3
t2
tCONVERT
t3
t4 4
t5 4
t6 4
t7
t8
t9
t10
t11
L Version, 0°C to +70°C, B Grade Only
L Version, –40°C to +85°C
CONVST Pulsewidth
CONVST↓ to BUSY↑ Propagation Delay
Conversion Time = 18 tCLKIN
L Version 1.8 (1) MHz CLKIN. Conversion Time = 18 tCLKIN
SYNC↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input)
SYNC↓ to SCLK↓ Setup Time (Continuous SCLK Input)
Delay from SYNC↓ Until DOUT Three-State Disabled
Delay from SYNC↓ Until DIN Three-State Disabled
Data Access Time After SCLK↓
Data Setup Time Prior to SCLK↑
Data Valid to SCLK Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK↑ to SYNC↑ Hold Time (Noncontinuous SCLK)
(Continuous SCLK)
Delay from SYNC↑ Until DOUT Three-State Enabled
Delay from SCLK↑ to DIN Being Configured as Output
Delay from SCLK↑ to DIN Being Configured as Input
CAL↑ to BUSY↑ Delay
CONVST↓ to BUSY↑ Delay in Calibration Sequence
Full Self-Calibration Time, Master Clock Dependent
(125013 tCLKIN)
Internal DAC Plus System Full-Scale Calibration Time, Master
Clock Dependent (111114 tCLKIN)
System Offset Calibration Time, Master Clock Dependent
(13899 tCLKIN)
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V.
See Table XI and timing diagrams for different interface modes and Calibration.
2
Mark/Space ratio for the master clock input is 40/60 to 60/40.
3
The CONVST pulsewidth will apply here only for normal operation. When the part is in power-down mode, a different CONVST pulsewidth will apply
(see Power-Down section).
4
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
5
t12 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t 12, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
6
t14 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is the
true delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line
knowing that a bus conflict will not occur.
7
The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to
the 1.8/1 MHz master clock.
Specifications subject to change without notice.
–4–
REV. B
AD7858/AD7858L
TYPICAL TIMING DIAGRAMS
Figures 2 and 3 show typical read and write timing diagrams for
serial Interface Mode 2. The reading and writing occurs after
conversion in Figure 2, and during conversion in Figure 3. To
attain the maximum sample rate of 100 kHz (AD7858L) or
200 kHz (AD7858), reading and writing must be performed
during conversion as in Figure 3. At least 400 ns acquisition
time must be allowed (the time from the falling edge of BUSY
to the next rising edge of CONVST) before the next conversion
begins to ensure that the part is settled to the 12-bit level. If the
user does not want to provide the CONVST signal, the conversion can be initiated in software by writing to the control register.
1.6mA
TO
OUTPUT
PIN
IOL
+2.1V
CL
100pF
200A
IOH
Figure 1. Load Circuit for Digital Output Timing
Specifications
tCONVERT = 4.6s MAX, 10s MAX FOR L VERSION
t1 = 100ns MIN, t4 = 50/90ns MAX 5V/3V, t7 = 40/60ns MIN 5V/3V
t1
CONVST (I/P)
tCONVERT
t2
BUSY (O/P)
SYNC (I/P)
t3
5
t4
t6
THREE-STATE
DOUT (O/P)
6
t6
DB15
16
t10
t12
DB11
DB0
THREESTATE
t8
t7
DIN (I/P)
t11
t9
1
SCLK (I/P)
DB15
DB11
DB0
Figure 2. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing After Conversion)
tCONVERT = 4.6s MAX, 10s MAX FOR L VERSION
t1 = 100ns MIN, t4 = 50/90ns MAX 5V/3V, t7 = 40/60ns MIN 5V/3V
t1
CONVST (I/P)
tCONVERT
t2
BUSY (O/P)
SYNC (I/P)
t3
5
t4
DOUT (O/P)
THREE-STATE
6
t6
t6
DB15
DB11
16
t10
t12
DB0
THREESTATE
t8
t7
DIN (I/P)
t11
t9
1
SCLK (I/P)
DB15
DB11
DB0
Figure 3. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing During Conversion)
REV. B
–5–
AD7858/AD7858L
ABSOLUTE MAXIMUM RATINGS 1
SOIC, SSOP Package, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . 75°C/W (SOIC) 115°C/W (SSOP)
θJC Thermal Impedance . . . . 25°C/W (SOIC) 35°C/W (SSOP)
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
REFIN/REFOUT to AGND . . . . . . . . . –0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . ± 10 mA
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 34.7°C/W
Lead Temperature, (Soldering, 10 sec) . . . . . . . . . . +260°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7858/AD7858L features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
AD7858AN
AD7858BN
AD7858LAN3
AD7858LBN3
AD7858AR
AD7858BR
AD7858LAR3
AD7858LBR3
AD7858LARS3
EVAL-AD7858CB4
EVAL-CONTROL BOARD5
Linearity Power
Error
Dissipation Package
(LSB)1
(mW)
Options2
±1
± 1/2
±1
±1
±1
± 1/2
±1
±1
±1
20
20
6.85
6.85
20
20
6.85
6.85
6.85
ESD SENSITIVE DEVICE
PIN CONFIGURATIONS
DIP, SOIC, AND SSOP
ORDERING GUIDE
Model
WARNING!
N-24
N-24
N-24
N-24
R-24
R-24
R-24
R-24
RS-24
CONVST 1
24 SYNC
BUSY 2
23 SCLK
SLEEP 3
22 CLKIN
REFIN /REFOUT 4
AVDD 5
21 DIN
AD7858/
AD7858L
20 DOUT
AGND 6
TOP VIEW 19 DGND
CREF1 7 (Not to Scale) 18 DVDD
CREF2 8
17 CAL
AIN1 9
16 AIN8
AIN2 10
15 AIN7
AIN3 11
14 AIN6
AIN4 12
13 AIN5
NOTES
1
Linearity error here refers to integral linearity error.
2
N = Plastic DIP; R = SOIC; RS = SSOP.
3
L signifies the low-power version.
4
This can be used as a stand-alone evaluation board or in conjunction with the EVALCONTROL BOARD for evaluation/demonstration purposes.
5
This board is a complete unit allowing a PC to control and communicate with all
Analog Devices evaluation boards ending in the CB designators.
–6–
REV. B
AD7858/AD7858L
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Description
1
CONVST
2
BUSY
3
SLEEP
4
REFIN/REFOUT
5
6
7
AVDD
AGND
CREF1
8
CREF2
Convert Start. Logic Input. A low to high transition on this input puts the track/hold into its hold mode
and starts conversion. When this input is not used, it should be tied to DVDD.
Busy Output. The busy output is triggered high by the falling edge of CONVST or rising edge of CAL,
and remains high until conversion is completed. BUSY is also used to indicate when the AD7858/
AD7858L has completed its on-chip calibration sequence.
Sleep Input/Low-Power Mode. A Logic 0 initiates a sleep, and all circuitry is powered down including the
internal voltage reference provided there is no conversion or calibration being performed. Calibration
data is retained. A Logic 1 results in normal operation. See Power-Down section for more details.
Reference Input/Output. This pin is connected to the internal reference through a series resistor and is
the reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V and this
appears at the pin. This pin can be overdriven by an external reference or can be taken as high as AVDD.
When this pin is tied to AVDD, or when an externally applied reference approaches AVDD, the CREF1 pin
should also be tied to AVDD.
Analog Positive Supply Voltage, +3.0 V to +5.5 V.
Analog Ground. Ground reference for track/hold, reference, and DAC.
Reference Capacitor (0.1 µF Multilayer Ceramic). This external capacitor is used as a charge source for
the internal DAC. The capacitor should be tied between the pin and AGND.
Reference Capacitor (0.01 µF Ceramic Disc). This external capacitor is used in conjunction with the onchip reference. The capacitor should be tied between the pin and AGND.
Analog Inputs. Eight analog inputs that can be used as eight single-ended inputs (referenced to AGND)
or four pseudo-differential inputs. Channel configuration is selected by writing to the control register.
Both the positive and negative inputs cannot go below AGND or above AVDD at any time. Also the positive input cannot go below the negative input. See Table III for channel selection.
Calibration Input. This pin has an internal pull-up current source of 0.15 µA. A Logic 0 on this pin resets
all calibration control logic and initiates a calibration on its rising edge. There is the option of connecting
a 10 nF capacitor from this pin to DGND to allow for an automatic self-calibration on power-up. This
input overrides all other internal operations. If the autocalibration is not required, this pin should be tied
to a logic high.
Digital Supply Voltage, +3.0 V to +5.5 V.
Digital Ground. Ground reference point for digital circuitry.
Serial Data Output. The data output is supplied to this pin as a 16-bit serial word.
Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can
act as an input pin or as a I/O pin depending on the serial interface mode the part is in (see Table X).
Master clock signal for the device (4 MHz AD7858, 1.8 MHz AD7858L). Sets the conversion and calibration times.
Serial Port Clock. Logic Input. The user must provide a serial clock on this input.
Frame Sync. Logic Input. This pin is level triggered active low and frames the serial clock for the read
and write operations (see Table IX).
9–16 AIN1–AIN8
17
CAL
18
19
20
21
DVDD
DGND
DOUT
DIN
22
CLKIN
23
24
SCLK
SYNC
REV. B
–7–
AD7858/AD7858L
TERMINOLOGY1
Integral Nonlinearity
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7858/AD7858L, it is
defined as:
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.
THD ( dB ) = 20 log
Differential Nonlinearity
2
2
2
2
2
(V2 + V3 + V4 + V5 + V6 )
V1
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Total Unadjusted Error
Peak Harmonic or Spurious Noise
This is the deviation of the actual code from the ideal code taking all errors into account (Gain, Offset, Integral Nonlinearity, and
other errors) at any point along the transfer function.
Unipolar Offset Error
This is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB).
Positive Full-Scale Error
This is the deviation of the last code transition from the ideal
AIN(+) voltage (AIN(–) + Full Scale – 1.5 LSB) after the offset
error has been adjusted out.
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and
(fa – 2fb).
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of crosstalk between
the channels. It is measured by applying a full-scale 25 kHz
signal to the other seven channels and determining how much
that signal is attenuated in the channel of interest. The figure
given is the worst case for all channels.
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode and the end of
conversion. Track/hold acquisition time is the time required for
the output of the track/hold amplifier to reach its final value,
within ± 1/2 LSB, after the end of conversion.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (fS/2), excluding dc. The ratio
is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise.
The theoretical signal to (noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by:
Testing is performed using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used. In
this case, the second order terms are usually distanced in frequency from the original sine waves, while the third order terms
are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the
THD specification where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals expressed in dBs.
Signal to (Noise + Distortion) = (6.02 N +1.76) dB
Thus for a 12-bit converter, this is 74 dB.
1
AIN(+) refers to the positive input of the pseudo differential pair, and AIN(–)
refers to the negative analog input of the pseudo differential pair or to AGND
depending on the channel configuration.
–8–
REV. B
AD7858/AD7858L
ON-CHIP REGISTERS
The AD7858/AD7858L powers up with a set of default conditions. The only writing required is to select the channel configuration.
Without performing any other write operations the AD7858/AD7858L still retains the flexibility for performing a full power-down
and a full self-calibration.
Extra features and flexibility, such as performing different power-down options, different types of calibrations including system
calibration, and software conversion start, can be selected by further writing to the part.
The AD7858/AD7858L contains a Control Register, ADC Output Data Register, Status Register, Test Register, and
10 Calibration Registers. The control register is write-only, the ADC output data register and the status register are read-only, and
the test and calibration registers are both read/write registers. The Test Register is used for testing the part and should not be written to.
Addressing the On-Chip Registers
Writing
A write operation to the AD7858/AD7858L consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine
which register is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are
written that the data is latched into the addressed registers. Table I shows the decoding of the address bits while Figure 4 shows the
overall write register hierarchy.
Table I. Write Register Addressing
ADDR1
ADDR0
Comment
0
0
0
1
1
0
1
1
This combination does not address any register so the subsequent 14 data bits are ignored.
This combination addresses the TEST REGISTER. The subsequent 14 data bits are written to the test
register.
This combination addresses the CALIBRATION REGISTERS. The subsequent 14 data bits are written
to the selected calibration register.
This combination addresses the CONTROL REGISTER. The subsequent 14 data bits are written to the
control register.
Reading
To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These
bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address
bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be
from the ADC output data register.
Once the read selection bits are set in the Control Register, all subsequent read operations that follow will be from the selected register until the read selection bits are changed in the Control Register.
Table II. Read Register Addressing
RDSLT1
RDSLT0 Comment
0
0
0
1
1
1
0
1
All successive read operations will be from ADC OUTPUT DATA REGISTER. This is the power-up
default setting. There will always be 4 leading zeros when reading from the ADC Output Data Register.
All successive read operations will be from TEST REGISTER.
All successive read operations will be from CALIBRATION REGISTERS.
All successive read operations will be from STATUS REGISTER.
RDSLT1, RDSLT0
DECODE
ADDR1, ADDR0
DECODE
01
10
TEST
REGISTER
CALSLT1, CALSLT0
DECODE
GAIN(1)
OFFSET(1)
DAC(8)
GAIN(1)
OFFSET(1)
00
01
00
11
CALIBRATION
REGISTERS
OFFSET(1)
10
ADC OUTPUT
DATA REGISTER
CONTROL
REGISTER
10
TEST
REGISTER
GAIN(1)
OFFSET(1)
DAC(8)
GAIN(1)
11
CALSLT1, CALSLT0
DECODE
Figure 4. Write Register Hierarchy/Address Decoding
REV. B
01
00
11
CALIBRATION
REGISTERS
GAIN(1)
OFFSET(1)
01
OFFSET(1)
10
STATUS
REGISTER
GAIN(1)
11
Figure 5. Read Register Hierarchy/Address Decoding
–9–
AD7858/AD7858L
CONTROL REGISTER
The arrangement of the Control Register is shown below. The control register is a write only register and contains 14 bits of data.
The control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are described below. The power-up status of all bits is 0.
MSB
SGL/DIFF
RDSLT0
CH2
CH1
CH0
PMGT1
PMGT0
RDSLT1
2/3 MODE
CONVST
CALMD
CALSLT1
CALSLT0
STCAL
LSB
CONTROL REGISTER BIT FUNCTION DESCRIPTION
Bit
Mnemonic
Comment
13
SGL/DIFF
12
11
10
9
8
7
6
5
CH2
CH1
CH0
PMGT1
PMGT0
RDSLT1
RDSLT0
2/3 MODE
A 0 in this bit position configures the input channels in pseudo-differential mode. A 1 in this bit position
configures the input channels in single-ended mode (see Table III).
These three bits are used to select the channel on which the conversion is performed. The channels can
be configured as eight single-ended channels or four pseudo-differential channels. The default selection
is AIN1 for the positive input and AIN2 for the negative input (see Table III for channel selection).
Power Management Bits. These two bits are used with the SLEEP pin for putting the part into various
Power-Down Modes (see Power-Down section for more details).
Theses two bits determine which register is addressed for the read operations (see Table II).
4
CONVST
3
2
1
0
CALMD
CALSLT1
CALSLT0
STCAL
Interface Mode Select Bit. With this bit set to 0, Interface Mode 2 is enabled. With this bit set to 1,
Interface Mode 1 is enabled where DIN is used as an output as well as an input. This bit is set to 0 by
default after every read cycle; thus when using the Two-Wire Interface Mode, this bit needs to be set to
1 in every write cycle.
Conversion Start Bit. A logic one in this bit position starts a single conversion, and this bit is automatically reset to 0 at the end of conversion. This bit may also be used in conjunction with system calibration
(see Calibration section.)
Calibration Mode Bit. A 0 here selects self-calibration, and a 1 selects a system calibration (see Table IV).
Calibration Selection Bits and Start Calibration Bit. These bits have two functions.
With the STCAL bit set to 1 the CALSLT1 and CALSLT0 bits determine the type of calibration per
formed by the part (see Table IV). The STCAL bit is automatically reset to 0 at the end of calibration.
With the STCAL bit set to 0 the CALSLT1 and CALSLT0 bits are decoded to address the calibration
register for read/write of calibration coefficients (see section on the Calibration Registers for more details).
–10–
REV. B
AD7858/AD7858L
Table III. Channel Selection
SGL/DIFF
CH2
CH1
CH0
AIN(+)*
AIN(–)*
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
AIN1
AIN3
AIN5
AIN7
AIN2
AIN4
AIN6
AIN8
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
AIN2
AIN4
AIN6
AIN8
AIN1
AIN3
AIN5
AIN7
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
AIN1
AIN3
AIN5
AIN7
AGND
AGND
AGND
AGND
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
AIN2
AIN4
AIN6
AIN8
AGND
AGND
AGND
AGND
*AIN(+) refers to the positive input seen by the AD7858/AD7858L sample and hold circuit,
*AIN(–) refers to the negative input seen by the AD7858/AD7858L sample and hold circuit.
Table IV. Calibration Selection
CALMD
CALSLT1
CALSLT0
Calibration Type
0
0
0
A Full Internal Calibration is initiated where the Internal DAC is calibrated
followed by the Internal Gain Error, and finally the Internal Offset Error is
calibrated out. This is the default setting.
0
0
1
Here the Internal Gain Error is calibrated out followed by the Internal Offset
Error calibrated out.
0
1
0
This calibrates out the Internal Offset Error only.
0
1
1
This calibrates out the Internal Gain Error only.
1
0
0
A Full System Calibration is initiated here where first the Internal DAC is
calibrated followed by the System Gain Error, and finally the System Offset
Error is calibrated out.
1
0
1
Here the System Gain Error is calibrated out followed by the System Offset
Error.
1
1
0
This calibrates out the System Offset Error only.
1
1
1
This calibrates out the System Gain Error only.
REV. B
–11–
AD7858/AD7858L
STATUS REGISTER
The arrangement of the Status Register is shown below. The status register is a read-only register and contains 16 bits of data. The
status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the bits
in the status register are described below. The power-up status of all bits is 0.
START
WRITE TO CONTROL REGISTER
SETTING RDSLT0 = RDSLT1 = 1
READ STATUS REGISTER
Figure 6. Flowchart for Reading the Status Register
MSB
ZERO
BUSY
SGL/DIFF
CH2
RDSLT1
RDSLT0
2/3 MODE
X
CH1
CALMD
CH0
PMGT1
PMGT0
CALSLT1
CALSLT0
STCAL
LSB
STATUS REGISTER BIT FUNCTION DESCRIPTION
Bit
Mnemonic
Comment
15
ZERO
This bit is always 0.
14
BUSY
Conversion/Calibration Busy Bit. When this bit is 1, it indicates that there is a conversion
or calibration in progress. When this bit is 0, there is no conversion or calibration in progress.
13
12
11
10
SGL/DIFF
CH2
CH1
CH0
These four bits indicate the channel selected for conversion (see Table III).
9
8
PMGT1
PMGT0
Power management bits. These bits along with the SLEEP pin will indicate if the part is in a
power-down mode or not. See Table VI for description.
7
6
RDSLT1
RDSLT0
Both of these bits are always 1, indicating it is the status register being read (see Table II).
5
2/3 MODE
Interface Mode Select Bit. With this bit at 0, the device is in Interface Mode 2. With this bit at
1, the device is in Interface Mode 1. This bit is reset to 0 after every read cycle.
4
X
Don’t care bit.
3
CALMD
Calibration Mode Bit. A 0 in this bit indicates a self-calibration is selected, and a 1 in this bit
indicates a system calibration is selected (see Table IV).
2
1
0
CALSLT1
CALSLT0
STCAL
Calibration Selection Bits and Start Calibration Bit. The STCAL bit is read as a 1 if a
calibration is in progress and as a 0 if there is no calibration in progress. The CALSLT1 and
CALSLT0 bits indicate which of the calibration registers are addressed for reading and writing
(see section on the Calibration Registers for more details).
–12–
REV. B
AD7858/AD7858L
CALIBRATION REGISTERS
The AD7858/AD7858L has 10 calibration registers in all, eight for the DAC, one for the offset, and one for gain. Data can be written
to or read from all 10 calibration registers. In self- and system calibration the part automatically modifies the calibration registers; only if the
user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers.
Addressing the Calibration Registers
The calibration selection bits in the control register CALSLT1 and CALSLT0 determine which of the calibration registers are addressed (see Table V). The addressing applies to both the read and write operations for the calibration registers. The user should not
attempt to read from and write to the calibration registers at the same time.
Table V. Calibration Register Addressing
CALSLT1
CALSLT0
Comment
0
0
1
1
0
1
0
1
This combination addresses the Gain (1), Offset (1) and DAC Registers (8). Ten registers in total.
This combination addresses the Gain (1) and Offset (1) Registers. Two registers in total.
This combination addresses the Offset Register. One register in total.
This combination addresses the Gain Register. One register in total.
Writing to/Reading from the Calibration Registers
For writing to the calibration registers a write to the control
register is required to set the CALSLT0 and CALSLT1 bits.
For reading from the calibration registers a write to the control
register is required to set the CALSLT0 and CALSLT1 bits,
but also to set the RDSLT1 and RDSLT0 bits to 10 (this addresses the calibration registers for reading). The calibration
register pointer is reset on writing to the control register setting
the CALSLT1 and CALSLT0 bits, or upon completion of all
the calibration register write/read operations. When reset it
points to the first calibration register in the selected write/read
sequence. The calibration register pointer will point to the gain
calibration register upon reset in all but one case, this case being
where the offset calibration register is selected on its own
(CALSLT1 = 1, CALSLT0 = 0). Where more than one calibration register is being accessed the calibration register pointer will
be automatically incremented after each calibration register
write/read operation. The order in which the 10 calibration
registers are arranged is shown in Figure 7. The user may abort
at any time before all the calibration register write/read operations are completed, and the next control register write operation will reset the calibration register pointer. The flow chart in
Figure 8 shows the sequence for writing to the calibration registers and Figure 9 for reading.
When reading from the calibration registers there will always be
two leading zeros for each of the registers. When operating in
Serial Interface Mode 1 the read operations to the calibration
registers cannot be aborted. The full number of read operations
must be completed (see section on Serial Interface Mode 1
Timing for more detail).
CALIBRATION REGISTERS
CAL REGISTER
ADDRESS POINTER
CALIBRATION REGISTER
ADDRESS POINTER
POSITION IS DETERMINED
BY THE NUMBER OF
CALIBRATION REGISTERS
ADDRESSED AND THE
NUMBER OF READ/WRITE
OPERATIONS
GAIN REGISTER
(1)
OFFSET REGISTER
(2)
DAC 1ST MSB REGISTER
(3)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
CAL REGISTER POINTER IS
AUTOMATICALLY RESET
WRITE TO CAL REGISTER
(ADDR1 = 1, ADDR0 = 0)
CAL REGISTER POINTER IS
AUTOMATICALLY INCREMENTED
LAST
REGISTER
WRITE
OPERATION
OR
ABORT
?
NO
FINISHED
Figure 8. Flowchart for Writing to the Calibration Registers
(10)
Figure 7. Calibration Register Arrangements
REV. B
WRITE TO CONTROL REGISTER SETTING STCAL = 0
AND CALSLT1, CALSLT0 = 00, 01, 10, 11
YES
.
.
.
.
.
.
.
DAC 8TH MSB REGISTER
START
–13–
AD7858/AD7858L
Q. If a +20 mV offset is present in the analog input signal and the
reference voltage is 2.5 V what code needs to be written to the
offset register to compensate for the offset?
START
WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1,
RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11
A. 2.5 V reference implies that the resolution in the offset register is 5% × 2.5 V/213 = 0.015 mV. +20 mV/0.015 mV =
1310.72; rounding to the nearest number gives 1311. In
binary terms this is 0101 0001 1111. Therefore, decrease the
offset register by 0101 0001 1111.
CAL REGISTER POINTER IS
AUTOMATICALLY RESET
This method of compensating for offset in the analog input
signal allows for fine tuning the offset compensation. If the
offset on the analog input signal is known, there will be no need
to apply the offset voltage to the analog input pins and do a
system calibration. The offset compensation can take place in
software.
READ CAL REGISTER
CAL REGISTER POINTER IS
AUTOMATICALLY INCREMENTED
LAST
REGISTER
READ
OPERATION
OR
ABORT
?
Adjusting the Gain Calibration Register
The gain calibration register contains 16 bits, two leading 0s
and 14 data bits. The data bits are binary weighted as in the
offset calibration register. The gain register value is effectively
multiplied by the analog input to scale the conversion result
over the full range. Increasing the gain register compensates for
a smaller analog input range and decreasing the gain register
compensates for a larger input range. The maximum analog
input range that the gain register can compensate for is 1.025
times the reference voltage, and the minimum input range is
0.975 times the reference voltage.
NO
YES
FINISHED
Figure 9. Flowchart for Reading from the Calibration
Registers
Adjusting the Offset Calibration Register
The offset calibration register contains 16 bits, two leading zeros,
and 14 data bits. By changing the contents of the offset register
different amounts of offset on the analog input signal can be
compensated for. Increasing the number in the offset calibration
register compensates for negative offset on the analog input
signal, and decreasing the number in the offset calibration register compensates for positive offset on the analog input signal.
The default value of the offset calibration register is 0010 0000
0000 0000 approximately. This is not an exact value, but the
value in the offset register should be close to this value. Each of
the 14 data bits in the offset register is binary weighted; the
MSB has a weighting of 5% of the reference voltage, the MSB-1
has a weighting of 2.5%, the MSB-2 has a weighting of 1.25%,
and so on down to the LSB which has a weighting of 0.0006%.
This gives a resolution of ± 0.0006% of VREF approximately.
More accurately the resolution is ± (0.05 × VREF )/213 volts =
± 0.015 mV, with a 2.5 V reference. The maximum offset that
can be compensated for is ± 5% of the reference voltage, which
equates to ± 125 mV with a 2.5 V reference and ± 250 mV with
a 5 V reference.
–14–
REV. B
AD7858/AD7858L
CIRCUIT INFORMATION
The AD7858/AD7858L is a fast, 12-bit single supply A/D converter. The part requires an external 4 MHz/1.8 MHz master
clock (CLKIN), two CREF capacitors, a CONVST signal to start
conversion, and power supply decoupling capacitors. The part
provides the user with track/hold, on-chip reference, calibration
features, A/D converter, and serial interface logic functions on a
single chip. The A/D converter section of the AD7858/AD7858L
consists of a conventional successive-approximation converter
based around a capacitor DAC. The AD7858/AD7858L accepts
an analog input range of 0 to +VDD where the reference can be
tied to VDD. The reference input to the part is buffered on-chip.
A major advantage of the AD7858/AD7858L is that a conversion
can be initiated in software as well as applying a signal to the
CONVST pin. Another innovative feature of the AD7858/
AD7858L is self-calibration on power-up, which is initiated
having a capacitor from the CAL pin to AGND, to give superior
dc accuracy. See Automatic Calibration on Power-Up section.
The part is available in a 24-pin SSOP package and this offers
the user considerable space-saving advantages over alternative
solutions. The AD7858L version typically consumes only
5.5 mW making it ideal for battery-powered applications.
CONVERTER DETAILS
The master clock for the part must be applied to the CLKIN
pin. Conversion is initiated on the AD7858/AD7858L by pulsing
the CONVST input or by writing to the control register and
setting the CONVST bit to 1. On the rising edge of CONVST
(or at the end of the control register write operation), the onchip track/hold goes from track to hold mode. The falling edge
of the CLKIN signal that follows the rising edge of the CONVST
signal initiates the conversion, provided the rising edge of
CONVST occurs at least 10 ns typically before this CLKIN
edge. The conversion cycle will take 16.5 CLKIN periods from
this CLKIN falling edge. If the 10 ns setup time is not met, the
conversion will take 17.5 CLKIN periods. The maximum specified conversion time is 4.6 µs for the AD7858 (18tCLKIN,
CLKIN = 4 MHz) and 10 µs for the AD7858L (18tCLKIN,
CLKIN = 1.8 MHz). When a conversion is completed, the
BUSY output goes low, and then the result of the conversion
can be read by accessing the data through the serial interface.
To obtain optimum performance from the part, the read operation should not occur during the conversion or 400 ns prior to
the next CONVST rising edge. However, the maximum
throughput rates are achieved by reading/writing during conversion, and reading/writing during conversion is likely to degrade
the Signal to (Noise + Distortion) by only 0.5 dBs. The AD7858
can operate at throughput rates up to 200 kHz, 100 kHz for the
AD7858L. For the AD7858 a conversion takes 18 CLKIN
periods; 2 CLKIN periods are needed for the acquisition time
giving a full cycle time of 5 µs (= 200 kHz, CLKIN = 4 MHz).
For the AD7858L 100 kHz throughput can be obtained as
follows: the CLKIN and CONVST signals are arranged to give
a conversion time of 16.5 CLKIN periods as described above,
1.5 CLKIN periods are allowed for the acquisition time. This
gives a full cycle time of 10 µs (=100 kHz, CLKIN = 1.8 MHz).
When using the software conversion start for maximum throughput the user must ensure the control register write operation
extends beyond the falling edge of BUSY. The falling edge of
BUSY resets the CONVST bit to 0 and allows it to be reprogrammed to 1 to start the next conversion.
TYPICAL CONNECTION DIAGRAM
Figure 10 shows a typical connection diagram for the AD7858/
AD7858L. The AGND and the DGND pins are connected
together at the device for good noise suppression. The CAL pin
has a 0.01 µF capacitor to enable an automatic self-calibration
on power-up. The conversion result is output in a 16-bit word
with four leading zeros followed by the MSB of the 12-bit result.
Note that after the AVDD and DVDD power-up the part will
4MHz/1.8MHz OSCILLATOR
200kHz/100kHz PULSE GENERATOR
ANALOG SUPPLY
+3V TO +5V
10F
MASTER CLOCK
INPUT
0.1F
0.1F
CONVERSION
START INPUT
AVDD DVDD
0V TO 2.5V
INPUT
0.1F
0.01F
DVDD
0.01F
AIN(–)
SCLK
CREF1
CREF2
OSCILLOSCOPE
CLKIN
AIN(+)
CH1
SERIAL CLOCK
INPUT
CONVST
AD7858/
AD7858L
SLEEP
CH2
SYNC
CH3
FRAME SYNC INPUT
DIN
CH5
DOUT
AGND
AUTO CAL ON
POWER-UP
CH4
SERIAL DATA INPUT
CAL
SERIAL DATA
OUTPUT
DGND
0.1F
INTERNAL/
EXTERNAL
REFERENCE
OPTIONAL
AD780/
EXTERNAL
REF-192
REFERENCE
DATA GENERATOR
PULSE GENERATOR
Figure 10. Typical Circuit
REV. B
–15–
4 LEADING
ZEROS FOR
ADC DATA
AD7858/AD7858L
For applications where power consumption is a major concern
then the SLEEP pin can be connected to DGND. See PowerDown section for more detail on low power applications.
ANALOG INPUT
The equivalent circuit of the analog input section is shown in
Figure 11. During the acquisition interval the switches are both
in the track position and the AIN(+) charges the 20 pF capacitor
through the 125 Ω resistance. On the rising edge of CONVST
switches SW1 and SW2 go into the hold position retaining
charge on the 20 pF capacitor as a sample of the signal on
AIN(+). The AIN(–) is connected to the 20 pF capacitor, and
this unbalances the voltage at node A at the input of the comparator. The capacitor DAC adjusts during the remainder of the
conversion cycle to restore the voltage at node A to the correct
value. This action transfers a charge, representing the analog
input signal, to the capacitor DAC which in turn forms a digital
representation of the analog input signal. The voltage on the
AIN(–) pin directly influences the charge transferred to the
capacitor DAC at the hold instant. If this voltage changes during the conversion period, the DAC representation of the analog
input voltage will be altered. Therefore it is most important that
the voltage on the AIN(–) pin remains constant during the conversion period. Furthermore it is recommended that the AIN(–)
pin is always connected to AGND or to a fixed dc voltage.
For ac applications, removing high frequency components from
the analog input signal is recommended by use of an RC lowpass filter on the AIN(+) pin as shown in Figure 13. In applications where harmonic distortion and signal to noise ratio are
critical the analog input should be driven from a low impedance
source. Large source impedances will significantly affect the ac
performance of the ADC. This may necessitate the use of an
input buffer amplifier. The choice of the op amp will be a function of the particular application.
When no amplifier is used to drive the analog input the source
impedance should be limited to low values. The maximum
source impedance will depend on the amount of total harmonic
distortion (THD) that can be tolerated. The THD will increase
as the source impedance increases and performance will degrade. Figure 12 shows a graph of the total harmonic distortion
versus analog input signal frequency for different source impedances. With the setup as in Figure 13, the THD is at the –90 dB
level. With a source impedance of 1 kΩ and no capacitor on the
AIN(+) pin, the THD increases with frequency.
–72
THD vs. FREQUENCY FOR DIFFERENT
SOURCE IMPEDANCES
–76
RIN = 1k⍀
THD – dB
require approximately 150 ms for the internal reference to settle
and for the automatic calibration on power-up to be completed.
Acquisition Time
The track and hold amplifier enters its tracking mode on the
falling edge of the BUSY signal. The time required for the track
and hold amplifier to acquire an input signal will depend on
how quickly the 20 pF input capacitance is charged. The acquisition time is calculated using the formula:
–80
–84
RIN = 50⍀, 10nF
AS IN FIGURE 13
–88
–92
0
tACQ = 9 × (RIN + 125 Ω) × 20 pF
where RIN is the source impedance of the input signal, and
125 Ω, 20 pF is the input R, C.
125⍀
TRACK
AIN(+)
AIN(–)
125⍀
SW1
HOLD
CAPACITOR
DAC
20pF
NODE A
SW2
TRACK
HOLD
COMPARATOR
CREF2
Figure 11. Analog Input Equivalent Circuit
DC/AC Applications
20
40
60
INPUT FREQUENCY – kHz
80
100
Figure 12. THD vs. Analog Input Frequency
In a single supply application (both 3 V and 5 V), the V+ and
V– of the op amp can be taken directly from the supplies to the
AD7858/AD7858L which eliminates the need for extra external
power supplies. When operating with rail-to-rail inputs and
outputs, at frequencies greater than 10 kHz care must be taken
in selecting the particular op amp for the application. In particular for single supply applications the input amplifiers should be
connected in a gain of –1 arrangement to get the optimum performance. Figure 13 shows the arrangement for a single supply
application with a 50 Ω and 10 nF low-pass filter (cutoff frequency 320 kHz) on the AIN(+) pin. Note that the 10 nF is a
capacitor with good linearity to ensure good ac performance.
Recommended single supply op amps are the AD820 and the
AD820-3 V.
For dc applications high source impedances are acceptable
provided there is enough acquisition time between conversions
to charge the 20 pF capacitor. The acquisition time can be
calculated from the above formula for different source impedances. For example with RIN = 5 kΩ, the required acquisition
time will be 922 ns.
+3V TO +5V
10k⍀
VIN
(0 TO VREF)
10k⍀
V+
10F
0.1F
50⍀
10k⍀
VREF
10k⍀
V+ AD820
AD820-3V
10nF
(NPO)
TO AIN(+) OF
AD7858/AD7858L
Figure 13. Analog Input Buffering
–16–
REV. B
AD7858/AD7858L
Input Range
REFERENCE SECTION
The analog input range for the AD7858/AD7858L is 0 V to
VREF. The AIN(–) pin on the AD7858/AD7858L can be biased
up above AGND, if required. The advantage of biasing the
lower end of the analog input range away from AGND is that
the user does not need to have the analog input swing all the
way down to AGND. This has the advantage in true singlesupply applications that the input amplifier does not need to
swing all the way down to AGND. The upper end of the analog
input range is shifted up by the same amount. Care must be
taken so that the bias applied does not shift the upper end of the
analog input above the AVDD supply. In the case where the
reference is the supply, AVDD, the AIN(–) must be tied to
AGND.
For specified performance, it is recommended that when using
an external reference this reference should be between 2.3 V
and the analog supply AVDD. The connections for the relevant
reference pins are shown in the typical connection diagrams. If
the internal reference is being used, the REFIN/REFOUT pin
should have a 100 nF capacitor connected to AGND very close
to the REFIN/REFOUT pin. These connections are shown in
Figure 16.
AIN(+)
VIN = 0 TO VREF
TRACK AND HOLD
AMPLIFIER
DOUT
AIN(–)
If the internal reference is required for use external to the ADC,
it should be buffered at the REFIN/REFOUT pin and a 100 nF
connected from this pin to AGND. The typical noise performance
for the internal reference, with 5 V supplies, is 150 nV/√Hz @
1 kHz and dc noise is 100 µV p-p.
ANALOG SUPPLY
+3V TO +5V
STRAIGHT
BINARY
FORMAT
10F
0.1F
0.1F
AVDD
DVDD
CREF1
AD7858/
AD7858L
0.1F
CREF2
Figure 14. 0 to VREF Input Configuration
AD7858/
AD7858L
0.01F
Transfer Function
For the AD7858/AD7858L input range the designed code transitions occur midway between successive integer LSB values
(i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . . FS – 3/2 LSBs). The
output coding is straight binary with 1 LSB = FS/4096 = 3.3 V/
4096 = 0.8 mV when VREF = 3.3 V. The ideal input/output
transfer characteristic is shown in Figure 15.
OUTPUT
CODE
111...111
111...110
111...101
111...100
000...011
1LSB = FS
4096
000...010
REFIN/REFOUT
0.1F
Figure 16. Relevant Connections When Using Internal
Reference
The other option is that the REFIN/REFOUT pin be overdriven
by connecting it to an external reference. This is possible due to
the series resistance from the REFIN/REFOUT pin to the internal
reference. This external reference can have a range that includes
AVDD. When using AVDD as the reference source, the 100 nF
capacitor from the REFIN/REFOUT pin to AGND should be as
close as possible to the REFIN/REFOUT pin, and also the CREF1
pin should be connected to AVDD to keep this pin at the same
level as the reference. The connections for this arrangement are
shown in Figure 17. When using AVDD it may be necessary to
add a resistor in series with the AVDD supply. This will have the
effect of filtering the noise associated with the AVDD supply.
000...001
ANALOG SUPPLY
+3V TO +5V
000...000
0V 1LSB
10F
0.1F
0.1F
+FS –1LSB
VIN = (AIN(+) – AIN(–)), INPUT VOLTAGE
AVDD
Figure 15. AD7858/AD7858L Transfer Characteristic
DVDD
CREF1
0.1F
CREF2
AD7858/
AD7858L
0.01F
REFIN/REFOUT
0.1F
Figure 17. Relevant Connections When Using AVDD as the
Reference
REV. B
–17–
AD7858/AD7858L
PERFORMANCE CURVES
–78
AVDD = DVDD = 3.3V/5.0V,
Figure 18 shows a typical FFT plot for the AD7858 at 200 kHz
sample rate and 10 kHz input frequency.
100mVp-p SINE WAVE ON AVDD
–80
0
–82
–20
PSRR – dB
AVDD = DVDD = 3.3V
fSAMPLE = 200kHz
fIN = 10kHz
SNR = 72.04dB
THD = –88.43dB
3.3V
–84
–40
SNR – dB
–86
5.0V
–60
–88
–80
–90
0
–100
20
40
60
INPUT FREQUENCY – kHz
80
100
Figure 20. PSRR vs. Frequency
–120
0
20
40
60
FREQUENCY – kHz
80
100
Figure 18. FFT Plot
Figure 19 shows the SNR vs. Frequency for different supplies
and different external references.
74
AVDD = DVDD WITH 2.5V REFERENCE
UNLESS STATED OTHERWISE
S(N+D) RATIO – dB
73
5.0V SUPPLIES, WITH 5V REFERENCE
72
5.0V SUPPLIES
5.0V SUPPLIES, L VERSION
71
3.3V SUPPLIES
70
69
0
20
40
60
INPUT FREQUENCY – kHz
80
100
Figure 19. SNR vs. Frequency
Figure 20 shows the Power Supply Rejection Ratio vs. Frequency for the part. The Power Supply Rejection Ratio is defined as the ratio of the power in adc output at frequency f to
the power of a full-scale sine wave.
PSRR (dB) = 10 log (Pf/Pfs)
Pf = Power at frequency f in adc output, Pfs = power of a
full-scale sine wave. Here a 100 mV peak-to-peak sine wave is
coupled onto the AVDD supply while the digital supply is left
unaltered. Both the 3.3 V and 5.0 V supply performances are
shown.
POWER-DOWN OPTIONS
The AD7858 provides flexible power management to allow the
user to achieve the best power performance for a given throughput rate. The power management options are selected by
programming the power management bits, PMGT1 and PMGT0,
in the control register and by use of the SLEEP pin. Table VI
summarizes the power-down options that are available and how
they can be selected by using either software, hardware, or a
combination of both. The AD7858 can be fully or partially
powered down. When fully powered down, all the on-chip circuitry is powered down and IDD is 1 µA typ. If a partial powerdown is selected, then all the on-chip circuitry except the reference
is powered down and IDD is 400 µA typ. The choice of full or partial power-down does not give any significant improvement in
throughput with a power-down between conversions. This is
discussed in the next section–Power-Up Times. However, a
partial power-down does allow the on-chip reference to be used
externally even though the rest of the AD7858 circuitry is powered down. It also allows the AD7858 to be powered up faster
after a long power-down period when using the on-chip reference (See Power-Up Times–Using On-Chip Reference).
When using the SLEEP pin, the power management bits PMGT1
and PMGT0 should be set to zero (default status on power-up).
Bringing the SLEEP pin logic high ensures normal operation,
and the part does not power down at any stage. This may be
necessary if the part is being used at high throughput rates when
it is not possible to power down between conversions. If the user
wishes to power down between conversions at lower throughput
rates (i.e.
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