AD7864AS-2REEL

4-Channel, Simultaneous Sampling, High Speed, 12-Bit ADC AD7864 FEATURES High Speed (1.65 s) 12-Bit ADC 4 Simultaneously Sampled Inputs 4 Track/Hold Amplifiers 0.35 s Track/Hold Acquisition Time 1.65 s Conversion Time per Channel HW/SW Select of Channel Sequence for Conversion Single-Supply Operation Selection of Input Ranges: 10 V, 5 V for AD7864-1 2.5 V for AD7864-3 0 V to 2.5 V, 0 V to 5 V for AD7864-2 High Speed Parallel Interface that Allows Interfacing to 3 V Processors Low Power, 90 mW Typ Power Saving Mode, 20 W Typ Overvoltage Protection on Analog Inputs APPLICATIONS AC Motor Control Uninterrupted Power Supplies Data Acquisition Systems Communications GENERAL DESCRIPTION The AD7864 is a high speed, low power, 4-channel simultaneous sampling 12-bit A/D converter that operates from a single 5 V supply. The part contains a 1.65 ms successive approximation ADC, four track/hold amplifiers, a 2.5 V reference, an on-chip clock oscillator, signal conditioning circuitry, and a high speed parallel interface. The input signals on four channels are sampled simultaneously, thus preserving the relative phase information of the signals on the four analog inputs. The part accepts analog input ranges of ± 10 V, ± 5 V (AD7864-1), 0 V to +2.5 V, 0 V to +5 V (AD7864-2), and ± 2.5 V (AD7864-3). The part allows any subset of the four channels to be converted in order to maximize the throughput rate on the selected sequence. The channels to be converted can be selected via hardware (channel select input pins) or software (programming the channel select register). A single conversion start signal (CONVST) simultaneously places all the track/holds into hold and initiates a conversion sequence for the selected channels. The EOC signal indicates the end of each individual conversion in the selected conversion sequence. The BUSY signal indicates the end of the conversion sequence. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. FUNCTIONAL BLOCK DIAGRAM AVDD STBY VREF TRACK/HOLD
4 VIN1A VIN1B SIGNAL SCALING VIN2A VIN2B SIGNAL SCALING 2.5V REFERENCE DGND AGND AD7864 RD MUX VIN3A VIN3B SIGNAL SCALING VIN4A VIN4B SIGNAL SCALING 12-BIT ADC OUTPUT DATA REGISTERS SOFTWARE LATCH FRSTDATA BUSY EOC 6k VDRIVE DVDD VREF GND CONVERSION CONTROL LOGIC CONVST SL1 SL2 SL3 SL4 H/S SEL DB0 TO DB3 DB11 DB0 CS WR INT/EXT CLOCK SELECT INT CLOCK CLKIN INT/EXT AGND AGND CLK Data is read from the part by means of a 12-bit parallel data bus using the standard CS and RD signals. Maximum throughput for a single channel is 500 kSPS. For all four channels, the maximum throughput is 130 kSPS for the read during conversion sequence operation. The throughput rate for the read after conversion sequence operation depends on the read cycle time of the processor. See the Timing and Control section. The AD7864 is available in a small (0.3 sq. inch area) 44-lead MQFP. PRODUCT HIGHLIGHTS 1. The AD7864 features four track/hold amplifiers and a fast (1.65 ms) ADC allowing simultaneous sampling and then conversion of any subset of the four channels. 2. The AD7864 operates from a single 5 V supply and consumes only 90 mW typ, making it ideal for low power and portable applications. Also see the Standby Mode Operation section. 3. The part offers a high speed parallel interface for easy connection to microprocessors, microcontrollers, and digital signal processors. 4. The part is offered in three versions with different analog input ranges. The AD7864-1 offers the standard industrial input ranges of ± 10 V and ± 5 V; the AD7864-3 offers the common signal processing input range of ± 2.5 V; the AD7864-2 can be used in unipolar 0 V to 2.5 V, 0 V to 5 V applications. 5. The part features very tight aperture delay matching between the four input sample-and-hold amplifiers. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved. (VDD = 5 V  5%, AGND = DGND = 0 V, VREF = Internal, Clock = Internal; all specifiMIN to TMAX, unless otherwise noted.) AD7864–SPECIFICATIONS cations T Parameter A Version1 B Version Unit SAMPLE AND HOLD –3 dB Full Power Bandwidth Aperture Delay Aperture Jitter Aperture Delay Matching 3 20 50 4 3 20 50 4 MHz typ ns max ps typ ns max DYNAMIC PERFORMANCE2 Signal-to-(Noise + Distortion) Ratio3 @ 25∞C TMIN to TMAX Total Harmonic Distortion3 Peak Harmonic or Spurious Noise3 Intermodulation Distortion3 Second-Order Terms Third-Order Terms Channel-to-Channel Isolation3 DC ACCURACY Resolution Relative Accuracy3 Differential Nonlinearity3 AD7864-1 Positive Gain Error3 Positive Gain Error Match3 Negative Gain Error3 Negative Gain Error Match3 Bipolar Zero Error Bipolar Zero Error Match AD7864-3 Positive Gain Error3 Positive Gain Error Match3 Negative Gain Error3 Negative Gain Error Match3 Bipolar Zero Error Bipolar Zero Error Match AD7864-2 Positive Gain Error3 Positive Gain Error Match3 Unipolar Offset Error Unipolar Offset Error Match ANALOG INPUTS AD7864-1 Input Voltage Range Input Resistance AD7864-3 Input Voltage Range Input Resistance AD7864-2 Input Voltage Range Input Current (0 V to 2.5 V Option) Input Resistance (0 V to 5 V Option) REFERENCE INPUT/OUTPUT VREF IN Input Voltage Range VREF IN Input Capacitance4 VREF OUT Output Voltage VREF OUT Error @ 25∞C VREF OUT Error TMIN to TMAX VREF OUT Temperature Coefficient VREF OUT Output Impedance Test Conditions/Comments fIN = 100.0 kHz, fS = 500 kSPS 70 70 –80 –80 72 70 –80 –80 dB min dB min dB max dB max –80 –80 –80 –80 –80 –80 dB typ dB typ dB max 12 ±1 ± 0.9 12 ± 1/2 ± 0.9 Bits LSB max LSB max ±3 3 ±3 3 ±4 2 ±3 ±3 ±3 ±3 ±3 ±2 LSB max LSB max LSB max LSB max LSB max LSB max fa = 49 kHz, fb = 50 kHz fIN = 50 kHz Sine Wave Any Channel ±3 2 ±3 2 ±3 2 LSB max LSB max LSB max LSB max LSB max LSB max ±3 3 ±3 2 LSB max LSB max LSB max LSB max ± 5, ± 10 9, 18 ± 5, ± 10 9, 18 V kW min ± 2.5 4.5 ± 2.5 4.5 V kW min 0 to 2.5, 0 to 5 ± 100 9 0 to 2.5, 0 to 5 ± 100 9 V nA max kW min 2.375/2.625 10 2.5 ± 10 ± 20 25 6 2.375/2.625 10 2.5 ± 10 ± 20 25 6 VMIN/VMAX pF max V nom mV max mV max ppm/∞C typ kW typ –2– No Missing Codes 2.5 V ± 5% See the Reference Section REV. B AD7864 Parameter A Version1 B Version Unit Test Conditions/Comments LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN4 2.4 0.8 ± 10 10 2.4 0.8 ± 10 10 V min V max mA max pF max VDD = 5 V ± 5% VDD = 5 V ± 5% 4.0 0.4 4.0 0.4 V min V max ISOURCE = 400 mA ISINK = 1.6 mA ± 10 10 ± 10 10 mA max pF max LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL DB11 to DB0 High Impedance Leakage Current Capacitance4 Output Coding AD7864-1, AD7864-3 AD7864-2 Twos Complement Straight (Natural) Binary CONVERSION RATE Conversion Time Track/Hold Acquisition Time2, 3 Throughput Time 1.65 0.35 130 1.65 0.35 130 ms max ms max kSPS max 5 5 V nom 24 20 24 20 mA max mA max 120 100 120 100 mW max mW max POWER REQUIREMENTS VDD IDD Normal Mode Standby Mode Power Dissipation Normal Mode Standby Mode For One Channel For All Four Channels ± 5% for Specified Performance (5 mA typ) Logic Inputs = 0 V or VDD Typically 4 mA Typically 90 mW Typically 20 mW NOTES 1 Temperature ranges are as follows: A, B Versions: –40∞C to +85∞C. The A Version is fully specified up to 105∞C with a maximum sample rate of 450 kSPS and I DD maximum (normal mode) of 26 mA. 2 Performance measured through full channel (SHA and ADC). 3 See Terminology section. 4 Sample tested at initial release to ensure compliance. Specifications subject to change without notice. REV. B –3– AD7864 TIMING CHARACTERISTICS1, 2 (VDRIVE = 5 V  5%, AGND = DGND = 0 V, VREF = Internal, Clock = Internal; all specifications TMIN to TMAX, unless otherwise noted.) Parameter A, B Versions Unit Test Conditions/Comments tCONV 1.65 13 2.6 0.34 No. of Channels ⫻ (tCONV + t9) – t9 2 6 ms max Clock Cycles ms max ms max ms max ms max ms max Conversion Time, Internal Clock Conversion Time, External Clock CLKIN = 5 MHz Acquisition Time Selected Number of Channels Multiplied by (tCONV + EOC Pulse Width)—EOC Pulse Width STBY Rising Edge to CONVST Rising Edge STBY Rising Edge to CONVST Rising Edge 35 70 ns min ns min CONVST Pulse Width CONVST Rising Edge to BUSY Rising Edge 0 0 35 35 40 5 30 10 75 180 70 15 0 ns min ns min ns min ns max ns max ns min ns max ns min ns min ns max ns max ns max ns min CS to RD Setup Time CS to RD Hold Time Read Pulse Width Data Access Time after Falling Edge of RD, VDRIVE = 5 V Data Access Time after Falling Edge of RD, VDRIVE = 3 V Bus Relinquish Time after Rising Edge of RD 20 0 0 5 5 ns min ns min ns min ns min ns min WR Pulse Width CS to WR Setup Time WR to CS Hold Time Input Data Setup Time of Rising Edge of WR Input Data Hold Time tACQ tBUSY tWAKE-UP—External VREF tWAKE-UP—Internal VREF3 t1 t2 Read Operation t3 t4 t5 t6 4 t7 5 t8 t9 t10 t11 t12 Write Operation t13 t14 t15 t16 t17 Time between Consecutive Reads EOC Pulse Width RD Rising Edge to FRSTDATA Edge (Rising or Falling) EOC Falling Edge to FRSTDATA Falling Delay EOC to RD Delay NOTES 1 Sample tested at initial release to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 See Figures 7, 8, and 9. 3 Refer to the Standby Mode Operation section. The maximum specification of 6 ms is valid when using a 0.1 mF decoupling capacitor on the V REF pin. 4 Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 5 These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part, and as such are independent of external bus loading capacitances. Specifications subject to change without notice. 1.6mA TO OUTPUT 1.6V 50pF 400A Figure 1. Load Circuit for Access Time and Bus Relinquish Time –4– REV. B AD7864 ABSOLUTE MAXIMUM RATINGS* DB6 VDRIVE DVDD DB4 DB5 DB2 DB3 DB0 DB1 EOC AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V AVDD TO DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Analog Input Voltage to AGND AD7864-1 (± 10 V Input Range) . . . . . . . . . . . . . . . . ± 20 V AD7864-1 (± 5 V Input Range) . . . . . . . . . . . –7 V to +20 V AD7864-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V to +20 V AD7864-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . –1 V to +20 V Reference Input Voltage to AGND . . . –0.3 V to VDD + 0.3 V Digital Input Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V Digital Output Voltage to DGND . . . . –0.3 V to VDD + 0.3 V VDRIVE to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V VDRIVE to DGND . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V Operating Temperature Range Commercial (A, B Version) . . . . . . . . . . . . –40∞C to +85∞C Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C MQFP Package, Power Dissipation . . . . . . . . . . . . . . 450 mW qJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95∞C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215∞C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C DGND PIN CONFIGURATION (TA = 25∞C, unless otherwise noted) 44 43 42 41 40 39 38 37 36 35 34 33 DB7 BUSY 1 FRSTDATA 2 PIN 1 IDENTIFIER 32 DB8 CONVST 3 31 DB9 CS 4 30 DB10 RD 5 WR 6 SL1 7 AD7864 29 DB11 TOP VIEW (Not to Scale) 28 CLKIN 27 INT/EXT CLK SL2 8 26 AGND SL3 9 25 AVDD SL4 10 24 VREF 23 VREFGND H/S SEL 11 STBY VIN1A VIN1B VIN2A VIN2B AGND VIN3A VIN3B VIN4A VIN4B AGND 12 13 14 15 16 17 18 19 20 21 22 *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model AD7864AS-1 AD7864AS-1 Reel AD7864BS-1 AD7864BS-1 Reel AD7864AS-2 AD7864AS-2 Reel AD7864AS-3 AD7864AS-3 Reel EVAL-AD7864-1CB2 EVAL-AD7864-2CB2 EVAL-AD7864-3CB2 EVAL-CONTROL BRD23 Input Ranges Relative Accuracy Temperature Range1 Package Description Package Option ± 5 V, ± 10 V ± 5 V, ± 10 V ± 5 V, ± 10 V ± 5 V, ± 10 V 0 V to 2.5 V, 0 V to 5 V 0 V to 2.5 V, 0 V to 5 V ± 2.5 V ± 2.5 V ± 1 LSB ± 1 LSB ± 0.5 LSB ± 0.5 LSB ± 1 LSB ± 1 LSB ± 1 LSB ± 1 LSB –40∞C to +85∞C –40∞C to +85∞C –40∞C to +85∞C –40∞C to +85∞C –40∞C to +85∞C –40∞C to +85∞C –40∞C to +85∞C –40∞C to +85∞C Metric Quad Flatpack Metric Quad Flatpack Metric Quad Flatpack Metric Quad Flatpack Metric Quad Flatpack Metric Quad Flatpack Metric Quad Flatpack Metric Quad Flatpack Evaluation Board Evaluation Board Evaluation Board Controller Board S-44-2 S-44-2 S-44-2 S-44-2 S-44-2 S-44-2 S-44-2 S-44-2 NOTES 1 The A Version is fully specified up to 105∞C with a maximum sample rate of 450 kSPS and I DD maximum (normal mode) of 26 mA. 2 This can be used as a stand alone evaluation board or in conjunction with the Evaluation Controller Board for evaluation/demonstration purposes. 3 This board is a complete unit, allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete evaluation kit, the particular ADC evaluation board needs to be ordered, for example, EVAL-AD7864-1CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See the Evaluation Board application note for more information. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7864 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B –5– AD7864 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 BUSY 2 FRSTDATA 3 CONVST 4 5 CS RD 6 WR 7 to 10 SL1 to SL4 11 H/S SEL 12 AGND 13 to 16 17 VIN4x, VIN3x AGND 18 to 21 22 VIN2x, VIN1x STBY 23 VREF GND 24 VREF 25 26 27 AVDD AGND INT/EXT CLK 28 CLKIN 29 to 34 DB11 to DB6 35 DVDD 36 VDRIVE 37 DGND 38, 39 40 to 43 DB5, DB4 DB3 to DB0 44 EOC Busy Output. The busy output is triggered high by the rising edge of CONVST and remains high until conversion is completed on all selected channels. First Data Output. FRSTDATA is a logic output which, when high, indicates that the output data register pointer is addressing Register 1—See the Accessing the Output Data Registers section. Convert Start Input. Logic input. A low-to-high transition on this input puts all track/holds into their hold mode and starts conversion on the selected channels. In addition, the state of the channel sequence selection is also latched on the rising edge of CONVST. Chip Select Input. Active low logic input. The device is selected when this input is active. Read Input. Active low logic input that is used in conjunction with CS low to enable the data outputs. Ensure the WR pin is at logic high while performing a read operation. Write Input. A rising edge on the WR input, with CS low and RD high, latches the logic state on DB0 to DB3 into the channel select register. Hardware Channel Select. Conversion sequence selection can also be made via the SL1 to SL4 pins if H/S SEL is Logic 0. The selection is latched on the rising edge of CONVST. See the Selecting a Conversion Sequence section. Hardware/Software Select Input. When this pin is at Logic 0, the AD7864 conversion sequence selection is controlled via the SL1 to SL4 input pins. When this pin is at Logic 1, the sequence is controlled via the channel select register. See the Selecting a Conversion Sequence section. Analog Ground. General analog ground. This AGND pin should be connected to the system’s AGND plane. Analog Inputs. See the Analog Input section. Analog Ground. Analog ground reference for the attenuator circuitry. This AGND pin should be connected to the system’s AGND plane. Analog Inputs. See the Analog Input section. Standby Mode Input. TTL compatible input that is used to put the device into the power save or standby mode. The STBY input is high for normal operation and low for standby operation. Reference Ground. Ground reference for the part’s on-chip reference buffer. The V REF GND pin should be connected to the system’s AGND plane. Reference Input/Output. This pin provides access to the internal reference (2.5 V ± 5%) and also allows the internal reference to be overdriven by an external reference source (2.5 V). A 0.1 mF decoupling capacitor should be connected between this pin and AGND. Analog Positive Supply Voltage, 5.0 V ± 5%. Analog Ground. Analog ground reference for the DAC circuitry. Internal/External Clock Select Input. When this pin is at Logic 0, the AD7864 uses its internally generated master clock. When this pin is at Logic 1, the master clock is generated externally to the device. Conversion Clock Input. This is an externally applied clock that allows the user to control the conversion rate of the AD7864. Each conversion needs 14 clock cycles in order for the conversion to be completed and an EOC pulse to be generated. The clock should have a duty cycle that is no worse than 60/40. See the Using an External Clock section. Data Bit 11 is the MSB, followed by Data Bit 10 to Data Bit 6. Three-state TTL outputs. Output coding is twos complement for the AD7864-1 and AD7864-3. Output coding is straight (natural) binary for the AD7864-2. Positive Supply Voltage for Digital Section, 5.0 V ± 5%. A 0.1 mF decoupling capacitor should be connected between this pin and AGND. Both DV DD and AVDD should be externally tied together. This pin provides the positive supply voltage for the output drivers (DB0 to DB11), BUSY, EOC, and FRSTDATA. It is normally tied to DVDD. VDRIVE should be decoupled with a 0.1 mF capacitor. It allows improved performance when reading during the conversion sequence. To facilitate interfacing to 3 V processors and DSPs, the output data drivers can also be powered by a 3 V ± 10% supply. Digital Ground. Ground reference for digital circuitry. This DGND pin should be connected to the system’s AGND plane at the AGND pin. Data Bit 5 to Data Bit 4. Three-state TTL outputs. Data Bit 3 to Data Bit 0. Bidirectional data pins. When a read operation takes place, these pins are threestate TTL outputs. The channel select register is programmed with the data on the DB0 to DB3 pins with standard CS and WR signals. DB0 represents Channel 1, and DB3 represents Channel 4. End-of-Conversion. Active low logic output indicating conversion status. The end of each conversion in a conversion sequence is indicated by a low-going pulse on this line. –6– REV. B AD7864 TERMINOLOGY Channel-to-Channel Isolation Signal-to-(Noise + Distortion) Ratio Channel-to-channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a fullscale 50 kHz sine wave signal to all nonselected input channels and determining how much that signal is attenuated in the selected channel. The figure given is the worst case across all four channels. This is the measured ratio of signal-to-(noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio depends on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Relative Accuracy Relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB. Differential Nonlinearity Total Harmonic Distortion (THD) This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7864, it is defined as Positive Full-Scale Error This is the deviation of the last code transition (01 . . . 110 to 01 . . . 111) from the ideal 4 ¥ VREF – 3/2 LSB (AD7864-1 ± 10 V), 2 ¥ VREF – 3/2 LSB (AD7864-1 ± 5 V range) or VREF – 3/2 LSB (AD7864-3, ± 2.5 V range), after the bipolar offset error has been adjusted out. V 2 + V32 + V42 + V52 + V62 THD (dB) = 20log 2 V1 where V1 is the rms amplitude of the fundamental, and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the fifth harmonics. Positive Full-Scale Error (AD7864-2, 0 V to 2.5 V and 0 V to 5 V) This is the deviation of the last code transition (11 . . . 110 to 11 . . . 111) from the ideal 2 ¥ VREF – 3/2 LSB (AD7864-2 0 V to 5 V range), or VREF – 3/2 LSB (AD7864-2 0 V to 2.5 V range), after the unipolar offset error has been adjusted out. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it is a noise peak. Bipolar Zero Error (AD7864-1, 10/5 V, AD7864-3, 2.5 V) This is the deviation of the midscale transition (all 0s to all 1s) from the ideal AGND – 1/2 LSB. Unipolar Offset Error (AD7864-2, 0 V to 2.5 V and 0 V to 5 V) Intermodulation Distortion This is the deviation of the first code transition (00 . . . 000 to 00 . . . 001) from the ideal AGND + 1/2 LSB. With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation terms are those for which neither m nor n are equal to zero. For example, the second-order terms include (fa + fb) and (fa – fb), while the third-order terms include (2 fa + fb), (2 fa – fb), (fa + 2 fb), and (fa – 2 fb). Negative Full-Scale Error (AD7864-1, 10/5 V, AD7864-3, 2.5 V) This is the deviation of the first code transition (10 . . . 000 to 10 . . . 001) from the ideal –4 ¥ VREF + 1/2 LSB (AD7864-1 ± 10 V), –2 ¥ VREF + 1/2 LSB (AD7864-1 ± 5 V range) or –VREF + 1/2 LSB (AD7864-3, ± 2.5 V range), after bipolar zero error has been adjusted out. The AD7864 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second- and third-order terms are of different significance. The second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. REV. B Track/Hold Acquisition Time Track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within ± 1/2 LSB, after the end of conversion (the point at which the track/hold returns to track mode). It also applies to situations where there is a step input change on the input voltage applied to the selected VINxA/VINxB input of the AD7864. It means that the user must wait for the duration of the track/hold acquisition time after the end of conversion or after a step input change to VINxA/VINxB before starting another conversion to ensure that the part operates to specification. –7– AD7864 CONVERTER DETAILS Track/Hold Section The AD7864 is a high speed, low power, 4-channel simultaneous sampling 12-bit A/D converter that operates from a single 5 V supply. The part contains a 1.65 ms successive approximation ADC, four track/hold amplifiers, an internal 2.5 V reference, and a high speed parallel interface. There are four analog inputs that can be simultaneously sampled, thus preserving the relative phase information of the signals on all four analog inputs. Thereafter, conversions will be completed on the selected subset of the four channels. The part accepts an analog input range of ± 10 V or ± 5 V (AD7864-1), ± 2.5 V (AD7864-3), and 0 V to +2.5 V or 0 V to +5 V (AD7864-2). Overvoltage protection on the analog inputs of the part allows the input voltage to go to ± 20 V, (AD7864-1 ±10 V range), –7 V or +20 V (AD7864-1 ±5 V range), –1 V to +20 V (AD7864-2), and –7 V to +20 V (AD7864-3), without causing damage. The AD7864 has two operating modes reading between conversions and reading after the conversion sequence. These modes are discussed in more detail in the Timing and Control section. The track/hold amplifiers on the AD7864 allow the ADCs to accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. The input bandwidth of the track/hold is greater than the Nyquist rate of the ADC even when the ADC is operated at its maximum throughput rate of 500 kSPS (i.e., the track/hold can handle input frequencies in excess of 250 kHz). The track/hold amplifiers acquire input signals to 12-bit accuracy in less than 350 ns. The operation of the track/holds are essentially transparent to the user. The four track/hold amplifiers sample their respective input channels simultaneously, on the rising edge of CONVST. The aperture time for the track/ holds (i.e., the delay time between the external CONVST signal and the track/hold actually going into hold) is typically 15 ns and, more importantly, is well matched across the four track/ holds on one device and also well matched from device to device. This allows the relative phase information between different input channels to be accurately preserved. It also allows multiple AD7864s to sample more than four channels simultaneously. At the end of a conversion sequence, the part returns to its tracking mode. The acquisition time of the track/hold amplifiers begin at this point. A conversion is initiated on the AD7864 by pulsing the CONVST input. On the rising edge of CONVST, all four on-chip track/ holds are placed into hold simultaneously and the conversion sequence is started on all the selected channels. Channel selection is made via the SL1 to SL4 pins if H/S SEL is Logic 0 or via the channel select register if H/S SEL is Logic 1—see the Selecting a Conversion Sequence section. The channel select register is programmed via the bidirectional data lines DB0 to DB3 and a standard write operation. The selected conversion sequence is latched on the rising edge of CONVST, so changing a selection will only take effect once a new conversion sequence is initiated. The BUSY output signal is triggered high on the rising edge of CONVST and will remain high for the duration of the conversion sequence. The conversion clock for the part is generated internally using a laser-trimmed clock oscillator circuit. There is also the option of using an external clock, by tying the INT/EXT CLK pin logic high, and applying an external clock to the CLKIN pin. However, the optimum throughput is obtained by using the internally generated clock—see the Using an External Clock section. The EOC signal indicates the end of each conversion in the conversion sequence. The BUSY signal indicates the end of the full conversion sequence, and at this time all four track and holds return to tracking mode. The conversion results can be read either at the end of the full conversion sequence (indicated by BUSY going low) or as each result becomes available (indicated by EOC going low). Data is read from the part via a 12-bit parallel data bus with standard CS and RD signals—see the Timing and Control section. Reference Section The AD7864 contains a single reference pin, labeled VREF, which either provides access to the part’s own 2.5 V reference or to which an external 2.5 V reference can be connected to provide the reference source for the part. The part is specified with a 2.5 V reference voltage. Errors in the reference source will result in gain errors in the AD7864’s transfer function and will add to the specified full-scale errors on the part. On the AD7864-1 and AD7864-3, it will also result in an offset error injected in the attenuator stage; see Figures 2 and 4. The AD7864 contains an on-chip 2.5 V reference. To use this reference as the reference source for the AD7864, simply connect a 0.1 mF disk ceramic capacitor from the VREF pin to AGND. The voltage that appears at this pin is internally buffered before being applied to the ADC. If this reference is used externally to the AD7864, it should be buffered, as the part has a FET switch in series with the reference output resulting in a 6 kW nominal source impedance for this output. The tolerance on the internal reference is ± 10 mV at 25∞C with a typical temperature coefficient of 25 ppm/∞C and a maximum error over temperature of ± 20 mV. If the application requires a reference with a tighter tolerance or the AD7864 needs to be used with a system reference, the user has the option of connecting an external reference to this VREF pin. The external reference effectively overdrives the internal reference and thus provides the reference source for the ADC. The reference input is buffered before being applied to the ADC with the maximum input current of ± 100 mA. Suitable reference sources for the AD7864 include the AD680, AD780, REF192, and REF43 precision 2.5 V references. Conversion time for each channel of the AD7864 is 1.65 ms, and the track/hold acquisition time is 0.35 ms. To obtain optimum performance from the part, the read operation should not occur during a channel conversion or during the 100 ns prior to the next CONVST rising edge. This allows the part to operate at throughput rates up to 130 kHz for all four channels and achieve data sheet specifications. CIRCUIT DESCRIPTION Analog Input Section The AD7864 is offered as three part types: the AD7864-1, where each input can be configured for ± 10 V or a ± 5 V input voltage range; the AD7864-3, which handles input voltage range ± 2.5 V; and the AD7864-2, where each input can be configured to have a 0 V to +2.5 V or 0 V to +5 V input voltage range. –8– REV. B AD7864 AD7864-1 AD7864-2 Figure 2 shows the analog input section of the AD7864-1. Each input can be configured for ± 5 V or ± 10 V operation on the AD7864-1. For ± 5 V (AD7864-1) operation, the VINxA and VINxB inputs are tied together and the input voltage is applied to both. For ± 10 V (AD7864-1) operation, the VINxB input is tied to AGND and the input voltage is applied to the VINxA input. The VINxA and VINxB inputs are symmetrical and fully interchangeable. Thus for ease of PCB layout on the ± 10 V range, the input voltage may be applied to the VINxB input while the VINxA input is tied to AGND. Figure 3 shows the analog input section of the AD7864-2. Each input can be configured for 0 V to 5 V operation or 0 V to 2.5 V operation. For 0 V to 5 V operation, the VINxB input is tied to AGND and the input voltage is applied to the VINxA input. For 0 V to 2.5 V operation, the VINxA and VINxB inputs are tied together and the input voltage is applied to both. The VINxA and VINxB inputs are symmetrical and fully interchangeable. Thus for ease of PCB layout on the 0 V to 5 V range, the input voltage may be applied to the VINxB input while the VINxA input is tied to AGND. For the AD7864-2, R1 = 6 kW and R2 = 6 kW. Once again, the designed code transitions occur on successive integer LSB values. Output coding is straight (natural) binary with 1 LSB = FSR/4096 = 2.5 V/4096 = 0.61 mV, and 5 V/4096 = 1.22 mV, for the 0 V to 2.5 V and 0 V to 5 V options, respectively. Table II shows the ideal input and output transfer function for the AD7864-2. AD7864-1 6k 2.5V REFERENCE VREF R1 TO ADC REFERENCE CIRCUITRY AD7864-2 R2 VIN1A 6k R3 T/H VIN1B TO INTERNAL COMPARATOR 2.5V REFERENCE VREF R4 TO ADC REFERENCE CIRCUITRY AGND Figure 2. AD7864-1 Analog Input Structure R1 VIN1A For the AD7864-1, R1 = 6 kW, R2 = 24 kW, R3 = 24 kW, and R4 = 12 kW. The resistor input stage is followed by the high input impedance stage of the track/hold amplifier. R2 T/H VIN1B The designed code transitions take place midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs, etc.). LSB size is given by the formula 1 LSB = FSR/4096. For the ± 5 V range, 1 LSB = 10 V/4096 = 2.44 mV. For the ± 10 V range, 1 LSB = 20 V/4096 = 4.88 mV. Output coding is twos complement binary with 1 LSB = FSR/4096. The ideal input/ output transfer function for the AD7864-1 is shown in Table I. TO INTERNAL COMPARATOR Figure 3. AD7864-2 Analog Input Structure Table II. Ideal Input/Output Code Table for the AD7864-2 Analog Input1 Digital Output Code Transition 2 Digital Output Code Transition +FSR – 3/2 LSB +FSR – 5/2 LSB +FSR – 7/2 LSB 111 . . . 110 to 111 . . . 111 111 . . . 101 to 111 . . . 110 111 . . . 100 to 111 . . . 101 +FSR/2 – 3/2 LSB +FSR/2 – 5/2 LSB +FSR/2 – 7/2 LSB 011 . . . 110 to 011 . . . 111 011 . . . 101 to 011 . . . 110 011 . . . 100 to 011 . . . 101 AGND + 5/2 LSB AGND + 3/2 LSB AGND + 1/2 LSB 000 . . . 010 to 000 . . . 011 000 . . . 001 to 000 . . . 010 000 . . . 000 to 000 . . . 001 AGND + 3/2 LSB AGND + 1/2 LSB AGND – 1/2 LSB AGND – 3/2 LSB 000 . . . 001 to 000 . . . 010 000 . . . 000 to 000 . . . 001 111 . . . 111 to 000 . . . 000 111 . . . 110 to 111 . . . 111 NOTES 1 FSR is full-scale range and is 0 V to 2.5 V and 0 V to 5 V for the AD7864-2 with VREF = 2.5 V. 2 1 LSB = FSR/4096 and is 0.61 mV (0 V to 2.5 V) and 1.22 mV (0 V to 5 V) for the AD7864-2 with V REF = 2.5 V. –FSR/2 + 5/2 LSB –FSR/2 + 3/2 LSB –FSR/2 + 1/2 LSB 100 . . . 010 to 100 . . . 011 100 . . . 001 to 100 . . . 010 100 . . . 000 to 100 . . . 001 Table I. Ideal Input/Output Code Table for the AD7864-1 Analog Input1 2 NOTES 1 FSR is full-scale range and is 20 V for the ± 10 V range and +10 V for the ± 5 V range, with VREF = 2.5 V. 2 1 LSB = FSR/4096 = 4.883 mV (± 10 V for the AD7864-1) and 2.441 mV (± 5 V for the AD7864-1) with V REF = 2.5 V. REV. B –9– AD7864 AD7864-3 SELECTING A CONVERSION SEQUENCE Figure 4 shows the analog input section of the AD7864-3. The analog input range is ± 2.5 V on the VIN1A input. The VIN1B input can be left unconnected, but if it is connected to a potential, that potential must be AGND. Any subset of the four channels VIN1 to VIN4 can be selected for conversion. The selected channels are converted in ascending order. For example, if the channel selection includes VIN4, VIN1, and VIN3, the conversion sequence will be VIN1, VIN3, and then VIN4. The conversion sequence selection may be made by either using the hardware channel select input pins (SL1 through SL4) or programming the channel select register. A logic high on a hardware channel select pin (or Logic 1 in the channel select register) when CONVST goes logic high marks the associated analog input channel for inclusion in the conversion sequence. AD7864-3 6k 2.5V REFERENCE VREF Figure 5 shows the arrangement used. The H/S SEL controls a multiplexer that selects the source of the conversion sequence information, i.e., from the hardware channel select pins (SL1 to SL4) or from the channel selection register. When a conversion is started, the output from the multiplexer is latched until the end of the conversion sequence. The data bus bits, DB0 to DB3, (DB0 representing Channel 1 through DB3 representing Channel 4) are bidirectional and become inputs to the channel select register when RD is logic high and CS and WR are logic low. The logic state on DB0 to DB3 is latched into the channel select register when WR goes logic high. TO ADC REFERENCE CIRCUITRY R1 R2 VIN1A T/H TO INTERNAL COMPARATOR VIN1B Figure 4. AD7864-3 Analog Input Structure For the AD7864-3, R1 = 6 kW and R2 = 6 kW. As a result, the VIN1A input should be driven from a low impedance source. The resistor input stage is followed by the high input impedance stage of the track/hold amplifier. The designed code transitions take place midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs, and so on) LSB size is given by the formula 1 LSB = FSR/ 4096. Output coding is twos complement binary with 1 LSB = FSR/4096 = 5 V/4096 = 1.22 mV. The ideal input/output transfer function for the AD7864-3 is shown in Table III. H/S Analog Input D3 D2 D1 D0 CHANNEL SELECT REGISTER +FSR/2 – 3/2 LSB +FSR/2 – 5/2 LSB +FSR/2 – 7/2 LSB 011 . . . 110 to 011 . . . 111 011 . . . 101 to 011 . . . 110 011 . . . 100 to 011 . . . 101 AGND + 3/2 LSB AGND + 1/2 LSB AGND – 1/2 LSB AGND – 3/2 LSB 000 . . . 001 to 000 . . . 010 000 . . . 000 to 000 . . . 001 111 . . . 111 to 000 . . . 000 111 . . . 110 to 111 . . . 111 –FSR/2 + 5/2 LSB –FSR/2 + 3/2 LSB –FSR/2 + 1/2 LSB M U L T I P L E X E R WR LATCH SEQUENCER TRANSPARENT WHILE WAITING FOR CONVST. LATCHED ON THE RISING EDGE OF CONVST AND DURING A CONVERSION SEQUENCE. CS WR Digital Output Code Transition 2 SL1 SL2 SL3 SL4 DATA BUS Table III. Ideal Input/Output Code Table for the AD7864-3 l SELECT INDIVIDUAL TRACK/HOLDS FOR CONVERSION HARDWARE CHANNEL SELECT PINS Figure 5. Channel Select Inputs and Registers RD t 13 WR t 15 t 14 100 . . . 010 to 100 . . . 011 100 . . . 001 to 100 . . . 010 100 . . . 000 to 100 . . . 001 CS t 16 NOTES 1 FSR is full-scale range and is 5 V, with V REF = 2.5 V. 2 1 LSB = FSR/4096 = 1.22 mV (± 2.5 V – AD7864-3) with V REF = 2.5 V. DATA t 17 DATA IN Figure 6. Channel Selection via Software Control –10– REV. B AD7864 t ACQ t1 CONVST BUSY t BUSY QUIET TIME t2 t CONV t CONV t CONV t CONV t8 EOC t 11 t 10 FRSTDATA t 12 RD t4 t3 t5 CS t7 t6 VIN1 DATA VIN2 VIN3 VIN4 100ns H/S SEL 100ns SL1 TO SL4 Figure 7. Timing Diagram for Reading During Conversion TIMING AND CONTROL Reading between Each Conversion in the Conversion Sequence drivers, VDRIVE) for optimum performance it is recommended that the read operation be completed when EOC is logic low, i.e., before the start of the next conversion. Although Figure 8 shows the read operation taking place during the EOC pulse, a read operation can take place at any time. Figure 8 shows a timing specification called Quiet Time. This is the amount of time that should be left after a read operation and before the next conversion is initiated. The quiet time depends heavily on data bus capacitance, but 50 ns to 100 ns is typical. Figure 7 shows the timing and control sequence required to obtain the optimum throughput rate from the AD7864. To obtain the optimum throughput from the AD7864, the user must read the result of each conversion as it becomes available. The timing diagram in Figure 7 shows a read operation each time the EOC signal goes logic low. The timing in Figure 7 shows a conversion on all four analog channels (SL1 to SL4 = 1, see the Channel Selection section), thus there are four EOC pulses and four read operations to access the result of each of the four conversions. A conversion is initiated on the rising edge of CONVST. This places all four track/holds into hold simultaneously. New data from this conversion sequence is available for the first channel selected (VIN1) 1.65 ms later. The conversion on each subsequent channel is completed at 1.65 ms intervals. The end of each conversion is indicated by the falling edge of the EOC signal. The BUSY output signal indicates the end of conversion for all selected channels (four in this case). Data is read from the part via a 12-bit parallel data bus with standard CS and RD signals. The CS and RD inputs are internally gated to enable the conversion result onto the data bus. The data lines DB0 to DB11 leave their high impedance state when both CS and RD are logic low. Therefore, CS may be permanently tied logic low and the RD signal used to access the conversion result. Since each conversion result is latched into its output data register prior to EOC going logic low, another option is to tie the EOC and RD pins together and use the rising edge of EOC to latch the conversion result. Although the AD7864 has some special features that permit reading during a conversion (e.g., a separate supply for the output data REV. B The signal labeled FRSTDATA (first data-word) indicates to the user that the pointer associated with the output data registers is pointing to the first conversion result by going logic high. The pointer is reset to point to the first data location (i.e., first conversion result,) at the end of the first conversion (FRSTDATA logic high). The pointer is incremented to point to the next register (next conversion result) when that conversion result is available. Thus, FRSTDATA in Figure 7 is seen to go low just prior to the second EOC pulse. Repeated read operations during a conversion continues to access the data at the current pointer location until the pointer is incremented at the end of that conversion. Note that FRSTDATA has an indeterminate logic state after initial power-up. This means that for the first conversion sequence after power-up, the FRSTDATA logic output may already be logic high before the end of the first conversion. This condition is indicated by the dashed line in Figure 7. Also the FRSTDATA logic output may already be high as a result of the previous read sequence as is the case after the fourth read in Figure 7. The fourth read (rising edge of RD) resets the pointer to the first data location. Therefore, FRSTDATA is already high when the next conversion sequence is initiated. See the Accessing the Output Data Registers section. –11– AD7864 t1 CONVST BUSY t BUSY QUIET TIME t2 EOC t8 RD t3 t4 CS t7 t6 VIN1 DATA VIN2 t 10 VIN3 VIN4 VIN1 t 10 FRSTDATA Figure 8. Timing Diagram, Reading after the Conversion Sequence Reading after the Conversion Sequence Using an External Clock Figure 8 shows the same conversion sequence as Figure 7. In this case, however, the results of the four conversions (on VIN1 to VIN4) are read after all conversions have finished, i.e., when BUSY goes logic low. The FRSTDATA signal goes logic high at the end of the first conversion just prior to EOC going logic low. As mentioned previously, FRSTDATA has an indeterminate state after initial power-up, therefore FRSTDATA may already be logic high. Unlike the case when reading between each conversion, the output data register pointer is incremented on the rising edge of RD because the next conversion result is available. This means FRSTDATA will go logic low after the first rising edge on RD. The logic input INT/EXT CLK allows the user to operate the AD7864 using the internal clock oscillator or an external clock. The optimum performance is achieved by using the internal clock on the AD7864. The highest external clock frequency allowed is 5 MHz. This means a conversion time of 2.6 ms compared to 1.65 ms using the internal clock. In some instances, however, it may be useful to use an external clock when high throughput rates are not required. For example, two or more AD7864s may be synchronized by using the same external clock for all devices. In this way, there is no latency between output logic signals like EOC due to differences in the frequency of the internal clock oscillators. Figure 9 shows how the various logic outputs are synchronized to the CLK signal. Each conversion requires 14 clocks. The output data register pointer is reset to point to the first register location on the falling edge of the 12th clock cycle of the first conversion in the conversion sequence— see the Accessing the Output Data Registers section. At this point, the logic output FRSTDATA goes logic high. The result of the first conversion is transferred to the output data registers on the falling edge of the 13th clock cycle. The FRSTDATA signal is reset on the falling edge of the 13th clock cycle of the next conversion, i.e., when the result of the second conversion is transferred to its output data register. As mentioned previously, the pointer is incremented by the rising edge of the RD signal if the result of the next conversion is available. The EOC signal goes logic low on the falling edge of the 13th clock cycle and is reset high again on the falling edge of the 14th clock cycle. Successive read operations will access the remaining conversion results in an ascending channel order. Each read operation increments the output data register pointer. The read operation that accesses the last conversion result causes the output data register pointer to be reset so that the next read operation will access the first conversion result again. This is shown in Figure 8 with the fifth read after BUSY goes low accessing the result of the conversion on VIN1. Thus the output data registers act as a circular buffer in which the conversion results may be continually accessed. The FRSTDATA signal will go high when the first conversion result is available. Data is enabled onto the data bus DB0 to DB11 using CS and RD. Both CS and RD have the same functionality as described in the previous section. There are no restrictions or performance implications associated with the position of the read operations after BUSY goes low. The only restriction is that there is minimum time between read operations. Notice also that the quiet time must be allowed before the start of the next conversion. –12– REV. B AD7864 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 13 14 CLK CONVST FRSTDATA EOC RD FIRST CONVERSION COMPLETE LAST CONVERSION COMPLETE BUSY Figure 9. Using an External Clock The AD7864 has a standby mode whereby the device can be placed in a low current consumption mode (5 mA typ). The AD7864 is placed in standby by bringing the logic input STBY low. The AD7864 can be powered up again for normal operation by bringing STBY logic high. The output data buffers are still operational while the AD7864 is in standby. This means the user can still continue to access the conversion results while the AD7864 is in standby. This feature can be used to reduce the average power consumption in a system using low throughput rates. To reduce average power consumption, the AD7864 can be placed in standby at the end of each conversion sequence, i.e., when BUSY goes low and is taken out of standby again prior to the start of the next conversion sequence. The time it takes the AD7864 to come out of standby is called the wake-up time. This wake-up time limits the maximum throughput rate at which the AD7864 can be operated when powering down between conversion sequences. The AD7864 wakes up in approximately 2 ms when using an external reference. The wake-up time is also 2 ms when the standby time is less than 1 ms while using the internal reference. Figure 11 shows the wake-up time of the AD7864 for standby times greater than 1 ms. Note that when the AD7864 is left in standby for periods of time greater than 1 ms, the part will require more than 2 ms to wake up. For example, after initial power-up, using the internal reference the AD7864 takes 6 ms to power up. The maximum throughput rate that can be achieved when powering down between conversions is 1/(tBUSY + 2 ms) = 100 kSPS, approximately. When operating the AD7864 in a standby mode between conversions, the power savings can be significant. For example, with a throughput rate of 10 kSPS, the AD7864 is powered down (IDD = 5 mA) for 90 ms out of every 100 ms (See Figure 10). Therefore, the average power consumption drops to 125/10 mW or 12.5 mW approximately. 1.0 0.9 0.8 POWER-UP TIME (ms) Standby Mode Operation 0.7 0.6 0.5 +105C 0.4 +25C 0.3 0.2 0.1 –40C 0 0.0001 0.001 0.01 0.1 STANDBY TIME (sec) Accessing the Output Data Registers There are four output data registers, one for each of the four possible conversion results from a conversion sequence. The result of the first conversion in a conversion sequence is placed in Register 1, the second result is placed in Register 2, and so on. For example, if the conversion sequence VIN1, VIN3, and VIN4 is selected (see the Conversion Sequence Selection section), the results of the conversion on VIN1, VIN3, and VIN4 are placed in Registers 1 to 3, respectively. The output data register pointer is reset to point to Register 1 at the end of the first conversion in the sequence, just prior to EOC going low. At this t BUSY t BUSY 7s BUSY tWAKE-UP STBY IDD = 20A 2s Figure 10. Power-Down between Conversion Sequences REV. B 10 Figure 11. Power-Up Time vs. Standby Time Using the On-Chip Reference (Decoupled with 0.1 m F Capacitor) 100s CONVST 1 –13– AD7864 point, the logic output FRSTDATA goes logic high to indicate that the output data register pointer is addressing Register 1. When CS and RD are both logic low, the contents of the addressed register are enabled onto the data bus (DB0 to DB11). When reading the output data registers after a conversion sequence, i.e., when BUSY goes low, the register pointer is incremented on the rising edge of the RD signal, as shown in Figure 12. However, when reading the conversion results during the conversion sequence, the pointer is not incremented until a valid conversion result is in the register to be addressed. In this case, the pointer is incremented when the conversion has ended and the result has been transferred to the output data register. This happens just prior to EOC going low, therefore EOC may be used to enable the register contents onto the data bus, as described in the reading between each conversion in the Conversion Sequence section. The pointer is reset to point to Register 1 on the rising edge of the RD signal when the last conversion result in the sequence is being read. In the example shown, this means that the pointer is set to Register 1 when the contents of Register 3 are read. Positive Full-Scale Adjust Apply a voltage of 9.9927 V (FS – 3/2 LSBs) at V1 and adjust R2 until the ADC output code flickers between 0111 1111 1110 and 0111 1111 1111. Negative Full-Scale Adjust Apply a voltage of –9.9976 V (–FS + 1/2 LSB) at V1 and adjust R2 until the ADC output code flickers between 1000 0000 0000 and 1000 0000 0001. An alternative scheme for adjusting full-scale error in systems that use an external reference is to adjust the voltage at the VREF pin until the full-scale error for any of the channels is adjusted out. The good full-scale matching of the channels ensures small full-scale errors on the other channels. INPUT RANGE = 10V V1 R1 10k R2 500 FRSTDATA VDRIVE 2-BIT COUNTER POINTER* DECODE OUTPUT DATA REGISTERS OE NO. 1 (VIN1) OE NO. 2 (VIN3) OE NO. 3 (VIN4) O/P DRIVERS OE NO. 4 NOT VALID RESET VINxA R4 R3 10k 10k R5 10k AD7864* AGND DB0 TO DB11 OE *ADDITIONAL PINS OMITTED FOR CLARITY AD7864 Figure 13. Full-Scale Adjust Circuit RD CS *THE POINTER WILL NOT BE INCREMENTED BY A RISING EDGE ON RD UNTIL THE CONVERSION RESULT IS IN THE OUTPUT DATA REGISTER. THE POINTER IS RESET WHEN THE LAST CONVERSION RESULT IS READ Figure 12. Output Data Registers OFFSET AND FULL-SCALE ADJUSTMENT In most digital signal processing (DSP) applications, offset and full-scale errors have little or no effect on system performance. Offset error can always be eliminated in the analog domain by ac coupling. Full-scale error effect is linear and does not cause problems as long as the input signal is within the full dynamic range of the ADC. Invariably, some applications require that the input signal spans the full analog input dynamic range. In such applications, offset and full-scale error have to be adjusted to zero. DYNAMIC SPECIFICATIONS The AD7864 is specified and 100% tested for dynamic performance specifications as well as traditional dc specifications such as integral and differential nonlinearity. These ac specifications are required for the signal processing applications such as phased array sonar, adaptive filters, and spectrum analysis. These applications require information on the ADC’s effect on the spectral content of the input signal. Thus, the parameters for which the AD7864 is specified include SNR, harmonic distortion, intermodulation distortion, and peak harmonics. These terms are discussed in more detail in the following sections. Signal-to-Noise Ratio (SNR) Figure 13 shows a circuit that can be used to adjust the offset and full-scale errors on the AD7864 (VA1 on the AD7864-1 version is shown for example purposes only). Where adjustment is required, offset error must be adjusted before full-scale error. This is achieved by trimming the offset of the op amp driving the analog input of the AD7864 while the input voltage is 1/2 LSB below analog ground. The trim procedure is as follows: apply a voltage of –2.44 mV (–1/2 LSB) at V1 in Figure 13 and adjust the op amp offset voltage until the ADC output code flickers between 1111 1111 1111 and 0000 0000 0000. Gain error can be adjusted at either the first code transition (ADC negative full scale) or the last code transition (ADC positive full scale). The trim procedures for both cases are as follows. SNR is the measured signal-to-noise ratio at the output of the ADC. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all the nonfundamental signals up to half the sampling frequency (fS/2) excluding dc. SNR depends on the number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-noise ratio for a sine wave input is given by SNR = (6.02N + 1.76) dB (1) where N is the number of bits. Thus, for an ideal 12-bit converter, SNR = 74 dB. Figure 14 shows a histogram plot for 8192 conversions of a dc input using the AD7864 with a 5 V supply. The analog input was set at the center of a code. It can be seen that all the codes appear in the one output bin, indicating very good noise performance from the ADC. –14– REV. B AD7864 12 8000 11 EFFECTIVE NUMBERS OF BITS 9000 7000 COUNTS 6000 5000 4000 3000 2000 –40C 10 +25C 9 8 +105C 7 6 5 1000 4 0 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 ADC CODE Figure 14. Histogram of 8192 Conversions of a DC Input 0 500 1000 1500 2000 FREQUENCY (kHz) 2500 3000 Figure 16. Effective Numbers of Bits vs. Frequency The output spectrum from the ADC is evaluated by applying a sine wave signal of very low distortion to the analog input. A Fast Fourier Transform (FFT) plot is generated from which the SNR data can be obtained. Figure 15 shows a typical 4096 point FFT plot of the AD7864 with an input signal of 99.9 kHz and a sampling frequency of 500 kHz. The SNR obtained from this graph is 72.6 dB. It should be noted that the harmonics are taken into account when calculating the SNR. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3 . . . Intermodulation terms are those for which neither m nor n are equal to zero. For example, the secondorder terms include (fa + fb) and (fa – fb), while the third-order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb). Using the CCIF standard where two input frequencies near the top end of the input bandwidth are used, the second- and thirdorder terms are of different significance. The second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and thirdorder terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. In this case, the input consists of two, equal amplitude, low distortion sine waves. Figure 17 shows a typical IMD plot for the AD7864. Figure 15. FFT Plot Effective Number of Bits The formula given in Equation 1 relates the SNR to the number of bits. Rewriting the formula, as in Equation 2, it is possible to get a measure of performance expressed in effective number of bits (N). SNR –1.76 N= (2) 6.02 The effective number of bits for a device can be calculated directly from its measured SNR. Figure 16 shows a typical plot of effective number of bits versus frequency for an AD7864-2. Figure 17. IMD Plot REV. B –15– AD7864 AC Linearity Plots Measuring Aperture Jitter The plots shown in Figure 18 below show typical DNL and INL plots for the AD7864. A convenient way to measure aperture jitter is to use the relationship it is known to have with SNR (signal-to-noise plus distortion) given below: 3.00 Ê ˆ 1 SNRJITTER = 20 ¥ log10 Á ˜ Ë (2 ¥ p ¥ f IN ¥ s) ¯ 2.00 (3) where: DNL (LSB) 1.00 SNR JITTER = signal-to-noise due to the rms time jitter s = rms time jitter. 0 fIN = sinusoidal input frequency (1 MHz in this case). –1.00 –2.00 –3.00 0 500 1000 1500 2000 2500 3000 3500 4000 ADC CODE From Equation 3, it can be seen that the signal-to-noise ratio due to jitter degrades significantly with frequency. At low input frequencies, the measured SNR performance of the AD7864 is indicative of noise performance due to quantization noise and system noise only (72 dBs used as a typical figure here). Therefore, by measuring the overall SNR performance (including noise due to jitter, system, and quantization) of the AD7864, a good estimation of the jitter performance of the AD7864 can be calculated. 2.50 2.00 1.50 12 0.50 0 11 –0.50 10 –1.00 –1.50 ENOB INL (LSB) 1.00 –2.00 –2.50 0 500 1000 1500 2000 2500 ADC CODE 3000 3500 9 8 4000 7 Figure 18. Typical DNL and INL Plots 6 5 900000 950000 1000000 FREQUENCY (Hz) 1050000 1100000 Figure 19. ENOB of the AD7864 at 1 MHz From Figure 19, the ENOB of the AD7864 at 1 MHz is approximately 11 bits. This is equivalent to 68 dBs SNR. SNRTOTAL = SNR JITTER + SNRQUANT = 68 dBs 68 dBs = SNR JITTER + 72 dBs (at 100 kHz) SNR JITTER = 70.2 dBs From Equation 3, 70.2 dBs = 20 ¥ log10 [1/(2 ¥ ␲ ¥ 1 MHz ¥ ␴)] s = 49 ps where s is the rms jitter of the AD7864. –16– REV. B AD7864 MICROPROCESSOR INTERFACING TMS320C5x The high speed parallel interface of the AD7864 allows easy interfacing to most DSPs and microprocessors. This interface consists of the data lines (DB0 to DB11), CS, RD, WR, EOC, and BUSY. ADDRESS DECODE A0 TO A13 DS VIN1 CS AD7864 to ADSP-2100/ADSP-2101/ADSP-2102 Interface VIN2 RD RD Figure 20 shows an interface between the AD7864 and the ADSP-2100. The CONVST signal can be generated by the ADSP-2100 or from some other external source. Figure 20 shows the CS being generated by a combination of the DMS signal and the address bus of the ADSP-2100. In this way, the AD7864 is mapped into the data memory space of the ADSP-2100. VIN3 WR WE VIN4 AD7864 The AD7864 BUSY line provides an interrupt to the ADSP2100 when the conversion sequence is complete on all the selected channels. The conversion results can then be read from the AD7864 using successive read operations. Alternately, one can use the EOC pulse to interrupt the ADSP-2100 when the conversion on each channel is complete when reading between each conversion in the conversion sequence (Figure 7). The AD7864 is read using the following instruction MR0 = DM(ADC) where MR0 is the ADSP-2100 MR0 register and ADC is the AD7864 address. ADSP-210x ADDRESS DECODE DMS CS VIN2 RD RD VIN3 WR WR VIN4 DB0 TO DB11 BUSY INTn CONVST PA0 Figure 21. AD7864 to TMS320C5x Interface AD7864 to MC68000 Interface An interface between the AD7864 and the MC68000 is shown in Figure 22. The conversion can be initiated from the MC68000 or from an external source. The AD7864 BUSY line can be used to interrupt the processor or, alternatively, software delays can ensure that the conversion has been completed before a read to the AD7864 is attempted. Because of the nature of its interrupts, the MC68000 requires additional logic (not shown in Figure 22) to allow it to be interrupted correctly. For further information on MC68000 interrupts, consult the MC68000 Users Manual. The MC68000 AS and R/W outputs are used to generate a separate RD input signal for the AD7864. RD is used to drive the MC68000 DTACK input to allow the processor to execute a normal read operation to the AD7864. The conversion results are read using the following MC68000 instruction: MOVE.W ADC,D0 A0 TO A13 VIN1 D0 TO D15 DB0 TO DB11 where D0 is the MC68000 D0 register and ADC is the AD7864 address. D0 TO D24 AD7864 BUSY CONVST IRQn MC68000 DT1/F0 ADDRESS DECODE Figure 20. AD7864 to ADSP-210x Interface VIN2 Figure 21 shows an interface between the AD7864 and the TMS320C5x. As with the previous interfaces, conversion can be initiated from the TMS320C5x or from an external source, and the processor is interrupted when the conversion sequence is completed. The CS signal to the AD7864 is derived from the DS signal and a decode of the address bus. This maps the AD7864 into external data memory. The RD signal from the TMS320C5x is used to enable the ADC data onto the data bus. The AD7864 has a fast parallel bus so there are no wait state requirements. The following instruction is used to read the conversion results from the AD7864 IN D,ADC VIN3 where D is the data memory address and ADC is the AD7864 address. REV. B CS VIN1 AD7864 to TMS320C5x Interface –17– DTACK AS RD VIN4 A0 TO A15 R/W AD7864 DB0 TO DB11 CONVST D0 TO D15 CLOCK Figure 22. AD7864 to MC68000 Interface AD7864 Vector Motor Control MULTIPLE AD7864s IN A SYSTEM The current drawn by a motor can be split into two components: one produces torque and the other produces magnetic flux. For optimal performance of the motor, these two components should be controlled independently. In conventional methods of controlling a 3-phase motor, the current (or voltage) supplied to the motor and the frequency of the drive are the basic control variables. However, both the torque and flux are functions of current (or voltage) and frequency. This coupling effect can reduce the performance of the motor because, for example, if the torque is increased by increasing the frequency, the flux tends to decrease. Figure 24 shows a system where a number of AD7864s can be configured to handle multiple input channels. This type of configuration is common in applications such as sonar and radar. The AD7864 is specified with maximum limits on aperture delay match. This means that the user knows the difference in the sampling instant between all channels. This allows the user to maintain relative phase information between the different channels. The AD7864 has a maximum aperture delay matching of 4 ns. Vector control of an ac motor involves controlling phase in addition to drive and current frequency. Controlling the phase of the motor requires feedback information on the position of the rotor relative to the rotating magnetic field in the motor. Using this information, a vector controller mathematically transforms the three phase drive currents into separate torque and flux components. The AD7864, with its 4-channel simultaneous sampling capability, is ideally suited for use in vector motor control applications. All AD7864s use the same external SAR clock (5 MHz). Therefore, the conversion time for all devices is the same and so all devices may be read simultaneously. In the example shown in Figure 24, the data outputs of two AD7864s are enabled onto a 32-bit wide data bus when EOC goes low. VIN1 EOC VIN2 VIN3 AD7864 VIN4 REF193 A block diagram of a vector motor control application using the AD7864 is shown in Figure 23. The position of the field is derived by determining the current in each phase of the motor. Only two phase currents need to be measured because the third can be calculated if two phases are known. VIN1 and VIN2 of the AD7864 are used to digitize this information. VREF CS CLKIN RD VIN1 VIN2 VIN3 AD7864 VIN4 Simultaneous sampling is critical to maintain the relative phase information between the two channels. A current sensing isolation amplifier, transformer, or Hall effect sensor is used between the motor and the AD7864. Rotor information is obtained by measuring the voltage from two of the inputs to the motor. VIN3 and VIN4 of the AD7864 are used to obtain this information. Once again the relative phase of the two channels is important. A DSP microprocessor is used to perform the mathematical transformations and control loop calculations on the information fed back by the AD7864. VREF CS CLKIN RD ADSP-2106x 12 32 RD 12 ADDRESS DECODE 5MHz Figure 24. Multiple AD7864s in Multichannel System DSP MICROPROCESSOR IC DAC TORQUE AND FLUX CONTROL LOOP CALCULATIONS AND TWO TO THREE PHASE INFORMATION TORQUE SETPOINT FLUX SETPOINT DRIVE CIRCUITRY DAC IB IA 3PHASE VA MOTOR VB DAC + + ISOLATION AMPLIFIERS – – VIN1 TRANSFORMATION TO TORQUE AND FLUX CURRENT COMPONENTS VIN2 AD7864* VIN3 VIN4 *ADDITIONAL PINS OMITTED FOR CLARITY VOLTAGE ATTENUATORS Figure 23. Vector Motor Control using the AD7864 –18– REV. B AD7864 OUTLINE DIMENSIONS 44-Lead Metric Quad Flat Package [MQFP] (S-44-2) Dimensions shown in millimeters 1.03 0.88 0.73 SEATING PLANE 13.90 BSC SQ 2.45 MAX 8 0.8 33 23 34 22 10.00 BSC SQ TOP VIEW (PINS DOWN) 2.10 2.00 1.95 7 0 VIEW A PIN 1 44 0.25 MIN COPLANARITY 0.10 VIEW A ROTATED 90 CCW 12 1 11 0.80 BSC 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MO-112-AA-1 REV. B –19– AD7864 Revision History Location Page 3/04—Data Sheet changed from REV. A to REV. B. Changes to TIMING CHARACTERISTICS footnote 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Addition to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to Figure 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Changes to Figure 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Added Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Updated Publication Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 –20– REV. B C01341–0–3/04(B) Changes to SPECIFICATIONS and to footnote 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2