Data Sheet
16-Bit, 1 MSPS/500 kSPS
Differential PulSAR ADCs
AD7915/AD7916
FEATURES
TYPICAL APPLICATIONS CIRCUIT
APPLICATIONS
Automated test equipment
Data acquisition systems
Medical instruments
Machine automation
2.5V TO 5V 2.5V
IN+
REF VDD VIO
SDI/CS
AD7915/
AD7916
±10V, ±5V, ..
IN–
ADA4940-1
GND
SCK
SDO
CNV
1.8V TO 5V
3- OR 4-WIRE
INTERFACE
(SPI, CS,
DAISY CHAIN)
12583-001
High performance
True differential analog input range: ±VREF
0 V to VREF with VREF between 2.5 V and 5 V
Throughput: 1 MSPS/500 kSPS options
Zero latency architecture
16-bit resolution with no missing codes
INL: ±0.4 LSB typical, ±1 LSB maximum
Dynamic range: 95.5 dB, VREF = 5 V
SNR: 94 dB at fIN = 1 kHz, VREF = 5 V
THD: −118.5 dB at fIN = 1 kHz, VREF = 5 V
SINAD: 93.5 dB at fIN = 1 kHz, VREF = 5 V
Low power dissipation
Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V
logic interface
AD7915: 4 mW at 1 MSPS (VDD only)
7 mW at 1 MSPS (total)
AD7916: 2 mW at 500 kSPS (VDD only)
3.7 mW at 500 kSPS (total)
70 μW at 10 kSPS
Proprietary serial interface: SPI-/QSPI-/MICROWIRE™-/DSPcompatible1
10-lead packages: MSOP and 3 mm × 3 mm LFCSP
Wide operating temperature range: −40°C to +125°C
Figure 1.
GENERAL DESCRIPTION
The AD7915/AD7916 are 16-bit, successive approximation,
analog-to-digital converters (ADCs) that operate from a single
power supply, VDD. They contain a low power, high speed,
16-bit sampling ADC and a versatile serial interface port. On
the CNV rising edge, the AD7915/AD7916 sample the voltage
difference between the IN+ and IN− pins. The voltages on these
pins typically swing in opposite phases between 0 V and VREF.
The reference voltage, REF, is applied externally and can be set
independent of the supply voltage, VDD. The power consumption
of the AD7915/AD7916 scales linearly with throughput.
The AD7915/AD7916 are serial peripheral interface (SPI)
compatible, which features the ability, using the SDI input, to
daisy-chain several ADCs on a single 3-wire bus. They are
compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic using the
separate VIO supply.
The AD7915/AD7916 are available in a 10-lead MSOP or a
10-lead LFCSP with operation specified from −40°C to +125°C.
1
Protected by U.S. Patent 6,703,961.
Table 1. MSOP, LFCSP 16-/18-/20-Bit Precision Successive Approximation Register (SAR) ADCs and SAR ADC-Based Devices
Type
Differential
20-Bit
18-Bit
16-Bit
Pseudo-Differential
18-Bit
16-Bit
1
≤100 kSPS
≤250 kSPS
AD7989-1
AD7691
1
AD7684
AD7988-1
AD7680
AD7683
1
AD76871
1
AD7685
AD7694
1
≤500 kSPS
≤1000 kSPS
≤2000 kSPS
AD40221
AD40111
AD76901
AD7989-51
AD76881
AD76931
AD79161
AD40211
AD40071
AD79821
AD79841
AD40051
AD79151
AD40201
AD40031
AD40101
AD40081
AD7988-51
AD76861
AD40061
AD40041
AD79801
AD79831
AD40021
AD40001
µModule® Data Acquisition Solutions
AD40011
ADAQ7980
ADAQ7988
Pin for pin compatible.
Rev. A
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AD7915/AD7916
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Driver Amplifier Choice ........................................................... 16
Applications ...................................................................................... 1
Single to Differential Driver ..................................................... 17
Typical Applications Circuit ........................................................... 1
Voltage Reference Input............................................................ 17
General Description ......................................................................... 1
Power Supply .............................................................................. 17
Revision History ............................................................................... 2
Digital Interface .......................................................................... 17
Specifications .................................................................................... 3
CS Mode, 3-Wire, Without Busy Indicator............................ 18
Timing Specifications .................................................................. 5
CS Mode 3-Wire, with Busy Indicator .................................... 19
Absolute Maximum Ratings ........................................................... 7
CS Mode, 4-Wire, Without Busy Indicator............................ 20
Thermal Resistance ...................................................................... 7
CS Mode 4-Wire with Busy Indicator ..................................... 21
ESD Caution.................................................................................. 7
Chain Mode, Without Busy Indicator .................................... 22
Pin Configurations and Function Descriptions ........................... 8
Chain Mode with Busy Indicator............................................. 23
Typical Performance Characteristics ............................................. 9
Applications Information ............................................................. 24
Terminology .................................................................................... 13
Interfacing to Blackfin DSP ...................................................... 24
Theory of Operation ...................................................................... 14
Layout .......................................................................................... 24
Circuit Information ................................................................... 14
Evaluating AD7915/AD7916 Performance ............................ 25
Converter Operation.................................................................. 14
Outline Dimensions ....................................................................... 26
Typical Connection Diagram ................................................... 15
Ordering Guide .......................................................................... 26
Analog Inputs ............................................................................. 16
REVISION HISTORY
7/2020—Rev. 0 to Rev. A
Changes to Features Section, Figure 1, and Table 1 .................... 1
Changes to Specifications Section and Table 2 ............................ 3
Added Endnote 1, Table 3 ............................................................... 5
Added Table 4; Renumbered Sequentially .................................... 6
Changes to Table 5 ........................................................................... 7
Added Thermal Resistance Section and Table 6...........................7
Changes to Figure 29 ..................................................................... 15
Changes to Driver Amplifier Choice Section and Table 9 ....... 16
Changes to Voltage Reference Input Section and Power Supply
Section .............................................................................................. 17
Deleted Figure 50; Renumbered Sequentially ............................ 25
3/2015—Revision 0: Initial Version
Rev. A | Page 2 of 27
Data Sheet
AD7915/AD7916
SPECIFICATIONS
VDD = 2.5 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, TA = −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Absolute Input Voltage
Common-Mode Input Range
Analog Input Common-Mode
Rejection Ratio (CMRR)
Leakage Current at 25°C
Input Impedance
ACCURACY
No Missing Codes
Differential Nonlinearity (DNL) Error
Integral Nonlinearity (INL) Error
Transition Noise
Gain Error 2
Gain Error Temperature Drift
Zero Error2
Zero Temperature Drift
Power Supply Sensitivity
THROUGHPUT
AD7915 Conversion Rate
AD7916 Conversion Rate
Transient Response
AC ACCURACY
Dynamic Range
Oversampled Dynamic Range 4
Signal-to-Noise Ratio (SNR)
Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
Signal-to-Noise-and-Distortion Ratio
(SINAD)
Test Conditions/Comments
Min
16
IN+ − IN−
IN+, IN−
IN+, IN−
fIN = 450 kHz
−VREF
−0.1
VREF × 0.475
Acquisition phase
VREF × 0.5
60
Max
Unit
Bits
+VREF
VREF + 0.1
VREF × 0.525
V
V
V
dB
1
See the Analog Inputs section
16
−0.9
VREF = 5 V
VREF = 2.5 V
VREF = 5 V
VREF = 2.5 V
VREF = 5 V
VREF = 2.5 V
TMIN to TMAX
−1
−10
TMIN to TMAX
−0.5
VDD = 2.5 V ± 5%
VIO > 2.3 V
VIO ≤ 2.3 V
±0.4
±0.5
±0.4
±0.5
0.75
1.2
0
±0.23
±0.08
0.28
±0.1
0
0
0
VREF = 5 V
VREF = 2.5 V
fO = 10 kSPS
fIN = 1 kHz, VREF = 5 V
fIN = 1 kHz, VREF = 2.5 V
fIN = 1 kHz
fIN = 1 kHz
fIN = 1 kHz, VREF = 5 V
93
89
+0.9
+1
+10
+0.5
1
833
500
290
Full-scale step
fIN = 1 kHz, VREF = 2.5 V
REFERENCE
Voltage Range
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
Typ
nA
Bits
LSB 1
LSB1
LSB1
LSB1
LSB1
LSB1
LSB1
ppm/°C
mV
ppm/°C
dB
MSPS
kSPS
kSPS
ns
95.5
92
113.5
94
91
−118
−118.5
93.5
dB 3
dB3
dB3
dB3
dB3
dB3
dB3
dB3
90.5
dB3
VREF = 5 V
2.4
330
V
µA
VDD = 2.5 V
10
2
MHz
ns
Rev. A | Page 3 of 27
5.1
AD7915/AD7916
Parameter
DIGITAL INPUTS
Logic Levels
VIL
VIH
Data Sheet
Test Conditions/Comments
Min
VIO > 3 V
VIO ≤ 3 V
VIO > 3 V
VIO ≤ 3 V
−0.3
−0.3
0.7 × VIO
0.9 × VIO
−1
−1
IIL
IIH
DIGITAL OUTPUTS
Data Format
Pipeline Delay
VOL
VOH
POWER SUPPLIES
VDD
VIO
Standby Current 5, 6
AD7915 Power Dissipation
Total
VDD Only
REF Only
VIO Only
AD7916 Power Dissipation
Total
VDD Only
REF Only
VIO Only
Energy per Conversion
TEMPERATURE RANGE
Specified Performance
Typ
Max
Unit
+0.3 × VIO
+0.1 × VIO
VIO + 0.3
VIO + 0.3
+1
+1
V
V
V
V
µA
µA
Serial, 16 bits, twos complement
Conversion results available immediately
after completed conversion
0.4
VIO − 0.3
ISINK = 500 µA
ISOURCE = −500 µA
2.375
1.71
VDD and VIO = 2.5 V, TA = 25°C
VDD = 2.625 V, VREF = 5 V, VIO = 3 V
10 kSPS throughput
1 MSPS throughput
1 MSPS throughput
1 MSPS throughput
1 MSPS throughput
VDD = 2.625 V, VREF = 5 V, VIO = 3 V
500 kSPS throughput
500 kSPS throughput
500 kSPS throughput
500 kSPS throughput
TMIN to TMAX
2.5
2.625
5.5
0.35
70
7
4
1.7
1.3
3.7
2
0.85
0.85
7.0
−40
9
V
V
V
V
µA
µW
mW
mW
mW
mW
4.5
mW
mW
mW
mW
nJ/
sample
+125
°C
LSB means least significant bit. With the ±5 V input range, 1 LSB is 152.6 µV.
See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.
3
All specifications expressed in decibels are referred to a full-scale range (FSR) and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4
Dynamic range is obtained by oversampling the ADC running at a throughput, fS, of 1 MSPS followed by postdigital filtering with an output word rate of fO.
5
With all digital inputs forced to VIO or ground as required.
6
During acquisition phase.
1
2
Rev. A | Page 4 of 27
Data Sheet
AD7915/AD7916
TIMING SPECIFICATIONS
TA = −40°C to +125°C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, CLOAD_SDO = 20 pF, unless otherwise noted.
Table 3.
Parameter 1
AD7915
Throughput Rate
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
AD7916
Throughput Rate
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Period (Chain Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 3 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
E
A
E
A
A
E
A
A
E
A
A
E
A
A
E
A
1
A
Symbol
Min
tCONV
tACQ
tCYC
500
290
1
tCONV
tACQ
tCYC
tCNVH
tSCK
0.5
400
2
10
Typ
Max
Unit
1
710
MSPS
ns
ns
µs
500
1.6
kSPS
µs
ns
μs
ns
10.5
12
13
15
ns
ns
ns
ns
11.5
13
14
16
4.5
4.5
3
ns
ns
ns
ns
ns
ns
ns
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
9.5
11
12
14
ns
ns
ns
ns
10
15
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tEN
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
5
2
5
5
2
3
15
Timing parameters measured with respect to a falling edge are defined as triggered at x% VIO. Timing parameters measured with respect to a rising edge are defined
as triggered at y% VIO. For VIO ≤ 3 V, x = 90 and y = 10. For VIO > 3 V, x = 70 and y = 30. The minimum VIH and maximum VIL are used. See the Digital Inputs
Specifications in Table 2.
Rev. A | Page 5 of 27
AD7915/AD7916
Data Sheet
VDD = 2.37 V to 2.63 V, VIO = 1.71 V to 2.3 V, TA = −40°C to +125°C, unless otherwise stated.
Table 4.
Parameter 1
AD7915
Throughput Rate
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions 2
AD7916
Throughput Rate
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (Chain Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
8F
9F
E
A
A
E
A
A
E
A
A
E
A
A
E
A
A
Symbol
Min
tCONV
tACQ
tCYC
500
290
1.2
tCONV
tACQ
tCYC
0.5
400
2
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
tDIS
tSSDICNV
tHSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
10
22
23
6
6
3
Typ
14
18
Max
Unit
833
710
kSPS
ns
ns
μs
500
1.6
kSPS
µs
ns
μs
21
40
20
5
10
0
5
5
2
3
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Timing parameters measured with respect to a falling edge are defined as triggered at x% VIO. Timing parameters measured with respect to a rising edge are defined
as triggered at y% VIO. For VIO ≤ 3 V, x = 90 and y = 10. For VIO > 3 V, x = 70 and y = 30. The minimum VIH and maximum VIL are used. See the Digital Inputs
Specifications in Table 2.
2
The time required to clock out N bits of data, tREAD, may be greater than tACQ depending on the magnitude of VIO. If tREAD is greater than tACQ, the throughput must be
limited to ensure that all N bits are read back from the device.
1
Rev. A | Page 6 of 27
Data Sheet
AD7915/AD7916
ABSOLUTE MAXIMUM RATINGS
1B
THERMAL RESISTANCE
Table 5.
Parameter
Analog Inputs
IN+, IN− to GND1
Supply Voltage
REF, VIO to GND
VDD to GND
VDD to VIO
Digital Inputs to GND
Digital Output to GND
Storage Temperature
Range
Junction Temperature
Reflow Soldering
1
16B
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Rating
−0.3 V to VREF + 0.3 V or ±130 mA
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure.
θJC is the junction to case thermal resistance.
−0.3 V to +6.0 V
−0.3 V to +3.0 V
−6 V to +3 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
Table 6. Thermal Resistance
Package Type1
RM-10
CP-10-9
150°C
JEDEC Standard (J-STD-020)
1
θJC
44
2.96
Unit
°C/W
°C/W
Test Condition 1: thermal impedance simulated values are based on use of a
2S2P JEDEC PCB. See the Ordering Guide.
See the Analog Inputs section for an explanation of IN+ and IN−.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
θJA
200
48.7
ESD CAUTION
17B
Rev. A | Page 7 of 27
AD7915/AD7916
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
2B
REF 1
IN+ 3
IN– 4
TOP VIEW
(Not to Scale)
VDD 2
AD7915/
AD7916
9
SDI/CS
IN+ 3
IN– 4
8
SCK
TOP VIEW
(Not to Scale)
7
SDO
6
CNV
GND 5
GND 5
9
SDI/CS
8
SCK
7
SDO
6
CNV
NOTES
1. THE EXPOSED PAD CAN BE CONNECTED TO GND.
THIS CONNECTION IS NOT REQUIRED TO MEET
THE ELECTRICAL PERFORMANCES.
Figure 2. 10-Lead MSOP Pin Configuration
12583-005
VIO
12583-004
10
REF 1
10 VIO
AD7915/
AD7916
VDD 2
Figure 3. 10-Lead LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1
Mnemonic
REF
Type 1
AI
2
3
4
5
6
VDD
IN+
IN−
GND
CNV
P
AI
AI
P
DI
10F
Description
Reference Input Voltage. The REF range is 2.4 V to 5.1 V. This pin is referred to the GND pin and must be
decoupled closely to the GND pin with a 10 µF capacitor.
Power Supply.
Differential Positive Analog Input.
Differential Negative Analog Input.
Power Supply Ground.
Conversion Input. This input has multiple functions. On its leading edge, CNV initiates the conversions
and
selects the interface mode of the device: chain mode or chip select (CS) mode. In CS mode, the SDO pin is
enabled when CNV is low. In chain mode, the data is read when CNV is high.
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock.
Serial Data Input/Chip Select. This input has multiple functions. It selects the interface mode of the ADC as
follows:
Chain mode is selected if this pin is low during the CNV rising edge. In this mode, SDI/CS is used as a data
input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data
level on SDI/CS is output on SDO with a delay of 16 SCK cycles.
CS mode is selected if SDI/CS is high during the CNV rising edge. In this mode, either SDI/CS or CNV can
enable the serial output signals when low.
Input/Output Interface Digital Power. This pin is nominally at the same supply as the host interface (1.8 V,
2.5 V, 3 V, or 5 V).
Exposed Pad. For the lead frame chip scale package (LFCSP), the exposed pad can be connected to GND.
This connection is not required to meet the electrical performances.
E
A
7
8
9
SDO
SCK
SDI/CS
A
E
DO
DI
DI
E
A
A
A
E
A
A
E
A
A
E
A
10
VIO
EP
P
E
A
A
E
A
AI is analog input, P is power, DI is digital input, and DO is digital output.
1
Rev. A | Page 8 of 27
A
A
Data Sheet
AD7915/AD7916
TYPICAL PERFORMANCE CHARACTERISTICS
3B
0.6
0.4
0.4
0.2
0.2
DNL (LSB)
0.6
0
–0.2
–0.2
–0.4
–0.6
–0.6
–0.8
–0.8
16384
32768
49152
65536
CODE
–1.0
12583-405
–1.0
0
1.0
POSITIVE INL: +0.39 LSB
0.8 NEGATIVE INL: –0.44 LSB
0.4
0.4
0.2
0.2
DNL (LSB)
0.6
0
–0.2
0
–0.4
–0.6
–0.6
–0.8
–0.8
65536
CODE
–1.0
12583-406
–1.0
49152
0
16384
32768
49152
65536
CODE
Figure 8. DNL vs. Code, REF = 2.5 V
Figure 5. INL vs. Code, REF = 2.5 V
0
0
fS = 500kSPS
fIN = 1kHz
–20
AMPLITUDE (dB of FULL SCALE)
–40
fS = 500kSPS
fIN = 1kHz
SNR = 90.61dB
THD = –117.23dB
SFDR = –102.55dB
SINAD = 90.61dB
–20
SNR = 94.98dB
THD = –114.39dB
SFDR = –114.73dB
SINAD = 94.93dB
–60
–80
–100
–120
–140
–40
–60
–80
–100
–120
–140
–180
0
100
200
FREQUENCY (kHz)
250
Figure 6. AD7916 FFT Plot, REF = 5 V
–180
0
100
200
FREQUENCY (kHz)
Figure 9. AD7916 FFT Plot, REF = 2.5 V
Rev. A | Page 9 of 27
250
12583-410
–160
–160
12583-407
AMPLITUDE (dB of FULL SCALE)
65536
–0.2
–0.4
32768
49152
POSITIVE DNL: +0.39 LSB
NEGATIVE DNL: –0.39 LSB
0.8
0.6
16384
32768
Figure 7. Differential Nonlinearity (DNL) vs. Code, REF = 5 V
1.0
0
16384
CODE
Figure 4. Integral Nonlinearity (INL) vs. Code, REF = 5 V
INL (LSB)
0
–0.4
0
POSITIVE DNL: +0.31 LSB
NEGATIVE DNL: –0.38 LSB
0.8
12583-408
0.8
INL (LSB)
1.0
POSITIVE INL: +0.35 LSB
NEGATIVE INL: –0.39 LSB
12583-409
1.0
AD7915/AD7916
Data Sheet
0
0
fS = 1MSPS
fIN = 1kHz
–40
fS = 1MSPS
fIN = 1kHz
SNR = 91.21dB
THD = –118.74dB
SFDR = –108.7dB
SINAD = 91.21dB
–20
SNR = 95.06dB
THD = –114.79dB
SFDR = –116.64dB
SINAD = 95.02dB
AMPLITUDE (dB of FULL SCALE)
–60
–80
–100
–120
–140
–160
–40
–60
–80
–100
–120
–140
0
100
200
300
400
500
FREQUENCY (kHz)
–180
12583-500
–180
0
100
Figure 10. AD7915 FFT Plot, REF = 5 V
300
400
500
Figure 13. AD7915 FFT Plot, REF = 2.5 V
45000
40000
40000
35000
35000
NUMBER OF OCCURRENCES
NUMBER OF OCCURRENCES
200
FREQUENCY (kHz)
12583-501
–160
30000
25000
20000
15000
10000
30000
25000
20000
15000
10000
5000
5000
FFE1 FFE2 FFE3 FFE4 FFE5 FFE6 FFE7 FFE8 FFE9 FFEA
CODES IN HEX
0
12583-411
0
Figure 11. Histogram of a DC Input at the Code Center, REF = 5 V
FFD2 FFD3 FFD4 FFD5 FFD6 FFD7 FFD8 FFD9 FFDA FFDB
CODES IN HEX
12583-412
AMPLITUDE (dB of FULL SCALE)
–20
Figure 14. Histogram of a DC Input at the Code Transition, REF = 5 V
45000
98
40000
96
SNR (dB)
30000
25000
20000
15000
95
94
10000
93
0
FFF1 FFF2 FFF3 FFF4 FFF5 FFF6 FFF7 FFF8 FFF9 FFFA FFFB
CODES IN HEX
Figure 12. Histogram of a DC Input at the Code Center, REF = 2.5 V
92
–10
–9
–8
–7
–6
–5
–4
–3
INPUT LEVEL (dB)
Figure 15. SNR vs. Input Level
Rev. A | Page 10 of 27
–2
–1
0
12583-415
5000
12583-414
NUMBER OF OCCURRENCES
97
35000
Data Sheet
AD7915/AD7916
16.0
100
SNR
SINAD
ENOB
115
–100
110
15.5
96
15.0
SFDR
14.0
90
88
13.5
THD (dB)
14.5
92
ENOB (Bits)
SNR, SINAD (dB)
94
–105
105
–110
100
–115
86
SFDR (dB)
98
–95
95
THD
13.0
84
–120
90
12.5
12583-413
12.0
80
2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
REFERENCE VOLTAGE (V)
–125
2.25
2.75
3.25
3.75
4.25
85
5.25
4.75
12583-416
82
REFERENCE VOLTAGE (V)
Figure 16. SNR, SINAD, and ENOB vs. Reference Voltage
Figure 19. THD and SFDR vs. Reference Voltage
–100
94.8
94.6
–105
THD (dB)
SNR (dB)
94.4
94.2
94.0
–110
–115
93.8
–120
–35
–15
5
25
45
65
85
TEMPERATURE (°C)
105
125
–125
–55
–35
–15
5
25
45
65
85
TEMPERATURE (°C)
105
125
12583-421
93.4
–55
12583-418
93.6
Figure 20. THD vs. Temperature
Figure 17. SNR vs. Temperature
–80
96
95
–85
94
–90
93
THD (dB)
–95
91
90
–100
–105
89
88
–110
87
85
10
100
INPUT FREQUENCY (kHz)
–120
10
100
INPUT FREQUENCY (kHz)
Figure 21. THD vs. Input Frequency
Figure 18. SINAD vs. Input Frequency
Rev. A | Page 11 of 27
12583-420
–115
86
12583-417
SINAD (dB)
92
AD7915/AD7916
Data Sheet
0.7
8
IVDD
7
POWER-DOWN CURRENTS (µA)
0.5
0.4
0.3
IREF
0.2
IVIO
0.1
6
5
4
3
IVDD + IVIO
2
2.425
2.475
2.525
2.575
2.625
VDD VOLTAGE (V)
0
–55
12583-118
0
2.375
–35
–15
5
25
45
65
TEMPERATURE (°C)
125
1.4
0.7
IVDD
IVDD
1.2
OPERATING CURRENTS (mA)
0.6
OPERATING CURRENTS (mA)
105
Figure 25. Power-Down Currents vs. Temperature
Figure 22. Operating Currents vs. VDD Voltage (AD7916)
0.5
0.4
0.3
IREF
0.2
IVIO
1.0
0.8
0.6
IREF
0.4
IVIO
0.2
0
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
12583-120
0.1
1.4
IVDD
1.2
1.0
0.8
0.6
IREF
0.4
IVIO
2.425
2.475
2.525
2.575
2.625
VDD VOLTAGE (V)
12583-121
0.2
0
2.375
0
–55
–35
–15
5
25
45
65
85
105
TEMPERATURE (°C)
Figure 26. Operating Currents vs. Temperature (AD7915)
Figure 23. Operating Currents vs. Temperature (AD7916)
OPERATING CURRENTS (mA)
85
12583-303
1
Figure 24. Operating Currents vs. VDD Voltage (AD7915)
Rev. A | Page 12 of 27
125
12583-123
OPERATING CURRENTS (mA)
0.6
Data Sheet
AD7915/AD7916
TERMINOLOGY
4B
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 29).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified
in terms of resolution for which no missing codes are
guaranteed.
Zero Error
Zero error is the difference between the ideal midscale voltage,
that is, 0 V, and the actual voltage producing the midscale
output code, that is, 0 LSB.
Gain Error
The first transition (from 100 … 00 to 100 …01) occurs at a
level ½ LSB above nominal negative full scale (−4.999981 V for
the ±5 V range). The last transition (from 011 … 10 to 011 …
11) occurs for an analog voltage 1½ LSB below the nominal full
scale (+4.999943 V for the ±5 V range). The gain error is the
deviation of the difference between the actual level of the last
transition and the actual level of the first transition from the
difference between the ideal levels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD as follows:
Effective Resolution
Effective resolution is calculated as
Effective Resolution = log2(2N/RMS Input Noise)
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels. It is
measured with a signal at −60 dB so that it includes all noise
sources and DNL artifacts.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the
Nyquist frequency, excluding harmonics and dc. The value for
SNR is expressed in decibels.
Signal-to-Noise-and-Distortion Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components that are less than
the Nyquist frequency, including harmonics but excluding dc.
The value of SINAD is expressed in decibels.
Aperture Delay
Aperture delay is the measure of the acquisition performance
and is the time between the rising edge of the CNV input and
when the input signal is held for a conversion.
Transient Response
Transient response is the time required for the ADC to accurately
acquire its input after a full-scale step function is applied.
ENOB = (SINADdB − 1.76)/6.02
ENOB is expressed in bits.
Noise-Free Code Resolution
Noise-free code resolution is the number of bits beyond which it is
impossible to distinctly resolve individual codes. It is calculated as
Noise-Free Code Resolution = log2(2N/Peak-to-Peak Noise)
and is expressed in bits.
Rev. A | Page 13 of 27
AD7915/AD7916
Data Sheet
THEORY OF OPERATION
5B
IN+
SWITCHES CONTROL
LSB
MSB
REF
32,768C 16,384C
4C
2C
C
SW+
C
BUSY
COMP
GND
32,768C 16,384C
4C
2C
C
CONTROL
LOGIC
C
MSB
OUTPUT CODE
LSB
SW–
12583-020
CNV
IN–
Figure 27. ADC Simplified Schematic
CIRCUIT INFORMATION
18B
The AD7915/AD7916 are high speed, low power, single-supply,
precise, 16-bit ADCs that use a successive approximation
architecture.
The AD7916 can convert 500,000 samples per second
(500 kSPS), whereas the AD7915 can convert 1,000,000 samples
per second (1 MSPS); both devices power down between conversions. When operating at 1 MSPS, the AD7915 typically
consumes 7 mW, making the ADC ideal for battery-powered
applications.
The AD7915/AD7916 provide the user with an on-chip trackand-hold amplifier and do not exhibit any pipeline delay or
latency, making these devices ideal for multiple multiplexed
channel applications.
The AD7915/AD7916 can be interfaced to any 1.8 V to 5 V
digital logic family. They are available in a 10-lead MSOP or a
tiny 10-lead LFCSP that allows space savings and flexible
configurations.
CONVERTER OPERATION
During the acquisition phase, terminals of the array tied to the
input of the comparator are connected to GND via SW+ and
SW−. All independent switches are connected to the analog
inputs. Therefore, the capacitor arrays are used as sampling
capacitors and acquire the analog signal on the IN+ and IN−
inputs. When the acquisition phase is complete and the CNV
input goes high, a conversion phase is initiated.
When the conversion phase begins, SW+ and SW− are opened
first. The two capacitor arrays are then disconnected from the
inputs and connected to the GND input. Therefore, the
differential voltage between the IN+ and IN− inputs captured
at the end of the acquisition phase is applied to the comparator
inputs, causing the comparator to become unbalanced. By
switching each element of the capacitor array between GND
and REF, the comparator input varies by binary-weighted
voltage steps (VREF/2, VREF/4 ... VREF/65,536). The control logic
toggles these switches, starting with the MSB, to bring the
comparator back into a balanced condition. After the
completion of this process, the device returns to the acquisition
phase, and the control logic generates the ADC output code.
19B
The AD7915/AD7916 are a successive approximation ADCs
based on a charge redistribution digital-to-analog converter
(DAC). Figure 28 shows the simplified schematic of the ADC.
The capacitive DAC consists of two identical arrays of 18
binary-weighted capacitors, which are connected to the two
comparator inputs.
Because the AD7915/AD7916 have an on-board conversion
clock, the serial clock, SCK, is not required for the conversion
process.
Rev. A | Page 14 of 27
Data Sheet
AD7915/AD7916
Transfer Functions
Table 8. Output Codes and Ideal Input Voltages
37B
Description
+FSR – 1 LSB
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
–FSR + 1 LSB
–FSR
011...111
011...110
011...101
1
2
Analog Input
VREF = 5 V
+4.999847 V
+152.6 µV
0V
−152.6 µV
−4.999847 V
−5 V
Digital Output
Code (Hex)
0x7FFF1
0x00001
0x00000
0xFFFF
0x8001
0x80002
This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
TYPICAL CONNECTION DIAGRAM
100...010
20B
100...001
100...000
–FSR
–FSR + 1 LSB
–FSR + 0.5 LSB
+FSR – 1 LSB
+FSR – 1.5 LSB
ANALOG INPUT
Figure 30 shows an example of the recommended connection
diagram for the AD7915/AD7916 when multiple supplies are
available.
12583-021
Figure 28. ADC Ideal Transfer Function
V+
REF1
V+
2.5V
CREF
10µF2
100nF
1.8V TO 5.5V
20Ω
0V TO VREF
100nF
REF
2.7nF
VDD
IN+
V–
AD7915/
AD7916
4
V+
IN–
20Ω
VREF TO 0V
ADA4805-x3
VIO
SDI/CS
SCK
SDO
3-WIRE INTERFACE
CNV
GND
2.7nF
V–
4
1SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
2C
REF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
SEE THE RECOMMENDED LAYOUT IN FIGURE 49 AND FIGURE 50.
3SEE THE DRIVER AMPLIFIER CHOICE SECTION.
4RECOMMENDED FILTER CONFIGURATION. SEE THE ANALOG INPUTS SECTION.
Figure 29. Typical Application Diagram with Multiple Supplies
Rev. A | Page 15 of 27
12583-022
ADC CODE (TWOS COMPLEMENT)
The ideal transfer characteristics for the AD7915/AD7916 are
shown in Figure 29 and Table 6.
AD7915/AD7916
Data Sheet
ANALOG INPUTS
Figure 31 shows an equivalent circuit of the input structure of
the AD7915/AD7916.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN−. Care must be taken to ensure that
the analog input signal does not exceed the reference input
voltage (REF) by more than 0.3 V. If the analog input signal
exceeds this level, the diodes become forward-biased and start
conducting current. These diodes can handle a forward-biased
current of 130 mA maximum. However, if the supplies of the
input buffer (for example, the supplies of the ADA4805-1 or
ADA4805-2, shown as ADA4805-x in Figure 30) are different
from those of REF, the analog input signal may eventually
exceed the supply rails by more than 0.3 V. In such a case (for
example, an input buffer with a short circuit), the current
limitation can be used to protect the device.
REF
D1
RIN
When the source impedance of the driving circuit is low, the
AD7915/AD7916 can be driven directly. Large source impedances
significantly affect the ac performance, especially THD. The dc
performances are less sensitive to the input impedance. The
maximum source impedance depends on the amount of THD that
can be tolerated. The THD degrades as a function of the source
impedance and the maximum input frequency.
DRIVER AMPLIFIER CHOICE
Although the AD7915/AD7916 are easy to drive, the driver
amplifier must meet the following requirements:
•
The noise generated by the driver amplifier must be kept
as low as possible to preserve the SNR and transition noise
performance of the AD7915/AD7916. The noise from the
driver is filtered by the one-pole, low-pass filter of the
AD7915/AD7916 analog input circuit made by RIN and CIN
or by the external filter, if one is used. Because the typical
noise of the AD7915/AD7916 is 60 µV rms, the SNR
degradation due to the amplifier is
CIN
IN+ OR IN–
SNRLOSS
D2
12583-023
CPIN
GND
Figure 30. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.
90
85
CMRR (dB)
80
75
70
60
1k
10k
100k
FREQUENCY (Hz)
1M
10M
12583-040
65
Figure 31. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog
inputs (IN+ or IN−) can be modeled as a parallel combination
of Capacitor CPIN and the network formed by the series connection
of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically
400 Ω and is a lumped component composed of serial resistors
and the on resistance of the switches. CIN is typically 30 pF and
is mainly the ADC sampling capacitor.
During the sampling phase, when the switches are closed, the
input impedance is limited to CPIN. RIN and CIN make a onepole, low-pass filter that reduces undesirable aliasing effects and
limits noise.
60
= 20 log
π
2
2
60 + f −3dB (Ne N )
2
where:
f–3dB is the input bandwidth, in megahertz, of the AD7915/
AD7916 (10 MHz) or the cutoff frequency of the input
filter, if one is used.
N is the noise gain of the amplifier (for example, 1 in
buffer configuration).
eN is the equivalent input noise voltage of the op amp, in
nV/√Hz.
•
For ac applications, use a driver with a THD performance
commensurate with the AD7915/AD7916.
•
For multichannel, multiplexed applications, the driver
amplifier and the AD7915/AD7916 analog input circuit
must settle for a full-scale step onto the capacitor array at a
16-bit level (0.0015%, 15 ppm). In the data sheet of the
amplifier, settling at 0.1% to 0.01% is more commonly
specified. This settling may differ significantly from the
settling time at a 16-bit level and must be verified prior to
driver selection.
The Precision ADC Driver Tool can be used to model the
settling behavior and to estimate the ac performance of the
AD7915 with a selected driver and RC filter.
Table 9. Recommended Driver Amplifiers1
Amplifier
ADA4805-1/
ADA4805-2
ADA4807-1/ADA4807-2
ADA4841-1/
ADA4841-2
ADA4941-1
ADA4945-1
LTC6363
1
Typical Application
Low noise, small size, and low power
Very low noise and high frequency
Low noise, low distortion and low power
Very low noise, low power single-to-differential
Low noise, low distortion, fully differential
Low power, low noise, fully differential
For the latest recommended drivers, see the product recommendations
listed on the AD7915/AD7916 product webpage.
Rev. A | Page 16 of 27
Data Sheet
AD7915/AD7916
R5
R6
R3
R4
+5V REF
10µF
+5.2V
100nF
REF
OUT–
+2.5V
20Ω
IN+
2.7nF
IN–
20Ω
IN
VDD
AD7915/
AD7916
2.7nF
OUT+
100nF
REF
GND
FB
ADA4941-1
R1
–0.2V
R2
12583-025
±10V,
±5V, ..
CF
Figure 32. Single-Ended to Differential Driver Circuit
SINGLE TO DIFFERENTIAL DRIVER
POWER SUPPLY
For applications using a single-ended analog signal, either bipolar
or unipolar, the ADA4941-1 single-ended to differential driver
allows a differential input to the device. The schematic is shown in
Figure 33. The ADA4940-1, which is a fully differential amplifier,
can be used as a single-ended to-differential driver as well.
The AD7915/AD7916 use two power supply pins: a core supply
(VDD) and a digital input/output interface supply (VIO). VIO
allows direct interface with any logic between 1.8 V and 5.5 V. To
reduce the number of supplies needed, VIO and VDD can be
tied together. When VIO is greater than or equal to VDD, the
AD7915/AD7916 are insensitive to power supply sequencing.
In normal operation, if the magnitude of VIO is less than the
magnitude of VDD, VIO must be applied before VDD.
Additionally, they are insensitive to power supply variations over
a wide frequency range, as shown in Figure 34.
95
R3 and R4 set the common mode on the IN− input, and R5 and R6
set the common mode on the IN+ input of the ADC. Make sure
that the common mode is close to VREF/2. For example, for the
±10 V range with a single supply, R3 = 8.45 kΩ, R4 = 11.8 kΩ,
R5 = 10.5 kΩ, and R6 = 9.76 kΩ.
90
PSRR (dB)
85
VOLTAGE REFERENCE INPUT
The AD7915/AD7916 voltage reference input, REF, has a
dynamic input impedance and must, therefore, be driven by a
low impedance source with efficient decoupling between the
REF and GND pins, as explained in the Layout section.
When REF is driven by a very low impedance source (for
example, a reference buffer using the AD8031, ADA4805-1 or
the ADA4807-1), a 10 µF (X5R, 0805 size) ceramic chip
capacitor is appropriate for optimum performance.
80
75
70
65
60
1k
10k
100k
FREQUENCY (Hz)
1M
12583-139
R1 and R2 set the attenuation ratio between the input range
and the ADC range (VREF). R1, R2, and CF are chosen
depending on the desired input resistance, signal bandwidth,
antialiasing, and noise contribution. For example, for the ±10 V
range with a 4 kΩ impedance, R2 = 1 kΩ and R1 = 4 kΩ.
Figure 33. Power Supply Rejection Ratio (PSRR) vs. Frequency
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 µF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift reference, such as
the ADR435, ADR445, LTC6655, or ADR4550.
The AD7915/AD7916 power down automatically at the end of
each conversion phase.
If desired, a reference decoupling capacitor with values as small
as 2.2 µF can be used with a minimal impact on performance,
especially DNL.
When in CS mode, the AD7915/AD7916 are compatible with
SPI, QSPI™, MIRCROWIRE™, digital hosts, and DSPs. In this
mode, the AD7915/AD7916 can use either a 3-wire or 4-wire
interface. A 3-wire interface using the CNV, SCK, and SDO
signals minimizes wiring connections, which is useful, for
instance, in isolated applications. A 4-wire interface using the
Regardless, there is no need for an additional lower value ceramic
decoupling capacitor (for example, 100 nF) between the REF
and GND pins.
DIGITAL INTERFACE
Although the AD7915/AD7916 have a reduced number of pins,
they offer flexibility in their serial interface modes.
Rev. A | Page 17 of 27
A
E
AD7915/AD7916
Data Sheet
•
SDI/CS, CNV, SCK, and SDO signals allows CNV, which initiates
the conversions, to be independent of the readback timing
(SDI). This is useful in low jitter sampling or simultaneous
sampling applications.
E
A
A
CS MODE, 3-WIRE, WITHOUT BUSY INDICATOR
E
A
This mode is usually used when a single AD7915/AD7916 is
connected to an SPI-compatible digital host. The connection
diagram is shown in Figure 35, and the corresponding timing is
given in Figure 36.
E
With SDI/CS tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. When the conversion is complete, the AD7915/
AD7916 enter the acquisition phase and power down. When
CNV goes low, the MSB is output onto SDO. The remaining
data bits are clocked by subsequent SCK falling edges. The data is
valid on both SCK edges. Although the rising edge can capture
the data, a digital host using the SCK falling edge allows a faster
reading rate, provided that it has an acceptable hold time. After
the 16th SCK falling edge or when CNV goes high (whichever
occurs first), SDO returns to high impedance.
A
E
A
E
E
A
E
A
A
A
E
A
E
A
A
A
A
The busy indicator feature is enabled
A
in CS mode if CNV or SDI is low when the ADC
conversion ends (see Figure 38 and Figure 42).
E
A
CONVERT
DIGITAL HOST
CNV
VIO
SDI/CS
AD7915/
AD7916
DATA IN
SDO
SCK
CLK
Figure 34. CS Mode Without Busy Indicator, 3-Wire Connection Diagram (SDI High)
E
A
A
SDI/CS = 1
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
SCK
1
2
3
14
tHSDO
16
tSCKH
tDSDO
tEN
D15
SDO
15
D14
D13
tDIS
D1
D0
Figure 35. CS Mode Without Busy Indicator, 3-Wire Serial Interface Timing (SDI High)
E
A
A
Rev. A | Page 18 of 27
12583-028
A
12583-027
•
A
A
E
A
A
A
When in chain mode, the AD7915/AD7916 provide a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line, similar to a shift register.
The mode in which the device operates depends on the SDI/CS
level when the CNV rising edge occurs. CS mode is selected if
SDI/CS is high, and chain mode is selected if SDI/CS is low.
The SDI/CS hold time is such that when SDI/CS and CNV are
connected together, chain mode is always selected. In either
mode, the AD7915/AD7916 offers the option of forcing a start
bit in front of the data bits. This start bit can be used as a busy
signal indicator to interrupt the digital host and to trigger the
data reading. Otherwise, without a busy indicator, the user must
time out the maximum conversion time prior to readback.
in chain mode if SCK is high during the CNV rising edge
(see Figure 46).
Data Sheet
AD7915/AD7916
SCK edges. Although the rising edge can capture the data, a
digital host using the SCK falling edge allows a faster reading
rate provided it has an acceptable hold time. After the optional
17th SCK falling edge, or when CNV goes high (whichever
occurs first), SDO returns to high impedance.
CS MODE 3-WIRE, WITH BUSY INDICATOR
E
A
This mode is typically used when a single AD7915/AD7916 is
connected to an SPI-compatible digital host having an interrupt
input.
The connection diagram is shown in Figure 37, and the
corresponding timing is given in Figure 38.
If multiple AD7915/AD7916 devices are selected at the same
time, the SDO output pin handles this contention without
damage or induced latch-up. Meanwhile, it is recommended to
keep this contention as short as possible to limit extra power
dissipation.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can select other
SPI devices, such as analog multiplexers, but CNV must be
returned low before the minimum conversion time elapses and
then held low for the maximum conversion time to guarantee
the generation of the busy signal indicator. When the
conversion is complete, SDO goes from high impedance to low.
With a pull-up on the SDO line, this transition can be used as an
interrupt signal to initiate the data reading controlled by the
digital host. The AD7915/AD7916 then enters the acquisition
phase and powers down. The data bits are clocked out, MSB
first, by subsequent SCK falling edges. The data is valid on both
E
A
A
SDI = 1
CONVERT
VIO
CNV
VIO
SDI
AD7915/
AD7916
DIGITAL HOST
47kΩ
SDO
DATA IN
SCK
IRQ
12583-017
A
CLK
Figure 36. 3-Wire CS Mode with Busy Indicator Connection Diagram
(SDI High)
E
A
A
tCYC
tCNVH
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
2
3
15
tHSDO
16
17
tSCKH
tDIS
tDSDO
SDO
D15
D14
D1
D0
Figure 37. 3-Wire CS Mode with Busy Indicator Serial Interface Timing (SDI High)
E
A
A
{
Rev. A | Page 19 of 27
12583-018
1
SCK
AD7915/AD7916
Data Sheet
minimum conversion time elapses and then held high for the
maximum possible conversion time. When the conversion is
complete, the AD7915/AD7916 enter the acquisition phase and
power down. Each ADC result can be read by bringing its SDI/CS
input low, which consequently outputs the MSB onto SDO. The
remaining data bits are then clocked by subsequent SCK falling
edges. The data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the SCK
falling edge allows a faster reading rate, provided that it has an
acceptable hold time. After the 16th SCK falling edge or when
SDI/CS goes high (whichever occurs first), SDO returns to high
impedance and another AD7915/AD7916 can be read.
CS MODE, 4-WIRE, WITHOUT BUSY INDICATOR
E
A
This mode is usually used when multiple AD7915/AD7916
devices are connected to an SPI-compatible digital host.
E
A
A connection diagram example using two AD7915/AD7916
devices is shown in Figure 39, and the corresponding timing is
given in Figure 40.
With SDI high, a rising edge on CNV initiates a conversion,
selects SDI/CS mode, and forces SDO to high impedance. In
this mode, CNV must be held high during the conversion phase
and the subsequent data read back; if SDI/CS and CNV are low,
SDO is driven low. Prior to the minimum conversion time,
SDI/CS can be used to select other SPI devices, such as analog
multiplexers, but SDI/CS must be returned high before the
E
A
A
E
E
A
A
A
A
E
A
A
E
A
A
CS2
CS1
CONVERT
CNV
SDI/CS
CNV
AD7915/
AD7916
SDO
SDI/CS
AD7915/
AD7916
SCK
DIGITAL HOST
SDO
SCK
12583-029
DATA IN
CLK
Figure 38. CS Mode Without Busy Indicator, 4-Wire Connection Diagram
E
A
A
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSSDICNV
SDI/CS (CS1)
tHSDICNV
SDI/CS (CS2)
tSCK
tSCKL
SCK
1
2
3
14
tHSDO
16
17
18
30
31
32
tSCKH
tDSDO
tEN
SDO
15
D15
D14
D13
tDIS
D1
D0
D15
D14
Figure 39. CS Mode Without Busy Indicator, 4-Wire Serial Interface Timing
E
A
A
Rev. A | Page 20 of 27
D1
D0
12583-030
A
A
Data Sheet
AD7915/AD7916
With a pull-up on the SDO line, this transition can be used as
an interrupt signal to initiate the data readback controlled by
the digital host. The AD7915/AD7916 then enters the
acquisition phase and powers down. The data bits are clocked
out, MSB first, by subsequent SCK falling edges. The data is
valid on both SCK edges. Although the rising edge can be used
to capture the data, a digital host using the SCK falling edge
allows a faster reading rate provided it has an acceptable hold
time. After the optional 17th SCK falling edge or SDI going
high, whichever is earlier, the SDO returns to high impedance.
CS MODE 4-WIRE WITH BUSY INDICATOR
E
A
This mode is usually used when a single AD7915/AD7916 is
connected to an SPI-compatible digital host that has an interrupt
input, and it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in applications
where low jitter on CNV is desired.
The connection diagram is shown in Figure 41, and the
corresponding timing is given in Figure 42.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase
and the subsequent data readback (if SDI and CNV are low,
SDO is driven low). Prior to the minimum conversion time,
SDI can be used to select other SPI devices, such as analog
multiplexers, but SDI must be returned low before the
minimum conversion time elapses and then held low for the
maximum conversion time to guarantee the generation of the
busy signal indicator. When the conversion is complete, SDO
goes from high impedance to low.
CS1
E
A
CONVERT
VIO
CNV
SDI
AD7915/
AD7916
DIGITAL HOST
47kΩ
SDO
DATA IN
SCK
IRQ
12583-300
A
CLK
Figure 40. 4-Wire CS Mode with Busy Indicator Connection Diagram
E
A
A
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSSDICNV
SDI
tSCK
tHSDICNV
tSCKL
1
SCK
2
3
15
16
17
tSCKH
tHSDO
tDSDO
tDIS
tEN
D15
SDO
D14
D1
Figure 41. 4-Wire CS Mode with Busy Indicator Serial Interface Timing
E
A
A
Rev. A | Page 21 of 27
D0
12583-301
A
AD7915/AD7916
Data Sheet
CHAIN MODE, WITHOUT BUSY INDICATOR
conversion is complete, the MSB is output onto SDO and the
AD7915/AD7916 enter the acquisition phase and power down.
The remaining data bits stored in the internal shift register are
clocked by subsequent SCK falling edges. For each ADC, SDI
feeds the input of the internal shift register and is clocked by
the SCK falling edge. Each ADC in the chain outputs its data
MSB first, and 16 × N clocks are required to read back the N
ADCs. The data is valid on both SCK edges. Although the
rising edge can be used to capture the data, a digital host using
the SCK falling edge allows a faster reading rate and,
consequently, more AD7915/AD7916 devices in the chain,
provided that the digital host has an acceptable hold time. The
maximum conversion rate may be reduced due to the total
readback time.
31B
This mode can be used to daisy-chain multiple AD7915/
AD7916 devices on a 3-wire serial interface. This feature is
useful for reducing component count and wiring connections,
for example, in isolated multiconverter applications or for
systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register.
A connection diagram example using two AD7915/AD7916
devices is shown in Figure 43, and the corresponding timing is
given in Figure 44.
When SDI/CS and CNV are low, SDO is driven low. With SCK
low, a rising edge on CNV initiates a conversion, and selects the
chain mode. In this mode, CNV is held high during the
conversion phase and the subsequent data readback. When the
E
A
A
CONVERT
CNV
AD7915/
AD7916
AD7915/
AD7916
SDO
SDI/CS
DIGITAL HOST
SDO
DATA IN
B
SCK
A
SCK
12583-031
SDI/CS
CNV
CLK
Figure 42. Chain Mode Without Busy Indicator Connection Diagram
SDI/CSA = 0
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
tSSCKCNV
SCK
1
2
3
14
15
tSSDISCK
tHSCKCNV
16
17
18
DA15
DA14
30
31
32
D A1
DA0
tSCKH
tHSDISCK
tEN
SDOA = SDI/CSB
DA15
DA14
DA13
DA 1
DA0
DB15
DB14
DB13
D B1
DB0
SDOB
Figure 43. Chain Mode Without Busy Indicator Serial Interface Timing
Rev. A | Page 22 of 27
12583-032
tHSDO
tDSDO
Data Sheet
AD7915/AD7916
completed their conversions, the SDO pin of the ADC closest
to the digital host (see the AD7915/AD7916 ADC labeled C in
Figure 45) is driven high. This transition on SDO can be used
as a busy indicator to trigger the data readback controlled by
the digital host. The AD7915/AD7916 then enter the
acquisition phase and powers down. The data bits stored in the
internal shift register are clocked out, MSB first, by subsequent
SCK falling edges. For each ADC, SDI feeds the input of the
internal shift register and is clocked by the SCK falling edge.
Each ADC in the chain outputs its data MSB first, and 16 × N + 1
clocks are required to readback the N ADCs. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate and, consequently,
more AD7915/AD7916 devices in the chain, provided that the
digital host has an acceptable hold time.
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7915/
AD7916 devices on a 3-wire serial interface while providing a
busy indicator. This feature is useful for reducing component
count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing
capacity. Data readback is analogous to clocking a shift register.
A connection diagram example using three AD7915/AD7916
devices is shown in Figure 45, and the corresponding timing is
given in Figure 46.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
CONVERT
CNV
CNV
AD7915/
AD7916
AD7915/
AD7916
SDO
SDI
SDO
SDI
A
B
C
SCK
SCK
SCK
DIGITAL HOST
SDO
DATA IN
IRQ
12583-302
SDI
CNV
AD7915/
AD7916
CLK
Figure 44. Chain Mode with Busy Indicator Connection Diagram
tCYC
CNV = SDIA
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSCKH
SCK
1
2
3
4
15
16
17
tSSDISCK
tHSDICNV
DA15
SDOA = SDIB
DA14
DA13
19
31
32
33
34
35
tSCKL
tHSDISC
tEN
18
DA1
tDSDOSDI
DB15
DB14
DB13
DB1
DB0
DA15
DA14
DA1
DA 0
DC15
DC14
DC13
DC1
DC0
DB15
DB14
D B1
DB0
tDSDOSDI
SDOC
49
DA 0
tDSDO
SDOB = SDIC
48
tDSDOSDI
tHSDO
tDSDOSDI
47
tDSDODSI
Figure 45. Chain Mode with Busy Indicator Serial Interface Timing
Rev. A | Page 23 of 27
DA15
DA14
DA1
D A0
12583-026
tSSDICNV
AD7915/AD7916
Data Sheet
APPLICATIONS INFORMATION
INTERFACING TO BLACKFIN DSP
LAYOUT
The AD7915/AD7916 can easily connect to a Blackfin® DSP SPI
or SPORT. The SPI configuration is straightforward using the
standard SPI interface, as shown in Figure 47.
Design the printed circuit board that houses the AD7915/
AD7916 so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7915/AD7916, with its analog signals on the left side and its
digital signals on the right side, eases this task.
SPI_MISO
SDO
SPI_MOSI
CNV
AD7915/
AD7916
Figure 46. Typical Connection to Blackfin SPI Interface
Similarly, the SPORT interface can be used to interface to this
ADC. The SPORT interface has some benefits in that it can use
direct memory access (DMA) and provides a lower jitter CNV
signal generated from a hardware counter.
Some glue logic may be required between SPORT and the
AD7915/AD7916 interface. The evaluation board for the
AD7915/AD7916 interfaces directly to the SPORT of the
Blackfin-based (ADSP-BF527) SDP board. The configuration
used for the SPORT interface requires the addition of some
glue logic as shown in Figure 48. The SCK input to the ADC
was gated off when CNV was high to keep the SCK line static
while converting the data, thereby ensuring the best integrity of
the result. This approach uses an AND gate and a NOT gate for
the SCK path. The other logic gates used on the RSCLK and
RFS paths are for delay matching purposes and may not be
necessary when path lengths are short.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7915/AD7916 is used as a shield. Do not run fast switching
signals, such as CNV or clocks, near analog signal paths. Avoid
crossover of digital and analog signals.
Using at least one ground plane is recommended. The ground
plane can be common or split between the digital and analog
sections. In the latter case, join the planes underneath the
AD7915/AD7916 devices.
The AD7915/AD7916 voltage reference input, REF, has a
dynamic input impedance. Decouple REF with minimal
parasitic inductances by placing the reference decoupling
ceramic capacitor close to, but ideally right up against, the REF
and GND pins and connecting them with wide, low impedance
traces.
Finally, decouple the power supplies of the AD7915/AD7916,
VDD and VIO, with ceramic capacitors, typically 100 nF,
placed close to the AD7915/AD7916 and connected using
short, wide traces to provide low impedance paths and to
reduce the effect of glitches on the power supply lines.
An example of a layout following these rules is shown in
Figure 49 and Figure 50.
This is one approach to using the SPORT interface for this
ADC; there may be other solutions similar to this approach.
VDRIVE
DR
SDO
AD7915/
AD7916
RSCLK
TSCLK
DSP
SCK
RFS
TFS
CNV
Figure 47. Evaluation Board Connection to Blackfin Sport Interface
Rev. A | Page 24 of 27
12583-045
SCK
12583-035
DSP
SPI_CLK
Data Sheet
AD7915/AD7916
EVALUATING AD7915/AD7916 PERFORMANCE
Other recommended layouts for the AD7915/AD7916 are
outlined in UG-340, the user guide of the evaluation board for the
AD7915/AD7916 (EVAL-AD7915SDZ/EVAL-AD7916SDZ). The
evaluation board package includes a fully assembled and tested
evaluation board, the user guide, and software for controlling
the board from a PC via the EVAL-SDP-CB1Z.
12583-034
AD7915/
AD7916
12583-033
Figure 49. Recommended Layout of the AD7915/AD7916 (Bottom Layer)
Figure 48. Recommended Layout of the AD7915/AD7916 (Top Layer)
Rev. A | Page 25 of 27
AD7915/AD7916
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
1
5.15
4.90
4.65
6
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.30
0.15
0.70
0.55
0.40
0.23
0.13
6°
0°
091709-A
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 50. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
2.48
2.38
2.23
3.10
3.00 SQ
2.90
0.50 BSC
10
6
PIN 1 INDEX
AREA
1.74
1.64
1.49
EXPOSED
PAD
0.50
0.40
0.30
1
5
BOTTOM VIEW
0.80
0.75
0.70
SEATING
PLANE
0.30
0.25
0.20
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 MIN
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
02-05-2013-C
TOP VIEW
0.20 REF
Figure 51. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2, 3
AD7915BRMZ
AD7915BRMZ-RL7
AD7915BCPZ-RL7
AD7916BRMZ
AD7916BRMZ-RL7
AD7916BCPZ-RL7
EVAL-AD7915SDZ
EVAL-AD7916SDZ
EVAL-SDP-CB1Z
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
10-Lead MSOP, Tube
10-Lead MSOP, 7” Tape and Reel
10-Lead LFCSP_WD, 7” Tape and Reel
10-Lead MSOP, Tube
10-Lead MSOP, 7” Tape and Reel
10-Lead LFCSP_WD, 7” Tape and Reel
Evaluation Board
Evaluation Board
System Demonstration Board, Used as a Controller
Board for Data Transfer via a USB Interface to PC
Package
Option
RM-10
RM-10
CP-10-9
RM-10
RM-10
CP-10-9
Ordering
Quantity
50
1,000
1,500
50
1,000
1,500
Branding
C85
C85
C87
C86
C86
C87
Z = RoHS Compliant Part.
The EVAL-AD7915DZ and EVAL-AD7916SDZ boards can be used as standalone evaluation boards, or in conjunction with the EVAL-SDP-CB1Z for evaluation and
demonstration purposes.
3
The EVAL-SDP-CB1Z board allows a PC to control and communicate with all Analog Devices, Inc., evaluation boards ending in the SD designator.
1
2
Rev. A | Page 26 of 27
Data Sheet
AD7915/AD7916
NOTES
©2015–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12583-7/20(A)
Rev. A | Page 27 of 27
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