AD7940BRJZ-REEL7

3 mW, 100 kSPS, 14-Bit ADC in 6-Lead SOT-23 AD7940 FUNCTIONAL BLOCK DIAGRAM FEATURES APPLICATIONS Battery-powered systems Personal digital assistants Medical instruments Mobile communications Instrumentation and control systems Remote data acquisition systems GENERAL DESCRIPTION 1 The AD7940 is a 14-bit, fast, low power, successive approximation ADC. The part operates from a single 2.50 V to 5.5 V power supply and features throughput rates up to 100 kSPS. The part contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 7 MHz. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is also initiated at this point. There are no pipelined delays associated with the part. The AD7940 uses advanced design techniques to achieve very low power dissipation at fast throughput rates. The reference for the part is taken internally from VDD, which allows the widest dynamic input range to the ADC. Thus, the analog input range for this part is 0 V to VDD. The conversion rate is determined by the SCLK frequency. VDD VIN T/H 14-BIT SUCCESSIVE APPROXIMATION ADC AD7940 CONTROL LOGIC SCLK SDATA CS 03305-0-001 Fast throughput rate: 100 kSPS Specified for VDD of 2.5 V to 5.5 V Low power 4 mW typ at 100 kSPS with 3 V supplies 17 mW typ at 100 kSPS with 5 V supplies Wide input bandwidth: 81 dB SINAD at 10 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface SPI®/QSPI™/MICROWIRE™/DSP compatible Standby mode: 0.5 µA max 6-Lead SOT-23 and 8-Lead MSOP packages GND Figure 1. Table 1. 16-Bit and 14-Bit ADC (MSOP and SOT-23) Type 16-Bit True Differential 16-Bit Pseudo Differential 16-Bit Unipolar 14-Bit True Differential 14-Bit Pseudo Differential 14-Bit Unipolar 100 kSPS AD7684 AD7683 AD7680 250 kSPS AD7687 AD7685 500 kSPS AD7688 AD7686 AD7944 AD7942 AD7947 AD7946 AD7940 This part features a standard successive approximation ADC with accurate control of the sampling instant via a CS input and once off conversion control. PRODUCT HIGHLIGHTS 1. First 14-bit ADC in a SOT-23 package. 2. High throughput with low power consumption. 3. Flexible power/serial clock speed management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. This allows the average power consumption to be reduced when a power-down mode is used while not converting. The part also features a shutdown mode to maximize power efficiency at lower throughput rates. Power consumption is 0.5 µA max when in shutdown. 4. Reference derived from the power supply. 5. No pipeline delay. 1 Protected by US. Patent No. 6,681,332. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 ©2004–2011 Analog Devices, Inc. All rights reserved. AD7940 TABLE OF CONTENTS Table of Contents .............................................................................. 2  Normal Mode.............................................................................. 13  Specifications..................................................................................... 3  Power-Down Mode .................................................................... 14  Timing Specifications....................................................................... 5  Power vs. Throughput Rate ........................................................... 15  Absolute Maximum Ratings............................................................ 6  Serial Interface ................................................................................ 16  ESD Caution .................................................................................. 6  Microprocessor Interfacing ........................................................... 17  Pin Configurations and Function Descriptions ........................... 7  AD7940 to TMS320C541 .......................................................... 17  Terminology ...................................................................................... 8  AD7940 to ADSP-218x .............................................................. 17  Typical Performance Characteristics ............................................. 9  AD7940 to DSP563xx ................................................................ 18  Circuit Information ........................................................................ 11  Application Hints ........................................................................... 19  Converter Operation .................................................................. 11  Grounding and Layout .............................................................. 19  Analog Input ............................................................................... 11  Evaluating the AD7940 Performance ...................................... 19  ADC Transfer Function ................................................................. 12  Outline Dimensions ....................................................................... 20  Typical Connection Diagram ................................................... 12  Ordering Guide .......................................................................... 20  Modes of Operation ....................................................................... 13  REVISION HISTORY 8/11—Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 20 7/04—Revision 0: Initial Version AD7940 SPECIFICATIONS1 VDD = 2.50 V to 5.5 V, fSCLK = 2.5 MHz, fSAMPLE = 100 kSPS, unless otherwise noted; TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD) 2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity2 Offset Error2 Gain Error2 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN2, 3 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance2, 3 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS VDD IDD Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode B Version1 Unit 81 −98 −95 dB min dB typ dB typ −94 −100 20 30 7 2 dB typ dB typ ns max ps typ MHz typ MHz typ 14 13 ±1 ±2 ±6 ±8 Bits min Bits min LSB max LSB max LSB max LSB max 0 to VDD ±0.3 30 V µA max pF typ 2.4 0.4 0.8 ±0.3 10 V min V max V max µA max pF max Test Conditions/Comments fIN = 10 kHz sine wave @ −3 dB @ −0.1 dB VDD = 2.5 V to 4.096 V VDD > 4.096 V VDD = 2.5 V to 4.096 V VDD > 4.096 V VDD = 3 V VDD = 5 V Typically 10 nA, VIN = 0 V or VDD VDD – 0.2 V min 0.4 V max ±0.3 µA max 10 pF max Straight (Natural) Binary ISOURCE = 200 µA; VDD = 2.50 V to 5.25 V ISINK = 200 µA 8 500 400 100 µs max ns max ns max kSPS max 16 SCLK cycles Full-scale step input Sine wave input ≤ 10 kHz See the Serial Interface section 2.50/5.5 V min/V max 5.2 2 4.8 1.9 0.5 0.3 mA max mA max mA max mA max µA max µA max Rev. A | Page 3 of 20 Digital I/PS = 0 V or VDD VDD = 5.5 V; SCLK on or off VDD = 3.6 V; SCLK on or off VDD = 5.5 V; fSAMPLE = 100 kSPS; 3.3 mA typ VDD = 3.6 V; fSAMPLE = 100 kSPS; 1.29 mA typ SCLK on or off. VDD = 5.5 V SCLK on or off. VDD = 3.6 V AD7940 Parameter Power Dissipation 4 Normal Mode (Operational) Full Power-Down B Version1 Unit 26.4 6.84 2.5 1.08 mW max mW max µW max µW max 1 Temperature range for B Version is –40°C to +85°C. See the Terminology section. Sample tested at initial release to ensure compliance. 4 See the Power vs. Throughput Rate section. 2 3 Rev. A | Page 4 of 20 Test Conditions/Comments VDD = 5.5 V VDD = 5.5 V; fSAMPLE = 100 kSPS VDD = 3.6 V; fSAMPLE = 100 kSPS VDD = 5.5 V VDD = 3.6 V AD7940 TIMING SPECIFICATIONS Sample tested at initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. VDD = 2.50 V to 5.5 V; TA = TMIN to TMAX, unless otherwise noted. Table 3. tCONVERT tQUIET Limit at TMIN, TMAX 3V 5V 250 250 2.5 2.5 16 × tSCLK 16 × tSCLK 50 50 Unit kHz min MHz max min ns min t1 t2 t3 2 t4 2 t5 t6 t7 t8 3 tPOWER-UP 4 10 10 48 120 0.4 tSCLK 0.4 tSCLK 10 45 1 ns min ns min ns max ns max ns min ns min ns min ns max µs typ Parameter fSCLK 1 10 10 35 80 0.4 tSCLK 0.4 tSCLK 10 35 1 Description Minimum quiet time required between bus relinquish and start of next conversion Minimum CS pulse width CS to SCLK setup time Delay from CS until SDATA three-state disabled Data access time after SCLK falling edge SCLK low pulse width SCLK high pulse width SCLK to data valid hold time SCLK falling edge to SDATA high impedance Power up time from full power-down 1 Mark/space ratio for the SCLK input is 40/60 to 60/40. Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 4 See the Power vs. Throughput Rate section. 2 3 200µA 1.6V CL 50pF 200µA IOH 03305-0-002 TO OUTPUT PIN IOL Figure 2. Load Circuit for Digital Output Timing Specification Rev. A | Page 5 of 20 AD7940 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter VDD to GND Analog Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND Input Current to Any Pin Except Supplies 1 Operating Temperature Range Commercial (B Version) Storage Temperature Range Junction Temperature SOT-23 Package, Power Dissipation θJA Thermal Impedance θJC Thermal Impedance MSOP Package, Power Dissipation θJA Thermal Impedance θJC Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 secs) Infared (15 secs) ESD 1 Rating −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to +7 V −0.3 V to VDD + 0.3 V ±10 mA −40°C to +85°C −65°C to +150°C 150°C 450 mW 229.6°C/W 91.99°C/W 450 mW 205.9°C/W 43.74°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 215°C 220°C 4 kV Transient currents of up to 100 mA will not cause SCR latch-up. Rev. A | Page 6 of 20 AD7940 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AD7940 6 CS 5 SDATA TOP VIEW VIN 3 (Not to Scale) 4 SCLK VDD 1 GND 2 03305-0-023 VDD 1 GND 2 AD7490 TOP VIEW GND 3 (Not to Scale) 4 VIN Figure 3. SOT-23 Pin Configuration 8 CS 7 SDATA 6 NC 5 SCLK NC = NO CONNECT 03305-0-003 MSOP SOT-23 Figure 4. MSOP Pin Configuration Table 5. Pin Function Descriptions Pin No. SOT-23 1 2 Pin No. MSOP 1 2, 3 Mnemonic VDD GND 3 4 4 5 VIN SCLK 5 7 SDATA 6 8 CS N/A 6 NC Function Power Supply Input. The VDD range for the AD7940 is from 2.5 V to 5.5 V. Analog Ground. Ground reference point for all circuitry on the AD7940. All analog input signals should be referred to this GND voltage. Analog Input. Single-ended analog input channel. The input range is 0 V to VDD. Serial Clock. Logic input. SCLK provides the serial clock for accessing data from this part. This clock input is also used as the clock source for the AD7940's conversion process. Data Out. Logic output. The conversion result from the AD7940 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7940 consists of two leading zeros followed by 14 bits of conversion data that are provided MSB first. This will be followed by four trailing zeroes if CS is held low for a total of 24 SCLK cycles. See the Serial Interface section. Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7940 and framing the serial data transfer. No Connect. This pin should be left unconnected. Rev. A | Page 7 of 20 AD7940 TERMINOLOGY Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition, and full scale, a point 1/2 LSB above the last code transition. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error This is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e., AGND + 1 LSB. Gain Error This is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., VREF − 1 LSB) after the offset error has been adjusted out. Track-and-Hold Acquisition Time The track-and-hold amplifier returns to track mode at the end of conversion. The track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1 LSB, after the end of the conversion. See the Serial Interface section for more details. Signal-to-(Noise + Distortion) Ratio This is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2, excluding dc). The ratio depends on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 14-bit converter, this is 86.04 dB. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7940, it is defined as THD (dB) = 20 log V2 2 + V3 2 + V4 2 + V5 2 + V6 2 V1 where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the secondorder terms include (fa + fb) and (fa − fb), while the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa −2fb). The AD7940 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs. Rev. A | Page 8 of 20 AD7940 TYPICAL PERFORMANCE CHARACTERISTICS Figure 5 shows a typical FFT plot for the AD7940 at 100 kSPS sample rate and 10 kHz input frequency. Figure 6 shows the signal-to-(noise + distortion) ratio performance versus the input frequency for various supply voltages while sampling at 100 kSPS with an SCLK of 2.5 MHz. Figure 7 shows a graph of the total harmonic distortion versus the analog input frequency for various supply voltages, while Figure 8 shows a graph of the total harmonic distortion versus the analog input frequency for various source impedances (see the Analog Input section). Figure 9 and Figure 10 show the typical INL and DNL plots for the AD7940. 110 0 VDD = 4.75V FSAMPLE = 100kSPS FIN = 10kHz SNR = 84.48dB SINAD = 84.35dB THD = –98.97dB SFDR = –100.84dB –20 –40 105 VDD = 3V VDD = 3.6V VDD = 2.7V 100 THD (dB) –80 VDD = 4.3V 95 –100 90 VDD = 5.25V VDD = 2.5V VDD = 4.75V –120 –160 0 10k 20k 30k 40k 03305-0-021 85 03305-0-019 –140 80 10 50k 100 INPUT FREQUENCY (kHz) FREQUENCY (kHz) Figure 5. AD7940 Dynamic Performance at 100 kSPS Figure 7. AD7940 THD vs. Analog Input Frequency for Various Supply Voltages at 100 kSPS 90 110 FSAMPLE = 100kSPS TA = 25°C 105 VDD = 4.75V FSAMPLE = 100kSPS TA = 25°C VDD = 5.25V 100 VDD = 4.75V SINAD (dB) 85 THD (dB) VDD = 3.6V VDD = 3V 80 VDD = 2.7V 75 10 RIN = 50Ω 90 RIN = 100Ω 85 80 03305-0-020 VDD = 2.5V RIN = 10Ω 95 VDD = 4.3V 75 RIN = 1000Ω 70 10 100 INPUT FREQUENCY (kHz) 100 INPUT FREQUENCY (kHz) Figure 8. AD7940 THD vs. Analog Input Frequency for Various Source Impedances Figure 6. AD7940 SINAD vs. Analog Input Frequency for Various Supply Voltages at 100 kSPS Rev. A | Page 9 of 20 03305-0-022 (dB) –60 FSAMPLE = 100kSPS TA = 25°C AD7940 0.8 VDD = 3.00V TEMP = 25°C 0.6 0.6 0.4 DNL ERROR (LSB) 0.8 0.4 0.2 0 VDD = 3.00V TEMP = 25°C 0.2 0 –0.2 –0.4 –0.6 0 2000 4000 6000 03305-0-017 –0.4 –0.2 03305-0-018 INL ERROR (LSB) 1.0 –0.6 –0.8 0 8000 10000 12000 14000 16000 18000 2000 4000 6000 8000 10000 12000 14000 16000 18000 CODE CODE Figure 9. AD7940 Typical INL Figure 10. AD7940 Typical DNL Rev. A | Page 10 of 20 AD7940 CIRCUIT INFORMATION The AD7940 provides the user with an on-chip track-and-hold ADC and a serial interface housed in a tiny 6-lead SOT-23 package or in an 8-lead MSOP package, which offer the user considerable space-saving advantages over alternative solutions. The serial clock input accesses data from the part and also provides the clock source for the successive approximation ADC. The analog input range for the AD7940 is 0 V to VDD. An external reference is not required for the ADC nor is there a reference on-chip. The reference for the AD7940 is derived from the power supply and thus gives the widest dynamic input range. The AD7940 also features a power-down option to save power between conversions. The power-down feature is implemented across the standard serial interface as described in the Modes of Operation section. CONVERTER OPERATION The AD7940 is a 14-bit, successive approximation ADC based around a capacitive DAC. The AD7940 can convert analog input signals in the 0 V to VDD range. Figure 11 and Figure 12 show simplified schematics of the ADC. The ADC comprises of control logic, SAR, and a capacitive DAC. Figure 11 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in Position A. The comparator is held in a balanced condition and the sampling capacitor acquires the signal on the selected VIN channel. CAPACITIVE DAC SAMPLING CAPACITOR CONTROL LOGIC B ACQUISITION SW2 PHASE VDD/2 COMPARATOR SAMPLING CAPACITOR A VIN SW1 CONTROL LOGIC B CONVERSION SW2 PHASE COMPARATOR VDD/2 Figure 12. ADC Conversion Phase ANALOG INPUT Figure 13 shows an equivalent circuit of the analog input structure of the AD7940. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 300 mV. This will cause these diodes to become forward-biased and to start conducting current into the substrate. The maximum current these diodes can conduct without causing irreversible damage to the part is 10 mA. Capacitor C1 in Figure 13 is typically about 5 pF and primarily can be attributed to pin capacitance. Resistor R1 is a lumped component made up of the on resistance of a switch (track-andhold switch). This resistor is typically about 25 Ω. Capacitor C2 is the ADC sampling capacitor and has a capacitance of 25 pF typically. For ac applications, removing high frequency components from the analog input signal is recommended by use of an RC low-pass filter on the relevant analog input pin. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances will significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp will be a function of the particular application. When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance will depend on the amount of total harmonic distortion (THD) that can be tolerated. The THD will increase as the source impedance increases, and performance will degrade (see Figure 8). VDD Figure 11. ADC Acquisition Phase D1 When the ADC starts a conversion, SW2 will open and SW1 will move to Position B, causing the comparator to become unbalanced (Figure 12). The control logic and the capacitive DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code (see the ADC Transfer Function section). Rev. A | Page 11 of 20 R1 C2 30pF VIN C1 4pF D2 CONVERSION PHASE - SWITCH OPEN TRACK PHASE - SWITCH CLOSED Figure 13. Equivalent Analog Input Circuit 03305-0-006 SW1 03305-0-004 A VIN CAPACITIVE DAC 03305-0-005 The AD7940 is a fast, low power, 14-bit, single-supply ADC. The part can be operated from a 2.50 V to 5.5 V supply. When operated at either 5 V or 3 V supply, the AD7940 is capable of throughput rates of 100 kSPS when provided with a 2.5 MHz clock. AD7940 ADC TRANSFER FUNCTION The output coding of the AD7940 is straight binary. The designed code transitions occur at successive integer LSB values, i.e., 1 LSB, 2 LSBs. The LSB size is VDD/16384. The ideal transfer characteristic for the AD7940 is shown in Figure 14. 111...111 111...110 111...000 1 LSB = VDD/16384 011...111 In fact, because the supply current required by the AD7940 is so low, a precision reference can be used as the supply source to the AD7940. For example, a REF19x voltage reference (REF195 for 5 V or REF193 for 3 V) or an AD780 can be used to supply the required voltage to the ADC (see Figure 15). This configuration is especially useful if the power supply available is quite noisy, or if the system supply voltages are at some value other than the required operating voltage of the AD7940, e.g., 15 V. The REF19x or AD780 will output a steady voltage to the AD7940. Recommended decoupling capacitors are a 100 nF low ESR ceramic (Farnell 335-1816) and a 10 µF low ESR tantalum (Farnell 197-130). 3V 10µF TANT 000...010 5V SUPPLY REF193 0.1µF 10µF 0.1µF 0V 1 LSB +VDD–1 LSB ANALOG INPUT VDD 0V TO VDD INPUT VIN Figure 14. AD7940 Transfer Characteristic SCLK AD7940 SDATA µC/µP CS GND TYPICAL CONNECTION DIAGRAM Figure 15 shows a typical connection diagram for the AD7940. VREF is taken internally from VDD and as such should be well decoupled. This provides an analog input range of 0 V to VDD. The conversion result is output in a 16-bit word. This 16-bit data stream consists of two leading zeros, followed by the 14 bits of conversion data, MSB first. For applications where power consumption is a concern, the power-down mode should be used between conversions or bursts of several conversions to improve power performance (see the Modes of Operation section). SERIAL INTERFACE 03305-0-008 000...000 03305-0-007 000...001 Figure 15. Typical Connection Diagram Digital Inputs The digital inputs applied to the AD7940 are not limited by the maximum ratings that limit the analog inputs. Instead, the digital inputs applied can go to 7 V and are not restricted by the VDD + 0.3 V limit as on the analog inputs. For example, if the AD7940 were operated with a VDD of 3 V, 5 V logic levels could be used on the digital inputs. However, it is important to note that the data output on SDATA will still have 3 V logic levels when VDD = 3 V. Another advantage of SCLK and CS not being restricted by the VDD + 0.3 V limit is the fact that power supply sequencing issues are avoided. If one of these digital inputs is applied before VDD, there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 V were applied prior to VDD. Rev. A | Page 12 of 20 AD7940 MODES OF OPERATION The mode of operation of the AD7940 is selected by controlling the (logic) state of the CS signal during a conversion. There are two possible modes of operation, normal and power-down. The point at which CS is pulled high after the conversion has been initiated will determine whether or not the AD7940 will enter power-down mode. Similarly, if already in power-down, CS can control whether the device will return to normal operation or remain in power-down. These modes of operation are designed to provide flexible power management options. These options can optimize the power dissipation/throughput rate ratio for differing application requirements. NORMAL MODE This mode provides the fastest throughput rate performance because the user does not have to worry about the power-up times with the AD7940 remaining fully powered all the time. Figure 16 shows the general diagram of the operation of the AD7940 in this mode. The conversion is initiated on the falling edge of CS as described in the Serial Interface section. To ensure that the part remains fully powered up at all times, CS must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CS. If CS is brought high any time after the 10th SCLK falling edge, but before the 16th SCLK falling edge, the part will remain powered up, but the conversion will be terminated and SDATA will go back into three-state. At least 16 serial clock cycles are required to complete the conversion and access the complete conversion result. CS may idle high until the next conversion or may idle low until CS returns high sometime prior to the next conversion, effectively idling CS low. Once a data transfer is complete (SDATA has returned to threestate), another conversion can be initiated after the quiet time, tQUIET, has elapsed by bringing CS low again. CS 1 12 16 SDATA 1 LEADING ZERO + CONVERSION RESULT Figure 16. Normal Mode Operation Rev. A | Page 13 of 20 03305-0-009 SCLK AD7940 POWER-DOWN MODE This mode is intended for use in applications where slower throughput rates are required. Either the ADC is powered down between each conversion, or a series of conversions may be performed at a high throughput rate, and then the ADC is powered down for a relatively long duration between these bursts of several conversions. When the AD7940 is in powerdown, all analog circuitry is powered down. To enter power-down, the conversion process must be interrupted by bringing CS high anywhere after the second falling edge of SCLK and before the 10th falling edge of SCLK as shown in Figure 17. Once CS has been brought high in this window of SCLKs, the part will enter power-down, the conversion that was initiated by the falling edge of CS will be terminated, and SDATA will go back into three-state. If CS is brought high before the second SCLK falling edge, the part will remain in normal mode and will not power down. This will avoid accidental power-down due to glitches on the CS line. In order to exit this mode of operation and power up the AD7940 again, a dummy conversion is performed. On the falling edge of CS, the device will begin to power up and will continue to power up as long as CS is held low until after the falling edge of the 10th SCLK. The device will be fully powered up once at least 16 SCLKs (or approximately 6 µs) have elapsed and valid data will result from the next conversion as shown in Figure 18. If CS is brought high before the 10th falling edge of SCLK, regardless of the SCLK frequency, the AD7940 will go back into power-down again. This avoids accidental power-up due to glitches on the CS line or an inadvertent burst of 8 SCLK cycles while CS is low. So although the device may begin to power-up on the falling edge of CS, it will power down again on the rising edge of CS as long as it occurs before the 10th SCLK falling edge. CS 1 2 10 16 THREE-STATE SDATA 03305-0-010 SCLK Figure 17. Entering Power-Down Mode THE PART IS FULLY POWERED UP WITH VIN FULLY ACQUIRED THE PART BEGINS TO POWER UP tPOWER UP CS 1 10 16 1 16 SDATA INVALID DATA VALID DATA Figure 18. Exiting Power-Down Mode Rev. A | Page 14 of 20 03305-0-011 SCLK AD7940 POWER VS. THROUGHPUT RATE Figure 19 shows the power dissipation versus the throughput rate when using the power-down mode with 3.6 V supplies and a 2.5 MHz SCLK. (7.4/100) × (6.84 mW) + (92.6/100) × (1.08 µW) = 0.51 mW Rev. A | Page 15 of 20 VDD = 3.6V FSCLK = 2.5MHz 1 0.1 03305-0-012 For example, if the AD7940 is operated in a continuous sampling mode, with a throughput rate of 10 kSPS and an SCLK of 2.5 MHz (VDD = 3.6 V), and the device is placed in powerdown mode between conversions, the power consumption is calculated as follows. The maximum power dissipation during normal operation is 6.84 mW (VDD = 3.6 V). If the power-up time from power-down is 1 µs, and the remaining conversion time is 6.4 µs, (using a 16 SCLK transfer), then the AD7940 can be said to dissipate 6.84 mW for 7.4 µs during each conversion cycle. With a throughput rate of 10 kSPS, the cycle time is 100 µs. For the remainder of the conversion cycle, 92.6 µs, the part remains in power-down mode. The AD7940 can be said to dissipate 1.08 µW for the remaining 92.6 µs of the conversion cycle. Therefore, with a throughput rate of 10 kSPS, the average power dissipated during each cycle is 10 POWER (mW) By using the power-down mode on the AD7940 when not converting, the average power consumption of the ADC decreases at lower throughput rates. Figure 19 shows how as the throughput rate is reduced, the part remains in its shutdown state longer, and the average power consumption over time drops accordingly. 0.01 0 5 10 15 20 25 30 35 40 45 50 THROUGHPUT (kSPS) Figure 19. Power vs. Throughput Using Power-Down Mode at 3.6 V AD7940 SERIAL INTERFACE Figure 20 shows the detailed timing diagram for serial interfacing to the AD7940. The serial clock provides the conversion clock and also controls the transfer of information from the AD7940 during conversion. The CS signal initiates the data transfer and conversion process. The falling edge of CS puts the track-and-hold into hold mode, takes the bus out of three-state, and samples the analog input. The conversion is also initiated at this point and will require at least 16 SCLK cycles to complete. Once 15 SCLK falling edges have elapsed, the track-and-hold will go back into track mode on the next SCLK rising edge as shown in Figure 20 at Point B. On the 16th SCLK falling edge, the SDATA line will go back into three-state. If the rising edge of CS occurs before 16 SCLKs have elapsed, the conversion will be terminated and the SDATA line will go back into three-state; otherwise SDATA returns to three-state on the 16th SCLK falling edge as shown in Figure 20. Sixteen serial clock cycles are required to perform the conversion process and to access data from the AD7940. CS going low provides the first leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges beginning with the second leading zero, thus the first falling clock edge on the serial clock has the first leading zero provided and also clocks out the second leading zero. The data transfer will consist of two leading zeros followed by the 14 bits of data. The final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. It is also possible to take valid data on each SCLK rising edge rather than falling edge, since the SCLK cycle time is long enough to ensure the data is ready on the rising edge of SCLK. However, the first leading zero will still be driven by the CS falling edge, and so it can be taken only on the first SCLK falling edge. It may be ignored, and the first rising edge of SCLK after the CS falling edge would have the second leading zero provided and the 15th rising SCLK edge would have DB0 provided. This method may not work with most microcontrollers/DSPs, but could possibly be used with FPGAs and ASICs. CS t6 1 SCLK 2 3 4 tCONVERT B 5 13 14 SDATA 3-STATE 16 t5 t7 t3 15 t8 tQUIET t4 0 ZERO DB13 DB12 DB11 DB10 DB2 DB1 2 LEADING ZEROS Figure 20. AD7940 Serial Interface Timing Diagram Rev. A | Page 16 of 20 DB0 3-STATE 03305-0-013 t2 AD7940 MICROPROCESSOR INTERFACING The serial interface on the AD7940 allows the part to be directly connected to a range of many different microprocessors. This section explains how to interface the AD7940 with some of the more common microcontroller and DSP serial interface protocols. AD7940 TO ADSP-218x The ADSP-218x family of DSPs can be interfaced directly to the AD7940 with no glue logic required. The SPORT control register should be set up as follows: TFSW = RFSW = 1, Alternate Framing AD7940 TO TMS320C541 INVRFS = INVTFS = 1, Active Low Frame Signal The serial interface on the TMS320C541 uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices such as the AD7940. The CS input allows easy interfacing between the TMS320C541 and the AD7940 with no glue logic required. The serial port of the TMS320C541 is set up to operate in burst mode with internal CLKX (TX serial clock) and FSX (TX frame sync). The serial port control register (SPC) must have the following setup: FO = 0 FSM = 1 MCM = 1 TXM = 1 The format bit, FO, must be set to 1 to set the word length to 8 bits, in order to implement the power-down mode on the AD7940. The connection diagram is shown in Figure 21. It should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the TMS320C541 provide equidistant sampling. AD7940* SCLK DTYPE = 00, Right Justify Data SLEN = 1111, 16-Bit Data-Words ISCLK = 1, Internal Serial Clock TFSR = RFSR = 0, Frame First Word IRFS = 0 ITFS = 1 To implement power-down mode, SLEN should be set to 0111 to issue an 8-bit SCLK burst. The connection diagram is shown in Figure 22. The ADSP-218x has the TFS and RFS of the SPORT tied together, with TFS set as an output and RFS set as an input. The DSP operates in alternate framing mode, and the SPORT control register is set up as described. The frame synchronization signal generated on the TFS is tied to CS, and, as with all signal processing applications, equidistant sampling is necessary. In this example, the timer interrupt is used to control the sampling rate of the ADC. AD7940* SCLK TMS320C541* CLKX SDATA ADSP-218x* SCLK DR CS CS RFS DR FSX FSR TFS 03305-0-014 SDATA *ADDITIONAL PINS OMITTED FOR CLARITY *ADDITIONAL PINS OMITTED FOR CLARITY Figure 21. Interfacing to the TMS320C541 03305-0-015 CLKR Figure 22. Interfacing to the ADSP-218x The timer register is loaded with a value that provides an interrupt at the required sample interval. When an interrupt is received, the values in the transmit autobuffer start to be transmitted and TFS is generated. The TFS is used to control the RFS and, therefore, the reading of data. The data is stored in the receive autobuffer for processing or to be shifted later. The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given, i.e., TX0 = AX0, the state of the SCLK is checked. The DSP waits until the SCLK has gone high, low, and high before transmission will start. If the timer and SCLK values are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, the data may be transmitted, or it may wait until the next clock edge. Rev. A | Page 17 of 20 AD7940 For example, if the ADSP-2189 had a 20 MHz crystal, such that it had a master clock frequency of 40 MHz, the master cycle time would be 25 ns. If the SCLKDIV register is loaded with the value 7, then a SCLK of 2.5 MHz is obtained, and 16 master clock periods will elapse for every 1 SCLK period. Depending on the throughput rate selected, if the timer register was loaded with the value 803 (803 + 1 = 804), then 50.25 SCLKs will occur between interrupts and subsequently between transmit instructions. This situation will result in nonequidistant sampling since the transmit instruction is occurring on a SCLK edge. If the number of SCLKs between interrupts is a whole integer figure of N, then equidistant sampling will be implemented by the DSP. AD7940 TO DSP563xx The connection diagram in Figure 23 shows how the AD7940 can be connected to the ESSI (synchronous serial interface) of the DSP-563xx family of DSPs from Motorola. Each ESSI (two on board) is operated in synchronous mode (SYN bit in CRB = 1) with internally generated 1-bit clock period frame sync for both Tx and Rx (Bits FSL1 = 0 and FSL0 = 0 in CRB). Normal operation of the ESSI is selected by making MOD = 0 in the CRB. Set the word length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. The FSP bit in the CRB should be set to 1 so that the frame sync is negative. It should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the DSP-563xx provide equidistant sampling. In the example shown in Figure 23, the serial clock is taken from the ESSI so the SCK0 pin must be set as an output, SCKD = 1. DSP-563xx* SCLK SCK DOUT SRD CS STD *ADDITIONAL PINS OMITTED FOR CLARITY Figure 23. Interfacing to the DSP-563xx Rev. A | Page 18 of 20 03305-0-016 AD7940* AD7940 APPLICATION HINTS GROUNDING AND LAYOUT The printed circuit board that houses the AD7940 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes, since it gives the best shielding. Digital and analog ground planes should be joined at only one place. If the AD7940 is in a system where multiple devices require an AGND to DGND connection, the connection should still be made at one point only, a star ground point that should be established as close as possible to the AD7940. Avoid running digital lines under the device since these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7940 to avoid noise coupling. The power supply lines to the AD7940 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other, which will reduce the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while the signals are placed on the solder side. Good decoupling is also very important. All analog supplies should be decoupled with 10 µF tantalum in parallel with 0.1 µF capacitors to AGND, as discussed in the Typical Connection Diagram section. To achieve the best performance from these decoupling components, the user should attempt to keep the distance between the decoupling capacitors and the VDD and GND pins to a minimum, with short track lengths connecting the respective pins. EVALUATING THE AD7940 PERFORMANCE The recommended layout for the AD7940 is outlined in the evaluation board for the AD7940. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the PC via the evaluation board controller. The evaluation board controller can be used in conjunction with the AD7940 evaluation board, as well as many other Analog Devices evaluation boards ending in the CB designator, to demonstrate/evaluate the ac and dc performance of the AD7940. The software allows the user to perform ac (fast Fourier transform) and dc (histogram of codes) tests on the AD7940. The software and documentation are on a CD shipped with the evaluation board. Rev. A | Page 19 of 20 AD7940 OUTLINE DIMENSIONS 3.00 2.90 2.80 1.70 1.60 1.50 6 5 4 1 2 3 3.00 2.80 2.60 PIN 1 INDICATOR 0.95 BSC 1.90 BSC 1.30 1.15 0.90 0.20 MAX 0.08 MIN 0.15 MAX 0.05 MIN 10° 4° 0° SEATING PLANE 0.50 MAX 0.30 MIN 0.60 BSC 0.55 0.45 0.35 12-16-2008-A 1.45 MAX 0.95 MIN COMPLIANT TO JEDEC STANDARDS MO-178-AB Figure 24. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6). Dimensions shown in millimeters 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5 5.15 4.90 4.65 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.40 0.25 6° 0° 0.23 0.09 COMPLIANT TO JEDEC STANDARDS MO-187-AA 0.80 0.55 0.40 10-07-2009-B 0.15 0.05 COPLANARITY 0.10 Figure 25. 8-Lead Mini Small Outline Package [MSOP] (RM-8). Dimensions shown in millimeters ORDERING GUIDE Models1 AD7940BRM AD7940BRM-REEL7 AD7940BRMZ AD7940BRMZ-REEL7 AD7940BRJZ-REEL7 EVAL-AD7940CBZ EVAL-CONTROL BRD2 Notes Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C 3 4 1 Linearity Error (LSB)2 14 bits min 14 bits min 14 bits min 14 bits min 14 bits min Package Description Mini Small Outline Package (MSOP) Mini Small Outline Package (MSOP) Mini Small Outline Package (MSOP) Mini Small Outline Package (MSOP) Small Outline Transistor Package (SOT-23) Evaluation Board Controller Board Package Option RM-8 RM-8 RM-8 RM-8 RJ-6 Branding CRB CRB C06 C06 C06 Z = RoHS Compliant Part. Linearity error here refers to no missing codes. 3 This can be used as a standalone evaluation board or in conjunction with the Evaluation Controller Board for evaluation/demonstration purposes. 4 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete evaluation kit, the particular ADC evaluation board needs to be ordered, e.g., EVAL-AD7940CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See the Evaluation Board application note for more information. 2 ©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03305-0-8/11(A)