14-Bit, 500 kSPS,
PulSAR ADC in MSOP and LFCSP
AD7946
Data Sheet
TYPICAL APPLICATION CIRCUIT
0.5V TO 5V
14-bit resolution with no missing codes
Throughput: 500 kSPS
INL: ±0.4 LSB typical, ±1 LSB maximum (±0.0061% of FSR)
SINAD: 85 dB at 20 kHz
THD: −100 dB at 20 kHz
Pseudo differential analog input range
0 V to REF with REF up to VDD
No pipeline delay
Single-supply 5 V operation with 1.8 V/2.5 V/3 V/5 V logic
interface
Proprietary serial interface
SPI-/QSPI™-/MICROWIRE™-/DSP-compatible
Daisy-chain multiple ADCs and BUSY indicator
Power dissipation
3.3 mW at 5 V/100 kSPS
3.3 µW at 5 V/100 SPS
Standby current: 1 nA
10-lead MSOP (MSOP-8 size) and
3 mm × 3 mm LFCSP (SOT-23 size)
Pin-for-pin compatible with the 16-bit AD7686
0V TO REF
IN+
IN–
5V
REF VDD VIO
SDI
AD7946
1.8V TO VDD
SCK
SDO
GND
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
CNV
04656-001
FEATURES
Figure 1.
GENERAL DESCRIPTION
The AD7946 1 is a 14-bit, charge redistribution, successive
approximation, analog-to-digital converter (ADC) that operates
from a single 5 V power supply, VDD. It contains a low power,
high speed, 14-bit sampling ADC with no missing codes, an
internal conversion clock, and a versatile serial interface port.
The part also contains a low noise, wide bandwidth, short
aperture delay track-and-hold circuit. On the CNV rising edge,
it samples an analog input IN+ between 0 V to REF with respect
to a ground sense IN−. The reference voltage, REF, is applied
externally and can be set up to the supply voltage.
APPLICATIONS
Its power scales linearly with throughput.
Battery-powered equipment
Data acquisition
Instrumentation
Medical instruments
Process control
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single,
3-wire bus, or it provides an optional BUSY indicator. It is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate
supply VIO.
The AD7946 is housed in a 10-lead MSOP or a 10-lead LFCSP
with operation specified from −40°C to +85°C.
1
Protected by U.S. Patent 6,703,961.
Table 1. MSOP, LFCSP 14-/16-/18-Bit PulSAR® ADC
Type
14-Bit
16-Bit
100 kSPS
AD7940
AD7680
AD7683
AD7684
18-Bit
1
250 kSPS
AD7942 1
AD76851
AD76871
AD7694
AD76911
400 kSPS to 500 kSPS
AD79461
AD76861
AD76881
AD76931
AD76901
≥1000 kSPS
ADC Driver
AD79801
AD79831
ADA4941
ADA4841
AD79821
AD79841
ADA4941
ADA4841
Pin-for-pin compatible.
Rev. B
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AD7946
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Voltage Reference Input ............................................................ 14
Applications ....................................................................................... 1
Power Supply............................................................................... 15
Typical Application Circuit ............................................................. 1
Supplying the ADC from the Reference.................................. 15
General Description ......................................................................... 1
Single-Supply Application ......................................................... 15
Revision History ............................................................................... 2
Digital Interface .......................................................................... 16
Specifications..................................................................................... 3
CS MODE 3-Wire, No BUSY Indicator .................................. 17
Timing Specifications .................................................................. 5
CS Mode 3-Wire with BUSY Indicator ................................... 18
Absolute Maximum Ratings ............................................................ 6
CS Mode 4-Wire, No BUSY Indicator ..................................... 19
ESD Caution .................................................................................. 6
CS Mode 4-Wire with BUSY Indicator ................................... 20
Pin Configurations and Function Descriptions ........................... 7
Chain Mode, No BUSY Indicator ............................................ 21
Typical Performance Characteristics ............................................. 8
Chain Mode with BUSY Indicator ........................................... 22
Terminology .................................................................................... 11
Application Guidelines .................................................................. 23
Theory of Operation ...................................................................... 12
Layout .......................................................................................... 23
Circuit Information .................................................................... 12
Evaluating the Performance of the AD7946 .............................. 23
Converter Operation .................................................................. 12
Outline Dimensions ....................................................................... 24
Typical Connection Diagram.................................................... 13
Ordering Guide .......................................................................... 24
Analog Input ............................................................................... 13
Driver Amplifier Choice ............................................................ 14
REVISION HISTORY
7/14—Rev. A to Rev. B
Replaced QFN with LFCSP .......................................... Throughout
Changed Application Diagram Section to Typical Application
Circuit Section .................................................................................. 1
Changes to Product Title and Features Section ............................ 1
Added Note 1, General Description Section................................. 1
Added EPAD Notation to Figure 5 and Table 6............................ 7
Changes to Figure 25 ...................................................................... 13
Changes to Evaluating the Performance of the AD7946 Section ... 23
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
12/07—Rev. 0 to Rev. A
QFN Package Available ...................................................... Universal
Changes to Table 1.............................................................................1
Changes to Table 5.............................................................................6
Changes to Ordering Guide .......................................................... 24
7/05—Revision 0: Initial Version
Rev. B | Page 2 of 24
Data Sheet
AD7946
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, REF = VDD, TA = −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Absolute Input Voltage
Analog Input CMRR
Leakage Current at 25°C
Input Impedance
ACCURACY
No Missing Codes
Differential Linearity Error
Integral Linearity Error
Transition Noise
Gain Error 2, TMIN to TMAX
Gain Error Temperature Drift
Offset Error2, TMIN to TMAX
Offset Temperature Drift
Power Supply Sensitivity
THROUGHPUT
Conversion Rate
Transient Response
AC ACCURACY
Signal-to-Noise
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
Test Conditions/Comments
Min
14
IN+ − IN−
IN+
IN−
fIN = 200 kHz
Acquisition phase
0
−0.1
−0.1
Typ
Max
Unit
Bits
REF
VDD + 0.1
0.1
V
V
V
dB
nA
65
1
See the Analog Input section
14
−0.7
−1
REF = VDD = 5 V
VDD = 5 V ± 5%
±0.3
±0.4
0.33
±0.3
±1
±0.3
±1
±0.1
0
Intermodulation Distortion 4
84.5
84.5
±6
±6
500
400
Full-scale step
fIN = 20 kHz, REF = 5 V
fIN = 20 kHz, REF = 2.5 V
fIN = 20 kHz
fIN = 20 kHz
fIN = 20 kHz, REF = 5 V
fIN = 20 kHz, REF = 5 V, −60 dB input
+0.7
+1
85
84
−100
−100
85
25
100
Bits
LSB 1
LSB
LSB
LSB
ppm/°C
LSB
ppm/°C
LSB
kSPS
ns
dB 3
dB
dB
dB
dB
dB
dB
LSB means least significant bit. With the 5 V input range, one LSB is 305.2 µV.
See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference.
3
All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4
fIN1 = 21.4 kHz, fIN2 = 18.9 kHz, each tone at −7 dB below full scale.
1
2
Rev. B | Page 3 of 24
AD7946
Data Sheet
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, REF = VDD, TA = −40°C to +85°C, unless otherwise noted.
Table 3.
Parameter
REFERENCE
Voltage Range
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
IIH
DIGITAL OUTPUTS
Data Format
Pipeline Delay
VOL
VOH
POWER SUPPLIES
VDD
VIO
VIO Range
Standby Current 1, 2
Power Dissipation
TEMPERATURE RANGE 3
Specified Performance
1
2
3
Test Conditions/Comments
Min
Typ
0.5
Max
Unit
VDD + 0.3
500 kSPS, REF = 5 V
100
V
µA
VDD = 5 V
9
2.5
MHz
ns
−0.3
0.7 × VIO
−1
−1
Serial 14-bits straight binary
Conversion results available immediately
after completed conversion
0.4
VIO − 0.3
ISINK = +500 µA
ISOURCE = −500 µA
Specified performance
Specified performance
4.5
2.3
1.8
VDD and VIO = 5 V, 25°C
VDD = 5 V, 100 SPS throughput
VDD = 5 V, 100 kSPS throughput
VDD = 5 V, 500 kSPS throughput
TMIN to TMAX
0.3 × VIO
VIO + 0.3
+1
+1
1
3.3
3.3
−40
With all digital inputs forced to VIO or GND as required.
During acquisition phase.
Contact sales for extended the temperature range.
Rev. B | Page 4 of 24
5.5
VDD + 0.3
VDD + 0.3
50
V
V
µA
µA
V
V
3.8
19
V
V
V
nA
µW
mW
mW
+85
°C
Data Sheet
AD7946
TIMING SPECIFICATIONS
TA = −40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
See Figure 2 and Figure 3 for load conditions.
Table 4.
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 4.5 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
VIO Above 4.5 V
VIO Above 2.3 V
Rev. B | Page 5 of 24
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
Min
0.5
400
2
10
15
Typ
Max
1.6
17
18
19
20
7
7
5
Unit
µs
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
15
16
17
ns
ns
ns
ns
15
18
22
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
26
ns
ns
tEN
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
15
0
5
5
3
4
AD7946
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Analog Inputs
IN+ 1, IN−1
REF
Supply Voltages
VDD, VIO to GND
VDD to VIO
Digital Inputs to GND
Digital Outputs to GND
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
10-Lead MSOP
10-Lead LFCSP
θJC Thermal Impedance
10-Lead MSOP
10-Lead LFCSP
Lead Temperature
Vapor Phase (60 sec)
Infrared (15 sec)
GND − 0.3 V to VDD + 0.3 V or
±130 mA
GND − 0.3 V to VDD + 0.3 V
−0.3 V to +7 V
±7 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
ESD CAUTION
200°C/W
48.7°C/W
44°C/W
2.96°C/W
215°C
220°C
See the Analog Input section.
500µA
TO
SDO
IOL
1.4V
CL
50pF
500µA
04656-002
IOH
Figure 2. Load Circuit for Digital Interface Timing
70% OVDD
30% VIO
tDELAY
tDELAY
2V or OVDD – 0.5V1
0.8V or 0.5V2
2V or VIO – 0.5V1
0.8V or 0.5V2
NOTES
12V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
20.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
Figure 3. Voltage Levels for Timing
Rev. B | Page 6 of 24
04656-003
1
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
Data Sheet
AD7946
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
10 VIO
9
SDI
IN+ 3
TOP VIEW
(Not to Scale)
8
SCK
IN– 4
GND 5
7
SDO
6
CNV
REF 1
VDD 2
IN+ 3
04656-004
AD7946
IN– 4
GND 5
10 VIO
AD7946
TOP VIEW
(Not to Scale)
9
SDI
8
SCK
7
SDO
6
CNV
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST
BE CONNECTED TO GROUND. THIS
CONNECTION IS NOT REQUIRED TO MEET
ELECTRICAL PERFORMANCES.
Figure 4. 10-Lead MSOP Pin Configuration
04656-005
REF 1
VDD 2
Figure 5. 10-Lead LFCSP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
Mnemonic
REF
Type 1
AI
2
3
VDD
IN+
P
AI
4
5
6
IN−
GND
CNV
AI
P
DI
7
8
9
SDO
SCK
SDI
DO
DI
DI
10
VIO
P
EPAD
N/A
1
Description
Reference Input Voltage. The REF range is from 0.5 V to VDD, and is referred to the GND pin. This pin
should be decoupled closely to the pin with a 10 µF capacitor.
Power Supply.
Analog Input. It is referred to IN−. The voltage range, that is, the difference between IN+ and IN−,
is 0 V to REF.
Analog Input Ground Sense. Connect to the analog ground plane or to a remote sense ground.
Power Supply Ground.
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
selects the interface mode, chain, or CS. In CS mode, it enables the SDO pin when low. In chain mode,
the data should be read when CNV is high.
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
Serial Data Input. This input provides multiple features. It selects the interface mode of the
ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data
input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital
data level on SDI is output on SDO with a delay of 14 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can
enable the serial output signals when low, and if SDI or CNV is low when the conversion is complete,
the BUSY indicator feature is enabled.
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V,
3 V, or 5 V).
Exposed Pad. The exposed pad must be connected to ground. This connection is not required to meet
electrical performances.
AI = analog input, DI = digital input, DO = digital output, and P = power.
Rev. B | Page 7 of 24
AD7946
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
1.0
POSITIVE INL = +0.17LSB
NEGATIVE INL = –0.26LSB
0.6
0.4
0.4
0.2
0.2
DNL (LSB)
0.6
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–1.0
4096
8192
12288
04656-009
0
–0.2
0
POSITIVE DNL = +0.20LSB
NEGATIVE DNL = –0.13LSB
0.8
04656-006
–0.8
–1.0
16384
0
4096
8192
CODE
Figure 6. Integral Nonlinearity vs. Code
150000
261120
VDD = REF = 5V
125000
200000
100000
COUNTS
250000
150000
50000
50000
25000
0
0
200A
200B
200C
0
0
0
200D
200E
200F
CODE IN HEX
–100
–120
04656-008
–140
–180
0
20
40
60
80
205C
0
0
205D
205E
CODE IN HEX
SNR REFERENCE TO FULL SCALE (dB)
–80
–160
0
205A
90
8192 POINT FFT
VDD = REF = 5V
fS = 500kSPS
fIN = 20.14kHz
SNR = 85.3dB
THD = –105.2dB
SECOND HARMONIC = –106dB
THIRD HARMONIC = –110dB
–60
0
2059
Figure 10. Histogram of a DC Input at the Code Transition
0
–40
205B
VDD = REF = 5V
0
Figure 7. Histogram of a DC Input at the Code Center
–20
129528
88
86
84
82
80
–10
100 120 140 160 180 200 220 240
FREQUENCY (kHz)
04656-011
0
2009
04656-046
0
131592
75000
100000
AMPLITUDE (dB of Full Scale)
16384
Figure 9. Differential Nonlinearity vs. Code
300000
COUNTS
12288
CODE
04656-047
INL (LSB)
0.8
–8
–6
–4
INPUT LEVEL (dB)
Figure 8. FFT Plot
Figure 11. SNR vs. Input Level
Rev. B | Page 8 of 24
–2
Data Sheet
AD7946
90.0
15.0
87.5
14.5
–90
14.0
SINAD
THD, SFDR (dB)
85.0
ENOB (Bits)
SNR
–100
THD
–105
SFDR
–110
ENOB
82.5
13.5
2.7
3.1
3.5
3.9
4.3
4.7
5.1
13.0
5.5
–120
2.3
04656-015
80.0
2.3
04656-012
–115
2.7
3.1
REFERENCE VOLTAGE (V)
3.5
3.9
4.3
4.7
5.5
Figure 15. THD, SFDR vs. Reference Voltage
90.0
–90
REF = 5V
REF = 5V
87.5
–100
THD (dB)
85.0
82.5
–110
80.0
–55
04656-013
–120
–35
–15
5
25
45
65
85
105
–130
–55
125
04656-016
SNR (dB)
5.1
REFERENCE VOLTAGE (V)
Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage
–35
–15
TEMPERATURE (°C)
25
45
65
85
105
125
Figure 16. THD vs. Temperature
–60
95
–70
90
–80
THD (dB)
100
REF = 5V, –10dB
85
80
5
TEMPERATURE (°C)
Figure 13. SNR vs. Temperature
REF = 5V, –1dB
–90
REF = 5V, –1dB
–100
REF = 5V, –10dB
75
70
0
50
100
150
04656-017
–110
04656-014
SINAD (dB)
SNR, SINAD (dB)
–95
–120
200
0
FREQUENCY (kHz)
50
100
FREQUENCY (kHz)
Figure 14. SINAD vs. Frequency
Figure 17. THD vs. Frequency
Rev. B | Page 9 of 24
150
200
AD7946
Data Sheet
3
1000
VDD
500
250
VIO
0
4.50
4.75
5.00
5.25
2
1
OFFSET ERROR
0
–1
GAIN ERROR
–2
–3
–55
5.50
04656-021
OFFSET AND GAIN ERROR (LSB)
750
04656-048
OPERATING CURRENT (µA)
fS = 100kSPS
–35
–15
Figure 18. Operating Current vs. Supply
25
45
65
85
105
125
Figure 21. Offset and Gain Error vs. Temperature
1000
25
20
750
TDSDO DELAY (ns)
POWER-DOWN CURRENT (nA)
5
TEMPERATURE (°C)
SUPPLY (V)
500
15
VDD = 5V, 85°C
10
VDD = 5V, 25°C
250
0
–55
–35
–15
5
25
45
65
85
04656-050
VDD+VIO
105
Figure 19. Power-Down Current vs. Temperature
750
VDD = 5V
500
250
04656-049
OPERATING CURRENT (µA)
fS = 100kSPS
–35
–15
5
25
45
65
85
105
20
60
80
40
SDO CAPACITIVE LOAD (pF)
100
Figure 22. tDSDO Delay vs. Capacitance Load and Supply
1000
VIO
0
0
125
TEMPERATURE (°C)
0
–55
04656-022
5
125
TEMPERATURE (°C)
Figure 20. Operating Current vs. Temperature
Rev. B | Page 10 of 24
120
Data Sheet
AD7946
TERMINOLOGY
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (Figure 24).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Offset Error
The first transition should occur at a level ½ LSB above analog
ground (152.6 µV for the 0 V to 5 V range). The offset error is
the deviation of the actual transition from that point.
Gain Error
The last transition (from 111 … 10 to 111 … 11) should occur
for an analog voltage 1½ LSB below the nominal full scale
(4.999542 V for the 0 V to 5 V range). The gain error is the
deviation of the actual level of the last transition from the ideal
level after the offset has been adjusted out.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the following formula:
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in dB.
Aperture Delay
Aperture delay is the measurement of the acquisition performance and is the time between the rising edge of the CNV input
and when the input signal is held for a conversion.
Transient Response
Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied.
Rev. B | Page 11 of 24
AD7946
Data Sheet
THEORY OF OPERATION
IN+
SWITCHES CONTROL
MSB
8192C
4096C
LSB
4C
2C
C
SW+
C
BUSY
REF
COMP
GND
8192C
4096C
4C
2C
C
CONTROL
LOGIC
OUTPUT CODE
C
MSB
LSB
SW–
04656-023
CNV
IN–
Figure 23. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7946 is a fast, low power, single-supply, precise 14-bit
ADC using a successive approximation architecture.
The AD7946 can convert 500,000 samples per second (500 kSPS)
and powers down between conversions. When operating at
100 SPS, for example, it consumes 3.3 µW typically, ideal for
battery-powered applications.
The AD7946 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
in order to bring the comparator back into a balanced condition.
After completing this process, the part returns to the acquisition
phase, and the control logic generates the ADC output code and
a BUSY signal indicator.
Because the AD7946 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Transfer Functions
The ideal transfer characteristic for the AD7946 is shown in
Figure 24 and Table 7.
ADC CODE (Straight Binary)
The AD7946 is specified from 4.5 V to 5.5 V and can be
interfaced to any of the 1.8 V to 5 V digital logic family. It is
housed in a 10-lead MSOP or a tiny 10-lead LFCSP that
combines space savings and allows flexible configurations.
It is pin-for-pin compatible with the 16-bit ADC AD7686.
CONVERTER OPERATION
The AD7946 is a successive approximation ADC based on a
charge redistribution DAC. Figure 23 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 14 binary weighted capacitors, which are
connected to the two comparator inputs.
111...111
111...110
111...101
000...010
000...000
–FSR
–FSR + 1 LSB
+FSR – 1 LSB
+FSR – 1.5 LSB
–FSR + 0.5 LSB
During the acquisition phase, the terminals of the array that are
tied to the comparator’s input are connected to GND via SW+
and SW−. All independent switches are connected to the analog
inputs. Thus, the capacitor arrays are used as sampling capacitors
and acquire the analog signal on the IN+ and IN− inputs. When
the acquisition phase is complete and the CNV input goes high,
a conversion phase is initiated. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. Therefore, the differential voltage between the
inputs IN+ and IN− captured at the end of the acquisition phase
is applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and REF, the comparator input varies by
binary weighted voltage steps (REF/2, REF/4 … REF/16,384).
The control logic toggles these switches, starting with the MSB,
ANALOG INPUT
04656-024
000...001
Figure 24. ADC Ideal Transfer Function
Table 7. Output Codes and Ideal Input Voltages
Description
FSR − 1 LSB
Midscale + 1 LSB
Midscale
Midscale − 1 LSB
−FSR + 1 LSB
−FSR
1
2
Analog Input
REF = 5 V
4.999695 V
2.500305 V
2.5 V
2.499695 V
305.2 µV
0V
Digital Output Code Hexa
3FFF1
2001
2000
1FFF
0001
00002
This is also the code for an overranged analog input (VIN+ − VIN− above REF − VGND).
This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
Rev. B | Page 12 of 24
Data Sheet
AD7946
TYPICAL CONNECTION DIAGRAM
Figure 25 shows an example of the recommended connection diagram for the AD7946 when multiple supplies are available.
(NOTE 1)
V+
5V
REF
10µF
(NOTE 2)
100nF
1.8V TO VDD
V+
100nF
REF
33Ω
VDD
VIO
SDI
IN+
0V TO REF
(ADA4841
OR NOTE 3)
SCK
AD7946
2.7nF
V–
(NOTE 4)
IN–
3- OR 4-WIRE INTERFACE
(NOTE 5)
SDO
CNV
GND
04656-025
NOTES
1. SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
2. CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
3. SEE DRIVER AMPLIFIER CHOICE SECTION.
4. OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
5. SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE.
Figure 25. Typical Application Diagram with Multiple Supplies
ANALOG INPUT
70
Figure 26 shows an equivalent circuit of the input structure of
the AD7946.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs IN+ and IN−. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V because this causes these diodes to begin to forwardbias and start conducting current. These diodes can handle a
maximum forward-biased current of 130 mA. For instance,
these conditions could eventually occur when the input buffer’s
(U1) supplies are different from VDD. In such a case, an input
buffer with a short-circuit current limitation can be used to
protect the part.
CMRR (dB)
60
D1
40
1
10
100
1k
10k
FREQUENCY (kHz)
Figure 27. Analog Input CMRR vs. Frequency
RIN
CIN
D2
04656-026
CPIN
04656-027
50
VDD
IN+
OR IN–
VDD = 5V
GND
Figure 26. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the
differential signal between IN+ and IN−. By using this
differential input, small signals common to both inputs are
rejected, as shown in Figure 27, which represents the typical
CMRR over frequency. For instance, by using IN− to sense a
remote signal ground, ground potential differences between the
sensor and the local ADC ground are eliminated.
During the acquisition phase, the impedance of the analog
inputs (IN+ or IN−) can be modeled as a parallel combination
of capacitor, CPIN, and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is
typically 600 Ω and is a lumped component made up of some
serial resistors and the on resistance of the switches. CIN is
typically 30 pF and is mainly the ADC sampling capacitor.
During the conversion phase, when the switches are opened, the
input impedance is limited to CPIN. RIN and CIN make a 1-pole,
low-pass filter, which reduces undesirable aliasing effects and
limits the noise.
When the source impedance of the driving circuit is low, the
AD7946 can be driven directly. Large source impedances
significantly affect the ac performance, especially total
harmonic distortion (THD). The dc performances are less
sensitive to the input impedance. The maximum source
impedance depends on the amount of THD that can be
tolerated. The THD degrades as a function of the source
Rev. B | Page 13 of 24
AD7946
Data Sheet
impedance and the maximum input frequency, as shown in
Figure 28.
Table 8. Recommended Driver Amplifiers
Amplifier
ADA4841
AD8021
AD8655
AD8022
OP184
AD8605, AD8615
AD8519
AD8031
–80
–85
THD (dB)
–90
RS = 250Ω
–95
RS =100Ω
–100
RS = 50Ω
VOLTAGE REFERENCE INPUT
RS = 33Ω
–105
The AD7946 voltage reference input REF has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
04656-028
–110
0
25
50
75
100
FREQUENCY (kHz)
Figure 28. THD vs. Analog Input Frequency and Source Resistance
When REF is driven by a very low impedance source, for
example, a reference buffer using the AD8031 or the AD8603, a
10 µF (X5R, 0805 size) ceramic chip capacitor is appropriate for
optimum performance.
DRIVER AMPLIFIER CHOICE
Although the AD7946 is easy to drive, the driver amplifier
needs to meet the following requirements:
•
•
•
Typical Application
Very low noise, small and low power
Very low noise and high frequency
5 V single-supply, low noise, and low power
Low noise and high frequency
Low power, low noise, and low frequency
5 V single-supply, low power
Small, low power, and low frequency
High frequency and low power
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7946. Note that the AD7946
has a noise much lower than most of the other 14-bit
ADCs and, therefore, can be driven by a noisier amplifier
to meet a given system noise specification. The noise
coming from the amplifier is filtered by the AD7946 analog
input circuit 1-pole, low-pass filter made by RIN and CIN or
by the external filter, if one is used.
For ac applications, the driver should have a THD performance commensurate with the AD7946. Figure 17 shows the
THD vs. frequency that the driver should exceed.
For multichannel multiplexed applications, the driver
amplifier and the AD7946 analog input circuit must settle a
full-scale step onto the capacitor array at a 14-bit level
(0.006%). In the amplifier’s data sheet, settling at 0.1% to
0.01% is more commonly specified. This could differ
significantly from the settling time at a 14-bit level and
should be verified prior to driver selection.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 µF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
If desired, smaller reference decoupling capacitor values down
to 2.2 µF can be used with a minimal impact on performance,
especially DNL.
Regardless, there is no need for an additional lower value ceramic
decoupling capacitor (for example, 100 nF) between the REF
and GND pins.
Rev. B | Page 14 of 24
Data Sheet
AD7946
POWER SUPPLY
SUPPLYING THE ADC FROM THE REFERENCE
The AD7946 is specified at 4.5 V to 5.5 V. It uses two power
supply pins: a core supply VDD and a digital input/output
interface supply VIO. VIO allows direct interface with any
logic between 1.8 V and VDD. To reduce the supplies needed,
the VIO and VDD can be tied together. The AD7946 is
independent of power supply sequencing between VIO and
VDD. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in Figure 29,
which represents PSRR over frequency.
For simplified applications, the AD7946, with its low operating
current, can be supplied directly using the reference circuit
shown in Figure 31. The reference line can be driven by one of
the following:
•
•
The system power supply directly.
A reference voltage with enough current output capability,
such as the ADR43x.
A reference buffer, such as the AD8031 or AD8603,
which can also filter the system power supply, as shown
in Figure 31.
•
90
80
5V
PSRR (dB)
10kΩ
VDD = 5V
70
5V
1kΩ
1µ F
60
47kΩ
1µ F
AD8603 10µF
(NOTE 1)
REF
50
VDD
VIO
AD7946
30
1
10
100
1k
NOTES
1. OPTIONAL REFERENCE BUFFER AND FILTER
Figure 31. Example of Application Circuit
10k
FREQUENCY (kHz)
SINGLE-SUPPLY APPLICATION
Figure 29. PSRR vs. Frequency
The AD7946 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, as shown in Figure 30. This makes the part
ideal for low sampling rate (even a few Hz) and low batterypowered applications.
1000
VIO
1
0.1
0.01
0.001
10
04656-051
OPERATING CURRENT (µA)
VDD = 5V
100
10
100
1k
10k
04656-031
04656-029
40
100k
SAMPLING RATE (SPS)
Figure 30. Operating Currents vs. Sampling Rate
1M
Figure 32 shows a typical 14-bit single-supply application. There
are different challenges to doing a single-supply, high resolution
design, and the ADA4841 addresses these nicely. The combination of low noise, low power, wide input range, rail-to-rail output,
and high speed make the ADA4841 a perfect driver solution for
low power, single-supply 14-bit ADCs, such as the AD7946. In a
single-supply system, one of the main challenges is to use the
amplifier in buffer mode to have the lowest output noise and
still preserve linearity compatible with the ADC. Rail-to-rail
input amplifiers usually have higher noise than the ADA4841
and cannot be used on their entire input range in buffer mode
because of the nonlinear region around the crossover point of
their input stage. The ADA4841, which has no crossover region
but has a wide linear input range from ground to 1 V below
positive rail, solves this issue, as shown in Figure 32, where it
can accept the 0 V to 4.096 V input range with a supply as low
as 5.2 V. This supply allows using a small, low dropout, low
temperature drift ADR364 reference voltage. Note that, like any
rail-to-rail output amplifier at the low end of its output range
close to ground, the ADA4841 can exhibit some nonlinearity on
a small region of approximately 25 mV from ground. The
ADA4841 drives a 1-pole, low-pass filter. This filter limits the
already very low noise contribution from the amplifier to the
AD7946.
Rev. B | Page 15 of 24
AD7946
Data Sheet
independent of the readback timing (SDI). This is useful in low
jitter sampling or simultaneous sampling applications.
>5.2V
100nF
ADR364
100nF
ADA4841
The AD7946, when in chain mode, provides a daisy chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
10µF
100nF
0V TO 4.096V
33Ω
REF
VDD
IN+
VIO
SDI
AD7946
2.7nF
SCK
SDO
IN–
CNV
04656-052
GND
Figure 32. Example of a Single-Supply Application Circuit
DIGITAL INTERFACE
Although the AD7946 has a reduced number of pins, it offers
flexibility in its serial interface modes.
The AD7946, when in CS mode, is compatible with SPI, QSPI™,
digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x or
ADSP-219x. This interface can use either 3-wire or 4-wire. A
3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections useful, for instance, in isolated
applications. A 4-wire interface using the SDI, CNV, SCK, and
SDO signals allows CNV, which initiates the conversions, to be
The operating mode depends on the SDI level when the CNV
rising edge occurs. CS mode is selected if SDI is high, and chain
mode is selected if SDI is low. The SDI hold time is such that
when SDI and CNV are connected, the chain mode is always
selected.
In either mode, the AD7946 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be
used as a BUSY signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a BUSY indicator,
the user must time out the maximum conversion time prior to
readback.
BUSY indicator feature is enabled
•
•
Rev. B | Page 16 of 24
In CS mode, if CNV or SDI is low when the ADC
conversion ends (see Figure 36 and Figure 40).
In chain mode, if SCK is high during the CNV rising edge
(see Figure 44).
Data Sheet
AD7946
CS MODE 3-WIRE, NO BUSY INDICATOR
are then clocked by subsequent SCK falling edges. The data is
valid on both SCK edges. Although the rising edge can be used
to capture the data, a digital host using the SCK falling edge
allows a faster reading rate, provided it has an acceptable hold
time. After the 14th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
This mode is usually used when a single AD7946 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 33 and the corresponding timing is given in
Figure 34.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues to
completion irrespective of the state of CNV. For instance, it
could be useful to bring CNV low to select other SPI devices,
such as analog multiplexers, but CNV must be returned high
before the minimum conversion time and held high until the
maximum conversion time to avoid the generation of the BUSY
signal indicator. When the conversion is complete, the AD7946
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
CONVERT
DIGITAL HOST
CNV
VIO
SDI
AD7946
DATA IN
SDO
04656-032
SCK
CLK
Figure 33. CS Mode 3-Wire, No BUSY Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
1
2
3
12
tHSDO
14
tSCKH
tDSDO
tEN
SDO
13
D13
D12
D11
tDIS
D1
D0
Figure 34. CS Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High)
Rev. B | Page 17 of 24
04656-033
SCK
AD7946
Data Sheet
CS MODE 3-WIRE WITH BUSY INDICATOR
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the optional
15th SCK falling edge, or when CNV goes high, whichever is
earlier, SDO returns to high impedance.
This mode is usually used when a single AD7946 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 35, and the
corresponding timing is given in Figure 36.
If multiple AD7946s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV could be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time and
held low until the maximum conversion time to guarantee the
generation of the BUSY signal indicator. When the conversion
is complete, SDO goes from high impedance to low. With a
pull-up on the SDO line, this transition can be used as an
interrupt signal to initiate the data reading controlled by the
digital host. The AD7946 then enters the acquisition phase and
powers down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
CONVERT
VIO
CNV
VIO
DIGITAL HOST
47kΩ
AD7946
DATA IN
SDO
SCK
IRQ
04656-034
SDI
CLK
Figure 35. CS Mode 3-Wire with BUSY Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
1
2
3
13
14
15
tSCKH
tHSDO
tDSDO
SDO
tDIS
D13
D12
D1
D0
Figure 36. CS Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High)
Rev. B | Page 18 of 24
04656-035
SCK
Data Sheet
AD7946
CS MODE 4-WIRE, NO BUSY INDICATOR
time and held high until the maximum conversion time to
avoid the generation of the BUSY signal indicator. When the
conversion is complete, the AD7946 enters the acquisition
phase and powers down. Each ADC result can be read by
bringing its SDI input low, which consequently outputs the MSB
onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the 14th SCK
falling edge, or when SDI goes high, whichever is earlier, SDO
returns to high impedance and another AD7946 can be read.
This mode is usually used when multiple AD7946s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7946s is shown in
Figure 37, and the corresponding timing is given in Figure 38.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
CS2
CS1
CONVERT
CNV
AD7946
SDO
SDI
AD7946
SCK
SDO
SCK
04656-036
SDI
DIGITAL HOST
CNV
DATA IN
CLK
Figure 37. CS Mode 4-Wire, No BUSY Indicator Connection Diagram
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSSDICNV
SDI(CS1)
tHSDICNV
SDI(CS2)
tSCK
tSCKL
SCK
1
2
12
3
tHSDO
14
15
16
26
27
28
tDSDO
tEN
D13
D12
D11
tDIS
D1
D0
D13
D12
D1
D0
04656-037
SDO
13
tSCKH
Figure 38. CS Mode 4-Wire, No BUSY Indicator Serial Interface Timing
Rev. B | Page 19 of 24
AD7946
Data Sheet
CS MODE 4-WIRE WITH BUSY INDICATOR
low. With a pull-up on the SDO line, this transition can be used
as an interrupt signal to initiate the data readback controlled by
the digital host. The AD7946 then enters the acquisition phase
and powers down. The data bits are then clocked out, MSB first,
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the optional
15th SCK falling edge or SDI going high, whichever is earlier, the
SDO returns to high impedance.
This mode is usually used when a single AD7946 is connected
to an SPI-compatible digital host, which has an interrupt input,
and it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 39, and the
corresponding timing is given in Figure 40.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the BUSY signal indicator. When
the conversion is complete, SDO goes from high impedance to
CS1
CONVERT
VIO
DIGITAL HOST
CNV
47kΩ
AD7946
DATA IN
SDO
SCK
IRQ
04656-038
SDI
CLK
Figure 39. CS Mode 4-Wire with BUSY Indicator Connection Diagram
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSSDICNV
SDI
tSCK
tHSDICNV
tSCKL
1
2
3
tHSDO
13
14
15
tSCKH
tDIS
tDSDO
tEN
SDO
D13
D12
D1
Figure 40. CS Mode 4-Wire with BUSY Indicator Serial Interface Timing
Rev. B | Page 20 of 24
D0
04656-039
SCK
Data Sheet
AD7946
CHAIN MODE, NO BUSY INDICATOR
onto SDO, and the AD7946 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are then clocked by subsequent SCK falling edges.
For each ADC, SDI feeds the input of the internal shift register
and is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 14 × N clocks are required to
readback the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and consequently more AD7946s in the chain, provided the
digital host has an acceptable hold time. The maximum conversion rate may be reduced due to the total readback time. For
instance, with a 3 ns digital host setup time and 3 V interface,
up to four AD7946s running at a conversion rate of 360 kSPS
can be daisy-chained on a 3-wire port.
This mode can be used to daisy-chain multiple AD7946s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7946s is shown in
Figure 41, and the corresponding timing is given in Figure 42.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the BUSY indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
CONVERT
SDI
CNV
AD7946
SDO
DIGITAL HOST
AD7946
SDI
A
B
SCK
SCK
SDO
DATA IN
04656-040
CNV
CLK
Figure 41. Chain Mode, No BUSY Indicator Connection Diagram
SDIA = 0
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
tSSCKCNV
SCK
1
2
3
12
13
tSSDISCK
tHSCKCNV
14
15
16
DA13
DA12
26
27
28
DA 1
DA0
tSCKH
SDOA = SDIB
DA13
DA12
DA11
DA 1
DA 0
DB13
DB12
DB11
DB1
DB0
tHSDO
tDSDO
SDOB
Figure 42. Chain Mode, No BUSY Indicator Serial Interface Timing
Rev. B | Page 21 of 24
04656-041
tHSDISCK
tEN
AD7946
Data Sheet
CHAIN MODE WITH BUSY INDICATOR
Figure 43) SDO is driven high. This transition on SDO can
be used as a BUSY indicator to trigger the data readback
controlled by the digital host. The AD7946 then enters the
acquisition phase and powers down. The data bits stored in
the internal shift register are then clocked out, MSB first, by
subsequent SCK falling edges. For each ADC, SDI feeds the
input of the internal shift register and is clocked by the SCK
falling edge. Each ADC in the chain outputs its data MSB first,
and 14 × N + 1 clocks are required to readback the N ADCs.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and consequently more AD7946s in the chain, provided the
digital host has an acceptable hold time. For instance, with a
3 ns digital host setup time and 3 V interface, up to four AD7946s
running at a conversion rate of 360 kSPS can be daisy-chained
to a single 3-wire port.
This mode can be used to daisy-chain multiple AD7946s on a
3-wire serial interface while providing a BUSY indicator. This
feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications or
for systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register.
A connection diagram example using three AD7946s is shown
in Figure 43, and the corresponding timing is given in Figure 44.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the BUSY indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the near-end ADC (ADC C in
CONVERT
SDI
AD7946
CNV
SDO
SDI
AD7946
DIGITAL HOST
CNV
SDO
SDI
AD7946
A
B
C
SCK
SCK
SCK
DATA IN
SDO
IRQ
04656-042
CNV
CLK
Figure 43. Chain Mode with BUSY Indicator Connection Diagram
tCYC
ACQUISITION
tCONV
tACQ
ACQUISITION
CONVERSION
tSSCKCNV
SCK
tSCKH
1
2
tSSDISCK
tHSCKCNV
tEN
SDOA = SDIB
3
4
tSCK
13
14
15
16
17
27
28
29
30
31
tSCKL
tHSDISCK
tDSDOSDI
DA13 DA12 DA11
DA1
DA0
DB13 DB12 DB11
DB 1
DB0 DA13 DA12
DA 1
DA0
43
DC13 DC12 DC11
DC 1
DC0 DB13 DB12
DB 1
DB0 DA13 DA12
tDSDOSDI
tDSDOSDI
SDOC
42
tDSDOSDI
tHSDO
tDSDO
SDOB = SDIC
41
tDSDOSDI
Figure 44. Chain Mode with BUSY Indicator Serial Interface Timing
Rev. B | Page 22 of 24
DA 1
DA 0
04656-043
CNV = SDIA
Data Sheet
AD7946
APPLICATION GUIDELINES
LAYOUT
The printed circuit board that houses the AD7946 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7946, with all its analog signals on the left side and all its
digital signals on the right side, eases this task.
At least one ground plane should be used. It could be common
or split between the digital and analog sections. In the latter
case, the planes should be joined underneath the AD7946s.
04656-044
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7946 is used as a shield. Fast switching signals, such as CNV
or clocks, should never run near analog signal paths. Crossover
of digital and analog signals should be avoided.
Figure 45. Example of Layout of the AD7946 (Top Layer)
The AD7946 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and connecting it with wide, low impedance
traces.
Finally, the power supplies VDD and VIO of the AD7946
should be decoupled with ceramic capacitors (typically 100 nF)
placed close to the AD7946 and connected using short and wide
traces to provide low impedance paths and reduce the effect of
glitches on the power supply lines.
04656-045
An example of layout following these rules is shown in
Figure 45 and Figure 46.
EVALUATING THE PERFORMANCE OF THE AD7946
Other recommended layouts for the AD7946 are outlined in the
documentation of the EVAL-AD7946SDZ evaluation board.
The evaluation board package includes a fully assembled and
tested evaluation board, documentation, and software for
controlling the board from a PC via the EVAL-SDP-CB1Z.
Rev. B | Page 23 of 24
Figure 46. Example of Layout of the AD7946 (Bottom Layer)
AD7946
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00
2.90
6
10
3.10
3.00
2.90
1
5.15
4.90
4.65
5
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.15
0.05
0.33
0.17
SEATING
PLANE
0.80
0.60
0.40
8°
0°
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 47.10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
2.48
2.38
2.23
3.10
3.00 SQ
2.90
0.50 BSC
10
6
PIN 1 INDEX
AREA
1.74
1.64
1.49
EXPOSED
PAD
0.50
0.40
0.30
1
5
BOTTOM VIEW
0.80
0.75
0.70
SEATING
PLANE
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.30
0.25
0.20
0.20 MIN
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
02-05-2013-C
TOP VIEW
0.20 REF
Figure 48. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2, 3
AD7946BRMZ
AD7946BRMZRL7
AD7946BCPZRL7
AD7946BCPZRL
EVAL-AD7946SDZ
EVAL-SDP-CB1Z
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
10-Lead MSOP
10-Lead MSOP
10-Lead LFCSP_WD
10-Lead LFCSP_WD
Evaluation Board
Controller Board
Package Option
RM-10
RM-10
CP-10-9
CP-10-9
Ordering Quantity
Tube, 50
Reel, 1,000
Reel, 1,000
Reel, 5,000
Branding
C4X
C4X
C4X
C4X
Z = RoHS Compliant Part.
The EVAL-AD7946SDZ can be used as a standalone evaluation board or in conjunction with the EVAL-SDP-CB1Z for evaluation and/or demonstration purposes.
3
The EVAL-SDP-CB1Z allows a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the SDZ designator.
1
2
©2005–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04656-0-7/14(B)
Rev. B | Page 24 of 24
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