AD7949_09

14-Bit, 8-Channel, 250 kSPS PulSAR ADC AD7949 FEATURES 14-bit resolution with no missing codes 8-channel multiplexer with choice of inputs Unipolar single-ended Differential (GND sense) Pseudobipolar Throughput: 250 kSPS INL/DNL: ±0.5/±0.25 LSB typical SINAD: 85 dB @ 20 kHz THD: −100 dB @ 20 kHz Analog input range: 0 V to VREF with VREF up to VDD Multiple reference types Internal selectable 2.5 V or 4.096 V External buffered (up to 4.096 V) External (up to VDD) Internal temperature sensor (TEMP) Channel sequencer, selectable 1-pole filter, busy indicator No pipeline delay, SAR architecture Single-supply 2.3 V to 5.5 V operation with 1.8 V to 5.5 V logic interface Serial interface compatible with SPI, MICROWIRE, QSPI, and DSP Power dissipation 2.9 mW @ 2.5 V/200 kSPS 10.8 mW @ 5 V/250 kSPS Standby current: 50 nA 20-lead 4 mm × 4 mm LFCSP package FUNCTIONAL BLOCK DIAGRAM 0.5V TO VDD – 0.5V 0.1µF REFIN 0.5V TO VDD 10µF REF 2.3V TO 5.5V VDD 1.8V VIO TO VDD BAND GAP REF TEMP SENSOR IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 COM AD7949 CNV MUX 14-BIT SAR ADC ONE-POLE LPF SEQUENCER 07351-001 SPI SERIAL INTERFACE SCK SDO DIN GND Figure 1. Table 1. Multichannel 14-/16-Bit PulSAR® ADCs Type 14-Bit 16-Bit 16-Bit Channels 8 4 8 250 kSPS AD7949 AD7682 AD7689 500 kSPS ADC Driver ADA4841-x ADA4841-x ADA4841-x AD7699 GENERAL DESCRIPTION The AD7949 is an 8-channel, 14-bit, charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC) that operates from a single power supply, VDD. The AD7949 contains all components for use in a multichannel, low power data acquisition system, including a true 14-bit SAR ADC with no missing codes; an 8-channel, low crosstalk multiplexer that is useful for configuring the inputs as singleended (with or without ground sense), differential, or bipolar; an internal low drift reference (selectable 2.5 V or 4.096 V) and buffer; a temperature sensor; a selectable one-pole filter; and a sequencer that is useful when channels are continuously scanned in order. The AD7949 uses a simple SPI interface for writing to the configuration register and receiving conversion results. The SPI interface uses a separate supply, VIO, which is set to the host logic level. Power dissipation scales with throughput. The AD7949 is housed in a tiny 20-lead LFCSP with operation specified from −40°C to +85°C. APPLICATIONS Multichannel system monitoring Battery-powered equipment Medical instruments: ECG/EKG Mobile communications: GPS Power line monitoring Data acquisition Seismic data acquisition systems Instrumentation Process control Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008–2009 Analog Devices, Inc. All rights reserved. AD7949 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  Functional Block Diagram .............................................................. 1  General Description ......................................................................... 1  Revision History ............................................................................... 2  Specifications..................................................................................... 3  Timing Specifications .................................................................. 5  Absolute Maximum Ratings............................................................ 7  ESD Caution .................................................................................. 7  Pin Configuration and Function Descriptions ............................. 8  Typical Performance Characteristics ............................................. 9  Terminology .................................................................................... 12  Theory of Operation ...................................................................... 13  Overview...................................................................................... 13  Converter Operation .................................................................. 13  Transfer Functions...................................................................... 14  Typical Connection Diagrams .................................................. 15  Analog Inputs .............................................................................. 16  Driver Amplifier Choice ............................................................ 18  Voltage Reference Output/Input .............................................. 18  Power Supply............................................................................... 20  Supplying the ADC from the Reference.................................. 20  Digital Interface .............................................................................. 21  Reading/Writing During Conversion, Fast Hosts.................. 21  Reading/Writing After Conversion, Any Speed Hosts.......... 21  Reading/Writing Spanning Conversion, Any Speed Host .... 21  Configuration Register, CFG .................................................... 21  General Timing Without a Busy Indicator ............................. 23  General Timing with a Busy Indicator .................................... 24  Channel Sequencer .................................................................... 25  Read/Write Spanning Conversion Without a Busy Indicator ....................................................................................................... 26  Read/Write Spanning Conversion with a Busy Indicator ..... 27  Application Hints ........................................................................... 28  Layout .......................................................................................... 28  Evaluating AD7949 Performance............................................. 28  Outline Dimensions ....................................................................... 29  Ordering Guide .......................................................................... 29  REVISION HISTORY 5/09—Rev. A to Rev. B Changes to Features Section, Applications Section, and Figure 1 .............................................................................................. 1 Changes to Specifications Section .................................................. 3 Changes to Timing Specifications Section .................................... 5 Changes to Table 5 ............................................................................ 7 Changes to Figure 4 and Table 6 ..................................................... 8 Changes to Figure 20 ...................................................................... 11 Changes to Converter Operation Section ................................... 13 Changes to Table 7 .......................................................................... 14 Changes to Figure 25 and Figure 26 ............................................. 15 Changes to Bipolar Single Supply Section, Input Structure Section, and Selectable Low-Pass Filter Section ......................... 16 Changes to Input Configurations Section, Sequencer Section, and Source Resistance Section ...................................................... 17 Changes to Internal Reference/Temperature Sensor Section ... 18 Added Figure 30; Renumbered Sequentially .............................. 18 Changes to External Reference and Internal Buffer Section, External Reference Section, and Reference Decoupling Section .............................................................................................. 19 Added Figure 31 and Figure 32..................................................... 19 Changes to Power Supply Section ................................................ 20 Changed Reading/Writing During Conversion, Fast Hosts Section to Reading/Writing After Conversion, Any Speed Hosts ............................................................................. 21 Changes to Configuration Register, CFG Section and Table 9 .............................................................................................. 22 Added General Timing Without a Busy Indicator Section and Figure 36 .......................................................................................... 23 Added General Timing with a Busy Indicator Section and Figure 37 .......................................................................................... 24 Added Channel Sequencer Section, Examples Section, and Figure 38 .......................................................................................... 25 Changes to Read/Write Spanning Conversion Without a Busy Indicator Section and Figure 40 ................................................... 26 Changes to Read/Write Spanning Conversion with a Busy Indicator Section and Figure 42 ................................................... 27 Changes to Evaluating AD7949 Performance Section .............. 28 Added Exposed Pad Notation to Outline Dimensions ............. 29 Changes to Ordering Guide .......................................................... 29 5/08—Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 26 5/08—Revision 0: Initial Version Rev. B | Page 2 of 32 AD7949 SPECIFICATIONS VDD = 2.3 V to 5.5 V, VIO = 1.8 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Conditions/Comments Min 14 0 −VREF/2 −0.1 −0.1 VREF/2 − 0.1 Typ Max Unit Bits V V Analog Input CMRR Leakage Current at 25°C Input Impedance1 THROUGHPUT Conversion Rate Full Bandwidth2 ¼ Bandwidth2 Transient Response ACCURACY No Missing Codes Integral Linearity Error Differential Linearity Error Transition Noise Gain Error4 Gain Error Match Gain Error Temperature Drift Offset Error4 Offset Error Match Offset Error Temperature Drift Power Supply Sensitivity AC ACCURACY5 Dynamic Range Signal-to-Noise Unipolar mode Bipolar mode Positive input, unipolar and bipolar modes Negative or COM input, unipolar mode Negative or COM input, bipolar mode fIN = 250 kHz Acquisition phase VREF/2 68 1 +VREF +VREF/2 VREF + 0.1 +0.1 VREF/2 + 0.1 dB nA VDD = 4.5 V to 5.5 V VDD = 2.3 V to 4.5 V VDD = 4.5 V to 5.5 V VDD = 2.3 V to 4.5 V Full-scale step, full bandwidth Full-scale step, ¼ bandwidth 0 0 0 0 250 200 62.5 50 1.8 14.5 kSPS kSPS kSPS kSPS μs μs Bits LSB3 LSB LSB LSB LSB ppm/°C LSB LSB ppm/°C LSB dB6 dB dB dB dB dB dB dB dB dB dB MHz MHz ns 14 −1 −1 REF = VDD = 5 V −5 −1 −1 VDD = 5 V  5% ±0.5 ±0.25 0.1 ±0.5 ±0.2 ±1 ±0.5 ±0.2 ±1 ±0.2 85.6 85.5 85 84 85 33.5 85 84 −100 108 −125 1.7 0.425 2.5 +1 +1 +5 +1 +1 SINAD Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Crosstalk SAMPLING DYNAMICS −3 dB Input Bandwidth Aperture Delay fIN = 20 kHz, VREF = 5 V fIN = 20 kHz, VREF = 4.096 V internal REF fIN = 20 kHz, VREF = 2.5 V internal REF fIN = 20 kHz, VREF = 5 V fIN = 20 kHz, VREF = 5 V, −60 dB input fIN = 20 kHz, VREF = 4.096 V internal REF fIN = 20 kHz, VREF = 2.5 V internal REF fIN = 20 kHz fIN = 20 kHz fIN = 100 kHz on adjacent channel(s) Full bandwidth ¼ bandwidth VDD = 5 V 84.5 84 Rev. B | Page 3 of 32 AD7949 Parameter INTERNAL REFERENCE REF Output Voltage REFIN Output Voltage7 REF Output Current Temperature Drift Line Regulation Long-Term Drift Turn-On Settling Time EXTERNAL REFERENCE Voltage Range Current Drain TEMPERATURE SENSOR Output Voltage8 Temperature Sensitivity DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format9 Pipeline Delay10 VOL VOH POWER SUPPLIES VDD VIO Standby Current11, 12 Power Dissipation Conditions/Comments 2.5 V, @ 25°C 4.096 V, @ 25°C 2.5 V, @ 25°C 4.096 V, @ 25°C Min 2.490 4.086 Typ 2.500 4.096 1.2 2.3 ±300 ±10 ±15 50 5 Max 2.510 4.106 Unit V V V V μA ppm/°C ppm/V ppm ms V V μA mV mV/°C VDD = 5 V ± 5% 1000 hours CREF = 10 μF REF input REFIN input (buffered) 250 kSPS, REF = 5 V @ 25°C 0.5 0.5 VDD + 0.3 VDD − 0.5 50 283 1 −0.3 0.7 × VIO −1 −1 +0.3 × VIO VIO + 0.3 +1 +1 V V μA μA ISINK = +500 μA ISOURCE = −500 μA Specified performance Specified performance Operating range VDD and VIO = 5 V, @ 25°C VDD = 2.5 V, 100 SPS throughput VDD = 2.5 V, 100 kSPS throughput VDD = 2.5 V, 200 kSPS throughput VDD = 5 V, 250 kSPS throughput VDD = 5 V, 250 kSPS throughput with internal reference 0.4 VIO − 0.3 2.3 2.3 1.8 50 1.5 1.45 2.9 10.8 13.5 50 5.5 VDD + 0.3 VDD + 0.3 V V V V V nA μW mW mW mW mW nJ 2.0 4.0 12.5 15.5 Energy per Conversion TEMPERATURE RANGE13 Specified Performance 1 2 3 TMIN to TMAX −40 +85 °C See the Analog Inputs section. The bandwidth is set in the configuration register. LSB means least significant bit. With the 5 V input range, one LSB = 305 μV. 4 See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference. 5 With VDD = 5 V, unless otherwise noted. 6 All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 7 This is the output from the internal band gap. 8 The output voltage is internal and present on a dedicated multiplexer input. 9 Unipolar mode: serial 14-bit straight binary. Bipolar mode: serial 14-bit twos complement. 10 Conversion results available immediately after completed conversion. 11 With all digital inputs forced to VIO or GND as required. 12 During acquisition phase. 13 Contact an Analog Devices, Inc., sales representative for the extended temperature range. Rev. B | Page 4 of 32 AD7949 TIMING SPECIFICATIONS VDD = 4.5 V to 5.5 V, VIO = 1.8 V to VDD, all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter1 Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions Data Write/Read During Conversion CNV Pulse Width SCK Period SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO Above 2.7 V VIO Above 2.3 V VIO Above 1.8 V CNV Low to SDO D15 MSB Valid VIO Above 2.7 V VIO Above 2.3 V VIO Above 1.8 V CNV High or Last SCK Falling Edge to SDO High Impedance CNV Low to SCK Rising Edge DIN Valid Setup Time from SCK Rising Edge DIN Valid Hold Time from SCK Rising Edge 1 Symbol tCONV tACQ tCYC tDATA tCNVH tSCK tSCKL tSCKH tHSDO tDSDO Min 1.8 4.0 Typ Max 2.2 1.0 10 tDSDO + 2 11 11 4 18 23 28 Unit μs μs μs μs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tEN 18 22 25 32 10 5 5 tDIS tCLSCK tSDIN tHDIN See Figure 2 and Figure 3 for load conditions. Rev. B | Page 5 of 32 AD7949 VDD = 2.3 V to 4.5 V, VIO = 1.8 V to VDD, all specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter1 Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions Data Write/Read During Conversion CNV Pulse Width SCK Period SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V VIO Above 1.8 V CNV Low to SDO D15 MSB Valid VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V VIO Above 1.8 V CNV High or Last SCK Falling Edge to SDO High Impedance CNV Low to SCK Rising Edge DIN Valid Setup Time from SCK Rising Edge DIN Valid Hold Time from SCK Rising Edge 1 Symbol tCONV tACQ tCYC tDATA tCNVH tSCK tSCKL tSCKH tHSDO tDSDO Min 1.8 5 Typ Max 3.2 1.2 10 tDSDO + 2 12 12 5 24 30 38 48 Unit μs μs μs μs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tEN 21 27 35 45 50 10 5 5 tDIS tCLSCK tSDIN tHDIN See Figure 2 and Figure 3 for load conditions. 500µA IOL TO SDO CL 50pF 500µA IOH 1.4V Figure 2. Load Circuit for Digital Interface Timing 70% VIO 30% VIO tDELAY 2V OR VIO – 0.5V1 0.8V OR 0.5V2 1 2 tDELAY 2V OR VIO – 0.5V1 0.8V OR 0.5V2 07351-003 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V. Figure 3. Voltage Levels for Timing Rev. B | Page 6 of 32 07351-002 AD7949 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs INx,1 COM1 REF, REFIN Supply Voltages VDD, VIO to GND VIO to VDD DIN, CNV, SCK to GND SDO to GND Storage Temperature Range Junction Temperature θJA Thermal Impedance (LFCSP) θJC Thermal Impedance (LFCSP) 1 Rating GND − 0.3 V to VDD + 0.3 V or VDD ± 130 mA GND − 0.3 V to VDD + 0.3 V −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −65°C to +150°C 150°C 47.6°C/W 4.4°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION See the Analog Inputs section. Rev. B | Page 7 of 32 AD7949 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 20 19 18 17 16 VDD IN3 IN2 IN1 IN0 PIN 1 INDICATOR VDD REF REFIN GND GND 1 2 3 4 5 AD7949 TOP VIEW (Not to Scale) IN4 6 IN5 7 IN6 8 IN7 9 COM 10 15 14 13 12 11 VIO SDO SCK DIN CNV Figure 4. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1, 20 Mnemonic VDD Type1 P Description Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled with 10 μF and 100 nF capacitors. When using the internal reference for 2.5 V output, the minimum should be 3.0 V. When using the internal reference for 4.096 V output, the minimum should be 4.5 V. Reference Input/Output. See the Voltage Reference Output/Input section. When the internal reference is enabled, this pin produces a selectable system reference = 2.5 V or 4.096 V. When the internal reference is disabled and the buffer is enabled, REF produces a buffered version of the voltage present on the REFIN pin (4.096 V maximum), useful when using low cost, low power references. For improved drift performance, connect a precision reference to REF (0.5 V to VDD). For any reference method, this pin needs decoupling with an external 10 μF capacitor connected as close to REF as possible. See the Reference Decoupling section. Internal Reference Output/Reference Buffer Input. See the Voltage Reference Output/Input section. When using the internal reference, the internal unbuffered reference voltage is present and needs decoupling with a 0.1 μF capacitor. When using the internal reference buffer, apply a source between 0.5 V and 4.096 V that is buffered to the REF pin as described above. Power Supply Ground. Channel 4 through Channel 7 Analog Inputs. Common Channel Input. All input channels, IN[7:0], can be referenced to a common-mode point of 0 V or VREF/2 V. Convert Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is held high, the busy indictor is enabled. Data Input. This input is used for writing to the 14-bit configuration register. The configuration register can be written to during and after conversion. Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN in an MSB first fashion. Serial Data Output. The conversion result is output on this pin, synchronized to SCK. In unipolar modes, conversion results are straight binary; in bipolar modes, conversion results are twos complement. Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). Channel 0 through Channel 3 Analog Inputs. The exposed pad is not connected internally. For increased reliability of the solder joints, it is recommended that the pad be soldered to the system ground plane. 2 REF AI/O 3 REFIN AI/O 4, 5 6 to 9 10 11 12 13 14 GND IN4 to IN7 COM CNV DIN SCK SDO P AI AI DI DI DI DO 15 16 to 19 21 (EPAD) 1 VIO IN0 to IN3 Exposed Pad (EPAD) P AI NC AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power. Rev. B | Page 8 of 32 07351-004 NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SYSTEM GROUND PLANE. AD7949 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 2.5 V to 5.5 V, VREF = 2.5 V to 5 V, VIO = 2.3 V to VDD, unless otherwise noted.. 1.0 1.0 0.5 0.5 DNL (LSB) 07351-005 INL (LSB) 0 0 –0.5 –0.5 0 4,096 8,192 CODES 12,288 16,384 0 4,096 8,192 CODES 12,288 16,384 Figure 5. Integral Nonlinearity vs. Code, VREF = VDD = 5 V 300k 261,120 250k VREF = VDD = 5V Figure 8. Differential Nonlinearity vs. Code, VREF = VDD = 5 V 300k 259,473 250k VREF = VDD = 2.5V 200k 200k COUNTS COUNTS 150k 150k 100k 100k 50k 0 0 1FFC 0 1FFD 0 1FFE 1 1FFF 0 2000 0 2001 0 2002 0 07351-006 50k 0 0 0 0 955 2000 693 2001 0 2002 0 2003 0 2004 07351-009 07351-010 2003 1FFC 1FFD 1FFE 1FFF CODE IN HEX CODE IN HEX Figure 6. Histogram of a DC Input at Code Center 0 –20 AMPLITUDE (dB of Full-Scale) Figure 9. Histogram of a DC Input at Code Center 0 VREF = VDD = 2.5V fs= 200kSPS fIN = 19.9kHz SNR = 84.2dB SINAD = 82.4dB THD = –84dB SFDR = 85dB SECOND HARMONIC = –100dB THIRD HARMONIC = –85dB AMPLITUDE (dB of Full-Scale) –40 –60 –80 –100 –120 –140 VREF = VDD = 5V fS= 250kSPS fIN = 19.9kHz SNR = 85.3dB SINAD = 85.2dB THD = –100dB SFDR = 103dB SECOND HARMONIC = –110dB THIRD HARMONIC = –103dB –20 –40 –60 –80 –100 –120 –140 –160 07351-007 –160 0 25 50 75 100 125 –180 0 25 50 FREQUENCY (kHz) 75 100 FREQUENCY (kHz) Figure 7. 20 kHz FFT, VREF = VDD = 5 V Figure 10. 20 kHz FFT, VREF = VDD = 2.5 V Rev. B | Page 9 of 32 07351-008 –1.0 –1.0 AD7949 90 90 85 85 80 SINAD (dB) VDD = VREF VDD = VREF VDD = VREF VDD = VREF = 5V, –0.5dB = 5V, –10dB = 2.5V, –0.5dB = 2.5V, –10dB SNR (dB) 80 75 75 70 70 VDD = VREF VDD = VREF VDD = VREF VDD = VREF = 5V, –0.5dB = 5V, –10dB = 2.5V, –0.5dB = 2.5V, –10dB 65 65 07351-011 0 50 100 FREQUENCY (kHz) 150 200 0 50 100 FREQUENCY (kHz) 150 200 Figure 11. SNR vs. Frequency 88 SNR SINAD ENOB 86 15.0 15.5 130 125 120 115 SNR, SINAD (dB) Figure 14. SINAD vs. Frequency –60 –65 –70 –75 –80 SFDR 100 95 90 85 THD –90 –95 110 SFDR (dB) 82 14.0 –100 –105 –110 –115 80 13.5 80 75 07351-012 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V) Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage 90 –90 Figure 15. SFDR and THD vs. Reference Voltage fIN = 20kHz fIN = 20kHz 85 VDD = VREF = 5V –95 80 VDD = VREF = 2.5V VDD = VREF = 5V SNR (dB) THD (dB) VDD = VREF = 2.5V –100 75 70 –105 65 07351-013 –35 –15 5 25 45 65 85 105 125 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 13. SNR vs. Temperature Figure 16. THD vs. Temperature Rev. B | Page 10 of 32 07351-016 60 –55 –110 –55 07351-015 78 1.0 13.0 70 1.0 –120 5.5 THD (dB) 84 14.5 ENOB (Bits) 105 –85 07351-014 60 60 AD7949 –60 2750 2500 2250 2.5V INTERNAL REF 4.096V INTERNAL REF INTERNAL BUFFER, TEMP ON INTERNAL BUFFER, TEMP OFF EXTERNAL REF, TEMP ON EXTERNAL REF, TEMP OFF VIO 100 fS = 200kSPS 90 80 70 60 50 40 30 20 5.5 –70 VDD CURRENT (µA) –80 THD (dB) 2000 1750 1500 1250 1000 –90 –100 VDD = VREF VDD = VREF VDD = VREF VDD = VREF 0 50 100 FREQUENCY (kHz) = 5V, –0.5dB = 2.5V, –0.5dB = 2.5V, –10dB = 5V, –10dB 07351-017 –110 150 200 3.0 3.5 4.0 VDD SUPPLY (V) 4.5 5.0 Figure 17. THD vs. Frequency 90 89 88 87 2500 3000 Figure 20. Operating Currents vs. Supply 180 fIN = 20kHz 2750 fS = 200kSPS 160 140 VDD = 5V, INTERNAL 4.096V REF 2250 2000 VDD = 5V, EXTERNAL REF 1750 1500 1250 1000 –55 VDD = 2.5, EXTERNAL REF VIO 80 60 40 20 125 120 100 VDD CURRENT (µA) 86 VDD = VREF = 5V SNR (dB) 85 84 83 82 81 80 79 –8 –6 –4 –2 0 VDD = VREF = 2.5V –35 –15 5 25 45 65 85 105 INPUT LEVEL (dB) TEMPERATURE (°C) Figure 18. SNR vs. Input Level 2 Figure 21. Operating Currents vs. Temperature 25 OFFSET ERROR AND GAIN ERROR (LSB) 20 1 VDD = 2.5V, 85°C tDSDO DELAY (ns) 15 VDD = 2.5V, 25°C 10 VDD = 5V, 85°C 5 VDD = 3.3V, 85°C VDD = 3.3V, 25°C VDD = 5V, 25°C 0 –1 UNIPOLAR ZERO UNIPOLAR GAIN BIPOLAR ZERO BIPOLAR GAIN –35 –15 5 25 45 65 85 105 125 07351-019 0 20 TEMPERATURE (°C) 40 60 80 SDO CAPACITIVE LOAD (pF) 100 120 Figure 19. Offset and Gain Errors vs. Temperature Figure 22. tDSDO Delay vs. SDO Capacitance Load and Supply Rev. B | Page 11 of 32 07351-022 –2 –55 0 07351-021 07351-018 78 –10 VIO CURRENT (µA) 07351-020 –120 750 2.5 VIO CURRENT (µA) AD7949 TERMINOLOGY Least Significant Bit (LSB) The LSB is the smallest increment that can be represented by a converter. For an analog-to-digital converter with N bits of resolution, the LSB expressed in volts is Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-(Noise + Distortion) Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD by the formula ENOB = (SINADdB − 1.76)/6.02 LSB (V)  VREF 2N Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 24). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Offset Error The first transition should occur at a level ½ LSB above analog ground. The offset error is the deviation of the actual transition from that point. Gain Error The last transition (from 111 … 10 to 111 … 11) should occur for an analog voltage 1½ LSB below the nominal full scale. The gain error is the deviation in LSB (or percentage of full-scale range) of the actual level of the last transition from the ideal level after the offset error is adjusted out. Closely related is the full-scale error (also in LSB or percentage of full-scale range), which includes the effects of the offset error. Aperture Delay Aperture delay is the measure of the acquisition performance. It is the time between the rising edge of the CNV input and the point at which the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels. and is expressed in bits. Channel-to-Channel Crosstalk Channel-to-channel crosstalk is a measure of the level of crosstalk between any two adjacent channels. It is measured by applying a dc to the channel under test and applying a full-scale, 100 kHz sine wave signal to the adjacent channel(s). The crosstalk is the amount of signal that leaks into the test channel and is expressed in decibels. Reference Voltage Temperature Coefficient Reference voltage temperature coefficient is derived from the typical shift of output voltage at 25°C on a sample of parts at the maximum and minimum reference output voltage (VREF) measured at TMIN, T (25°C), and TMAX. It is expressed in ppm/°C as TCV REF (ppm/C)  V REF ( Max ) – V REF ( Min) V REF ( 25C )  (T MAX – T MIN )  10 6 where: VREF (Max) = maximum VREF at TMIN, T (25°C), or TMAX. VREF (Min) = minimum VREF at TMIN, T (25°C), or TMAX. VREF (25°C) = VREF at 25°C. TMAX = +85°C. TMIN = –40°C. Rev. B | Page 12 of 32 AD7949 THEORY OF OPERATION INx+ SWITCHES CONTROL MSB 8,192C REF COMP GND 8,192C 4,096C MSB 4C 2C C C LSB SW– CNV 4,096C 4C 2C C C CONTROL LOGIC OUTPUT CODE LSB SW+ BUSY INx– OR COM Figure 23. ADC Simplified Schematic OVERVIEW The AD7949 is an 8-channel, 14-bit, charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC). The AD7949 is capable of converting 250,000 samples per second (250 kSPS) and powers down between conversions. For example, when operating with an external reference at 1 kSPS, it consumes 15 μW typically, ideal for battery-powered applications. The AD7949 contains all of the components for use in a multichannel, low power data acquisition system, including       CONVERTER OPERATION The AD7949 is a successive approximation ADC based on a charge redistribution DAC. Figure 23 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 14 binary-weighted capacitors, which are connected to the two comparator inputs. During the acquisition phase, terminals of the array tied to the comparator input are connected to GND via SW+ and SW−. All independent switches are connected to the analog inputs. Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the INx+ and INx− (or COM) inputs. When the acquisition phase is complete and the CNV input goes high, a conversion phase is initiated. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the INx+ and INx− (or COM) inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary-weighted voltage steps (VREF/2, VREF/4, ... VREF/8,192). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase, and the control logic generates the ADC output code and a busy signal indicator. Because the AD7949 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process. 14-bit SAR ADC with no missing codes 8-channel, low crosstalk multiplexer Internal low drift reference and buffer Temperature sensor Selectable one-pole filter Channel sequencer These components are configured through an SPI-compatible, 14-bit register. Conversion results, also SPI compatible, can be read after or during conversions with the option for reading back the configuration associated with the conversion. The AD7949 provides the user with an on-chip track-and-hold and does not exhibit pipeline delay or latency. The AD7949 is specified from 2.3 V to 5.5 V and can be interfaced to any 1.8 V to 5 V digital logic family. The part is housed in a 20-lead, 4 mm × 4 mm LFCSP that combines space savings and allows flexible configurations. It is pin-for-pin compatible with the 16-bit AD7682, AD7689, and AD7699. Rev. B | Page 13 of 32 07351-023 AD7949 TRANSFER FUNCTIONS With the inputs configured for unipolar range (single-ended, COM with ground sense, or paired differentially with INx− as ground sense), the data output is straight binary. With the inputs configured for bipolar range (COM = VREF/2 or paired differentially with INx− = VREF/2), the data outputs are twos complement. The ideal transfer characteristic for the AD7949 is shown in Figure 24 and for both unipolar and bipolar ranges with the internal 4.096 V reference. TWOS STRAIGHT COMPLEMENT BINARY 011...111 011...110 011...101 111...111 111...110 111...101 ADC CODE 100...010 100...001 100...000 000...010 000...001 000...000 –FSR –FSR + 1LSB +FSR – 1LSB +FSR – 1.5LSB ANALOG INPUT –FSR + 0.5LSB Figure 24. ADC Ideal Transfer Function Table 7. Output Codes and Ideal Input Voltages Description FSR − 1 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR 1 2 Unipolar Analog Input1 VREF = 4.096 V 4.095750 V 2.048250 V 2.048000 V 2.047750 V 250 μV 0V Digital Output Code (Straight Binary Hex) 0x3FFF3 0x2001 0x2000 0x1FFF 0x0001 0x00004 Bipolar Analog Input2 VREF = 4.096 V 2.047750 V 250 μV 0V −250 μV −2.047750 V −2.048 V Digital Output Code (Twos Complement Hex) 0x1FFF3 0x0001 0x0000 0x3FFF 0x2001 0x20004 With COM or INx− = 0 V or all INx referenced to GND. With COM or INx− = VREF /2. 3 This is also the code for an overranged analog input ((INx+) − (INx−), or COM, above VREF − GND). 4 This is also the code for an underranged analog input ((INx+) − (INx−), or COM, below GND). Rev. B | Page 14 of 32 07351-024 AD7949 TYPICAL CONNECTION DIAGRAMS 5V 1.8V TO VDD V+ 10µF2 100nF 100nF 100nF REF 0V TO VREF ADA4841-x 3 V– V+ IN[7:1] IN0 REFIN VDD VIO DIN MOSI SCK MISO SS AD7949 0V TO VREF ADA4841-x 3 V– 0V OR VREF /2 COM GND SCK SDO CNV Figure 25. Typical Application Diagram with Multiple Supplies +5V 1.8V TO VDD 10µF2 V+ 100nF 100nF 100nF REF ADA4841-x 3 V– IN0 REFIN VDD VIO DIN IN[7:1] V+ ADA4841-x 3 V– MOSI SCK MISO SS AD7949 SCK SDO CNV VREF p-p VREF /2 COM GND Figure 26. Typical Application Diagram Using Bipolar Input Rev. B | Page 15 of 32 07351-026 NOTES 1. INTERNAL REFERENCE SHOWN. SEE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR REFERENCE SELECTION. 2. CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). 3. SEE THE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS. 4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA. 07351-025 NOTES 1. INTERNAL REFERENCE SHOWN. SEE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR REFERENCE SELECTION. 2. CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). 3. SEE THE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS. 4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA. AD7949 Unipolar or Bipolar Figure 25 shows an example of the recommended connection diagram for the AD7949 when multiple supplies are available. 70 65 60 55 Bipolar Single Supply Figure 26 shows an example of a system with a bipolar input using single supplies with the internal reference (optional different VIO supply). This circuit is also useful when the amplifier/signal conditioning circuit is remotely located with some common mode present. Note that for any input configuration, the INx inputs are unipolar and are always referenced to GND (no negative voltages even in bipolar range). For this circuit, a rail-to-rail input/output amplifier can be used; however, the offset voltage vs. input common-mode range should be noted and taken into consideration (1 LSB = 250 μV with VREF = 4.096 V). Note that the conversion results are in twos complement format when using the bipolar input configuration. Refer to the AN-581 Application Note, Biasing and Decoupling Op Amps in Single Supply Applications, at www.analog.com for additional details about using single-supply amplifiers. CMRR (dB) 50 45 40 35 30 07351-028 1 10 100 FREQUENCY (kHz) 1k 10k Figure 28. Analog Input CMRR vs. Frequency ANALOG INPUTS Input Structure Figure 27 shows an equivalent circuit of the input structure of the AD7949. The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN[7:0] and COM. Care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 0.3 V because this causes the diodes to become forward biased and to start conducting current. These diodes can handle a forward-biased current of 130 mA maximum. For instance, these conditions may eventually occur when the input buffer supplies are different from VDD. In such a case, for example, an input buffer with a short circuit, the current limitation can be used to protect the part. VDD INx+ OR INx– OR COM CPIN GND D1 CIN During the acquisition phase, the impedance of the analog inputs can be modeled as a parallel combination of the capacitor, CPIN, and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 2.4 kΩ and is a lumped component composed of serial resistors and the on resistance of the switches. CIN is typically 27 pF and is mainly the ADC sampling capacitor. Selectable Low-Pass Filter During the conversion phase, where the switches are opened, the input impedance is limited to CPIN. While the AD7949 is acquiring, RIN and CIN make a one-pole, low-pass filter that reduces undesirable aliasing effects and limits the noise from the driving circuitry. The low-pass filter can be programmed for the full bandwidth or ¼ of the bandwidth with CFG[6], as shown in Table 9. This setting changes RIN to 19 kΩ. Note that the converter throughput must also be reduced by ¼ when using the filter. If the maximum throughput is used with the bandwidth (BW) set to ¼, the converter acquisition time, tACQ, is violated, resulting in increased THD. RIN D2 07351-027 Figure 27. Equivalent Analog Input Circuit This analog input structure allows the sampling of the true differential signal between INx+ and COM or INx+ and INx−. (COM or INx− = GND ± 0.1 V or VREF ± 0.1 V). By using these differential inputs, signals common to both inputs are rejected, as shown in Figure 28. Rev. B | Page 16 of 32 AD7949 Input Configurations Figure 29 shows the different methods for configuring the analog inputs with the configuration register, CFG[12:10]. Refer to the Configuration Register, CFG, section for more details. The analog inputs can be configured as  CH0+ CH1+ CH2+ CH3+ CH4+ CH5+ IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 COM GND A—8 CHANNELS, SINGLE ENDED CH0+ CH1+ CH2+ CH3+ CH4+ CH5+ CH6+ CH7+ COM– IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 COM GND B—8 CHANNELS, COMMON REFERNCE    Figure 29A, single-ended referenced to system ground; CFG[12:10] = 1112. In this configuration, all inputs (IN[7:0]) have a range of GND to VREF. Figure 29B, bipolar differential with a common reference point; COM = VREF/2; CFG[12:10] = 0102. Unipolar differential with COM connected to a ground sense; CFG[12:10] = 1102. In these configurations, all inputs IN[7:0] have a range of GND to VREF. Figure 29C, bipolar differential pairs with the negative input channel referenced to VREF/2; CFG[12:10] = 00X2. Unipolar differential pairs with the negative input channel referenced to a ground sense; CFG[12:10] = 10X2. In these configurations, the positive input channels have the range of GND to VREF. The negative input channels are senses referred to VREF/2 for bipolar pairs, or GND for unipolar pairs. The positive channel is configured with CFG[9:7]. If CFG[9:7] is even, then IN0, IN2, IN4, and IN6 are used. If CFG[9:7] is odd, then IN1, IN3, IN5, and IN7 are used (channels with parentheses). For example, for IN0/IN1 pairs with the positive channel on IN0, CFG[9:7] = 0002. For IN4/IN5 pairs with the positive channel on IN5, CFG[9:7] = 1012. Note that for the sequencer, detailed in the Channel Sequencer section, the positive channels are always IN0, IN2, IN4, and IN6. Figure 29D, inputs configured in any of the preceding combinations (showing that the AD7949 can be configured dynamically). CH6+ CH7+ CH0+ (–) CH0– (+) CH1+ (–) CH1– (+) CH2+ (–) CH2– (+) CH3+ (–) CH3– (+) IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 COM GND C—4 CHANNELS, DIFFERENTIAL CH0+ (–) CH0– (+) CH1+ (–) CH1– (+) CH2+ CH3+ CH4+ CH5+ COM– IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 COM GND D—COMBINATION 07351-029 Figure 29. Multiplexed Analog Input Configurations Sequencer The AD7949 includes a channel sequencer useful for scanning channels in a repeated fashion. Refer to the Channel Sequencer section for further details of the sequencer operation. Source Resistance When the source impedance of the driving circuit is low, the AD7949 can be driven directly. Large source impedances significantly affect the ac performance, especially THD. The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency. Rev. B | Page 17 of 32 AD7949 DRIVER AMPLIFIER CHOICE Although the AD7949 is easy to drive, the driver amplifier must meet the following requirements:  VOLTAGE REFERENCE OUTPUT/INPUT The AD7949 allows the choice of a very low temperature drift internal voltage reference, an external reference, or an external buffered reference. The internal reference of the AD7949 provides excellent performance and can be used in almost all applications. There are six possible choices of voltage reference schemes briefly described in Table 9, with more details in each of the following sections.   The noise generated by the driver amplifier must be kept as low as possible to preserve the SNR and transition noise performance of the AD7949. Note that the AD7949 has a noise much lower than most of the other 14-bit ADCs and, therefore, can be driven by a noisier amplifier to meet a given system noise specification. The noise from the amplifier is filtered by the AD7949 analog input circuit low-pass filter made by RIN and CIN or by an external filter, if one is used. For ac applications, the driver should have a THD performance commensurate with the AD7949. Figure 17 shows THD vs. frequency for the AD7949. For multichannel, multiplexed applications on each input or input pair, the driver amplifier and the AD7949 analog input circuit must settle a full-scale step onto the capacitor array at a 14-bit level (0.0015%). In amplifier data sheets, settling at 0.1% to 0.01% is more commonly specified. This may differ significantly from the settling time at a 14-bit level and should be verified prior to driver selection. Internal Reference/Temperature Sensor The precision internal reference, suitable for most applications, can be set for either a 2.5 V or a 4.096 V output, as detailed in Table 9. With the internal reference enabled, the band gap voltage is also present on the REFIN pin, which requires an external 0.1 μF capacitor. Because the current output of REFIN is limited, it can be used as a source if followed by a suitable buffer, such as the AD8605. Note that the voltage of REFIN changes depending on the 2.5 V or 4.096 V internal reference. Enabling the reference also enables the internal temperature sensor, which measures the internal temperature of the AD7949 and is thus useful for performing a system calibration. Note that, when using the temperature sensor, the output is straight binary referenced from the AD7949 GND pin. The internal reference is temperature-compensated to within 10 mV. The reference is trimmed to provide a typical drift of ±10 ppm/°C. Connect the AD7949 as shown in Figure 30 for either a 2.5 V or 4.096 V internal reference. 10µF REF 100nF REFIN Table 8. Recommended Driver Amplifiers Amplifier ADA4841-x AD8655 AD8021 AD8022 OP184 AD8605, AD8615 Typical Application Very low noise, small, and low power 5 V single supply, low noise Very low noise and high frequency Low noise and high frequency Low power, low noise, and low frequency 5 V single supply, low power AD7949 TEMP GND Figure 30. 2.5 V or 4.096 V Internal Reference Connection Rev. B | Page 18 of 32 07351-030 AD7949 External Reference and Internal Buffer For improved drift performance, an external reference can be used with the internal buffer, as shown in Figure 31. The external source is connected to REFIN, the input to the on-chip unity gain buffer, and the output is produced on the REF pin. An external reference can be used with the internal buffer with or without the temperature sensor enabled. Refer to Table 9 for register details. With the buffer enabled, the gain is unity and is limited to an input/output of VDD = −0.2 V; however, the maximum voltage allowable must be ≤(VDD − 0.5 V). The internal reference buffer is useful in multiconverter applications because a buffer is typically required in these applications. In addition, a low power reference can be used because the internal buffer provides the necessary performance to drive the SAR architecture of the AD7949. REF SOURCE ≤ (VDD – 0.5V) 10µF REF 100nF REFIN Reference Decoupling Whether using an internal or external reference, the AD7949 voltage reference output/input, REF, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins. This decoupling depends on the choice of the voltage reference but usually consists of a low ESR capacitor connected to REF and GND with minimum parasitic inductance. A 10 μF (X5R, 1206 size) ceramic chip capacitor is appropriate when using the internal reference, the ADR43x/ADR44x external reference, or a low impedance buffer such as the AD8031 or the AD8605. The placement of the reference decoupling capacitor is also important to the performance of the AD7949, as explained in the Layout section. Mount the decoupling capacitor on the same side as the ADC at the REF pin with a thick PCB trace. The GND should also be connected to the reference decoupling capacitor with the shortest distance and to the analog ground plane with several vias. If desired, smaller reference decoupling capacitor values down to 2.2 μF can be used with minimal impact on performance, especially on DNL. Regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REF and GND pins. For applications that use multiple AD7949 devices or other PulSAR devices, it is more effective to use the internal reference buffer to buffer the external reference voltage, thus reducing SAR conversion crosstalk. The voltage reference temperature coefficient (TC) directly impacts full scale; therefore, in applications where full-scale accuracy matters, care must be taken with the TC. For instance, a ±10 ppm/°C TC of the reference changes full scale by ±1 LSB/°C. AD7949 TEMP GND Figure 31. External Reference Using Internal Buffer External Reference In any of the six voltage reference schemes, an external reference can be connected directly on the REF pin as shown in Figure 32 because the output impedance of REF is >5 kΩ. To reduce power consumption, the reference and buffer should be powered down. For applications requiring the use of the temperature sensor, the internal reference must be active (internal buffer can be disabled in this case). Refer to Table 9 for register details. For improved drift performance, an external reference such as the ADR43x or ADR44x is recommended. 10µF REF SOURCE 0.5V < REF < (VDD + 0.3V) NO CONNECTION REQUIRED REFIN REF AD7949 TEMP 07351-031 GND Figure 32. External Reference Note that the best SNR is achieved with a 5 V external reference as the internal reference is limited to 4.096 V. The SNR degradation is as follows: SNR LOSS  20 log 4.096 5 07351-032 Rev. B | Page 19 of 32 AD7949 POWER SUPPLY The AD7949 uses two power supply pins: an analog and digital core supply (VDD) and a digital input/output interface supply (VIO). VIO allows direct interface with any logic between 1.8 V and VDD. To reduce the supplies needed, the VIO and VDD pins can be tied together. The AD7949 is independent of power supply sequencing between VIO and VDD. Additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in Figure 33. 75 70 65 60 PSSR (dB) 5V 10kΩ 1µF 5V SUPPLYING THE ADC FROM THE REFERENCE For simplified applications, the AD7949, with its low operating current, can be supplied directly using an external reference circuit like the one shown in Figure 35. The reference line can be driven by:    The system power supply directly A reference voltage with enough current output capability, such as the ADR43x or ADR44x A reference buffer, such as the AD8605, which can also filter the system power supply, as shown in Figure 35 5V 10Ω 55 50 AD8605 1 10µF 1µF 0.1µF 0.1µF 45 40 35 30 07351-033 REF VDD VIO AD7949 07351-035 1 10 100 FREQUENCY (kHz) 1k 10k 1OPTIONAL REFERENCE BUFFER AND FILTER. Figure 35. Example of an Application Circuit Figure 33. PSRR vs. Frequency The AD7949 powers down automatically at the end of each conversion phase; therefore, the operating currents and power scale linearly with the sampling rate. This makes the part ideal for low sampling rates (even of a few hertz) and low batterypowered applications. 10,000 1000 VDD = 5V, INTERNAL REF OPERATING CURRENT (µA) 100 10 1 VDD = 5V, EXTERNAL REF VDD = 2.5V, EXTERNAL REF VIO 0.1 0.010 0.001 10 100 1k 10k SAMPLING RATE (SPS) 100k 1M Figure 34. Operating Currents vs. Sampling Rate Rev. B | Page 20 of 32 07351-034 AD7949 DIGITAL INTERFACE The AD7949 uses a simple 4-wire interface and is compatible with SPI, MICROWIRE™, QSPI™, digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x, SHARC®, ADSP-219x, and ADSP-218x. The interface uses the CNV, DIN, SCK, and SDO signals and allows CNV, which initiates the conversion, to be independent of the readback timing. This is useful in low jitter sampling or simultaneous sampling applications. A 14-bit register, CFG[13:0], is used to configure the ADC for the channel to be converted, the reference selection, and other components, which are detailed in the Configuration Register, CFG, section. When CNV is low, reading/writing can occur during conversion, acquisition, and spanning conversion (acquisition plus conversion), as detailed in the following sections. The CFG word is updated on the first 14 SCK rising edges, and conversion results are output on the first 13 (or 14 if busy mode is selected) SCK falling edges. If the CFG readback is enabled, an additional 14 SCK falling edges are required to output the CFG word associated with the conversion results with the CFG MSB following the LSB of the conversion result. A discontinuous SCK is recommended because the part is selected with CNV low, and SCK activity begins to write a new configuration word and clock out data. Note that in the following sections, the timing diagrams indicate digital activity (SCK, CNV, DIN, SDO) during the conversion. However, due to the possibility of performance degradation, digital activity should occur only prior to the safe data reading/ writing time, tDATA, because the AD7949 provides error correction circuitry that can correct for an incorrect bit during this time. From tDATA to tCONV, there is no error correction and conversion results may be corrupted. The user should configure the AD7949 and initiate the busy indicator (if desired) prior to tDATA. It is also possible to corrupt the sample by having SCK or DIN transitions near the sampling instant. Therefore, it is recommended to keep the digital pins quiet for approximately 20 ns before and 10 ns after the rising edge of CNV, using a discontinuous SCK whenever possible to avoid any potential performance degradation. The SCK frequency required is calculated by f SCK  Number _ SCK _ Edges t DATA The time between tDATA and tCONV is a safe time when digital activity should not occur, or sensitive bit decisions may be corrupted. READING/WRITING AFTER CONVERSION, ANY SPEED HOSTS When reading/writing after conversion, or during acquisition (n), conversion results are for the previous (n − 1) conversion, and writing is for the (n + 1) acquisition. For the maximum throughput, the only time restriction is that the reading/writing take place during the tACQ (minimum) time. For slow throughputs, the time restriction is dictated by the throughput required by the user, and the host is free to run at any speed. Thus for slow hosts, data access must take place during the acquisition phase. READING/WRITING SPANNING CONVERSION, ANY SPEED HOST When reading/writing spanning conversion, the data access starts at the current acquisition (n) and spans into the conversion (n). Conversion results are for the previous (n − 1) conversion, and writing the CFG register is for the next (n + 1) acquisition and conversion. Similar to reading/writing during conversion, reading/writing should only occur up to tDATA. For the maximum throughput, the only time restriction is that reading/writing take place during the tACQ + tDATA time. For slow throughputs, the time restriction is dictated by the user’s required throughput, and the host is free to run at any speed. Similar to reading/writing during acquisition, for slow hosts, the data access must take place during the acquisition phase with additional time into the conversion. Note that data access spanning conversion requires the CNV to be driven high to initiate a new conversion, and data access is not allowed when CNV is high. Thus, the host must perform two bursts of data access when using this method. READING/WRITING DURING CONVERSION, FAST HOSTS When reading/writing during conversion (n), conversion results are for the previous (n − 1) conversion, and writing the CFG register is for the next (n + 1) acquisition and conversion. After the CNV is brought high to initiate conversion, it must be brought low again to allow reading/writing during conversion. Reading/writing should only occur up to tDATA and, because this time is limited, the host must use a fast SCK. CONFIGURATION REGISTER, CFG The AD7949 uses a 14-bit configuration register (CFG[13:0]), as detailed in Table 9, to configure the inputs, the channel to be converted, the one-pole filter bandwidth, the reference, and the channel sequencer. The CFG register is latched (MSB first) on DIN with 14 SCK rising edges. The CFG update is edge dependent, allowing for asynchronous or synchronous hosts. Rev. B | Page 21 of 32 AD7949 The register can be written to during conversion, during acquisition, or spanning acquisition/conversion, and is updated at the end of conversion, tCONV (maximum). There is always a one deep delay when writing the CFG register. Note that, at power-up, the CFG register is undefined and two dummy conversions are required to update the register. To preload the CFG register with a factory setting, hold DIN high for two conversions. Thus CFG[13:0] = 0x3FFF. This sets the AD7949 for the following: 13 CFG 12 INCC 11 INCC 10 INCC 9 INx 8 INx 7 INx      IN[7:0] unipolar referenced to GND, sequenced in order Full bandwidth for a one-pole filter Internal reference/temperature sensor disabled, buffer enabled Enables the internal sequencer No readback of the CFG register Table 9 summarizes the configuration register bit details. See the Theory of Operation section for more details. 6 BW 5 REF 4 REF 3 REF 2 SEQ 1 SEQ 0 RB Table 9. Configuration Register Description Bit(s) [13] Name CFG Description Configuration update. 0 = keep current configuration settings. 1 = overwrite contents of register. Input channel configuration. Selection of pseudo bipolar, pseudo differential, pairs, single-ended, or temperature sensor. Refer to the Input Configurations section. Bit 12 Bit 11 Bit 10 Function 0 0 X1 Bipolar differential pairs; INx− referenced to VREF/2 ± 0.1 V. 0 1 0 Bipolar; INx referenced to COM = VREF/2 ± 0.1 V. 0 1 1 Temperature sensor. 1 0 X1 Unipolar differential pairs; INx− referenced to GND ± 0.1 V. 1 1 0 Unipolar, INx referenced to COM = GND ± 0.1 V. Unipolar, INx referenced to GND. 1 1 1 Input channel selection in binary fashion. Bit 9 Bit 8 Bit 7 Channel 0 0 0 IN0 0 0 1 IN1 … … … 1 1 1 IN7 Select bandwidth for low-pass filter. Refer to the Selectable Low-Pass Filter section. 0 = ¼ of BW, uses an additional series resistor to further bandwidth limit the noise. Maximum throughput must also be reduced to ¼. 1 = full BW. Reference/buffer selection. Selection of internal, external, external buffered, and enabling of the on-chip temperature sensor. Refer to the Voltage Reference Output/Input section. Bit 5 Bit 4 Bit 3 Function 0 0 0 Internal reference, REF = 2.5 V output. 0 0 1 Internal reference, REF = 4.096 V output. 0 1 0 External reference, temperature enabled. 0 1 1 External reference, internal buffer, temperature enabled. 1 1 0 External reference, temperature disabled. 1 1 1 External reference, internal buffer, temperature disabled. Channel sequencer. Allows for scanning channels in an IN0 to IN[7:0] fashion. Refer to the Channel Sequencer section. Bit 2 Bit 1 Function 0 0 Disable sequencer. 0 1 Update configuration during sequence. 1 0 Scan IN0 to IN[7:0] (set in CFG[9:7]), then temperature. 1 1 Scan IN0 to IN[7:0] (set in CFG[9:7]). Read back the CFG register. 0 = read back current configuration at end of data. 1 = do not read back contents of configuration. [12:10] INCC [9:7] INx [6] BW [5:3] REF [2:1] SEQ [0] RB 1 X = don’t care. Rev. B | Page 22 of 32 AD7949 GENERAL TIMING WITHOUT A BUSY INDICATOR Figure 36 details the timing for all three modes: read/write during conversion (RDC), read/write after conversion (RAC), and read/write spanning conversion (RSC). Note that the gating item for both CFG and data readback is at the end of conversion (EOC). At EOC, if CNV is high, the busy indicator is disabled. As detailed previously in the Digital Interface section, the data access should occur up to safe data reading/writing time, tDATA. If the full CFG word was not written to prior to EOC, it is discarded and the current configuration remains. If the conversion result is not read out fully prior to EOC, it is lost as the ADC updates SDO with the MSB of the current conversion. For detailed timing, refer to Figure 39 and Figure 40, which depict reading/writing spanning conversion with all timing details, including setup, hold, and SCK. tCYC POWER UP PHASE SOC EOC EOC ACQUISITION (n) CONVERSION (n) ACQUISITION (n + 1) CONVERSION (n + 1) When CNV is brought low after EOC, SDO is driven from high impedance to the MSB. Falling SCK edges clock out bits starting with MSB − 1. The SCK can idle high or low depending on the clock polarity (CPOL) and clock phase (CPHA) settings if SPI is used. A simple solution is to use CPOL = CPHA = 0 as shown in Figure 36 with SCK idling low. From power-up, in any read/write mode, the first three conversion results are undefined because a valid CFG does not take place until the 2nd EOC; thus two dummy conversions are required. Also, if the state machine writes the CFG during the power-up state (RDC shown), the CFG register needs to be rewritten again at the next phase. Note that the first valid data occurs in Phase (n + 1) when the CFG register is written during Phase (n − 1). EOC ACQUISITION (n + 2) tCONV CONVERSION (n – 2) UNDEFINED EOC ACQUISITION (n – 1) UNDEFINED NOTE 1 tDATA CONVERSION (n – 1) UNDEFINED CNV DIN RDC SDO SCK MSB XXX 1 DATA (n – 3) XXX 14 1 DATA (n – 2) XXX MSB XXX 1 DATA (n – 1) XXX MSB (n) XXX CFG (n) CFG (n + 1) CFG (n + 2) DATA (n) 1 14 NOTE 2 14 14 NOTE 1 CNV DIN RAC SDO SCK 1 CFG (n) DATA (n – 2) XXX CFG (n + 1) DATA (n – 1) XXX 1 CFG (n + 2) DATA (n) 1 CFG (n + 3) DATA (n + 1) 1 14 14 14 NOTE 2 NOTE 1 CNV DIN RSC SDO SCK 1 CFG (n) DATA (n – 2) XXX n n+1 CFG (n) DATA (n – 2) XXX CFG (n + 1) DATA (n – 1) XXX 1 n n+1 CFG (n + 1) DATA (n – 1) XXX CFG (n + 2) DATA (n) 1 n n+1 CFG (n + 2) DATA (n) CFG (n + 3) DATA (n + 1) 1 n 14 NOTE 2 14 14 Figure 36. General Interface Timing for the AD7949 Without a Busy Indicator Rev. B | Page 23 of 32 07351-036 NOTES 1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR. 2. A TOTAL OF 14 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 28 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. 3. WITH THE SEQUENCER ENABLED, THE NEXT ACQUISITION PHASE WILL BE FOR IN0 AFTER THE LAST CHANNEL SET IN CFG[9:7] IS CONVERTED. AD7949 GENERAL TIMING WITH A BUSY INDICATOR Figure 37 details the timing for all three modes: read/write during conversion (RDC), read/write after conversion (RAC), and read/write spanning conversion (RSC). Note that the gating item for both CFG and data readback is at the end of conversion (EOC). As detailed previously, the data access should occur up to safe data reading/writing time, tDATA. If the full CFG word is not written to prior to EOC, it is discarded and the current configuration remains. At the EOC, if CNV is low, the busy indicator is enabled. In addition, to generate the busy indicator properly, the host must assert a minimum of 15 SCK falling edges to return SDO to high impedance because the last bit on SDO remains active. Unlike the case detailed in the General Timing Without a Busy Indicator section, if the conversion result is not read out fully prior to EOC, the last bit clocked out remains. If this bit is low, the busy signal indicator cannot be generated because the busy tCYC POWER UP PHASE START OF CONVERSION (SOC) EOC EOC EOC generation requires either a high impedance or a remaining bit high-to-low transition. Because most SPI hosts are usually limited to 8-bit or 16-bit bursts, this should not be an issue. Additional clocks are not a concern because SDO remains high impedance after the 15th falling edge. The SCK can idle high or low depending on the CPOL and CPHA settings if SPI is used. A simple solution is to use CPOL = CPHA = 1 (not shown) with SCK idling high. From power-up, in any read/write mode, the first three conversion results are undefined because a valid CFG does not take place until the 2nd EOC; thus, two dummy conversions are required. Also, if the state machine writes the CFG during the power-up state (RDC shown), the CFG register needs to be rewritten again at the next phase. Note that the first valid data occurs in Phase (n + 1) when the CFG register is written during Phase (n − 1). tCONV CONVERSION (n – 2) UNDEFINED EOC ACQUISITION (n – 1) UNDEFINED tDATA CONVERSION (n – 1) UNDEFINED ACQUISITION (n) CONVERSION (n) ACQUISITION (n + 1) CONVERSION (n + 1) ACQUISITION (n + 2) CNV DIN RDC SDO SCK 1 DATA (n – 3) XXX NOTE 1 XXX CFG (n) DATA (n – 2) XXX CFG (n + 1) DATA (n – 1) XXX CFG (n + 2) DATA (n) 15 1 15 NOTE 2 1 15 1 15 CNV DIN RAC SDO SCK NOTE 1 CFG (n) DATA (n – 2) XXX CFG (n + 1) DATA (n – 1) XXX CFG (n + 2) DATA (n) 1 15 1 CFG (n + 3) DATA (n + 1) 1 15 NOTE 2 1 15 CNV DIN RSC SDO SCK NOTE 1 CFG (n) DATA (n – 2) XXX DATA (n – 2) XXX CFG (n + 1) DATA (n – 1) XXX DATA (n – 1) XXX CFG (n + 2) DATA (n) 1 n n+1 DATA (n) 15 1 CFG (n + 3) DATA (n + 1) 1 n n+1 NOTE 2 15 1 n n+1 15 Figure 37. General Interface Timing for the AD7949 With a Busy Indicator Rev. B | Page 24 of 32 07351-037 NOTES 1. CNV MUST BE LOW PRIOR TO THE END OF CONVERSION (EOC) TO GENERATE THE BUSY INDICATOR. 2. A TOTAL OF 15 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 29 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. AD7949 CHANNEL SEQUENCER The AD7949 includes a channel sequencer useful for scanning channels in a repeated fashion. Channels are scanned as singles or pairs, with or without the temperature sensor, after the last channel is sequenced. The sequencer starts with IN0 and finishes with IN[7:0] set in CFG[9:7]. For paired channels, the channels are paired depending on the last channel set in CFG[9:7]. Note that in sequencer mode, the channels are always paired with the positive input on the even channels (IN0, IN2, IN4, IN6), and with the negative input on the odd channels (IN1, IN3, IN5, IN7). For example, setting CFG[9:7] = 110 or 111 scans all pairs with the positive inputs dedicated to IN0, IN2, IN4, and IN6. CFG[2:1] are used to enable the sequencer. After the CFG register is updated, DIN must be held low while reading data out for Bit 13, or the CFG register begins updating again. Note that while operating in a sequence, some bits of the CFG register can be changed. However, if changing CFG[11] (paired or single channel) or CFG[9:7] (last channel in sequence), the sequence reinitializes and converts IN0 (or IN0/IN1 pairs) after the CFG register is updated. Figure 38 details the timing for all three modes without a busy indicator. Refer to the General Timing Without a Busy Indicator section and the Read/Write Spanning Conversion Without a tCYC POWER UP PHASE SOC EOC EOC ACQUISITION (n), IN0 CONVERSION (n), IN0 ACQUISITION (n + 1), IN1 CONVERSION (n + 1), IN1 Busy Indicator section for more details. The sequencer can also be used with the busy indicator and details for these timings can be found in the General Timing with a Busy Indicator section and the Read/Write Spanning Conversion with a Busy Indicator section. For sequencer operation, the CFG register should be set during the (n − 1) phase after power-up. On phase (n), the sequencer setting takes place and acquires IN0. The first valid conversion result is available at phase (n + 1). After the last channel set in CFG[9:7] is converted, the internal temperature sensor data is output (if enabled), followed by acquisition of IN0. Examples With all channels configured for unipolar mode to GND, including the internal temperature sensor, the sequence scans in the following order: IN0, IN1, IN2, IN3, IN4, IN5, IN6, IN7, TEMP, IN0, IN1, IN2, … For paired channels with the internal temperature sensor enabled, the sequencer scans in the following order: IN0, IN2, IN4, IN6, TEMP, IN0, … Note that IN1, IN3, IN5, and IN7 are referenced to a GND sense or VREF/2, as detailed in the Input Configurations section. tCONV CONVERSION (n – 2) UNDEFINED EOC ACQUISITION (n – 1) UNDEFINED NOTE 1 EOC ACQUISITION (n + 2), IN2 tDATA CONVERSION (n – 1) UNDEFINED CNV DIN RDC SDO SCK MSB XXX 1 DATA (n – 3) XXX 14 1 DATA (n – 2) XXX 14 NOTE 2 NOTE 1 MSB XXX 1 DATA (n – 1) XXX 14 MSB IN0 1 DATA IN0 14 XXX CFG (n) CNV DIN RAC SDO SCK 1 CFG (n) DATA (n – 2) XXX 14 NOTE 2 NOTE 1 1 DATA (n – 1) XXX 14 1 DATA IN0 14 1 DATA IN1 CNV DIN RSC SDO SCK 1 CFG (n) DATA (n – 2) XXX n n+1 CFG (n) DATA (n – 2) XXX 14 NOTE 2 1 DATA (n – 1) XXX n n+1 DATA (n – 1) XXX 14 1 DATA IN0 n n+1 DATA IN0 14 1 DATA IN1 n Figure 38. General Channel Sequencer Timing Without a Busy Indicator Rev. B | Page 25 of 32 07351-038 NOTES 1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR. 2. A TOTAL OF 14 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 28 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. AD7949 READ/WRITE SPANNING CONVERSION WITHOUT A BUSY INDICATOR This mode is used when the AD7949 is connected to any host using an SPI, serial port, or FPGA. The connection diagram is shown in Figure 39, and the corresponding timing is given in Figure 40. For the SPI, the host should use CPHA = CPOL = 0. Reading/writing spanning conversion is shown, which covers all three modes detailed in the Digital Interface section. For this mode, the host must generate the data transfer based on the conversion time. For an interrupt driven transfer that uses a busy indicator, refer to the Read/Write Spanning Conversion with a Busy Indicator section. A rising edge on CNV initiates a conversion, forces SDO to high impedance, and ignores data present on DIN. After a conversion is initiated, it continues until completion irrespective of the state of CNV. CNV must be returned high before the safe data transfer time, tDATA, and then held high beyond the conversion time, tCONV, to avoid generation of the busy signal indicator. After the conversion is complete, the AD7949 enters the acquisition phase and power-down. When the host brings CNV AD7949 CNV SDO DIN SCK low after tCONV (maximum), the MSB is enabled on SDO. The host also must enable the MSB of the CFG register at this time (if necessary) to begin the CFG update. While CNV is low, both a CFG update and a data readback take place. The first 14 SCK rising edges are used to update the CFG, and the first 13 SCK falling edges clock out the conversion results starting with MSB − 1. The restriction for both configuring and reading is that they both must occur before the tDATA time of the next conversion elapses. All 14 bits of CFG[13:0] must be written, or they are ignored. In addition, if the 14-bit conversion result is not read back before tDATA elapses, it is lost. The SDO data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 14th (or 28th) SCK falling edge, or when CNV goes high (whichever occurs first), SDO returns to high impedance. If CFG readback is enabled, the CFG register associated with the conversion result is read back MSB first following the LSB of the conversion result. A total of 28 SCK falling edges is required to return SDO to high impedance if this is enabled. DIGITAL HOST SS MISO MOSI SCK 07351-039 FOR SPI USE CPHA = 0, CPOL = 0. Figure 39. Connection Diagram for the AD7949 Without a Busy Indicator tCYC > tCONV tCONV tDATA EOC CNV RETURN CNV HIGH FOR NO BUSY tCONV tDATA tCNVH EOC RETURN CNV HIGH FOR NO BUSY tACQ ACQUISITION (n - 1) CONVERSION (n – 1) (QUIET TIME) UPDATE (n) CFG/SDO 13 14/ 28 1 2 12 13 ACQUISITION (n) CONVERSION (n) SEE NOTE 14/ 28 (QUIET TIME) UPDATE (n + 1) CFG/SDO tSCKH SCK tSCK 12 tSCKL DIN CFG LSB X X tCLSCK CFG MSB tSDIN CFG MSB – 1 tHDIN CFG LSB X X tEN END CFG (n) SDO LSB tEN MSB BEGIN CFG (n + 1) tHSDO tDSDO tEN END CFG (n + 1) SEE NOTE LSB tDIS END DATA (n – 2) tDIS BEGIN DATA (n – 1) tDIS END DATA (n – 1) tDIS 07351-040 NOTES 1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF 13 SCK FALLING EDGES = LSB OF CONVERSION RESULTS. 27 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER. ON THE 14TH OR 28TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPEDANCE. Figure 40. Serial Interface Timing for the AD7949 Without a Busy Indicator Rev. B | Page 26 of 32 AD7949 READ/WRITE SPANNING CONVERSION WITH A BUSY INDICATOR This mode is used when the AD7949 is connected to any host using an SPI, serial port, or FPGA with an interrupt input. The connection diagram is shown in Figure 41, and the corresponding timing is given in Figure 42. For the SPI, the host should use CPHA = CPOL = 1. Reading/writing spanning conversion is shown, which covers all three modes detailed in the Digital Interface section. A rising edge on CNV initiates a conversion, ignores data present on DIN and forces SDO to high impedance. After the conversion is initiated, it continues until completion irrespective of the state of CNV. CNV must be returned low before the safe data transfer time, tDATA, and then held low beyond the conversion time, tCONV, to generate the busy signal indicator. When the conversion is complete, SDO transitions from high impedance to low (data ready), and with a pull-up to VIO, SDO can be used to interrupt the host to begin data transfer. After the conversion is complete, the AD7949 enters the acquisition phase and power-down. The host must enable the MSB of the CFG register at this time (if necessary) to begin the VIO CFG update. While CNV is low, both a CFG update and a data readback take place. The first 14 SCK rising edges are used to update the CFG register, and the first 14 SCK falling edges clock out the conversion results starting with the MSB. The restriction for both configuring and reading is that they both occur before the tDATA time elapses for the next conversion. All 14 bits of CFG[13:0] must be written or they are ignored. Also, if the 14-bit conversion result is not read back before tDATA elapses, it is lost. The SDO data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the optional 15th (or 29st) SCK falling edge, SDO returns to high impedance. Note that if the optional SCK falling edge is not used, the busy feature cannot be detected, as described in the General Timing with a Busy Indicator section. If CFG readback is enabled, the CFG register associated with the conversion result is read back MSB first following the LSB of the conversion result. A total of 29 SCK falling edges is required to return SDO to high impedance if this is enabled. AD7949 SDO CNV DIN SCK DIGITAL HOST MISO IRQ SS MOSI SCK 07351-041 FOR SPI USE CPHA = 1, CPOL = 1. Figure 41. Connection Diagram for the AD7949 with a Busy Indicator tCYC tDATA tACQ tCNVH tDATA tCONV CNV CONVERSION (n – 1) CONVERSION (n – 1) (QUIET TIME) UPDATE (n) CFG/SDO ACQUISITION (n) CONVERSION (n) NOTE 1 (QUIET TIME) ACQUISITION (n + 1) tSCKH SCK tSCK 13 14 15/ 29 UPDATE (n + 1) CFG/SDO 1 2 13 14 15/ 29 tSCKL DIN X X X tSDIN tHDIN X X X CFG CFG MSB MSB –1 END CFG (n) SDO LSB +1 END DATA (n – 2) LSB tDIS BEIGN CFG (n + 1) MSB MSB –1 tHSDO tDSDO tEN END CFG (n + 1) LSB +1 LSB tDIS tEN BEGIN DATA (n – 1) tDIS END DATA (n – 1) NOTE 1 tEN Figure 42. Serial Interface Timing for the AD7949 with a Busy Indicator Rev. B | Page 27 of 32 07351-042 NOTES: 1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF 14 SCK FALLING EDGES = LSB OF CONVERSION RESULTS. 28 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER. ON THE 15TH OR 29TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPEDANCE. OTHERWISE, THE LSB REMAINS ACTIVE UNTIL THE BUSY INDICATOR IS DRIVEN LOW. AD7949 APPLICATION HINTS LAYOUT The printed circuit board (PCB) that houses the AD7949 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7949, with all its analog signals on the left side and all its digital signals on the right side, eases this task. Avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the AD7949 is used as a shield. Fast switching signals, such as CNV or clocks, should not run near analog signal paths. Avoid crossover of digital and analog signals. At least one ground plane should be used. It can be common or split between the digital and analog sections. In the latter case, the planes should be joined underneath the AD7949. The AD7949 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the REF and GND pins and connecting them with wide, low impedance traces. Finally, the power supplies VDD and VIO of the AD7949 should be decoupled with ceramic capacitors, typically 100 nF, placed close to the AD7949, and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. EVALUATING AD7949 PERFORMANCE Other recommended layouts for the AD7949 are outlined in the documentation of the evaluation board for the AD7949 (EVALAD7949EDZ). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the converter and evaluation development data capture board, EVAL-CED1Z. Rev. B | Page 28 of 32 AD7949 OUTLINE DIMENSIONS 4.00 BSC SQ 0.60 MAX 15 16 20 1 0.60 MAX PIN 1 INDICATOR 2.65 2.50 SQ 2.35 5 PIN 1 INDICATOR 3.75 BSC SQ 0.50 BSC EXPOSED PAD (BOTTOM VIEW) 10 6 TOP VIEW 0.80 MAX 0.65 TYP 0.50 0.40 0.30 11 0.25 MIN 1.00 0.85 0.80 SEATING PLANE 12° MAX COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1 Figure 43. 20-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 4 mm × 4 mm Body, Very Thin Quad (CP-20-4) Dimensions shown in millimeters ORDERING GUIDE Model AD7949BCPZ1 AD7949BCPZRL71 EVAL-AD7949EDZ1 EVAL-CED1Z1, 2 1 2 Temperature Range –40°C to +85°C –40°C to +85°C Package Description 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ Evaluation Board Controller Board Package Option CP-20-4 CP-20-4 090408-B 0.30 0.23 0.18 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Ordering Quantity Tray, 490 Reel, 1,500 Z = RoHS Compliant Part. This controller board allows a PC to control and communicate with all Analog Devices evaluation boards whose model numbers end in ED. Rev. B | Page 29 of 32 AD7949 NOTES Rev. B | Page 30 of 32 AD7949 NOTES Rev. B | Page 31 of 32 AD7949 NOTES ©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07351-0-5/09(B) Rev. B | Page 32 of 32