14-Bit, 1 MSPS, Unipolar/Bipolar
Programmable Input PulSAR® ADC
AD7951
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
Process control
Medical instruments
High speed data acquisition
Digital signal processing
Instrumentation
Spectrum analysis
ATE
AGND
AVDD
SWITCHED
CAP DAC
IN–
The AD7951 is a 14-bit, charge redistribution, successive
approximation register (SAR) architecture analog-to-digital
converter (ADC) fabricated on Analog Devices, Inc.’s iCMOS
high voltage process. The device is configured through hardware or
via a dedicated write only serial configuration port for input
range and operating mode. The AD7951 contains a high speed
14-bit sampling ADC, an internal conversion clock, an internal
reference (and buffer), error correction circuits, and both serial
and parallel system interface ports. A falling edge on CNVST
samples the analog input on IN+ with respect to a ground
sense, IN−. The AD7951 features four different analog input
ranges and three different sampling modes: warp mode for the
fastest throughput, normal mode for the fastest asynchronous
throughput, and impulse mode where power is scaled with
throughput. Operation is specified from −40°C to +85°C.
OGND
SERIAL
CONFIGURATION
14
PORT
PDBUF
IN+
OVDD
SERIAL DATA
PORT
REF
PDREF
DGND
AD7951
REF
AMP
D[13:0]
SER/PAR
BYTESWAP
CLOCK
CNVST
PARALLEL
INTERFACE
OB/2C
BUSY
PD
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
RESET
RD
CS
WARP IMPULSE BIPOLAR TEN
Figure 1.
Table 1. 48-Lead 14-/16-/18-Bit PulSAR Selection
Type
Pseudo
Differential
True Bipolar
GENERAL DESCRIPTION
Rev. B
TEMP REFBUFIN REF REFGND VCC VEE DVDD
06396-001
Multiple pins/software programmable input ranges:
5 V, 10 V, ±5 V, ±10 V
Pins or serial SPI® compatible input ranges/mode selection
Throughput
1 MSPS (warp mode)
800 kSPS (normal mode)
670 kSPS (impulse mode)
14-bit resolution with no missing codes
INL: ±0.3 LSB typ, ±1 LSB max (±61 ppm of FSR)
SNR: 85 dB @ 2 kHz
iCMOS® process technology
5 V internal reference: typical drift 3 ppm/°C; TEMP output
No pipeline delay (SAR architecture)
Parallel (14- or 8-bit bus) and serial 5 V/3.3 V interface
SPI-/QSPI™-/MICROWIRE™-/DSP-compatible
Power dissipation:
10 mW @ 100 kSPS
235 mW @ 1 MSPS
48-lead LQFP and LFCSP (7 mm × 7 mm) packages
100 kSPS to
250 kSPS
AD7651
AD7660
AD7661
AD7610
AD7663
500 kSPS to
570 kSPS
AD7650
AD7652
AD7664
AD7666
AD7665
570 kSPS to
1000 kSPS
AD7653
AD7667
>1000
kSPS
AD7951
True
Differential
AD7675
AD7676
AD7612
AD7671
AD7677
18-Bit, True
Differential
Multichannel/
Simultaneous
AD7678
AD7679
AD7674
AD7621
AD7622
AD7623
AD7641
AD7643
AD7654
AD7655
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Technical Support
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AD7951
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog Inputs.............................................................................. 20
Applications ....................................................................................... 1
Voltage Reference Input/Output .............................................. 21
General Description ......................................................................... 1
Power Supplies ............................................................................ 22
Functional Block Diagram .............................................................. 1
Conversion Control ................................................................... 23
Revision History ............................................................................... 2
Interfaces.......................................................................................... 24
Specifications..................................................................................... 3
Digital Interface .......................................................................... 24
Timing Specifications .................................................................. 5
Parallel Interface ......................................................................... 24
Absolute Maximum Ratings ............................................................ 7
Serial Interface ............................................................................ 25
ESD Caution .................................................................................. 7
Master Serial Interface ............................................................... 25
Pin Configuration and Function Descriptions ............................. 8
Slave Serial Interface .................................................................. 27
Typical Performance Characteristics ........................................... 12
Hardware Configuration ........................................................... 29
Terminology .................................................................................... 16
Software Configuration ............................................................. 29
Theory of Operation ...................................................................... 17
Microprocessor Interfacing ....................................................... 30
Overview...................................................................................... 17
Application Information ................................................................ 31
Converter Operation .................................................................. 17
Layout Guidelines....................................................................... 31
Modes of Operation ................................................................... 18
Outline Dimensions ....................................................................... 32
Transfer Functions...................................................................... 18
Ordering Guide .......................................................................... 32
Typical Connection Diagram.................................................... 19
REVISION HISTORY
5/15—Rev. A to Rev. B
Change to Acquisition Time Parameter, Table 3 .......................... 5
Deleted Evaluating Performance Section .................................... 31
Changes to Ordering Guide .......................................................... 32
12/12—Rev. 0 to Rev. A
Added Exposed Pad Note ................................................................ 8
Changes to Power Sequencing Section ........................................ 23
Updated Outline Dimensions ....................................................... 32
Changes to Ordering Guide .......................................................... 32
10/06—Revision 0: Initial Version
Rev. B | Page 2 of 32
Data Sheet
AD7951
SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range, VIN
Analog Input CMRR
Input Current
Input Impedance
THROUGHPUT SPEED
Complete Cycle
Throughput Rate
Time Between Conversions
Complete Cycle
Throughput Rate
Complete Cycle
Throughput Rate
DC ACCURACY
Integral Linearity Error2
No Missing Codes2
Differential Linearity Error2
Transition Noise
Zero Error (Unipolar or Bipolar)
Zero Error Temperature Drift
Full-Scale Error (Unipolar or Bipolar)
Full-Scale Error Temperature Drift
Power Supply Sensitivity
AC ACCURACY
Dynamic Range
Signal-to-Noise Ratio
Signal-to-(Noise + Distortion) (SINAD)
Total Harmonic Distortion
Spurious-Free Dynamic Range
–3 dB Input Bandwidth
Aperture Delay
Aperture Jitter
Transient Response
INTERNAL REFERENCE
Output Voltage
Temperature Drift
Line Regulation
Long-Term Drift
Turn-On Settling Time
Conditions/Comments
Min
14
VIN+ − VIN− = 0 V to 5 V
VIN+ − VIN− = 0 V to 10 V
VIN+ − VIN− = ±5 V
VIN+ − VIN− = ±10 V
VIN− to AGND
fIN = 100 kHz
VIN = ±5 V, ±10 V @ 1 MSPS
See the Analog Inputs section
−0.1
−0.1
−5.1
−10.1
−0.1
In warp mode
In warp mode
In warp mode
In normal mode
In normal mode
In impulse mode
In impulse mode
Typ
Max
Unit
Bits
+5.1
+10.1
+5.1
+10.1
+0.1
V
V
V
V
V
dB
µA
1
1
1
1.25
800
1.49
670
μs
MSPS
ms
μs
kSPS
μs
kSPS
+1
LSB3
Bits
LSB
LSB
LSB
ppm/°C
LSB
ppm/°C
LSB
75
3001
1
0
0
−1
14
−1
±0.3
+1
0.55
−15
+15
±1
−20
AVDD = 5 V ± 5%
fIN = 2 kHz, −60 dB
fIN = 2 kHz
fIN = 20 kHz
fIN = 2 kHz
fIN = 2 kHz
fIN = 2 kHz
VIN = 0 V to 5 V
Full-scale step
PDREF = PDBUF = low
REF @ 25°C
–40°C to +85°C
AVDD = 5 V ± 5%
1000 hours
CREF = 22 µF
Rev. B | Page 3 of 32
+20
±1
±0.8
84.5
84.5
83
85.5
85.5
85.5
85.4
−105
102
45
2
5
500
4.965
5.000
±3
±15
50
10
5.035
dB4
dB
dB
dB
dB
dB
MHz
ns
ps rms
ns
V
ppm/°C
ppm/V
ppm
ms
AD7951
Parameter
REFERENCE BUFFER
REFBUFIN Input Voltage Range
EXTERNAL REFERENCE
Voltage Range
Current Drain
TEMPERATURE PIN
Voltage Output
Temperature Sensitivity
Output Resistance
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
IIH
DIGITAL OUTPUTS
Data Format
Pipeline Delay5
VOL
VOH
POWER SUPPLIES
Specified Performance
AVDD
DVDD
OVDD
VCC
VEE
Operating Current7, 8
AVDD
With Internal Reference
With Internal Reference Disabled
DVDD
OVDD
VCC
VEE
Power Dissipation
With Internal Reference
With Internal Reference Disabled
In Power-Down Mode9
TEMPERATURE RANGE10
Specified Performance
Data Sheet
Conditions/Comments
PDREF = high
PDREF = PDBUF = high
REF
1 MSPS throughput
Min
Typ
Max
Unit
2.4
2.5
2.6
V
4.75
5
200
AVDD + 0.1
V
µA
@ 25°C
311
1
4.33
−0.3
2.1
−1
−1
mV
mV/°C
kΩ
+0.6
OVDD + 0.3
+1
+1
V
V
µA
µA
0.4
V
V
5.25
5.25
5.25
15.75
0
V
V
V
V
V
Parallel or serial 14-bit
ISINK = 500 µA
ISOURCE = –500 µA
OVDD − 0.6
4.756
4.75
2.7
7
−15.75
5
5
15
−15
@ 1 MSPS throughput
20
18.5
7
0.5
4
3
2
VCC = 15 V, with internal reference buffer
VCC = 15 V
VEE = −15 V
@ 1 MSPS throughput
PDREF = PDBUF = low
PDREF = PDBUF = high
PD = high
TMIN to TMAX
235
215
10
−40
mA
mA
mA
mA
mA
mA
mA
260
240
mW
mW
µW
+85
°C
With VIN = 0 V to 5 V or 0 V to 10 V ranges, the input current is typically 100 μA. In all input ranges, the input current scales with throughput. See the Analog Inputs section.
Linearity is tested using endpoints, not best fit. All linearity is tested with an external 5 V reference.
3
LSB means least significant bit. All specifications in LSB do not include the error contributed by the reference.
4
All specifications in dB are referred to a full-scale range input, FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
5
Conversion results are available immediately after completed conversion.
6
4.75 V or VREF – 0.1 V, whichever is larger.
7
Tested in parallel reading mode.
8
With internal reference, PDREF = PDBUF = low; with internal reference disabled, PDREF = PDBUF = high. With internal reference buffer, PDBUF = low.
9
With all digital inputs forced to OVDD.
10
Consult sales for extended temperature range.
1
2
Rev. B | Page 4 of 32
Data Sheet
AD7951
TIMING SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
CONVERSION AND RESET (See Figure 33 and Figure 34)
Convert Pulse Width
Time Between Conversions
Warp Mode/Normal Mode/Impulse Mode1
CNVST Low to BUSY High Delay
BUSY High All Modes (Except Master Serial Read After Convert)
Warp Mode/Normal Mode/Impulse Mode
Aperture Delay
End of Conversion to BUSY Low Delay
Conversion Time
Warp Mode/Normal Mode/Impulse Mode
Acquisition Time
Warp Mode/Normal Mode/Impulse Mode
RESET Pulse Width
PARALLEL INTERFACE MODES (See Figure 35 and Figure 37)
CNVST Low to DATA Valid Delay
Warp Mode/Normal Mode/Impulse Mode
DATA Valid to BUSY Low Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
MASTER SERIAL INTERFACE MODES2 (See Figure 39 and Figure 40)
CS Low to SYNC Valid Delay
CS Low to Internal SDCLK Valid Delay2
CS Low to SDOUT Delay
CNVST Low to SYNC Delay, Read During Convert
Warp Mode/Normal Mode/Impulse Mode
SYNC Asserted to SDCLK First Edge Delay
Internal SDCLK Period3
Internal SDCLK High3
Internal SDCLK Low3
SDOUT Valid Setup Time3
SDOUT Valid Hold Time3
SDCLK Last Edge to SYNC Delay3
CS High to SYNC High-Z
CS High to Internal SDCLK High-Z
CS High to SDOUT High-Z
BUSY High in Master Serial Read After Convert3
CNVST Low to SYNC Delay, Read After Convert
Warp Mode/Normal Mode/Impulse Mode
SYNC Deasserted to BUSY Low Delay
Symbol
Min
t1
t2
10
Typ
Max
ns
1/1.25/1.49
t3
t4
t5
t6
t7
Unit
35
μs
ns
850/1100/1350
ns
ns
ns
850/1100/1350
ns
2
10
t8
t9
148
10
ns
ns
t10
850/1100/1350
t11
t12
t13
40
15
ns
ns
ns
ns
10
10
10
ns
ns
ns
20
2
t14
t15
t16
t17
50/290/530
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
Rev. B | Page 5 of 32
3
30
15
10
4
5
5
45
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
See Table 4
710/950/1190
25
ns
ns
AD7951
Data Sheet
Parameter
SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES2
(See Figure 42, Figure 43, and Figure 45)
External SDCLK, SCCLK Setup Time
External SDCLK Active Edge to SDOUT Delay
SDIN/SCIN Setup Time
SDIN/SCIN Hold Time
External SDCLK/SCCLK Period
External SDCLK/SCCLK High
External SDCLK/SCCLK Low
Symbol
Min
t31
t32
t33
t34
t35
t36
t37
5
2
5
5
25
10
10
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
18
In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time.
In serial interface modes, the SDSYNC, SDSCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
3
In serial master read during convert mode. See Table 4 for serial master read after convert mode.
1
2
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1]
DIVSCLK[0]
SYNC to SDCLK First Edge Delay Minimum
Internal SDCLK Period Minimum
Internal SDCLK Period Maximum
Internal SDCLK High Minimum
Internal SDCLK Low Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SDCLK Last Edge to SYNC Delay Minimum
BUSY High Width Maximum
Warp Mode
Normal Mode
Impulse Mode
1.6mA
0
0
3
30
45
12
10
4
5
5
0
1
20
60
90
30
25
20
8
7
1
0
20
120
180
60
55
20
35
35
1
1
20
240
360
120
115
20
90
90
Unit
ns
ns
ns
ns
ns
ns
ns
ns
1.60
1.85
2.10
2.35
2.60
2.85
3.75
4.00
4.25
6.75
7.00
7.25
µs
µs
µs
IOL
1.4V
2V
CL
60pF
0.8V
tDELAY
IOH
NOTES
1. IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT ARE DEFINED WITH A MAXIMUM LOAD
CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
tDELAY
2V
0.8V
2V
0.8V
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SCLK Outputs, CL = 10 pF
Figure 3. Voltage Reference Levels for Timing
Rev. B | Page 6 of 32
06396-003
500µA
06396-002
TO OUTPUT
PIN
Symbol
t18
t19
t19
t20
t21
t22
t23
t24
t28
Data Sheet
AD7951
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Analog Inputs/Outputs
IN+1, IN−1 to AGND
REF, REFBUFIN, TEMP,
REFGND to AGND
Ground Voltage Differences
AGND, DGND, OGND
Supply Voltages
AVDD, DVDD, OVDD
AVDD to DVDD, AVDD to OVDD
DVDD to OVDD
VCC to AGND, DGND
VEE to GND
Digital Inputs
PDREF, PDBUF2
Internal Power Dissipation3
Internal Power Dissipation4
Junction Temperature
Storage Temperature Range
Rating
VEE − 0.3 V to VCC + 0.3 V
AVDD + 0.3 V to
AGND − 0.3 V
±0.3 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
−0.3 V to +7 V
±7 V
±7 V
–0.3 V to +16.5 V
+0.3 V to −16.5 V
−0.3 V to OVDD + 0.3 V
±20 mA
700 mW
2.5 W
125°C
−65°C to +125°C
See the Analog Inputs section.
See the Voltage Reference Input section.
3
Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W,
θJC = 30°C/W.
4
Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W.
1
2
Rev. B | Page 7 of 32
AD7951
Data Sheet
48 47 46 45 44 43 42
REF
IN–
REFGND
VCC
VEE
IN+
AGND
AVDD
TEMP
REFBUFIN
PDREF
PDBUF
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
41 40 39 38 37
AGND 1
36
BIPOLAR
35
CNVST
3
34
PD
4
33
RESET
32
CS
31
RD
30
TEN
8
29
BUSY
NC 9
28
D13/SCCS
NC 10
27
D12/SCCLK
D0/DIVSCLK[0] 11
26
D11/SCIN
D1/DIVSCLK[1] 12
25
D10/HW/SW
AVDD
2
AGND
BYTESWAP
PIN 1
OB/2C 5
WARP
AD7951
6
TOP VIEW
(Not to Scale)
IMPULSE 7
SER/PAR
NOTES
1. NC = NO CONNECT.
2. FOR THE LEAD FRAME CHIP SCALE PACKAGE (LFCSP), THE EXPOSED
PAD SHOULD BE CONNECTED TO VEE. THIS CONNECTION IS NOT
REQUIRED TO MEET THE ELECTRICAL PERFORMANCES.
06396-004
D9/RDERROR
D8/SYNC
D7/SDCLK
DGND
D6/SDOUT
DVDD
OVDD
OGND
D5/RDC/SDIN
D4/INVSCLK
D2/EXT/INT
D3/INVSYNC
13 14 15 16 17 18 19 20 21 22 23 24
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1, 3, 42
Mnemonic
AGND
Type1
P
2, 44
4
AVDD
BYTESWAP
P
DI
5
OB/2C
DI2
6
WARP
DI2
7
IMPULSE
DI2
8
SER/PAR
DI
9, 10
NC
DO
Description
Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be
referenced to AGND and should be connected to the analog ground plane of the system. In addition,
the AGND, DGND, and OGND voltages should be at the same potential.
Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors.
Parallel Mode Selection (8-Bit/14-Bit). When high, the LSB is output on D[15:8] and the MSB is output
on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8].
Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary.
When low, the MSB is inverted resulting in a twos complement output from its internal shift register.
Conversion Mode Selection. Used in conjunction with the IMPULSE input per the following:
Conversion Mode WARP
IMPULSE
Normal
Low
Low
Impulse
Low
High
Warp
High
Low
Normal
High
High
See the Modes of Operation section for a more detailed description.
Conversion Mode Selection. See the WARP pin description in the previous row of this table. See the
Modes of Operation section for a more detailed description.
Serial/Parallel Selection Input.
When SER/PAR = low, the parallel mode is selected.
When SER/PAR = high, the serial modes are selected. Some bits of the data bus are used as a serial port
and the remaining data bits are high impedance outputs.
No Connect. Do not connect.
Rev. B | Page 8 of 32
Data Sheet
AD7951
Pin No.
11, 12
Mnemonic
D[0:1] or
DIVSCLK[0:1]
Type1
DI/O
13
D2 or
EXT/INT
DI/O
14
D3 or
INVSYNC
DI/O
15
D4 or
INVSCLK
DI/O
16
D5 or
RDC or
DI/O
SDIN
17
OGND
P
18
OVDD
P
19
DVDD
P
20
DGND
P
21
D6 or
SDOUT
DO
22
D7 or
SDCLK
DI/O
Description
In parallel mode, these outputs are used as Bit 0 and Bit 1 of the parallel port data output bus.
Serial Data Division Clock Selection. In serial master read after convert mode (SER/PAR = high,
EXT/INT = low, RDC/SDIN = low) these inputs can be used to slow down the internally generated serial
data clock that clocks the data output. In other serial modes, these pins are high impedance outputs.
In parallel mode, this output is used as Bit 2 of the parallel port data output bus.
Serial Data Clock Source Select. In serial mode, this input is used to select the internally generated
(master) or external (slave) serial data clock for the AD7951 output data.
When EXT/INT = low, master mode; the internal serial data clock is selected on SDCLK output.
When EXT/INT = high, slave mode; the output data is synchronized to an external clock signal (gated
by CS) connected to the SDCLK input.
In parallel mode, this output is used as Bit 3 of the parallel port data output bus.
Serial Data Invert Sync Select. In serial master mode (SER/PAR = high, EXT/INT = low). This input is used
to select the active state of the SYNC signal.
When INVSYNC = low, SYNC is active high.
When INVSYNC = high, SYNC is active low.
In parallel mode, this output is used as Bit 4 of the parallel port data output bus.
In all serial modes, invert SDCLK/SCCLK select. This input is used to invert both SDCLK and SCCLK.
When INVSCLK = low, the rising edge of SDCLK/SCCLK are used.
When INVSCLK = high, the falling edge of SDCLK/SCCLK are used.
In parallel mode, this output is used as Bit 5 of the parallel port data output bus.
Serial Data Read During Convert. In serial master mode (SER/PAR = high, EXT/INT = low) RDC is used to
select the read mode. Refer to the Master Serial Interface section.
When RDC = low, the current result is read after conversion. Note the maximum throughput is not
attainable in this mode.
When RDC = high, the previous conversion result is read during the current conversion.
Serial Data In. In serial slave mode (SER/PAR = high EXT/INT = high) SDIN can be used as a data input to
daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data
level on SDIN is output on SDOUT with a delay of 16 SDCLK periods after the initiation of the read sequence.
Input/Output Interface Digital Power Ground. Ground reference point for digital outputs. Should be
connected to the system digital ground ideally at the same potential as AGND and DGND.
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface
2.5 V, 3 V, or 5 V and decoupled with 10 μF and 100 nF capacitors.
Digital Power. Nominally at 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. Can be
supplied from AVDD.
Digital Power Ground. Ground reference point for digital outputs. Should be connected to system
digital ground ideally at the same potential as AGND and OGND.
In parallel mode, this output is used as Bit 6 of the parallel port data output bus.
Serial Data output. In all serial modes this pin is used as the serial data output synchronized to SDCLK.
Conversion results are stored in an on-chip register. The AD7951 provides the conversion result, MSB
first, from its internal shift register. The data format is determined by the logic level of OB/2C.
When EXT/INT = low (master mode), SDOUT is valid on both edges of SDCLK.
When EXT/INT = high (slave mode):
When INVSCLK = low, SDOUT is updated on SDCLK rising edge.
When INVSCLK = high, SDOUT is updated on SDCLK falling edge.
In parallel mode, this output is used as Bit 7 of the parallel port data output bus.
Serial Data Clock. In all serial modes, this pin is used as the serial data clock input or output, dependent
on the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends on
the logic state of the INVSCLK pin.
Rev. B | Page 9 of 32
AD7951
Data Sheet
Pin No.
23
Mnemonic
D8 or
SYNC
Type1
DO
24
D9 or
RDERROR
DO
25
D10 or
HW/SW
DI/O
26
D11 or
SCIN
DI/O
27
D12 or
SCCLK
DI/O
28
D13 or
SCCS
DI/O
29
BUSY
DO
30
TEN
DI2
31
32
RD
CS
DI
DI
33
RESET
DI
34
PD
DI2
35
CNVST
DI
36
BIPOLAR
DI2
Description
In parallel mode, this output is used as Bit 8 of the parallel port data output bus.
Serial Data Frame Synchronization. In serial master mode (SER/PAR = high, EXT/INT= low), this output
is used as a digital output frame synchronization for use with the internal data clock.
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while the
SDOUT output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while the
SDOUT output is valid.
In parallel mode, this output is used as Bit 9 of the parallel port data output bus.
Serial Data Read Error. In serial slave mode (SER/PAR = high, EXT/INT = high), this output is used as an
incomplete data read error flag. If a data read is started and not completed when the current
conversion is complete, the current data is lost and RDERROR is pulsed high.
In parallel mode, this output is used as Bit 10 of the parallel port data output bus.
Serial Configuration Hardware/Software Select. In serial mode, this input is used to configure
the AD7951 by hardware or software. See the Hardware Configuration section and Software
Configuration section.
When HW/SW = low, the AD7951 is configured through software using the serial configuration register.
When HW/SW = high, the AD7951 is configured through dedicated hardware input pins.
In parallel mode, this output is used as Bit 11 of the parallel port data output bus.
Serial Configuration Data Input. In serial software configuration mode (SER/PAR = high, HW/SW = low)
this input is used to serially write in, MSB first, the configuration data into the serial configuration
register. The data on this input is latched with SCCLK. See the Software Configuration section.
In parallel mode, this output is used as Bit 12 of the parallel port data output bus.
Serial Configuration Clock. In serial software configuration mode (SER/PAR = high, HW/SW = low) this
input is used to clock in the data on SCIN. The active edge where the data SCIN is updated depends on
the logic state of the INVSCLK pin. See the Software Configuration section.
In parallel mode, this output is used as Bit 13 of the parallel port data output bus.
Serial Configuration Chip Select. In serial software configuration mode (SER/PAR = high, HW/SW = low)
this input enables the serial configuration port. See the Software Configuration section.
Busy Output. Transitions high when a conversion is started, and remains high until the conversion
is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be
used as a data ready clock signal. Note that in master read after convert mode (SER/PAR = high,
EXT/INT = low, RDC = low), the busy time changes according to Table 4.
Input Range Select. Used in conjunction with BIPOLAR per the following:
Input Range BIPOLAR TEN
0 V to 5 V
Low
Low
0 V to 10 V
Low
High
±5 V
High
Low
±10 V
High
High
Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.
Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is
also used to gate the external clock in slave serial mode (not used for serial programmable port).
Reset Input. When high, reset the AD7951. Current conversion, if any, is aborted. The falling edge of
RESET resets the data outputs to all zeros (with OB/2C = high) and clears the configuration register. See
the Digital Interface section. If not used, this pin can be tied to OGND.
Power-Down Input. When PD = high, powers down the ADC. Power consumption is reduced and
conversions are inhibited after the current one is completed. The digital interface remains active
during power-down.
Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and
initiates a conversion.
Input Range Select. See description for Pin 30.
Rev. B | Page 10 of 32
Data Sheet
AD7951
Pin No.
37
Mnemonic
REF
Type1
AI/O
38
39
40
41
43
45
REFGND
IN−
VCC
VEE
IN+
TEMP
AI
AI
P
P
AI
AO
46
REFBUFIN
AI
47
PDREF
DI
48
PDBUF
DI
49
EPAD3
NC
Description
Reference Input/Output. When PDREF/PDBUF = low, the internal reference and buffer are enabled,
producing 5 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled,
allowing an externally supplied voltage reference up to AVDD volts. Decoupling with at least a 22 μF is
required with or without the internal reference and buffer. See the Reference Decoupling section.
Reference Input Analog Ground. Connected to analog ground plane.
Analog Input Ground Sense. Should be connected to the analog ground plane or to a remote sense ground.
High Voltage Positive Supply. Normally +7 V to +15 V.
High Voltage Negative Supply. Normally 0 V to −15 V (0 V in unipolar ranges).
Analog Input. Referenced to IN−.
Temperature Sensor Analog Output. Enabled when the internal reference is turned on
(PDREF = PDBUF = low). See the Temperature Sensor section.
Reference Buffer Input. When using an external reference with the internal reference buffer
(PDBUF = low, PDREF = high), applying 2.5 V on this pin produces 5 V on the REF pin.
See the Voltage Reference Input section.
Internal Reference Power-Down Input.
When low, the internal reference is enabled.
When high, the internal reference is powered down, and an external reference must be used.
Internal Reference Buffer Power-Down Input.
When low, the buffer is enabled (must be low when using internal reference).
When high, the buffer is powered-down.
Exposed Pad. The exposed pad is not connected internally. It is recommended that the pad be
soldered to VEE.
AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.
In serial configuration mode (SER/PAR = high, HW/SW = low), this input is programmed with the serial configuration register and this pin is a don’t care. See the
Hardware Configuration section and Software Configuration section.
3
LFCSP_VQ package only.
1
2
Rev. B | Page 11 of 32
AD7951
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = DVDD = 5 V; OVDD = 5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; TA = 25°C.
1.0
1.0
POSITIVE INL = +0.15
NEGATIVE INL = –0.15
0.5
DNL (LSB)
0
–0.5
0
–0.5
0
12288
8192
4096
16384
CODE
–1.0
06396-005
–1.0
0
12288
16384
Figure 8. Differential Nonlinearity vs. Code
200
NEGATIVE INL
POSITIVE INL
NEGATIVE DNL
POSITIVE DNL
180
200
160
NUMBER OF UNITS
NUMBER OF UNITS
8192
CODE
Figure 5. Integral Nonlinearity vs. Code
250
4096
06396-008
INL (LSB)
0.5
POSITIVE DNL = +0.27
NEGATIVE DNL = –0.27
150
100
50
140
120
100
80
60
40
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
INL DISTRIBUTION (LSB)
1.0
0
–1.0
06396-006
–0.8
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
DNL DISTRIBUTION (LSB)
Figure 6. Integral Nonlinearity Distribution (239 Devices)
06396-009
20
0
–1.0
Figure 9. Differential Nonlinearity Distribution (239 Devices)
300000
140000
132052
261120
129068
120000
250000
100000
COUNTS
150000
80000
60000
100000
40000
50000
0
1FFF
0
2000
2001
0
2002
0
2003
CODE IN HEX
Figure 7. Histogram of 261,120 Conversions of a DC Input
at the Code Center
0
0
0
8192
8193
8194
8195
0
0
8196
8197
CODE IN HEX
Figure 10. Histogram of 261,120 Conversions of a DC Input
at the Code Transition
Rev. B | Page 12 of 32
06396-010
0
20000
06396-007
COUNTS
200000
Data Sheet
AD7951
SNR, SINAD REFERRED TO FULL SCALE (dB)
–20
AMPLITUDE (dB OF FULL SCALE)
86.5
fS = 1000kSPS
fIN = 19.94kHz
SNR = 85.4dB
THD = –107dB
SFDR = 116dB
SINAD = 85.4dB
–40
–60
–80
–100
–120
–140
0
300
200
100
500
400
FREQUENCY (kHz)
SNR
SINAD
85.5
85.0
–60
06396-011
–160
86.0
–50
–20
–30
–40
–10
0
INPUT LEVEL (dB)
Figure 11. FFT 20 kHz
06396-014
0
Figure 14. SNR and SINAD vs. Input Level (Referred to Full Scale)
14.5
88
–70
–80
14.3
86
120
110
SFDR
ENOB
13.9
82
–90
100
–100
THIRD
HARMONIC
–110
–120
1
10
06396-012
13.5
100
78
FREQUENCY (kHz)
70
–130
1
86.0
Figure 15. THD, Harmonics, and SFDR vs. Frequency
86.0
0V TO 5V
0V TO 10V
±5V
±10V
85.5
0V TO 5V
0V TO 10V
±5V
±10V
SINAD (dB)
85.5
85.0
84.5
85.0
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
125
Figure 13. SNR vs. Temperature
84.0
–55
–35
–15
5
25
45
65
85
TEMPERATURE (°C)
Figure 16. SINAD vs. Temperature
Rev. B | Page 13 of 32
105
125
06396-016
84.5
06396-013
84.0
–55
60
100
10
FREQUENCY (kHz)
Figure 12. SNR, SINAD, and ENOB vs. Frequency
SNR (dB)
80
SECOND
HARMONIC
13.7
80
90
THD
SFDR (dB)
14.1
ENOB (Bits)
SINAD
84
06396-015
THD, HARMONICS (dB)
SNR, SINAD (dB)
SNR
AD7951
–96
Data Sheet
124
0V TO 5V
0V TO 10V
±5V
±10V
–100
0V TO 5V
0V TO 10V
±5V
±10V
122
120
118
SFDR (dB)
THD (dB)
–104
–108
116
114
112
–112
110
–116
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
106
–55
06396-017
–120
–55
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
Figure 17. THD vs. Temperature
Figure 20. SFDR vs. Temperature (Excludes Harmonics)
1.5
5.008
ZERO ERROR
POSITIVE FS ERROR
NEGATIVE FS ERROR
1.0
5.006
5.004
0
5.002
–0.5
5.000
–1.0
4.998
–1.5
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
4.996
–55
Figure 18. Zero Error, Positive and Negative Full Scale vs. Temperature
60
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
06396-021
VREF (V)
0.5
06396-018
ZERO ERROR, FULL SCALE ERROR (LSB)
–35
06396-020
108
Figure 21. Typical Reference Voltage Output vs. Temperature (3 Devices)
100000
AVDD, WARP/NORMAL
10000
DVDD, ALL MODES
OPERATING CURRENTS (µA)
NUMBER OF UNITS
50
40
30
20
1000
100
10 AVDD, IMPULSE
VCC +15V
VEE –15V
ALL MODES
1
0.1
OVDD, ALL MODES
10
0.01
1
2
3
4
5
6
REFERENCE DRIFT (ppm/°C)
7
8
0.001
10
06396-019
0
100
1000
10000
100000
SAMPLING RATE (SPS)
Figure 19. Reference Voltage Temperature Coefficient Distribution (247 Devices)
Rev. B | Page 14 of 32
Figure 22. Operating Currents vs. Sample Rate
1000000
06396-022
PDREF = PDBUF = HIGH
0
Data Sheet
AD7951
50
PD = PDBUF = PDREF = HIGH
VEE = –15V
VCC = +15V
600
DVDD
OVDD
AVDD
500
OVDD = 2.7V @ 85°C
45
OVDD = 2.7V @ 25°C
40
t12 DELAY (ns)
35
400
300
30
25
OVDD = 5V @ 85°C
20
OVDD = 5V @ 25°C
15
200
10
100
0
–35
–15
5
25
45
65
85
105
TEMPERATURE (°C)
Figure 23. Power-Down Operating Currents vs. Temperature
0
50
100
150
CL (pF)
Figure 24. Typical Delay vs. Load Capacitance CL
Rev. B | Page 15 of 32
200
06396-024
0
–55
5
06396-023
POWER–DOWN OPERATING CURRENTS (nA)
700
AD7951
Data Sheet
TERMINOLOGY
Least Significant Bit (LSB)
The least significant bit, or LSB, is the smallest increment that
can be represented by a converter. For an analog-to-digital
converter with N bits of resolution, the LSB expressed in volts is
LSB (V) =
VINp − p (max)
2
N
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full-scale through positive fullscale. The point used as negative full-scale occurs a ½ LSB
before the first code transition. Positive full-scale is defined as a
level 1½ LSBs beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Bipolar Zero Error
The difference between the ideal midscale input voltage (0 V)
and the actual voltage producing the midscale output code.
Unipolar Offset Error
The first transition should occur at a level ½ LSB above analog
ground. The unipolar offset error is the deviation of the actual
transition from that point.
Full-Scale Error
The last transition (from 111…10 to 111…11) should occur for
an analog voltage 1½ LSB below the nominal full-scale. The
full-scale error is the deviation in LSB (or % of full-scale range)
of the actual level of the last transition from the ideal level and
includes the effect of the offset error. Closely related is the gain
error (also in LSB or % of full-scale range), which does not
include the effects of the offset error.
Dynamic Range
Dynamic range is the ratio of the rms value of the full-scale to
the rms noise measured for an input typically at −60 dB. The
value for dynamic range is expressed in decibels.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD and is expressed in bits by
ENOB = [(SINADdB − 1.76)/6.02]
Aperture Delay
Aperture delay is a measure of the acquisition performance
measured from the falling edge of the CNVST input to when
the input signal is held for a conversion.
Transient Response
The time required for the AD7951 to achieve its rated accuracy
after a full-scale step function is applied to its input.
Reference Voltage Temperature Coefficient
Reference voltage temperature coefficient is derived from the
typical shift of output voltage at 25°C on a sample of parts at the
maximum and minimum reference output voltage (VREF)
measured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C as
TCVREF (ppm/°C) =
VREF ( Max ) – VREF ( Min)
VREF (25°C) × (TMAX – TMIN )
× 106
where:
VREF (Max) = maximum VREF at TMIN, T(25°C), or TMAX.
VREF (Min) = minimum VREF at TMIN, T(25°C), or TMAX.
VREF (25°C) = VREF at 25°C.
TMAX = +85°C.
TMIN = –40°C.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Rev. B | Page 16 of 32
Data Sheet
AD7951
THEORY OF OPERATION
IN+
REF
REFGND
MSB
8,192C
4,096C
LSB
4C
2C
C
SWA
SWITCHES
CONTROL
C
BUSY
COMP
CONTROL
LOGIC
IN–
SWB
CNVST
06396-025
OUTPUT
CODE
16,384C
Figure 25. ADC Simplified Schematic
OVERVIEW
CONVERTER OPERATION
The AD7951 is a very fast, low power, precise, 14-bit analog-todigital converter (ADC) using successive approximation capacitive
digital-to-analog (CDAC) converter architecture.
The AD7951 is a successive approximation ADC based on a
charge redistribution DAC. Figure 25 shows the simplified
schematic of the ADC. The CDAC consists of two identical
arrays of 16 binary weighted capacitors, which are connected to
the two comparator inputs.
The AD7951 can be configured at any time for one of four input
ranges and conversion mode with inputs in parallel and serial
hardware modes or by a dedicated write only, SPI-compatible
interface via a configuration register in serial software mode.
The AD7951 uses Analog Devices’ patented iCMOS high
voltage process to accommodate 0 to 5 V, 0 to 10 V, ±5 V, and
±10 V input ranges without the use of conventional thin films.
Only one acquisition cycle, t8, is required for the inputs to latch to
the correct configuration. Resetting or power cycling is not
required for reconfiguring the ADC.
The AD7951 features different modes to optimize performance
according to the applications. It is capable of converting
1,000,000 samples per second (1 MSPS) in warp mode, 800 kSPS
in normal mode, and 670 kSPS in impulse mode.
The AD7951 provides the user with an on-chip track-and-hold,
successive approximation ADC that does not exhibit any pipeline or latency, making it ideal for multiple, multiplexed channel
applications.
For unipolar input ranges, the AD7951 typically requires three
supplies; VCC, AVDD (which can supply DVDD), and OVDD
which can be interfaced to either 5 V, 3.3 V, or 2.5 V digital
logic. For bipolar input ranges, the AD7951 requires the use of
the additional VEE supply.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to AGND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on IN+ and IN− inputs. A conversion
phase is initiated once the acquisition phase is complete and the
CNVST input goes low. When the conversion phase begins,
SW+ and SW− are opened first. The two capacitor arrays are
then disconnected from the inputs and connected to the REFGND
input. Therefore, the differential voltage between the inputs
(IN+ and IN−) captured at the end of the acquisition phase is
applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between REFGND and REF, the comparator input varies
by binary weighted voltage steps (VREF/2, VREF/4 through VREF/
16,384). The control logic toggles these switches, starting with
the MSB first, in order to bring the comparator back into a
balanced condition.
After the completion of this process, the control logic generates
the ADC output code and brings the BUSY output low.
The device is housed in Pb-free, 48-lead LQFP or tiny LFCSP
7 mm × 7 mm packages that combine space savings with
flexibility. In addition, the AD7951 can be configured as either a
parallel or a serial SPI-compatible interface.
Rev. B | Page 17 of 32
AD7951
Data Sheet
Impulse Mode
Warp Mode
Setting WARP = high and IMPULSE = low allows the fastest
conversion rate up to 1 MSPS. However, in this mode, the full
specified accuracy is guaranteed only when the time between
conversions does not exceed 1 ms. If the time between two
consecutive conversions is longer than 1 ms (after power-up),
the first conversion result should be ignored since in warp mode,
the ADC performs a background calibration during the SAR
conversion process. This calibration can drift if the time between
conversions exceeds 1 ms thus causing the first conversion to
appear offset. This mode makes the AD7951 ideal for applications
where both high accuracy and fast sample rate are required.
Normal Mode
Setting WARP = low and IMPULSE = high uses the lowest power
dissipation mode and allows power saving between conversions.
The maximum throughput in this mode is 670 kSPS and in this
mode, the ADC powers down circuits after conversion making
the AD7951 ideal for battery-powered applications.
TRANSFER FUNCTIONS
Using the OB/2C digital input or via the configuration register,
the AD7951 offers two output codings: straight binary and twos
complement. See Figure 26 and Table 7 for the ideal transfer
characteristic and digital output codes for the different analog
input ranges, VIN. Note that when using the configuration
register, the OB/2C input is a don’t care and should be tied to
either high or low.
111...111
111...110
111...101
000...010
000...001
000...000
–FSR
Setting WARP = IMPULSE = low or WARP = IMPULSE = high
allows the fastest mode (800 kSPS) without any limitation on
time between conversions. This mode makes the AD7951 ideal
for asynchronous applications such as data acquisition systems,
where both high accuracy and fast sample rate are required.
–FSR + 1 LSB
–FSR + 0.5 LSB
+FSR – 1 LSB
+FSR – 1.5 LSB
ANALOG INPUT
Figure 26. ADC Ideal Transfer Function
Table 7. Output Codes and Ideal Input Voltages
Description
FSR − 1 LSB
FSR − 2 LSB
Midscale + 1 LSB
Midscale
Midscale − 1 LSB
−FSR + 1 LSB
−FSR
1
2
VIN = 5 V
4.999695 V
4.999390 V
2.500305 V
2.5 V
2.499695 V
305.2 μV
0V
VIN = 10 V
9.999389 V
9.998779 V
5.000610 V
5.000000 V
4.999389 V
610.4 μV
0V
VREF = 5 V
VIN = ±5 V
+4.999389 V
+4.998779 V
+610.4 μV
0V
−610.4 μV
−4.999389 V
−5 V
VIN = ±10 V
+9.998779 V
+9.997558 V
+1.221 mV
0V
−1.221 mV
−9.998779 V
−10 V
This is also the code for overrange analog input (VIN+ − VIN− above VREF − VREFGND).
This is also the code for overrange analog input (VIN+ − VIN− below VREF − VREFGND).
Rev. B | Page 18 of 32
Digital Output Code
Straight Binary
Twos Complement
0x3FFF1
0x1FFF1
0x3FFE
0x1FFE
0x2001
0x0001
0x2000
0x0000
0x1FFF
0x3FFF
0x0001
0x2001
0x00002
0x20002
06396-026
The AD7951 features three modes of operation: warp, normal,
and impulse. Each of these modes is more suitable to specific
applications. The mode is configured with the input pins, WARP
and IMPULSE, or via the configuration register. See Table 6 for
the pin details and the Hardware Configuration section and
Software Configuration section for programming the mode
selection with either pins or configuration register. Note that
when using the configuration register, the WARP and IMPULSE
inputs are don’t cares and should be tied to either high or low.
ADC CODE (Straight Binary)
MODES OF OPERATION
Data Sheet
AD7951
TYPICAL CONNECTION DIAGRAM
Figure 27 shows a typical connection diagram for the AD7951 using the internal reference, serial data and serial configuration interfaces.
Different circuitry from that shown in Figure 27 is optional and is discussed in the following sections.
DIGITAL
SUPPLY (5V)
NOTE 5
DIGITAL
INTERFACE
SUPPLY
(2.5V, 3.3V, OR 5V)
10Ω
ANALOG
SUPPLY (5V)
100nF
10µF
10µF
AVDD
+7V TO +15.75V
SUPPLY
10µF
100nF
10µF
100nF
AGND
100nF
DGND
10µF
100nF
DVDD
OVDD
VCC
OGND
MICROCONVERTER/
MICROPROCESSOR/
DSP
BUSY
SDCLK
–7V TO –15.75V
SUPPLY
SERIAL
PORT 1
SDOUT
SCCLK
VEE
SERIAL
PORT 2
SCIN
NOTE 6
REF
CREF
22µF
NOTE 4
100nF
NOTE 3
SCCS
REFBUFIN
REFGND
CNVST
AD7951
50Ω
NOTE 7
D
OB/2C
NOTE 2
15Ω
IN+
OVDD
HW/SW
BIPOLAR
CC
2.7nF
TEN
WARP
ANALOG
INPUT–
IN–
NOTE 1
IMPULSE
NOTE 3
PDREF PDBUF
CLOCK
PD
RD
CS RESET
NOTES
1. SEE ANALOG INPUT SECTION. ANALOG INPUT(–) IS REFERENCED TO AGND ±0.1V.
2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT SECTION.
4. A 22µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (FOR EXAMPLE, PANASONIC ECJ4YB1A226M).
SEE VOLTAGE REFERENCE INPUT SECTION.
5. OPTION, SEE POWER SUPPLY SECTION.
6. THE VCC AND VEE SUPPLIES SHOULD BE VCC = [VIN(MAX) +2V] AND VEE = [VIN(MIN) –2V] FOR BIPOLAR INPUT RANGES.
FOR UNIPOLAR INPUT RANGES, VEE CAN BE 0V. SEE POWER SUPPLY SECTION.
7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION.
Figure 27. Typical Connection Diagram Shown with Serial Interface and Serial Programmable Port
Rev. B | Page 19 of 32
06396-027
ANALOG
INPUT+
U1
SER/PAR
AD7951
Data Sheet
Input Range Selection
In parallel mode and serial hardware mode, the input range is
selected by using the BIPOLAR (bipolar) and TEN (10 Volt
range) inputs. See Table 6 for pin details and the Hardware
Configuration section and Software Configuration section for
programming the mode selection with either pins or configuration
register. Note that when using the configuration register, the
BIPOLAR and TEN inputs are don’t cares and should be tied to
either high or low.
For instance, by using IN− to sense a remote signal ground,
ground potential differences between the sensor and the local
ADC ground are eliminated.
100
90
80
70
CMRR (dB)
ANALOG INPUTS
Input Structure
60
50
40
30
Figure 28 shows an equivalent circuit for the input structure of
the AD7951.
20
0
1
AVDD
VCC
10
100
1000
FREQUENCY (kHz)
D1
D3
D2
D4
RIN
10000
06396-029
10
0V TO 5V
RANGE ONLY
Figure 29. Analog Input CMRR vs. Frequency
CIN
CPIN
VEE
AGND
06396-028
IN+ OR IN–
Figure 28. AD7951 Simplified Analog Input
The four diodes, D1 to D4, provide ESD protection for the analog
inputs, IN+ and IN−. Care must be taken to ensure that the analog
input signal never exceeds the supply rails by more than 0.3 V,
because this causes the diodes to become forward-biased and to
start conducting current. These diodes can handle a forwardbiased current of 120 mA maximum. For instance, these conditions
could eventually occur when the input buffer’s U1 supplies are
different from AVDD, VCC, and VEE. In such a case, an input
buffer with a short-circuit current limitation can be used to protect
the part although most op amps’ short circuit current is
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