FEATURES
CONNECTION DIAGRAM
Low power replacement for Burr-Brown
OPA111, OPA121 op amps
Low noise
3.3 μV p-p maximum, 0.1 Hz to 10 Hz
11 nV/√Hz maximum at 10 kHz
0.6 fA/√Hz at 1 kHz
High dc accuracy
500 μV maximum offset voltage
10 μV/°C maximum drift
2 pA maximum input bias current
Low power: 1.5 mA maximum supply current
NC 1
8
NC
–IN 2
7
+VS
+IN 3
6
OUTPUT
–VS 4
5
NC
AD795
NC = NO CONNECT
00845-001
Data Sheet
Low Power, Low Noise
Precision FET Op Amp
AD795
Figure 1. 8-Lead SOIC (R) Package
APPLICATIONS
Low noise photodiode preamps
CT scanners
Precision l-to-V converters
GENERAL DESCRIPTION
The AD795 is a low noise, precision, FET input operational
amplifier. It offers both the low voltage noise and low offset
drift of a bipolar input op amp and the very low bias current of a
FET-input device. The 1014 Ω common-mode impedance
insures that input bias current is essentially independent of
common-mode voltage and supply voltage variations.
The AD795 has both excellent dc performance and a guaranteed
and tested maximum input voltage noise. It features 2 pA
maximum input bias current and 500 μV maximum offset
voltage, along with low supply current of 1.5 mA maximum.
Furthermore, the AD795 features a guaranteed low input noise
of 3.3 μV p-p (0.1 Hz to 10 Hz) and a 11 nV/√Hz maximum
noise level at 10 kHz. The AD795 has a fully specified and
tested input offset voltage drift of only 10 μV/°C maximum.
The AD795 is useful for many high input impedance, low noise
applications. The AD795 is rated over the commercial temperature range of 0°C to +70°C.
The AD795 is available in an 8-lead SOIC package.
50
SAMPLE SIZE = 570
PERCENTAGE OF UNITS
40
100
30
20
0
–5
1
10
100
1k
FREQUENCY (Hz)
10k
–4
–3
–2
–1
0
1
2
3
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
4
5
00845-003
10
10
00845-002
VOLTAGE NOISE SPECTRAL DENSITY (nV/ Hz)
1k
Figure 3. Typical Distribution of Average Input Offset Voltage Drift
Figure 2. Voltage Noise Spectral Density
Rev. D
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AD795
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Offset Nulling ............................................................................. 13
Applications ....................................................................................... 1
Connection Diagram ....................................................................... 1
AC Response with High Value Source and Feedback Resistance
........................................................................................................... 14
General Description ......................................................................... 1
Overload Issues ............................................................................... 15
Revision History ............................................................................... 2
Input Protection ......................................................................... 15
Specifications..................................................................................... 3
Preamplifier Applications.......................................................... 16
Absolute Maximum Ratings ............................................................ 5
Minimizing Noise Contributions ............................................. 16
Thermal Resistance ...................................................................... 5
Using a T Network ..................................................................... 17
ESD Caution .................................................................................. 5
A pH Probe Buffer Amplifier ................................................... 17
Typical Performance Characteristics ............................................. 6
Outline Dimensions ....................................................................... 18
Minimizing Input Current ............................................................ 11
Ordering Guide .......................................................................... 18
Circuit Board Notes........................................................................ 12
REVISION HISTORY
8/2019—Rev. C to Rev. D
Changes to Table 1 ............................................................................ 3
Changes to Ordering Guide .......................................................... 18
12/2009—Rev. B to Rev. C
Changes to Features Section and General Description Section . 1
Changes to Input Bias Current Parameter, Table 1 ...................... 3
Changes to Table 2 ............................................................................ 5
Added Thermal Resistance Section ............................................... 5
Added Table 3; Renumbered Sequentially .................................... 5
Changes to Minimizing Input Current Section .......................... 11
Changes to Circuit Board Notes Section and Figure 33 ............ 12
Changes to Input Protection Section ........................................... 15
Changes to Ordering Guide .......................................................... 18
10/2002—Rev. A to Rev. B
Deleted Plastic Mini-DIP (N) Package ............................ Universal
Edits to Features.................................................................................1
Edits to Specifications .......................................................................2
Edits to Absolute Maximum Ratings ..............................................3
Edits to Ordering Guide ...................................................................3
Edits to Circuit Board Notes ............................................................9
Edits to Figure 31 ...............................................................................9
Edits to Offset Nulling ................................................................... 10
Deleted Figure 34............................................................................ 10
Deleted Low Noise Op Amp Selection Tree ............................... 15
Updated Outline Dimensions ....................................................... 15
10/1992—Revision 0: Initial Version
Rev. D | Page 2 of 20
Data Sheet
AD795
SPECIFICATIONS
At +25°C and ±15 V dc, unless otherwise noted.
Table 1.
Parameter
INPUT OFFSET VOLTAGE 1
Initial Offset
Offset
vs. Temperature
vs. Supply (PSRR)
vs. Supply (PSRR)
INPUT BIAS CURRENT 2
Either Input
Either Input at TMAX = 70°C
Either Input
Offset Current
Offset Current at TMAX = 70°C
OPEN-LOOP GAIN
INPUT VOLTAGE NOISE
INPUT CURRENT NOISE
FREQUENCY RESPONSE
Unity Gain, Small Signal
Full Power Response
Slew Rate, Unity Gain
SETTLING TIME 3
To 0.1%
To 0.01%
Overload Recovery 4
Total Harmonic
Distortion
INPUT IMPEDANCE
Differential
Common Mode
INPUT VOLTAGE RANGE
Differential 5
Common-Mode Voltage
Over Maximum Operating Temperature
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Voltage
Current
Test Conditions/Comments
Min
AD795JRZ
Typ
86
84
TMIN − TMAX
TMIN − TMAX
VCM = 0 V
VCM = 0 V
VCM = +10 V
VCM = 0 V
VCM = 0 V
VO = ±10 V
RL ≥ 10 kΩ
RL ≥ 10 kΩ
0.1 Hz to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
f = 0.1 Hz to 10 Hz
f = 1 kHz
110
100
Max
Unit
100
300
3
110
100
500
1000
10
µV
µV
µV/°C
dB
dB
1
23
1
0.1
2
2
pA
pA
pA
pA
pA
120
108
1.0
20
12
11
9
13
0.6
1.0
3.3
50
40
17
11
dB
dB
µV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
fA p-p
fA/√Hz
G = −1
VO = 20 V p-p, RL = 2 kΩ
VO = 20 V p-p, RL = 2 kΩ
1.6
16
1
MHz
kHz
V/µs
10 V step
10 V step
50% overdrive
f = 1 kHz
R1 ≥ 10 kΩ, VO = 3 V rms
10
11
2
µs
µs
µs
−108
dB
VDIFF = ±1 V
1012||2
1014||2.2
Ω||pF
Ω||pF
±20
±11
V
V
V
dB
dB
±10
±10
90
86
VCM = ±10 V
TMIN − TMAX
RL ≥ 2 kΩ
TMIN − TMAX
VOUT = ±10 V
Short circuit
VS − 4
VS − 4
±5
Rev. D | Page 3 of 20
110
100
VS − 2.5
±10
±15
V
V
mA
mA
AD795
Parameter
POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
Data Sheet
Test Conditions/Comments
Min
AD795JRZ
Typ
Max
Unit
±18
1.5
V
V
mA
±15
±4
1.3
Input offset voltage specifications are guaranteed after 5 minutes of operation at TA = +25°C.
Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at TA = +25°C. For higher temperature, the current doubles every 10°C.
Gain = −1, R1 = 10 kΩ.
4
Defined as the time required for the amplifier’s output to return to normal operation after removal of a 50% overload from the amplifier input.
5
Defined as the maximum continuous voltage between the inputs such that neither input exceeds ±10 V from ground.
1
2
3
Rev. D | Page 4 of 20
Data Sheet
AD795
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage
Internal Power Dissipation (at TA = +25°C)
SOIC Package
Input Voltage
Input Current1
Output Short-Circuit Duration
Differential Input Voltage
Storage Temperature Range (R)
Operating Temperature Range
AD795J
1
Rating
±18 V
500 mW
±VS
±10 mA
Indefinite
+VS and −VS
−65°C to +125°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered on a 4-layer circuit board for surface-mount packages.
Table 3. Thermal Resistance
0°C to +70°C
Limit input current to 10 mA or less whenever the input signal exceeds the
power supply rail by 0.1 V.
Package Type
8-Lead SOIC
ESD CAUTION
Rev. D | Page 5 of 20
θJA
155
Unit
°C/W
AD795
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
20
1.00
0.95
INPUT BIAS CURRENT (pA)
15
+VIN
10
–VIN
5
0.90
0.85
0.80
0.75
0.70
0
5
10
SUPPLY VOLTAGE (±V)
15
20
0.60
0
5
Figure 4. Common-Mode Voltage Range vs. Supply Voltage
20
50
SAMPLE SIZE = 1058
RL = 10kΩ
40
PERCENTAGE OF UNITS
15
+VOUT
10
–VOUT
5
30
20
10
0
5
10
SUPPLY VOLTAGE (±V)
15
20
0
00845-005
OUTPUT VOLTAGE RANGE (±V)
15
Figure 7. Input Bias Current vs. Supply Voltage
20
0
10
SUPPLY VOLTAGE (±V)
0
Figure 5. Output Voltage Range vs. Supply Voltage
0.5
1.0
1.5
INPUT BIAS CURRENT (pA)
2.0
00845-008
0
00845-007
0.65
00845-004
INPUT COMMON-MODE RANGE (±V)
RL = 10kΩ
Figure 8. Typical Distribution of Input Bias Current
10–9
30
25
20
15
10
5
0
10
100
1k
LOAD RESISTANCE (Ω)
10k
10–11
10–12
10–13
10–14
–60
Figure 6. Output Voltage Swing vs. Load Resistance
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
100
Figure 9. Input Bias Current vs. Temperature
Rev. D | Page 6 of 20
120
140
00845-009
INPUT BIAS CURRENT (A)
10–10
00845-006
OUTPUT VOLTAGE SWING (V p-p)
VS = ±15V
Data Sheet
AD795
1k
1.00
NOISE BANDWIDTH: 0.1Hz TO 10Hz
0.90
VOLTAGE NOISE (µV p-p)
INPUT BIAS CURRENT (pA)
0.95
0.85
0.80
0.75
0.70
100
10
–10
–5
0
5
COMMON-MODE VOLTAGE (V)
10
15
1
1k
00845-010
0.60
–15
10k
100k
1M
10M
SOURCE RESISTANCE (Ω)
100M
00845-013
0.65
1G
Figure 13. Input Voltage Noise vs. Source Resistance
Figure 10. Input Bias Current vs. Common-Mode Voltage
50
10–4
SAMPLE SIZE = 344
10–5
40
PERCENTAGE OF UNITS
INPUT BIAS CURRENT (A)
+IIN
–IIN
10–6
10–7
10–8
10–9
10–10
10–11
10–12
f = 0.1Hz TO 10Hz
30
20
10
–4
–3 –2 –1
0
1
2
3
4
DIFFERENTIAL INPUT VOLTAGE (±V)
5
6
0
0
1
CURRENT NOISE
0.1
7.5
5.0
–60
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
0.01
140
CURRENT NOISE (fA/ Hz)
VOLTAGE NOISE
10.0
00845-012
VOLTAGE NOISE (nV/ Hz)
10
Figure 12. Voltage and Current Noise Spectral Density vs. Temperature
Rev. D | Page 7 of 20
VOLTAGE NOISE (REFERRED TO INPUT) (nV/ Hz)
100
f = 1kHz
12.5
3
Figure 14. Typical Distribution of Input Voltage Noise
Figure 11. Input Bias Current vs. Differential Input Voltage
15.0
1
2
INPUT VOLTAGE NOISE (µV p-p)
1k
100
10
1
1
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
Figure 15. Input Voltage Noise Spectral Density
10M
00845-015
–5
00845-011
10–14
–6
00845-014
10–13
AD795
Data Sheet
120
–OUTPUT CURRENT
20
+OUTPUT CURRENT
15
10
5
–60
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
100
+PSRR
80
–PSRR
60
40
20
0
1
Figure 16. Short-Circuit Current Limit vs. Temperature
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
10M
00845-019
POWER SUPPLY REJECTION (dB)
25
00845-016
SHORT-CIRCUIT CURRENT (mA)
30
Figure 19. Power Supply Rejection vs. Frequency
10
120
COMMON-MODE REJECTION (dB)
OUTPUT SWING FROM 0 TO ±V
8
6
0.1%
4
0.01%
2
0
ERROR
–2
0.01%
–4
0.1%
–6
100
80
60
40
20
3
4
5
6
7
8
SETTLING TIME (µs)
9
10
11
0
00845-017
–10
1
Figure 17. Output Swing and Error vs. Settling Time
100
1k
10k
FREQUENCY (Hz)
100k
1M
10M
Figure 20. Common-Mode Rejection vs. Frequency
1000
120
120
900
OPEN-LOOP GAIN (dB)
700
600
500
400
300
100
PHASE
80
80
60
60
GAIN
40
40
20
20
0
0
PHASE MARGIN (Degrees)
100
800
100
0
–15
–10
–5
0
5
10
INPUT COMMON-MODE VOLTAGE (V)
15
–20
10
Figure 18. Absolute Input Error Voltage vs. Input Common-Mode Voltage
Rev. D | Page 8 of 20
100
1k
10k
100k
FREQUENCY (Hz)
1M
–20
10M
Figure 21. Open-Loop Gain and Phase Margin vs. Frequency
00845-021
200
00845-018
ABSOLUTE INPUT ERROR VOLTAGE (µV)
10
00845-020
–8
Data Sheet
AD795
30
2.0
QUIESCENT SUPPLY CURRENT (mA)
OUTPUT VOLTAGE (V p-p)
25
20
15
10
0
1k
10k
100k
FREQUENCY (Hz)
1M
00845-022
5
1.5
1.0
0.5
0
Figure 22. Large Signal Frequency Response
5
10
SUPPLY VOLTAGE (±V)
15
20
Figure 25. Quiescent Supply Current vs. Supply Voltage
1000
50
SAMPLE SIZE = 1419
40
PERCENTAGE OF UNITS
100
10
1
30
20
0.1
1k
10k
100k
1M
10M
FREQUENCY (Hz)
0
–500 –400 –300 –200 –100
0
100 200 300
INPUT OFFSET VOLTAGE (µV)
Figure 23. Closed-Loop Output Impedance vs. Frequency
400
Figure 26. Typical Distribution of Input Offset Voltage
–60
VIN = 3V rms
RL = 10kΩ
–70
10kΩ
–90
+VS
0.1µF
VIN
10kΩ
7
2
AD795
–110
3
4
–120
100
1k
10k
FREQUENCY (Hz)
100k
Figure 24. Total Harmonic Distortion vs. Frequency
VOUT
6
RL
10kΩ
CL
100pF
0.1µF
–VS
Figure 27. Unity Gain Inverter
Rev. D | Page 9 of 20
00845-027
–100
00845-024
THD (dB)
–80
500
00824-026
10
00845-023
CLOSED-LOOP OUTPUT IMPEDANCE (Ω)
0
00845-025
RL = 10kΩ
Data Sheet
5µs
20V
20V
100
100
90
90
10
0%
00845-028
10
0%
5V
5V
Figure 28. Unity Gain Inverter Large Signal Pulse Response
10mV
5µs
00845-031
AD795
Figure 31. Unity Gain Follower Large Signal Pulse Response
500ns
20mV
100
100
90
90
10
0%
00845-032
00845-029
10
0%
500ns
Figure 29. Unity Gain Inverter Small Signal Pulse Response
Figure 32. Unity Gain Follower Small Signal Pulse Response
+VS
0.1µF
7
2
AD795
3
4
VOUT
6
RL
10kΩ
CL
100pF
0.1µF
–VS
00845-030
VIN
Figure 30. Unity Gain Follower
Rev. D | Page 10 of 20
Data Sheet
AD795
MINIMIZING INPUT CURRENT
The AD795 is guaranteed to 1 pA maximum input current
with ±15 V supply voltage at room temperature. Careful attention to how the amplifier is used is necessary to maintain this
performance.
The amplifier’s operating temperature should be kept as low as
possible. Like other JFET input amplifiers, the AD795’s input
current doubles for every 10°C rise in junction temperature
(illustrated in Figure 9). On-chip power dissipation raises the
device operating temperature, causing an increase in input
current. Reducing supply voltage to cut power dissipation
reduces the AD795’s input current (see Figure 7). Heavy output
loads can also increase junction temperature; maintaining a
minimum load resistance of 10 kΩ is recommended.
Rev. D | Page 11 of 20
AD795
Data Sheet
CIRCUIT BOARD NOTES
The AD795 is designed for mounting on printed circuit boards
(PCBs). Maintaining picoampere resolution in those environments requires a lot of care. Both the board and the amplifier’s
package have finite resistance. Voltage differences between the
input pins and other pins as well as PCB metal traces causes
parasitic currents (see Figure 33) larger than the AD795’s input
current unless special precautions are taken. Two methods of
minimizing parasitic leakages include guarding of the input lines
and maintaining adequate insulation resistance.
CF
RF
VE
2
AD795
IS
6
3
–
CP
RP
IP =
VS
dV
VS dCP
VS +
C
+
dT P
RP dT
Figure 33. Sources of Parasitic Leakage Currents
CF
8
2
7
3
6
TOP VIEW
4 (“R” PACKAGE) 5
RF
GUARD
2
IS
AD795
+
VOUT
6
3
–
00845-034
NOTES
1. ON THE “R” PACKAGE PIN 1, PIN 5, AND PIN 8 ARE OPEN
AND CAN BE CONNECTED TO ANALOG COMMON OR TO
THE DRIVEN GUARD TO REDUCE LEAKAGE.
Figure 34. Guarding Scheme—lnverter
GUARD
GUARD TRACES
2
INPUT
TRACE
AD795
8
TOP VIEW
7
3
6
4
5
3
AD795
VS
+
VOUT
6
2
CONNECT TO JUNCTION OF
RF AND RI OR TO PIN 6 FOR
UNITY GAIN.
RF
RI
–
Figure 35. Guard Scheme—Follower
Rev. D | Page 12 of 20
00845-035
1
00845-033
IP
Figure 34 and Figure 35 show the recommended guarding
schemes for noninverting and inverting topologies. Pin 1 is not
connected, and can be safely connected to the guard. The high
impedance input trace should be guarded on both edges for its
entire length.
1
+
VOUT
Data Sheet
AD795
Leakage through the bulk of the circuit board can still occur
with the guarding schemes shown in Figure 34 and Figure 35.
Standard G10 type PCB material may not have high enough
volume resistivity to hold leakages at the sub-picoampere level
particularly under high humidity conditions. One option that
eliminates all effects of board resistance is shown in Figure 36.
The AD795’s sensitive input pin (either Pin 2 when connected
as an inverter, or Pin 3 when connected as a follower) is bent up
and soldered directly to a Teflon® insulated standoff. Both the
signal input and feedback component leads must also be
insulated from the circuit board by Teflon standoffs or low
leakage shielded cable.
INPUT PIN:
PIN 2 FOR INVERTER
OR PIN 3 FOR FOLLOWER.
7
3
6
4
5
AD795
PC
BOARD
TEFLON INSULATED STANDOFF
or by injection of parasitic currents by changes in capacitance
due to mechanical vibration:
dCp
V
dT
Both proper shielding and rigid mechanical mounting of
components help minimize error currents from both of these
sources.
The circuit in Figure 37 can be used when the amplifier is used
as an inverter. This method introduces a small voltage in series
with the amplifier’s positive input terminal. The amplifier’s input
offset voltage drift with temperature is not affected. However,
variation of the power supply voltages causes offset shifts.
Figure 36. Input Pin to Insulating Standoff
RF
RI
Contaminants such as solder flux on the board’s surface and on
the amplifier’s package can greatly reduce the insulation resistance
between the input pin and those traces with supply or signal
voltages. Both the package and the board must be kept clean
and dry. An effective cleaning procedure is to first swab the
surface with high grade isopropyl alcohol, then rinse it with
deionized water and, finally, bake it at 100°C for 1 hour. Polypropylene and polystyrene capacitors should not be subjected to
the 100°C bake because they can be damaged at temperatures
greater than 80°C.
Other guidelines include making the circuit layout as compact
as possible and reducing the length of input lines. Keeping
circuit board components rigid and minimizing vibration
reduce triboelectric and piezoelectric effects. All precision high
impedance circuitry requires shielding from electrical noise and
interference. For example, a ground plane should be used under
all high value (that is, greater than 1 MΩ) feedback resistors. In
some cases, a shield placed over the resistors, or even the entire
amplifier, may be needed to minimize electrical interference
originating from other circuits. Referring to the equation in
Rev. D | Page 13 of 20
2
AD795
VI
+
VOUT
6
3
+VS
499kΩ
200Ω
499kΩ
–
100kΩ
0.1µF
–VS
00845-037
AD795
00845-036
2
8
dV
CP
dT
OFFSET NULLING
INPUT SIGNAL
LED
1
Figure 33, this coupling can take place in either, or both, of two
different forms via time varying fields:
Figure 37. Alternate Offset Null Circuit for Inverter
AD795
Data Sheet
AC RESPONSE WITH HIGH VALUE SOURCE AND FEEDBACK RESISTANCE
Source and feedback resistances greater than 100 kΩ magnifies
the effect of input capacitances (stray and inherent to the
AD795) on the ac behavior of the circuit. The effects of
common-mode and differential input capacitances should be
taken into account because the circuit’s bandwidth and stability
can be adversely affected.
the response of the same circuit with a 1 pF feedback
capacitance. Typical differential input capacitance for the
AD795 is 2 pF.
10mV
5µs
100
90
10
0%
00845-039
In a follower, the source resistance, RS, and input commonmode capacitance, CS (including capacitance due to board and
capacitance inherent to the AD795), form a pole that limits
circuit bandwidth to 1/2 π RSCS. Figure 38 shows the follower
pulse response from a 1 MΩ source resistance with the
amplifier’s input pin isolated from the board; only the effect of
the AD795’s input common-mode capacitance is seen.
10mV
5µs
Figure 39. Inverter Pulse Response with 1 MΩ Source and Feedback
Resistance
100
90
10mV
5µs
100
90
10
00845-038
0%
Figure 38. Follower Pulse Response from 1 MΩ Source Resistance
Rev. D | Page 14 of 20
10
0%
00845-040
In an inverting configuration, the differential input capacitance
forms a pole in the circuit’s loop transmission. This can create
peaking in the ac response and possible instability. A feedback
capacitance can be used to stabilize the circuit. The inverter
pulse response with RF and RS equal to 1 MΩ and the input pin
isolated from the board appears in Figure 39. Figure 40 shows
Figure 40. Inverter Pulse Response with 1 MΩ Source and Feedback
Resistance, 1 pF Feedback Capacitance
Data Sheet
AD795
OVERLOAD ISSUES
Driving the amplifier output beyond its linear region causes
some sticking; recovery to normal operation is within 2 µs of
the input voltage returning within the linear range.
RF
CF
RP
If either input is driven below the negative supply, the amplifier’s
output is driven high, causing a phenomenon called phase
reversal. Normal operation is resumed within 30 µs of the input
voltage returning within the linear range.
2
SOURCE
AD795
6
00845-042
3
Figure 42. Inverter with Input Current Limit
Figure 41 shows the AD795’s input bias currents vs. differential
input voltage. Picoamp level input current is maintained for
differential voltages up to several hundred millivolts. This
behavior is only important if the AD795 is in an open-loop
application where substantial differential voltages are produced.
RP
3
SOURCE
AD795
6
00845-043
2
10–4
Figure 43. Follower with Input Current Limit
10–5
10–7
10–8
10–9
10–10
10–11
10–12
–5
–4
–3 –2 –1
0
1
2
3
4
DIFFERENTIAL INPUT VOLTAGE (±V)
5
6
Figure 41. Input Bias Current vs. Differential Input Voltage
INPUT PROTECTION
To achieve the low input bias currents of the AD795, it is not
possible to use the same on-chip protection as used in other
Analog Devices, Inc., op amps. This makes the AD795 sensitive
to handling and precautions should be taken to minimize ESD
exposure whenever possible.
RF
The AD795 safely handles any input voltage within the supply
voltage range. Some applications may subject the input terminals
to voltages beyond the supply voltages. In these cases, the
following guidelines should be used to maintain the AD795’s
functionality and performance.
If the inputs are driven more than a 0.5 V below the minus
supply, milliamp level currents can be produced through the
input terminals. That current should be limited to 10 mA for
transient overloads (less than 1 second) and 1 mA for continuous
overloads. This can be accomplished with a protection resistor
in the input terminal (as shown in Figure 42 and Figure 43).
The protection resistor’s Johnson noise adds to the amplifier’s
input voltage noise and impacts the frequency response.
Driving the input terminals above the positive supply causes the
input current to increase and limit at 40 µA. This condition is
maintained until 15 V above the positive supply—any input
voltage within this range does not harm the amplifier. Input
voltage above this range causes destructive breakdown and
should be avoided.
Rev. D | Page 15 of 20
2
SOURCE
AD795
6
3
PROTECTED DIODES
(LOW LEAKAGE)
Figure 44. Input Voltage Clamp with Diodes
10pF
1GΩ
GUARD
2
AD795
PHOTODIODE
3
OUTPUT
6
8
FILTERED
OUTPUT
OPTIONAL 26Hz
FILTER
Figure 45. AD795 Used as a Photodiode Preamplifier
00845-045
10–14
–6
00845-041
10–13
00845-044
INPUT BIAS CURRENT (A)
Figure 44 is a schematic of the AD795 as an inverter with an
input voltage clamp. Bootstrapping the clamp diodes at the
inverting input minimizes the voltage across the clamps and
keeps the leakage due to the diodes low. Low leakage diodes
(less than 1 pA), such as the FD333s should be used, and should
be shielded from light to keep photocurrents from being
generated. Even with these precautions, the diodes measurably
increase the input current and capacitance.
+IIN
–IIN
10–6
AD795
Data Sheet
CF
10pF
PREAMPLIFIER APPLICATIONS
The low input current and offset voltage levels of the AD795
together with its low voltage noise make this amplifier an
excellent choice for preamplifiers used in sensitive photodiode
applications. In a typical preamp circuit, shown in Figure 45,
the output of the amplifier is equal to:
RF
1GΩ
PHOTODIODE
RD
IS
CD
50pF
IN
IF
OUTPUT
00845-047
IS
en
VOUT = ID (Rf) = Rp (P) Rf
where:
ID is the photodiode signal current, in amps (A).
Rp is the photodiode sensitivity, in amps/watt (A/W).
Rf is the value of the feedback resistor, in ohms (Ω).
P is the light power incident to photodiode surface, in watts (W).
Figure 47. Noise Contributions of Various Sources
An equivalent model for a photodiode and its dc error sources
is shown in Figure 46. The amplifier’s input current, IB, contributes an output voltage error, which is proportional to the value
of the feedback resistor. The offset voltage error, VOS, causes a
dark current error due to the photodiode’s finite shunt resistance,
Rd. The resulting output voltage error, VE, is equal to:
VE = (1 + Rf/Rd) VOS + Rf IB
A shunt resistance on the order of 109 Ω is typical for a small
photodiode. Resistance Rd is a junction resistance, which
typically drops by a factor of two for every 10°C rise in
temperature. In the AD795, both the offset voltage and drift are
low, which helps minimize these errors.
CF
10pF
RF
1GΩ
An output filter with a passband close to that of the signal can
greatly improve the preamplifier’s signal to noise ratio. The
photodiode preamplifier shown in Figure 47, without a bandpass
filter, has a total output noise of 50 μV rms. Using a 26 Hz
single-pole output filter, the total output noise drops to 23 μV
rms, a factor of 2 improvement with no loss in signal bandwidth.
10µV
VOS
OUTPUT
CD
50pF
IQ AND IF
IB
OUTPUT VOLTAGE NOISE (V/ Hz)
ID
00845-046
RD
Figure 46. A Photodiode Model Showing DC Error Sources
MINIMIZING NOISE CONTRIBUTIONS
The noise level limits the resolution obtainable from any
preamplifier. The total output voltage noise divided by the
feedback resistance of the op amp defines the minimum
detectable signal current. The minimum detectable current
divided by the photodiode sensitivity is the minimum
detectable light power.
2
2
IN
WITH FILTER
NO FILTER
100nV
en
1
10
100
1k
FREQUENCY (Hz)
10k
100k
Figure 48. Voltage Noise Spectral Density of the Circuit of Figure 47 With and
Without an Output Filter
Rf
Rf 1sCdRd
2
VOUT in if is
en 1
1s Cf Rf
Rd 1sCfRf
2
1µV
10nV
Sources of noise in a typical preamp are shown in Figure 47.
The total noise contribution is defined as:
2
SIGNAL BANDWIDTH
00845-048
PHOTODIODE
Figure 48, a spectral density vs. frequency plot of each source’s
noise contribution, shows that the bandwidth of the amplifier’s
input voltage noise contribution is much greater than its signal
bandwidth. In addition, capacitance at the summing junction
results in a peaking of noise gain in this configuration. This
effect can be substantial when large photodiodes with large shunt
capacitances are used. Capacitor Cf sets the signal bandwidth
and limits the peak in the noise gain. Each source’s rms or rootsum-square contribution to noise is obtained by integrating the
sum of the squares of all the noise sources and then by
obtaining the square root of this sum. Minimizing the total area
under these curves optimizes the preamplifier’s overall noise
performance.
2
Rev. D | Page 16 of 20
Data Sheet
AD795
USING A T NETWORK
A T network, shown in Figure 49, can be used to boost the
effective transimpedance of an I-to-V converter, for a given
feedback resistor value. However, amplifier noise and offset
voltage contributions are also amplified by the T network gain.
A low noise, low offset voltage amplifier, such as the AD795,
is needed for this type of application.
10pF
RG
10kΩ
RF
100MΩ
The slope of the pH probe transfer function, 50 mV per pH
unit at room temperature, has a 3300 ppm/°C temperature
coefficient. The buffer of Figure 50 provides an output voltage
equal to 1 V/pH unit. Temperature compensation is provided
by resistor RT, which is a special temperature compensation
resistor, Part Number Q81, 1 kΩ, 1%, 3500 ppm/°C, available
from Tel Labs, Inc.
VOUT
AD795
VOUT = IDRF (1 +
+VS
VOS ADJUST
100kΩ
RI
1.1kΩ
RG
RI
)
COM
0.1µF
–VS
–15V
4
3
AD795
2
Figure 49. Photodiode Preamp Employing a T Network for Added Gain
+15V
0.1µF
–VS
1
GUARD
PH
PROBE
00845-049
PHOTODIODE
minimize leakage are all needed to maintain the accuracy of this
circuit.
5
6
OUTPUT
1V/pH UNIT
7
8
19.6kΩ
+VS
A typical pH probe requires a buffer amplifier, shown in Figure 50,
to isolate its 106 Ω to 109 Ω source resistance from external
circuitry. The low input current of the AD795 allows the voltage
error produced by the bias current and electrode resistance to
be minimal. The use of guarding, shielding, high insulation
resistance standoffs, and other such standard methods used to
Rev. D | Page 17 of 20
RT
1kΩ
3500ppm/°C
Figure 50. pH Probe Amplifier
00845-050
A pH PROBE BUFFER AMPLIFIER
AD795
Data Sheet
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
4.00 (0.1574)
3.80 (0.1497)
Figure 51. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
AD795JRZ
AD795JRZ-REEL
AD795JRZ-REEL7
1
Temperature Range
0°C to +70°C
0°C to +70°C
0°C to +70°C
Package Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
Z= RoHS Compliant Part.
Rev. D | Page 18 of 20
Package Option
R-8
R-8
R-8
Data Sheet
AD795
NOTES
Rev. D | Page 19 of 20
AD795
Data Sheet
NOTES
©1992–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00845-0-8/19(D)
Rev. D | Page 20 of 20
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