AD797AN

Ultralow Distortion, Ultralow Noise Op Amp AD797 FEATURES Low noise 0.9 nV/√Hz typical (1.2 nV/√Hz maximum) input voltage noise at 1 kHz 50 nV p-p input voltage noise, 0.1 Hz to 10 Hz Low distortion −120 dB total harmonic distortion at 20 kHz Excellent ac characteristics 800 ns settling time to 16 bits (10 V step) 110 MHz gain bandwidth (G = 1000) 8 MHz bandwidth (G = 10) 280 kHz full power bandwidth at 20 V p-p 20 V/μs slew rate Excellent dc precision 80 μV maximum input offset voltage 1.0 μV/°C VOS drift Specified for ±5 V and ±15 V power supplies High output drive current of 50 mA PIN CONFIGURATION OFFSET NULL 1 –IN 2 +IN 3 –VS 4 TOP VIEW AD797 DECOMPENSATION AND DISTORTION NEUTRALIZATION 7 +VS 8 5 OFFSET NULL Figure 1. 8-Lead Plastic Dual In-Line Package [PDIP] and 8-Lead Standard Small Outline Package [SOIC] GENERAL DESCRIPTION The AD797 is a very low noise, low distortion operational amplifier ideal for use as a preamplifier. The low noise of 0.9 nV/√Hz and low total harmonic distortion of −120 dB at audio bandwidths give the AD797 the wide dynamic range necessary for preamps in microphones and mixing consoles. Furthermore, the AD797’s excellent slew rate of 20 V/μs and 110 MHz gain bandwidth make it highly suitable for low frequency ultrasound applications. The AD797 is also useful in infrared (IR) and sonar imaging applications, where the widest dynamic range is necessary. The low distortion and 16-bit settling time of the AD797 make it ideal for buffering the inputs to Σ-Δ ADCs or the outputs of high resolution DACs, especially when the device is used in critical applications such as seismic detection or in spectrum analyzers. Key features such as a 50 mA output current drive and the specified power supply voltage range of ±5 V to ±15 V make the AD797 an excellent general-purpose amplifier. APPLICATIONS Professional audio preamplifiers IR, CCD, and sonar imaging systems Spectrum analyzers Ultrasound preamplifiers Seismic detectors Σ-Δ ADC/DAC buffers 5 –90 INPUT VOLTAGE NOISE (nV/√Hz) 4 –100 00846-001 6 OUTPUT 0.001 THD (dB) –110 0.0003 2 –120 0.0001 MEASUREMENT LIMIT 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 00846-002 300 1k 3k 10k FREQUENCY (Hz) 30k 100k 300k Figure 2. AD797 Voltage Noise Spectral Density Figure 3. THD vs. Frequency Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. 00846-003 0 –130 100 THD (%) 3 AD797 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Pin Configuration............................................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Typical Performance Characteristics ............................................. 6 Theory of Operation ...................................................................... 11 Noise and Source Impedance Considerations........................ 11 Low Frequency Noise ................................................................ 12 Wideband Noise ......................................................................... 12 Bypassing Considerations ......................................................... 12 The Noninverting Configuration............................................. 13 The Inverting Configuration .................................................... 14 Driving Capacitive Loads.......................................................... 14 Settling Time............................................................................... 14 Distortion Reduction ................................................................. 15 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 19 REVISION HISTORY 1/08—Rev. E to Rev. F Changes to Absolute Maximum Ratings ....................................... 5 Change to Equation 1..................................................................... 12 Changes to the Noninverting Configuration Section................ 13 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 7/05—Rev. D to Rev. E Updated Figure 1 Caption ............................................................... 1 Deleted Metallization Photo ........................................................... 6 Changes to Equation 1 ................................................................... 12 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 10/02—Rev. C to Rev. D Deleted 8-Lead CERDIP Package (Q-8)..........................Universal Edits to Specifications ...................................................................... 2 Edits to Absolute Maximum Ratings ............................................. 3 Edits to Ordering Guide .................................................................. 3 Edits to Table I .................................................................................. 9 Deleted Operational Amplifiers Graphic .................................... 15 Updated Outline Dimensions ....................................................... 15 Rev. F | Page 2 of 20 AD797 SPECIFICATIONS TA = 25°C and VS = ±15 V dc, unless otherwise noted. Table 1. Parameter INPUT OFFSET VOLTAGE Offset Voltage Drift INPUT BIAS CURRENT TMIN to TMAX INPUT OFFSET CURRENT OPEN-LOOP GAIN TMIN to TMAX VOUT = ±10 V RLOAD = 2 kΩ TMIN to TMAX RLOAD = 600 Ω TMIN to TMAX @ 20 kHz 1 G = 1000 G = 1000 2 G = 10 VOUT = 20 V p-p, RLOAD = 1 kΩ RLOAD = 1 kΩ 10 V step VCM = CMVR TMIN to TMAX VS = ±5 V to ±18 V TMIN to TMAX f = 0.1 Hz to 10 Hz f = 10 Hz f = 1 kHz f = 10 Hz to 1 MHz f = 1 kHz ±5 V, ±15 V ±15 V 1 1 1 1 14,000 Conditions TMIN to TMAX ±5 V, ±15 V ±5 V, ±15 V Supply Voltage (V) ±5 V, ±15 V Min AD797A Typ 25 50 0.2 0.25 0.5 100 120 20 6 15 5 20,000 Max 80 125/180 1.0 1.5 3.0 400 600/700 Min AD797B Typ 10 30 0.2 0.25 0.25 80 120 2 20 2 10 2 15 2 7 14,000 20,000 Max 40 60 0.6 0.9 2.0 200 300 Unit μV μV μV/°C μA μA nA nA V/μV V/μV V/μV V/μV V/V DYNAMIC PERFORMANCE Gain Bandwidth Product –3 dB Bandwidth Full Power Bandwidth1 Slew Rate Settling Time to 0.0015% COMMON-MODE REJECTION POWER SUPPLY REJECTION INPUT VOLTAGE NOISE ±15 V 15 V ±15 V ±15 V ±15 V ±15 V ±5 V, ±15 V 12.5 114 110 114 110 110 450 8 280 20 800 130 120 130 120 50 1.7 0.9 1.0 2.0 ±12 ±3 ±13 ±13 ±3 80 50 −98 −120 110 450 8 280 12.5 1200 120 114 120 130 20 800 130 120 114 120 50 1.7 0.9 1.0 2.0 ±11 ±2.5 ±13 ±13 ±3 80 50 −98 −120 MHz MHz MHz kHz V/μs ns dB dB dB dB nV p-p nV/√Hz nV/√Hz μV rms pA/√Hz V V V V V mA mA dB dB 1200 INPUT CURRENT NOISE INPUT COMMON-MODE VOLTAGE RANGE OUTPUT VOLTAGE SWING RLOAD = 2 kΩ RLOAD = 600 Ω RLOAD = 600 Ω Short-Circuit Current Output Current 3 TOTAL HARMONIC DISTORTION RLOAD = 1 kΩ, CN = 50 pF, f = 250 kHz, 3 V rms RLOAD = 1 kΩ, f = 20 kHz, 3 V rms ±15 V ±15 V ±15 V ±15 V ±15 V ±15 V ±5 V ±15 V ±15 V ±5 V ±5 V, ±15 V ±5 V, ±15 V ±15 V ±15 V 1.2 1.3 2.5 1.2 1.2 ±12 ±3 ±11 ±2.5 ±12 ±11 ±2.5 30 ±12 ±11 ±2.5 30 −90 −110 −90 −110 INPUT CHARACTERISTICS Input Resistance Differential Common Mode Input Capacitance Differential 4 Common Mode 7.5 100 20 5 7.5 100 20 5 kΩ MΩ pF pF Rev. F | Page 3 of 20 AD797 Parameter OUTPUT RESISTANCE POWER SUPPLY Operating Range Quiescent Current 1 2 Conditions AV = 1, f = 1 kHz Supply Voltage (V) Min AD797A Typ Max 3 ±18 10.5 Min AD797B Typ Max 3 ±18 10.5 Unit mΩ V mA ±5 ±5 V, ±15 V 8.2 ±5 8.2 Full power bandwidth = slew rate/2π VPEAK. Specified using external decompensation capacitor. 3 Output current for |VS – VOUT| > 4 V, AOL > 200 kΩ. 4 Differential input capacitance consists of 1.5 pF package capacitance and 18.5 pF from the input differential pair. Rev. F | Page 4 of 20 AD797 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage Internal Power Dissipation @ 25°C1 PDIP SOIC Input Voltage Differential Input Voltage2 Output Short-Circuit Duration Ratings ±18 V 1.3 W − (TA − 25°C)/θJA 0.9 W (TA − 25°C)/θJA ±VS ±0.7 V Indefinite within maximum internal power dissipation −65°C to +125°C −40°C to +85°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Storage Temperature Range (N, R Suffix) Operating Temperature Range Lead Temperature Range (Soldering 60 sec) 1 2 θJA = 95°C/W for the 8-lead PDIP; 155°C/W for the 8-lead SOIC. The AD797 inputs are protected by back-to-back diodes. To achieve low noise, internal current-limiting resistors are not incorporated into the design of this amplifier. If the differential input voltage exceeds ±0.7 V, the input current should be limited to less than 25 mA by series protection resistors. Note, however, that this degrades the low noise performance of the device. Rev. F | Page 5 of 20 AD797 TYPICAL PERFORMANCE CHARACTERISTICS 20 INPUT COMMON-MODE RANGE (±V) 15 10 5 VERTICAL SCALE (0.01µV/DIV) 0 5 10 SUPPLY VOLTAGE (±V) 15 20 00846-004 0 HORIZONTAL SCALE (5sec/DIV) Figure 4. Input Common-Mode Voltage Range vs. Supply Voltage Figure 7. 0.1 Hz to 10 Hz Noise 20 0 OUTPUT VOLTAGE SWING (±V) INPUT BIAS CURRENT (µA) 15 –0.5 10 –VOUT +VOUT –1.0 5 –1.5 00846-005 0 5 10 SUPPLY VOLTAGE (±V) 15 20 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) Figure 5. Output Voltage Swing vs. Supply Voltage Figure 8. Input Bias Current vs. Temperature 30 VS = ± 15V 140 OUTPUT VOLTAGE SWING (V p-p) SHORT-CIRCUIT CURRENT (mA) 120 20 100 SINK CURRENT 80 SOURCE CURRENT 10 VS = ±5 60 TEMPERATURE (°C) Figure 6. Output Voltage Swing vs. Load Resistance Figure 9. Short-Circuit Current vs. Temperature Rev. F | Page 6 of 20 00846-009 100 1k LOAD RESISTANCE (Ω) 10k 00846-006 0 10 40 –60 –40 –20 0 20 40 60 80 100 120 140 00846-008 0 –2.0 –60 00846-007 AD797 11 140 200 QUIESCENT SUPPLY CURRENT (mA) POWER SUPPLY REJECTION (dB) 10 +125°C 100 PSR –SUPPLY PSR +SUPPLY 150 9 8 +25°C 80 CMR 60 125 100 7 –55°C 6 40 75 1 10 100 1k 10k 100k SUPPLY VOLTAGE (±V) FREQUENCY (Hz) Figure 10. Quiescent Supply Current vs. Supply Voltage Figure 13. Power Supply and Common-Mode Rejection vs. Frequency 12 –60 f = 1kHz RL = 600Ω G = +10 RL = 600Ω G = +10 f = 10kHz NOISE BW = 100kHz 9 OUTPUT VOLTAGE (V rms) 6 THD + NOISE (dB) –80 VS = ±5V –100 VS = ±15V 3 0.1 OUTPUT LEVEL (V) 1 10 SUPPLY VOLTAGE (±V) Figure 11. Output Voltage vs. Supply Voltage for 0.01% Distortion Figure 14. Total Harmonic Distortion (THD) + Noise vs. Output Level 1.0 30 ±15V SUPPLIES 0.8 SETTLING TIME (µs) 0.0015% OUTPUT VOLTAGE (V p-p) RL = 600Ω 20 0.6 0.01% 0.4 10 0.2 ±5V SUPPLIES 00846-012 0 0 2 4 6 8 10 STEP SIZE (V) 100k 1M 10M FREQUENCY (Hz) Figure 12. Settling Time vs. Step Size (±) Figure 15. Large-Signal Frequency Response Rev. F | Page 7 of 20 00846-015 0 10k 00846-014 0 ±5 ±10 ±15 ±20 00846-011 0 –120 0.01 00846-013 0 5 10 15 20 00846-010 20 50 1M COMMON MODE REJECTION (dB) 120 175 AD797 5 35 120 GAIN/BANDWIDTH PRODUCT (MHz (G = 1000)) 00846-021 00846-020 00846-019 INPUT VOLTAGE NOISE (nV/√Hz) 4 GAIN/BANDWIDTH PRODUCT 30 SLEW RATE (V/µs) 110 SLEW RATE RISING EDGE 100 3 25 2 SLEW RATE FALLING EDGE 20 90 1 00846-016 0 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 15 –60 –40 –20 0 20 40 60 80 100 120 80 140 TEMPERATURE (°C) Figure 16. Input Voltage Noise Spectral Density Figure 19. Slew Rate and Gain/Bandwidth Product vs. Temperature 120 100 160 PHASE MARGIN 100 OPEN-LOOP GAIN (dB) 80 60 OPEN-LOOP GAIN (dB) WITH RS* PHASE MARGIN (Degrees) WITHOUT RS* 80 140 60 40 GAIN 40 20 120 *RS = 100 20 WITHOUT RS* WITH RS* 0 *SEE FIGURE 25. 0 100 1k 10k 00846-017 100k 1M FREQUENCY (Hz) 10M 100M 100 100 1k LOAD RESISTANCE (Ω) 10k Figure 17. Open-Loop Gain and Phase Margin vs. Frequency Figure 20. Open-Loop Gain vs. Load Resistance 300 100 INPUT OFFSET CURRENT (nA) 150 OVERCOMPENSATED MAGNITUDE OF OUTPUT IMPEDANCE (Ω) 10 0 1 WITHOUT CN* –150 UNDER COMPENSATED 0.1 *SEE FIGURE 32. WITH CN* TEMPERATURE (°C) 00846-018 –300 –60 –40 –20 0 20 40 60 80 100 120 140 0.01 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 18. Input Offset Current vs. Temperature Figure 21. Magnitude of Output Impedance vs. Frequency Rev. F | Page 8 of 20 AD797 20pF 1kΩ +VS 1kΩ 2 100Ω +VS ** * 7 VIN 2 7 AD797 3 4 6 VOUT VIN RS* AD797 3 4 6 VOUT 600Ω ** * –VS *SEE FIGURE 35. 00846-022 –VS 00846-025 *VALUE OF SOURCE RESISTANCE (SEE THE NOISE AND SOURCE IMPEDANCE CONSIDERATIONS SECTION). **SEE FIGURE 35. Figure 22. Inverter Connection Figure 25. Follower Connection 1µs 100 90 5V 100 90 1µs 10 10 5V Figure 23. Inverter Large-Signal Pulse Response 00846-023 Figure 26. Follower Large-Signal Pulse Response 50mV 100 90 100ns 100 90 50mV 100ns 10 00846-024 10 00846-027 0% 0% Figure 24. Inverter Small-Signal Pulse Response Figure 27. Follower Small-Signal Pulse Response Rev. F | Page 9 of 20 00846-026 0% 0% AD797 50mV 100 90 500ns 100 90 50mV 500ns 10 00846-028 10 00846-029 0% 0% Figure 28. 16-Bit Settling Time Positive Input Pulse Figure 29. 16-Bit Settling Time Negative Input Pulse Rev. F | Page 10 of 20 AD797 THEORY OF OPERATION The architecture of the AD797 was developed to overcome inherent limitations in previous amplifier designs. Previous precision amplifiers used three stages to ensure high open-loop gain (see Figure 30) at the expense of additional frequency compensation components. Slew rate and settling performance are usually compromised, and dynamic performance is not adequate beyond audio frequencies. As can be seen in Figure 30, the first stage gain is rolled off at high frequencies by the compensation network. Second stage noise and distortion then appears at the input and degrade performance. The AD797, on the other hand, uses a single ultrahigh gain stage to achieve dc as well as dynamic precision. As shown in the simplified schematic (Figure 31), Node A, Node B, and Node C track the input voltage, forcing the operating points of all pairs of devices in the signal path to match. By exploiting the inherent matching of devices fabricated on the same IC chip, high open-loop gain, CMRR, PSRR, and low VOS are guaranteed by pairwise device matching (that is, NPN to NPN and PNP to PNP), not by an absolute parameter such as beta and the early voltage. gm R1 C1 BUFFER RL VOUT benefit of making the low noise of the AD797 (5 × 106 and VOS < 80 μV, while at the same time providing a THD + noise of less than −120 dB and true 16-bit settling in less than 800 ns. The elimination of second-stage noise effects has the additional NOISE AND SOURCE IMPEDANCE CONSIDERATIONS The AD797 ultralow voltage noise of 0.9 nV/√Hz is achieved with special input transistors running at nearly 1 mA of collector current. Therefore, it is important to consider the total input-referred noise (eNtotal), which includes contributions Rev. F | Page 11 of 20 00846-032 C AD797 from voltage noise (eN), current noise (iN), and resistor noise (√4 kTRS). The plot in Figure 7 uses a slightly different technique: an FFT-based instrument (Figure 34) is used to generate a 10 Hz “brickwall” filter. A low frequency pole at 0.1 Hz is generated with an external ac coupling capacitor, which is also the instrument being dc coupled. Several precautions are necessary to attain optimum low frequency noise performance: • Care must be used to account for the effects of RS. Even a 10 Ω resistor has 0.4 nV/√Hz of noise (an error of 9% when root sum squared with 0.9 nV/√Hz). The test setup must be fully warmed up to prevent eOS drift from erroneously contributing to input noise. Circuitry must be shielded from air currents. Heat flow out of the package through its leads creates the opportunity for a thermoelectric potential at every junction of different metals. Selective heating and cooling of these by random air currents appears as 1/f noise and obscures the true device noise. The results must be interpreted using valid statistical techniques. 100k Ω +VS * 1Ω 2 7 e N total = [e N 2 + 4 kTR S + (i N × R S ) 2 ]1 / 2 where RS is the total input source resistance. (1) This equation is plotted for the AD797 in Figure 33. Because optimum dc performance is obtained with matched source resistances, this case is considered even though it is clear from Equation 1 that eliminating the balancing source resistance lowers the total noise by reducing the total RS by a factor of 2. At very low source resistance (RS < 50 Ω), the voltage noise of the amplifier dominates. As source resistance increases, the Johnson noise of RS dominates until a higher resistance of RS > 2 kΩ is achieved; the current noise component is larger than the resistor noise. 100 • • TOTAL NOISE 10 NOISE (nV/√Hz) • 1 RESISTOR NOISE ONLY 1.5µF 6 AD797 3 00846-033 VOUT 0.1 10 100 1000 10000 SOURCE RESISTANCE (Ω) 4 HP 3465 DYNAMIC SIGNAL ANALYZER (10Hz) * –VS *USE THE POWER SUPPLY BYPASSING SHOWN IN FIGURE 35. 00846-034 Figure 33. Noise vs. Source Resistance The AD797 is the optimum choice for low noise performance if the source resistance is kept