16-Bit, 1.33 MSPS PulSAR ADC in
MSOP/LFCSP
AD7983
Data Sheet
APPLICATION DIAGRAM
High performance
Pseudo differential analog input range
0 V to VREF with VREF between 2.9 V to 5 V
Throughput: 1.33 MSPS
Zero latency architecture
16-bit resolution with no missing codes
INL: ±0.6 LSB typical, ±1.0 LSB maximum
Dynamic range: 93 dB, VREF = 5 V
SNR: 92 dB at fIN = 1 kHz, VREF = 5 V
THD: −115 dB at fIN = 1 kHz, VREF = 5 V
SINAD: 92 dB at fIN = 1 kHz, VREF = 5 V
Low power dissipation
Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V
logic interface
5.25 mW at 1.33 MSPS (VDD only)
10.5 mW at 1.33 MSPS (total)
80 μW at 10 kSPS
Proprietary serial interface
SPI-/QSPI™-/MICROWIRE™-/DSP-compatible1
Daisy-chain multiple ADCs and busy indicator
10-lead MSOP and 10-lead, 3 mm × 3 mm LFCSP
Wide operating temperature range: −40°C to +85°C
APPLICATIONS
Automated test equipment
Data acquisition systems
Medical instruments
Machine automation
2.9V TO 5V
0 TO VREF
IN+
IN–
2.5V
REF VDD VIO
SDI
AD7983
SCK
SDO
GND
1.8V TO 5V
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
CNV
06974-001
FEATURES
Figure 1.
GENERAL DESCRIPTION
The AD7983 is a 16-bit, successive approximation, analog-todigital converter (ADC) that operates from a single power
supply, VDD. It contains a low power, high speed, 16-bit
sampling ADC and a versatile serial interface port. On the CNV
rising edge, it samples an analog input IN+ between 0 V to REF
with respect to a ground sense IN−. The reference voltage, REF,
is applied externally and can be set independent of the supply
voltage, VDD. Its power scales linearly with throughput.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single,
3-wire bus and provides an optional busy indicator. It is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the
separate supply VIO.
The AD7983 is housed in a 10-lead MSOP or a 10-lead LFCSP
with operation specified from −40°C to +85°
1
Protected by U.S. Patent 6,703,961.
Table 1. MSOP, LFCSP 16-/18-/20-Bit Precision SAR ADCs and SAR ADC-Based µModule Data Acquisition Solutions
Type
Differential
20-Bit
18-Bit
16-Bit
Pseudo Differential
18-Bit
16-Bit
1
≤100 kSPS
≤250 kSPS
AD7989-1
AD7691
1
AD7684
AD7988-1
AD7680
AD7683
1
AD76871
1
AD7685
AD7694
1
≤500 kSPS
≤1000 kSPS
≤2000 kSPS
AD40221
AD40111
AD76901
AD7989-51
AD76881
AD76931
AD79161
AD40211
AD40071
AD79821
AD79841
AD40051
AD79151
AD40201
AD40031
AD40101
AD40081
AD7988-51
AD76861
AD40061
AD40041
AD79801
AD79831
AD40021
AD40001
µModule Data Acquisition Solutions
AD40011
ADAQ7980
ADAQ7988
Pin for pin compatible.
Rev. C
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Technical Support
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AD7983
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog Inputs ............................................................................. 15
Applications ...................................................................................... 1
Driver Amplifier Choice ........................................................... 15
Application Diagram ....................................................................... 1
Voltage Reference Input............................................................ 16
General Description ......................................................................... 1
Power Supply .............................................................................. 16
Revision History ............................................................................... 2
Digital Interface .......................................................................... 17
Specifications .................................................................................... 3
CS MODE, 3-Wire Without Busy Indicator .......................... 18
Timing Specifications ...................................................................... 5
CS Mode, 3-Wire with Busy Indicator .................................... 19
Absolute Maximum Ratings ........................................................... 7
CS Mode, 4-Wire Without Busy Indicator............................. 20
Thermal Resistance ...................................................................... 7
CS Mode, 4-Wire with Busy Indicator .................................... 21
ESD Caution.................................................................................. 7
Chain Mode Without Busy Indicator ..................................... 22
Pin Configurations and Function Descriptions ........................... 8
Chain Mode with Busy Indicator............................................. 23
Typical Performance Characteristics ............................................. 9
Application Hints ........................................................................... 24
Terminology .................................................................................... 12
Layout .......................................................................................... 24
Theory of Operation ...................................................................... 13
Evaluating the Performance of the AD7983 .............................. 24
Circuit Information ................................................................... 13
Outline Dimensions ....................................................................... 25
Converter Operation.................................................................. 13
Ordering Guide .......................................................................... 25
Typical Connection Diagram ................................................... 14
REVISION HISTORY
6/2020—Rev. B to Rev. C
Changes to Data Sheet Title, Features Section, Applications
Section, General Description Section, and Table 1 ..................... 1
Changes to Specifications Section and Endnote 1, Table 1 ........ 3
Change to Power Supplies Parameter, Table 3 ............................ 4
Changes to Timing Specifications Section .................................... 5
Added Endnote 1, Table 4 ............................................................... 5
Added Table 5; Renumbered Sequentially .................................... 6
Deleted Figure 3; Renumbered Sequentially ................................ 6
Changes to Table 6 ........................................................................... 7
Added Thermal Resistance Section and Table 7 .......................... 7
Changes to Figure 22 ..................................................................... 14
Changes to Driver Amplifier Choice Section and Table 10 ..... 15
Changes to Voltage Reference Input Section and Power Supply
Section .............................................................................................. 16
7/2014—Rev. A to Rev. B
Added Patent Endnote and Changes to Table 1 ...........................1
Changed Standby Current from 0.35 nA to 1.1 mA ....................4
Added EPAD Note ............................................................................7
Changes to Figure 21 ..................................................................... 12
Changes to Power Supply Section................................................ 15
Changes to Evaluating the Performance of the AD7983 Section . 23
Updated Outline Dimensions ...................................................... 24
Changes to Ordering Guide .......................................................... 24
3/2010—Rev. 0 to Rev. A
Deleted Endnote 1 from Features Section, General Description
Section, and Table 1 ..........................................................................1
Changes to Table 5 ............................................................................6
Deleted Endnote 1 from Figure 5 Caption ....................................7
Changes to Figure 21 ..................................................................... 12
Deleted Endnote 1 from Circuit Information Section .............. 12
Changes to Figure 41 Caption ...................................................... 24
Changes to Ordering Guide .......................................................... 24
11/2007—Revision 0: Initial Version
Rev. C | Page 2 of 25
Data Sheet
AD7983
SPECIFICATIONS
VDD = 2.5 V, VIO = 1.71 V to 5.5 V, REF = 5 V, TA = –40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Absolute Input Voltage
Analog Input CMRR
Leakage Current @ 25°C
Input Impedance
ACCURACY
No Missing Codes
Differential Linearity Error
Integral Linearity Error
Transition Noise
Gain Error, TMIN to TMAX 3
Gain Error Temperature Drift
Zero Error, TMIN to TMAX3
Zero Temperature Drift
Power Supply Sensitivity
THROUGHPUT
Conversion Rate
Transient Response
AC ACCURACY
Dynamic Range
Signal-to-Noise Ratio, SNR
Spurious-Free Dynamic Range, SFDR
Total Harmonic Distortion, THD
Signal-to-(Noise + Distortion), SINAD
1
2
3
Conditions
Min
16
IN+ − IN−
IN+
IN−
fIN = 100 kHz
Acquisition phase
0
−0.1
−0.1
Typ
Unit
Bits
VREF
VREF + 0.1
+0.1
V
V
V
dB 1
nA
60
1
See the Analog Inputs section
16
−0.9
−1.0
−0.9
VDD = 2.5 V ± 5%
±0.4
±0.6
0.52
±2
±0.41
±0.44
0.54
±0.1
0
90.5
+0.9
+1.0
+0.9
1.33
290
Full-scale step
fIN = 1 kHz
fIN = 10 kHz
fIN = 10 kHz
fIN = 10 kHz
Max
93
92
114
−115
91.6
All specifications in dB are referred to a full-scale range (FSR). Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 µV.
See the Terminology section. These specifications include full temperature range variation, but not the error contribution from the external reference.
Rev. C | Page 3 of 25
Bits
LSB 2
LSB2
LSB2
LSB2
ppm/°C
mV
ppm/°C
LSB2
MSPS
ns
dB1
dB1
dB1
dB1
dB1
AD7983
Data Sheet
VDD = 2.5 V, VIO = 1.71 V to 5.5 V, REF = 5 V, TA = –40°C to +85°C, unless otherwise noted.
Table 3.
Parameter
REFERENCE
Voltage Range
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
DIGITAL INPUTS
Logic Levels
VIL
VIH
VIL
VIH
IIL
IIH
DIGITAL OUTPUTS
Data Format
Pipeline Delay
Conditions
VOL
VOH
POWER SUPPLIES
VDD
VIO
Standby Current 1, 2
Power Dissipation
Energy per Conversion
TEMPERATURE RANGE 3
Specified Performance
ISINK = 500 µA
ISOURCE = −500 µA
Min
Typ
Max
Unit
5.1
500
V
µA
10
2.0
MHz
ns
2.9
1.33 MSPS
VIO > 3 V
VIO > 3 V
VIO ≤ 3 V
VIO ≤ 3 V
–0.3
0.7 × VIO
–0.3
0.9 × VIO
−1
−1
Serial 16 bits straight binary
Conversion results available immediately
after completed conversion
0.4
VIO − 0.3
2.375
1.71
VDD and VIO = 2.5 V
1.33 MSPS throughput
TMIN to TMAX
0.3 × VIO
VIO + 0.3
0.1 × VIO
VIO + 0.3
+1
+1
2.5
1.1
10.5
7.9
−40
With all digital inputs forced to VIO or GND as required.
During the acquisition phase.
3
Contact sales for extended temperature range.
1
2
Rev. C | Page 4 of 25
2.625
5.5
12
+85
V
V
V
V
µA
µA
V
V
V
V
mA
mW
nJ/sample
°C
Data Sheet
AD7983
TIMING SPECIFICATIONS
VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, TA = −40°C to +85°C, unless otherwise noted. See Figure 2 for load conditions.
Table 4.
Parameter 1
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Period (Chain Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 3 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (Chain Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
1
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
Min
300
250
750
10
Typ
Max
500
Unit
ns
ns
ns
ns
10.5
12
13
15
ns
ns
ns
ns
11.5
13
14
16
4.5
4.5
3
ns
ns
ns
ns
ns
ns
ns
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
9.5
11
12
14
ns
ns
ns
ns
10
15
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tEN
tDIS
tSSDICNV
tHSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
5
2
0
5
5
2
3
15
Timing parameters measured with respect to a falling edge are defined as triggered at x% VIO. Timing parameters measured with respect to a rising edge are defined
as triggered at y% VIO. For VIO ≤ 3 V, x = 90 and y = 10. For VIO > 3 V, x = 70 and y = 30. The minimum VIH and maximum VIL are used. See the Digital Inputs
Specifications in Table 2.
Rev. C | Page 5 of 25
AD7983
Data Sheet
VDD = 2.37 V to 2.63 V, VIO = 1.71 to 2.3 V, TA = −40°C to +85°C, unless otherwise stated. See Figure 2 for load conditions.
Table 5.
Parameter 1
Throughput Rate
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions 2
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (Chain Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
Symbol
Min
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
tDIS
tSSDICNV
tHSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
300
250
1.2
10
22
23
6
6
3
Typ
Max
833
500
14
18
21
40
20
5
10
0
5
5
2
3
22
Unit
kSPS
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Timing parameters measured with respect to a falling edge are defined as triggered at x% VIO. Timing parameters measured with respect to a rising edge are defined
as triggered at y% VIO. For VIO ≤ 3 V, x = 90 and y = 10. For VIO > 3 V, x = 70 and y = 30. The minimum VIH and maximum VIL are used. See the Digital Inputs
Specifications in Table 2.
2
The time required to clock out N bits of data, tREAD, may be greater than tACQ depending on the magnitude of VIO. If tREAD is greater than tACQ, the throughput must be
limited to ensure that all N bits are read back from the device.
1
500µA
IOL
1.4V
TO SDO
500µA
IOH
06974-002
CL
20pF
Figure 2. Load Circuit for Digital Interface Timing
Rev. C | Page 6 of 25
Data Sheet
AD7983
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 6.
Parameter
Analog Inputs
IN+, IN− to GND1
Supply Voltage
REF, VIO to GND
VDD to GND
VDD to VIO
Digital Inputs to GND
Digital Outputs to GND
Storage Temperature Range
Junction Temperature
Lead Temperature
Vapor Phase (60 sec)
Infrared (15 sec)
1
Rating
−0.3 V to VREF + 0.3 V or ±130 mA
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure.
θJC is the junction to case thermal resistance.
−0.3 V to +6 V
−0.3 V to +3 V
+3 V to −6 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
Table 7. Thermal Resistance
Package Type1
RM-10
CP-10-9
1
215°C
220°C
θJC
44
2.96
Unit
°C/W
°C/W
Test Condition 1: thermal impedance simulated values are based on use of a
2S2P JEDEC PCB. See the Ordering Guide.
ESD CAUTION
See the Analog Inputs section.
θJA
200
48.7
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. C | Page 7 of 25
AD7983
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
10 VIO
VDD 2
IN+ 3
IN– 4
AD7983
TOP VIEW
(Not to Scale)
GND 5
10
VIO
9
SDI
8
SCK
7
SDO
6
CNV
IN+ 3
IN– 4
GND 5
TOP VIEW
(Not to Scale)
9 SDI
8 SCK
7 SDO
6 CNV
NOTES
1. EXPOSED PAD. CONNECT THE EXPOSED PAD
TO GND. THIS CONNECTION IS NOT REQUIRED
TO MEET THE ELECTRICAL PERFORMANCES.
06974-004
REF 1
AD7983
Figure 3. 10-Lead MSOP Pin Configuration
06974-005
REF 1
VDD 2
Figure 4. 10-Lead LFCSP Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
1
Mnemonic
REF
Type1
AI
2
3
VDD
IN+
P
AI
4
5
6
IN−
GND
CNV
AI
P
DI
7
8
9
SDO
SCK
SDI
DO
DI
DI
10
VIO
P
EPAD
1
Description
Reference Input Voltage. The REF range is from 2.9 V to 5.1 V. It is referred to the GND pin. This pin should
be decoupled closely to the pin with a 10 μF capacitor.
Power Supply.
Analog Input. It is referred to IN−. The voltage range, for example, the difference between IN+ and IN−, is
0 V to VREF.
Analog Input Ground Sense. To be connected to the analog ground plane or to a remote sense ground.
Power Supply Ground.
Convert Input. This input has multiple functions. On its risng edge, it initiates the conversions and
selects the interface mode of the part: chain or CS mode. In CS mode, it enables the SDO pin when low.
In chain mode, the data should be read when CNV is high.
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as
follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data
input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital
data level on SDI is output on SDO with a delay of 16 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can
enable the serial output signals when low; if SDI or CNV is low when the conversion is complete,
the busy indicator feature is enabled.
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V,
3 V, or 5 V).
Exposed Pad. For the 10-lead LFCSP only, connect the exposed pad to GND. This connection is not
required to meet the electrical performances.
AI = analog input, DI = digital input, DO = digital output, and P = power.
Rev. C | Page 8 of 25
Data Sheet
AD7983
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 2.5 V, REF = 5 V, VIO = 3.3 V, unless otherwise noted.
1.25
1.00
POSITIVE INL: 0.30LSB
NEGATIVE INL: –0.37LSB
1.00
POSITIVE DNL: 0.14LSB
NEGATIVE DNL: –0.14LSB
0.75
0.75
0.50
0.25
DNL (LSB)
INL (LSB)
0.50
0
–0.25
0.25
0
–0.25
–0.50
–0.50
–0.75
–1.25
0
32768
16384
49152
06974-029
–0.75
06974-026
–1.00
–1.00
0
65536
16384
32768
65536
49152
CODE
CODE
Figure 5. Integral Nonlinearity vs. Code
Figure 8. Differential Nonlinearity vs. Code
80k
120k
67532
70k
96765
100k
61565
60k
80k
COUNTS
COUNTS
50k
60k
40k
30k
40k
20k
0
0
0
0
58
55
0
0
0
0
10k
0
0
0
0
0
0
0
0
7FB6 7FB7 7FB8 7FB9 7FBA 7FBB 7FBC 7FBD 7FBE 7FBF 7FC0 7FC1 7FC2
7FF7 7FF8 7FF9 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003
CODE IN HEX
CODE IN HEX
Figure 6. Histogram of a DC Input at the Code Center
Figure 9. Histogram of a DC Input at the Code Transition
0
95
fS = 1.33MSPS
fIN = 10kHz
–20
94
SNR = 91.6dB
THD = –114.9dB
SFDR = 113.8dB
SINAD = 91.6dB
–40
93
92
SNR (dB)
–60
–80
–100
–120
91
90
89
88
–140
–160
–180
0
100
200
300
400
500
06974-032
87
06974-028
AMPLITUDE (dB of Full Scale)
1146 0
829
0
06974-042
0
17590
06974-041
16604
20k
86
85
–10
600
FREQUENCY (kHz)
–9
–8
–7
–6
–5
–4
–3
INPUT LEVEL (dB of Full Scale)
Figure 7. FFT Plot
Figure 10. SNR vs. Input Level
Rev. C | Page 9 of 25
–2
–1
0
Data Sheet
–110
95
–112
93
–114
91
SNR (dB)
–116
89
06974-038
–35
–15
5
25
45
65
85
105
85
–55
125
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. THD vs. Temperature
Figure 14. SNR vs. Temperature
–105
130
–110
125
100
16
–120
115
15
SNR
ENOB
SNR, SINAD (dB)
120
THD
SFDR (dB)
–115
90
14
SINAD
SFDR
85
–125
13
110
3.0
3.5
4.0
4.5
5.0
105
5.5
REFERENCE VOLTAGE (V)
80
2.5
06974-033
–130
2.5
3.0
3.5
4.0
4.5
5.0
12
5.5
REFERENCE VOLTAGE (V)
Figure 12. THD, SFDR vs. Reference Voltage
Figure 15. SNR, SINAD, and ENOB vs. Reference Voltage
100
–70
–75
95
–80
90
THD (dB)
–85
85
80
–90
–95
–100
–105
75
65
1
10
100
06974-037
–110
70
06974-034
SINAD (dB)
THD (dB)
95
ENOB (Bits)
–120
–55
06974-035
87
–118
06974-031
THD (dB)
AD7983
–115
–120
1000
1
FREQUENCY (kHz)
10
100
FREQUENCY (kHz)
Figure 13. SINAD vs. Frequency
Figure 16. THD vs. Frequency
Rev. C | Page 10 of 25
1000
Data Sheet
AD7983
1.5
2.5
1.4
1.3
STANDBY CURRENTS (mA)
1.5
1.0
IREF
0
2.375
06974-036
IVIO
1.0
0.9
0.8
2.425
2.475
2.525
0.6
0.5
–55
2.625
2.575
2.5
IVDD
2.0
1.5
1.0
IREF
–15
5
25
06974-039
IVIO
–35
45
–15
5
25
45
65
85
Figure 19. Standby Currents vs. Temperature
Figure 17. Operating Currents vs. Supply
0.5
–35
TEMPERATURE (°C)
VDD VOLTAGE (V)
OPERATING CURRENTS (mA)
IVDD + IVIO
1.1
0.7
0.5
0
–55
1.2
06974-040
OPERATING CURRENTS (mA)
IVDD
2.0
65
85
105
125
TEMPERATURE (°C)
Figure 18. Operating Currents vs. Temperature
Rev. C | Page 11 of 25
105
125
AD7983
Data Sheet
TERMINOLOGY
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 21).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified
in terms of resolution for which no missing codes are
guaranteed.
Offset Error
The first transition should occur at a level ½ LSB above analog
ground (38.1 µV for the 0 V to 5 V range). The offset error is
the deviation of the actual transition from that point.
Gain Error
The last transition (from 111 … 10 to 111 … 11) should
occur for an analog voltage 1½ LSB below the nominal full
scale (4.999886 V for the 0 V to 5 V range). The gain error is
the deviation of the actual level of the last transition from the
ideal level after the offset is adjusted out.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Resolution
Effective resolution is calculated as
Effective Resolution = log2(2N/RMS Input Noise)
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in dB. It is measured
with a signal at −60 dBFS to include all noise sources and DNL
artifacts.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the
Nyquist frequency, excluding harmonics and dc. The value for
SNR is expressed in dB.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for SINAD is expressed in dB.
Aperture Delay
Aperture delay is the measurement of the acquisition performance.
It is the time between the rising edge of the CNV input and
when the input signal is held for a conversion.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD as follows:
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
Noise-Free Code Resolution
Noise-free code resolution is the number of bits beyond which
it is impossible to distinctly resolve individual codes. It is
calculated as
Transient Response
Transient response is the time required for the ADC to
accurately acquire its input after a full-scale step function is
applied.
Noise-Free Code Resolution = log2(2N/Peak-to-Peak Noise)
and is expressed in bits.
Rev. C | Page 12 of 25
Data Sheet
AD7983
THEORY OF OPERATION
IN+
MSB
LSB
32,768C
16,384C
4C
2C
C
SWITCHES CONTROL
SW+
C
BUSY
REF
COMP
GND
32,768C
16,384C
4C
2C
C
CONTROL
LOGIC
OUTPUT CODE
C
LSB
MSB
SW+
06974-006
CNV
IN–
Figure 20. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7983 is a fast, low power, single-supply, precise 16-bit
ADC that uses a successive approximation architecture.
The AD7983 is capable of converting 1,000,000 samples per
second (1 MSPS) and powers down between conversions.
When operating at 10 kSPS, for example, it consumes 70 µW
typically, making it ideal for battery-powered applications.
The AD7983 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
The AD7983 can be interfaced to any 1.8 V to 5 V digital logic
family. It is available in a 10-lead MSOP or a tiny 10-lead
LFCSP that allows space savings and flexible configurations.
It is pin-for-pin compatible with the 18-bit AD7982.
CONVERTER OPERATION
The AD7983 is a successive approximation ADC based on a
charge redistribution DAC. Figure 20 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
input of the comparator are connected to GND via SW+ and
SW−. All independent switches are connected to the analog
inputs. Therefore, the capacitor arrays are used as sampling
capacitors and acquire the analog signal on the IN+ and IN−
inputs. When the acquisition phase is complete and the CNV
input goes high, a conversion phase is initiated. When the
conversion phase begins, SW+ and SW− are opened first. The two
capacitor arrays are then disconnected from the inputs and
connected to the GND input. Therefore, the differential voltage
between the inputs IN+ and IN− captured at the end of the
acquisition phase is applied to the comparator inputs, causing
the comparator to become unbalanced. By switching each
element of the capacitor array between GND and REF, the
comparator input varies by binary weighted voltage steps
(VREF/2, VREF/4 … VREF/65,536). The control logic toggles these
switches, starting with the MSB, to bring the comparator back
into a balanced condition. After the completion of this process,
the part returns to the acquisition phase and the control logic
generates the ADC output code and a busy signal indicator.
Because the AD7983 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Rev. C | Page 13 of 25
AD7983
Data Sheet
Transfer Functions
Table 9. Output Codes and Ideal Input Voltages
The ideal transfer characteristic for the AD7983 is shown in
Figure 21 and Table 9.
Description
FSR − 1 LSB
Midscale + 1 LSB
Midscale
Midscale − 1 LSB
−FSR + 1 LSB
−FSR
111 ... 101
1
2
Analog Input
Digital Output Code (Hex)
FFFF1
8001
8000
7FFF
0001
00002
This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
TYPICAL CONNECTION DIAGRAM
Figure 22 shows an example of the recommended connection
diagram for the AD7983 when multiple supplies are available.
000 ... 010
000 ... 001
000 ... 000
+FSR – 1 LSB
+FSR – 1.5 LSB
–FSR –FSR + 1LSB
–FSR + 0.5LSB
ANALOG INPUT
06974-007
Figure 21. ADC Ideal Transfer Function
REF1
V+
2.5V
10µF2
100nF
V+
1.8V TO 5V
100nF
20Ω
0 TO VREF
REF
3
2.7nF
VDD
VIO
IN+
SDI
SCK
V–
3- OR 4-WIRE INTERFACE5
AD7983
SDO
4
IN–
GND
CNV
1SEE
THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
3SEE THE DRIVER AMPLIFIER CHOICE SECTION.
4RECOMMENDED FILTER CONFIGURATION. SEE THE ANALOG INPUTS SECTION.
5SEE THE DIGITAL INTERFACE SECTION FOR THE MOST CONVENIENT INTERFACE MODE.
2C
REF
Figure 22. Typical Application Diagram with Multiple Supplies
Rev. C | Page 14 of 25
06974-008
ADC CODE (STRAIGHT BINARY)
111 ... 111
111 ... 110
VREF = 5 V
4.999924 V
2.500076 V
2.5 V
2.499924 V
76.3 µV
0V
Data Sheet
AD7983
ANALOG INPUTS
DRIVER AMPLIFIER CHOICE
Figure 23 shows an equivalent circuit of the input structure of
the AD7983.
Although the AD7983 is easy to drive, the driver amplifier
needs to meet the following requirements:
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN−. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V, because this causes these diodes to become forwardbiased and start conducting current. These diodes can handle a
forward-biased current of 130 mA maximum. For instance,
these conditions could eventually occur when the supplies of
the input buffer (U1) are different from VDD. In such a case
(for example, an input buffer with a short circuit), the current
limitation can be used to protect the part.
•
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7983. The noise coming from
the driver is filtered by the AD7983 analog input circuit’s
1-pole, low-pass filter made by RIN and CIN or by the external
filter, if one is used. Because the typical noise of the AD7983
is 39.7 µV rms, the SNR degradation due to the amplifier is
SNRLOSS
REF
D1
IN+
OR IN–
D2
GND
Figure 23. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.
During the acquisition phase, the impedance of the analog
inputs (IN+ and IN−) can be modeled as a parallel combination of
capacitor, CPIN, and the network formed by the series connection of
RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically
400 Ω and is a lumped component made up of some serial
resistors and the on resistance of the switches. CIN is typically
30 pF and is mainly the ADC sampling capacitor. During the
conversion phase, where the switches are opened, the input
impedance is limited to CPIN. RIN and CIN make a 1-pole, low-pass
filter that reduces undesirable aliasing effects and limits the noise.
When the source impedance of the driving circuit is low, the
AD7983 can be driven directly. Large source impedances
significantly affect the ac performance, especially THD. The dc
performances are less sensitive to the input impedance. The
maximum source impedance depends on the amount of THD
that can be tolerated. The THD degrades as a function of the
source impedance and the maximum input frequency.
where:
f–3dB is the input bandwidth in MHz of the AD7983
(10 MHz) or the cutoff frequency of the input filter, if
one is used.
N is the noise gain of the amplifier (for example, 1 in
buffer configuration).
eN is the equivalent input noise voltage of the op amp,
in nV/√Hz.
CIN
06974-009
CPIN
RIN
39.7
= 20 log
π
2
2
39.7 + f −3dB (Ne N )
2
•
For ac applications, the driver should have a THD
performance commensurate with the AD7983.
•
For multichannel multiplexed applications, the driver
amplifier and the AD7983 analog input circuit must settle
for a full-scale step onto the capacitor array at a 16-bit level
(0.0015%, 15 ppm). In the data sheet of the amplifier, settling
at 0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 16-bit level
and should be verified prior to driver selection.
The Precision ADC Driver Tool can be used to model the
settling behavior and to estimate the ac performance of the
AD7983 with a selected driver and RC filter.
Table 10. Recommended Driver Amplifiers
Amplifier
ADA4805-1
ADA4807-1
ADA4627-1
ADA4522-1
ADA4841-1
Rev. C | Page 15 of 25
Typical Application
Low noise, small size, and low power
Very low noise and high frequency
Precision, low noise, and low input bias current
Precision, zero drift, and EMI enhanced
Low noise, low distortion, and low power
AD7983
Data Sheet
VOLTAGE REFERENCE INPUT
POWER SUPPLY
The AD7983 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
The AD7983 uses two power supply pins: a core supply (VDD)
and a digital input/output interface supply (VIO). VIO allows
direct interface with any logic between 1.8 V and 5.0 V. To
reduce the number of supplies needed, VIO and VDD can be
tied together. When VIO is greater than or equal to VDD, the
AD7983 is insensitive to power supply sequencing. In normal
operation, if the magnitude of VIO is less than the magnitude
of VDD, VIO must be applied before VDD. Additionally, it is
very insensitive to power supply variations over a wide frequency
range, as shown in Figure 24.
If desired, a reference-decoupling capacitor value as small as
2.2 µF can be used with a minimal impact on performance,
especially DNL.
Regardless, there is no need for an additional lower value ceramic
decoupling capacitor (for example, 100 nF) between the REF
and GND pins.
80
75
70
65
60
55
1
10
100
FREQUENCY (kHz)
Figure 24. PSRR vs. Frequency
Rev. C | Page 16 of 25
1000
06974-010
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 µF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift reference, such as
the ADR435, ADR445, LTC6655, or ADR4550.
PSRR (dB)
When REF is driven by a very low impedance source, for example,
a reference buffer using the AD8031, ADA4805-1, or
ADA4807-1, a ceramic chip capacitor is appropriate for
optimum performance.
Data Sheet
AD7983
DIGITAL INTERFACE
Though the AD7983 has a reduced number of pins, it offers
flexibility in its serial interface modes.
When in CS mode, the AD7983 is compatible with SPI, QSPI,
and digital hosts. This interface can use either a 3-wire or a 4-wire
interface. A 3-wire interface using the CNV, SCK, and SDO
signals minimizes wiring connections useful, for instance, in
isolated applications. A 4-wire interface using the SDI, CNV,
SCK, and SDO signals allows CNV, which initiates the
conversions, to be independent of the readback timing (SDI).
This is useful in low jitter sampling or simultaneous sampling
applications.
The AD7983, when in chain mode, provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high, and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected,
the chain mode is always selected.
In either mode, the AD7983 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be
used as a busy signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a busy indicator,
the user must time out the maximum conversion time prior to
readback.
The busy indicator feature is enabled
• In CS mode if CNV or SDI is low when the ADC conversion
ends (see Figure 28 and Figure 32).
• In chain mode if SCK is high during the CNV rising edge
(see Figure 36).
Rev. C | Page 17 of 25
AD7983
Data Sheet
When CNV goes low, the MSB is output onto SDO. The
remaining data bits are then clocked by subsequent SCK falling
edges. The data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the SCK
falling edge allows a faster reading rate provided that it has an
acceptable hold time. After the 16th SCK falling edge or when
CNV goes high, whichever is earlier, SDO returns to high
impedance.
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7983 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 25, and the corresponding timing is given in
Figure 26.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. When a conversion is initiated, it continues until
completion irrespective of the state of CNV. This can be useful,
for example, to bring CNV low to select other SPI devices, such
as analog multiplexers; however, CNV must be returned high
before the minimum conversion time elapses and then held
high for the maximum conversion time to avoid the generation
of the busy signal indicator. When the conversion is complete, the
AD7983 enters the acquisition phase and goes into standby mode.
CONVERT
DIGITAL HOST
CNV
VIO
SDI
AD7983
SDO
DATA IN
06974-012
SCK
CLK
Figure 25. CS Mode, 3-Wire Without Busy Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
2
3
14
tHSDO
16
tSCKH
tEN
SDO
15
tDIS
tDSDO
D15
D14
D13
D1
D0
Figure 26. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)
Rev. C | Page 18 of 25
06974-013
1
SCK
Data Sheet
AD7983
If multiple AD7983s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended that this contention be
kept as short as possible to limit extra power dissipation.
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7983 is connected
to an SPI-compatible digital host that has an interrupt input.
The connection diagram is shown in Figure 27, and the
corresponding timing is given in Figure 28.
CONVERT
SDI = 1
VIO
CNV
VIO
DIGITAL HOST
47kΩ
SDI
AD7983
SDO
DATA IN
SCK
IRQ
06974-014
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time
elapses and then held low for the maximum conversion time to
guarantee the generation of the busy signal indicator. When the
conversion is complete, SDO goes from high impedance to low.
With a pull-up on the SDO line, this transition can be used as an
interrupt signal to initiate the data read back controlled by the
digital host. The AD7983 then enters the acquisition phase and
goes into standby mode. The data bits are then clocked out,
MSB first, by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to capture
the data, a digital host using the SCK falling edge allows a faster
reading rate provided it has an acceptable hold time. After the
optional 17th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
CLK
Figure 27. CS Mode, 3-Wire with Busy Indicator
Connection Diagram (SDI High)
tCYC
tCNVH
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
1
2
3
15
tHSDO
16
17
tSCKH
tDIS
tDSDO
SDO
D15
D14
D1
D0
Figure 28. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High)
Rev. C | Page 19 of 25
06974-015
SCK
AD7983
Data Sheet
When the conversion is complete, the AD7983 enters the
acquisition phase and goes into standby mode. Each ADC
result can be read by bringing its SDI input low, which
consequently outputs the MSB onto SDO. The remaining data
bits are then clocked by subsequent SCK falling edges. The data
is valid on both SCK edges. Although the rising edge can be used
to capture the data, a digital host using the SCK falling edge
allows a faster reading rate provided it has an acceptable hold
time. After the 16th SCK falling edge or when SDI goes high,
whichever is earlier, SDO returns to high impedance and
another AD7983 can be read.
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7983s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7983s is shown in
Figure 29, and the corresponding timing is given in Figure 30.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase
and the subsequent data readback (if SDI and CNV are low,
SDO is driven low). Prior to the minimum conversion time,
SDI can be used to select other SPI devices, such as analog
multiplexers, but SDI must be returned high before the
minimum conversion time elapses and then held high for the
maximum conversion time to avoid the generation of the busy
signal indicator.
CS2
CS1
CONVERT
AD7983
SDI
SDO
AD7983
SDO
SCK
SCK
06974-016
SDI
DIGITAL HOST
CNV
CNV
DATA IN
CLK
Figure 29. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSSDICNV
SDI(CS1)
tHSDICNV
SDI(CS2)
tSCK
tSCKL
SCK
2
14
3
tHSDO
SDO
15
16
17
18
30
31
32
tSCKH
tEN
tDIS
tDSDO
D15
D14
D13
D1
D0
D15
D14
Figure 30. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing
Rev. C | Page 20 of 25
D1
D0
06974-017
1
Data Sheet
AD7983
With a pull-up on the SDO line, this transition can be used as
an interrupt signal to initiate the data readback controlled by
the digital host. The AD7983 then enters the acquisition phase
and goes into standby mode. The data bits are clocked out,
MSB first, by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to
capture the data, a digital host using the SCK falling edge allows
a faster reading rate provided it has an acceptable hold time.
After the optional 17th SCK falling edge or SDI going high,
whichever is earlier, the SDO returns to high impedance.
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7983 is connected
to an SPI-compatible digital host that has an interrupt input,
and when it is desired to keep CNV, which is used to sample
the analog input, independent of the signal used to select the
data reading. This requirement is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 31, and the
corresponding timing is given in Figure 32.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase
and the subsequent data readback (if SDI and CNV are low,
SDO is driven low). Prior to the minimum conversion time,
SDI can be used to select other SPI devices, such as analog
multiplexers, but SDI must be returned low before the
minimum conversion time elapses and then held low for the
maximum conversion time to guarantee the generation of the
busy signal indicator. When the conversion is complete, SDO
goes from high impedance to low.
CS1
CONVERT
VIO
CNV
DIGITAL HOST
47kΩ
AD7983
SDO
DATA IN
SCK
IRQ
06974-018
SDI
CLK
Figure 31. CS Mode, 4-Wire with Busy Indicator Connection Diagram
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSSDICNV
SDI
tSCK
tHSDICNV
tSCKL
2
3
15
tHSDO
16
17
tSCKH
tDIS
tDSDO
tEN
SDO
D15
D14
D1
Figure 32. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing
Rev. C | Page 21 of 25
D0
06974-019
1
SCK
AD7983
Data Sheet
When SDI and CNV are low, SDO is driven low. With SCK
low, a rising edge on CNV initiates a conversion, selects the
chain mode, and disables the busy indicator. In this mode,
CNV is held high during the conversion phase and the
subsequent data readback. When the conversion is complete,
the MSB is output onto SDO and the AD7983 enters the
acquisition phase and goes into standby mode. The remaining
data bits stored in the internal shift register are clocked by
subsequent SCK falling edges. For each ADC, SDI feeds the
input of the internal shift register and is clocked by the SCK
falling edge. Each ADC in the chain outputs its data MSB first,
and 16 × N clocks are required to readback the N ADCs. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge allows a faster reading rate and, consequently, more
AD7983s in the chain, provided the digital host has an
acceptable hold time. The maximum conversion rate can be
reduced due to the total readback time.
CHAIN MODE WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7983s on a
3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7983s is shown in
Figure 33, and the corresponding timing is given in Figure 34.
CONVERT
CNV
AD7983
SDO
SDI
AD7983
A
SCK
SDO
DATA IN
B
SCK
06974-020
SDI
DIGITAL HOST
CNV
CLK
Figure 33. Chain Mode Without Busy Indicator Connection Diagram
SDIA = 0
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
tSSCKCNV
SCK
1
2
3
15
tSSDISCK
tHSCKCNV
16
17
18
30
31
32
D A1
DA0
tSCKH
tHSDISCK
tEN
SDOA = SDIB
14
DA15
DA14
DA13
DA1
DA0
D B1
DB0
tHSDO
SDOB
DB15
DB14
DB13
DA15
DA14
Figure 34. Chain Mode Without Busy Indicator Serial Interface Timing
Rev. C | Page 22 of 25
06974-021
tDSDO
Data Sheet
AD7983
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the SDO pin of the ADC closest
to the digital host (see the AD7983 ADC labeled C in Figure 35)
is driven high. This transition on SDO can be used as a busy
indicator to trigger the data readback controlled by the digital
host. The AD7983 then enters the acquisition phase and goes
into standby mode. The data bits stored in the internal shift
register are clocked out, MSB first, by subsequent SCK falling
edges. For each ADC, SDI feeds the input of the internal shift
register and is clocked by the SCK falling edge. Each ADC in the
chain outputs its data MSB first, and 16 × N + 1 clocks are required
to readback the N ADCs. Although the rising edge can be used to
capture the data, a digital host using the SCK falling edge allows
a faster reading rate and, consequently, more AD7983s in the
chain, provided the digital host has an acceptable hold time.
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7983s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications
or for systems with a limited interfacing capacity. Data
readback is analogous to clocking a shift register.
A connection diagram example using three AD7983s is shown
in Figure 35, and the corresponding timing is given in Figure 36.
CONVERT
SDI
AD7983
CNV
SDO
SDI
DIGITAL HOST
CNV
AD7983
SDO
AD7983
SDI
A
B
C
SCK
SCK
SCK
SDO
DATA IN
IRQ
06974-022
CNV
CLK
Figure 35. Chain Mode with Busy Indicator Connection Diagram
tCYC
CNV = SDIA
tCONV
tACQ
ACQUISITION
ACQUISITION
CONVERSION
tSCK
tSCKH
tSSCKCNV
1
2
3
4
15
16
17
tSSDISCK
tHSCKCNV
DA15
SDOA = SDIB
DA14
DA13
19
31
32
33
34
35
tSCKL
tHSDISCK
tEN
18
DA1
tDSDOSDI
DB15
DB14
DB13
DB 1
DB0
DA15
DA14
DA1
DA0
DC15
DC14
DC13
DC1
DC0
DB15
DB14
D B1
D B0
tDSDOSDI
SDOC
49
DA 0
tDSDO
tDSDOSDI
48
tDSDOSDI
tHSDO
SDOB = SDIC
47
tDSDODSI
Figure 36. Chain Mode with Busy Indicator Serial Interface Timing
Rev. C | Page 23 of 25
DA15
DA14
DA1
D A0
06974-023
SCK
AD7983
Data Sheet
APPLICATION HINTS
LAYOUT
The printed circuit board (PCB) that houses the AD7983
should be designed so that the analog and digital sections are
separated and confined to certain areas of the board. The pinout of
the AD7983, with all its analog signals on the left side and all its
digital signals on the right side, eases this task.
AD7983
At least one ground plane should be used. The ground plane
can be common or split between the digital and analog section.
In the latter case, the planes should be joined underneath the
AD7983.
06974-024
Avoid running digital lines under the device because these couple
noise onto the die, unless a ground plane under the AD7983 is
used as a shield. Fast switching signals, such as CNV or clocks,
should never run near analog signal paths. Crossover of digital
and analog signals should be avoided.
Figure 37. Example Layout of the AD7983 (Top Layer)
The AD7983 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, ideally right up against, the REF and
GND pins and connecting them with wide, low impedance traces.
Finally, the AD7983 power supplies, VDD and VIO, should be
decoupled with ceramic capacitors, typically 100 nF, placed
close to the AD7983 and connected using short and wide traces
to provide low impedance paths and to reduce the effect of
glitches on the power supply lines.
EVALUATING THE PERFORMANCE OF THE AD7983
Other recommended layouts for the AD7983 are outlined
in the documentation of the evaluation board for the AD7983
(EVAL-AD7983SDZ). The evaluation board package includes
a fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the
EVAL-SDP-CB1Z.
Rev. C | Page 24 of 25
06974-025
An example of a layout following these rules is shown in
Figure 37 and Figure 38.
Figure 38. Example Layout of the AD7983 (Bottom Layer)
Data Sheet
AD7983
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
1
5.15
4.90
4.65
6
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.30
0.15
0.70
0.55
0.40
0.23
0.13
6°
0°
091709-A
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 39.10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
DETAIL A
(JEDEC 95)
2.48
2.38
2.23
3.10
3.00 SQ
2.90
0.50 BSC
10
6
PIN 1
INDICATOR
AREA
1.74
1.64
1.49
EXPOSED
PAD
0.50
0.40
0.30
1
5
SIDE VIEW
0.30
0.25
0.20
SEATING
PLANE
0.05 MAX
0.02 NOM
COPLANARITY
0.08
P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
08-20-2018-C
PKG-004362
0.80
0.75
0.70
0.20 MIN
BOTTOM VIE W
TOP VIEW
0.20 REF
Figure 40. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2, 3
AD7983BRMZ
AD7983BRMZRL7
AD7983BCPZ-R2
AD7983BCPZ-RL
AD7983BCPZ-RL7
EVAL-AD7983SDZ
EVAL-SDP-CB1Z
1
2
3
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
10-Lead MSOP
10-Lead MSOP
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead LFCSP_WD
Evaluation Board
Controller Board
Package Option
RM-10
RM-10
CP-10-9
CP-10-9
CP-10-9
Ordering Quantity
Tube, 50
Reel, 1000
Reel, 250
Reel, 1000
Reel, 5000
Z = RoHS Compliant Part.
The EVAL-AD7983SDZ can be used as a standalone evaluation board or in conjunction with the EVAL-SDP-CB1Z for evaluation/demonstration purposes.
The EVAL-SDP-CB1Z allows a PC to control and communicate with all Analog Devices evaluation boards ending in the SDZ designator.
©2007–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06974-6/20(C)
Rev. C | Page 25 of 25
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