18-Bit, 1.33 MSPS PulSAR 10.5 mW
ADC in MSOP/LFCSP
AD7984
Data Sheet
FEATURES
APPLICATION DIAGRAM
APPLICATIONS
Automated test equipment
Data acquisition systems
Medical instruments
Machine automation
2.9V TO 5V 2.5V
IN+
REF VDD VIO
SDI
AD7984
±10V, ±5V, ..
SCK
SDO
IN–
ADA4941
1.8V TO 5V
GND
CNV
3- OR 4-WIRE
INTERFACE
(SPI, CS
DAISY CHAIN)
06973-001
High performance
True differential analog input range: ±VREF
0 V to VREF with VREF between 2.9 V to 5 V
Easy to drive with the ADA4941
Throughput: 1.33 MSPS
Zero latency architecture
18-bit resolution with no missing codes
INL: ±2.25 LSB maximum
Dynamic range: 99.7 dB, VREF = 5 V
SNR: 98.5 dB at fIN = 1 kHz, VREF = 5 V
THD: −110.5 dB at fIN = 1 kHz, VREF = 5 V
SINAD: 97.5 dB at fIN = 1 kHz, VREF = 5 V
Low power dissipation
Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V
logic interface
5.3 mW at 1.33 MSPS (VDD only)
10.5 mW at 1.33 MSPS (total)
80 μW at 10 kSPS
Proprietary serial interface
SPI/QSPI/MICROWIRE™/DSP compatible
Ability to daisy-chain multiple ADCs and busy indicator
10-lead MSOP and 10-lead, 3 mm × 3 mm LFCSP
Wide operating temperature range: −40°C to +85°C
Figure 1.
GENERAL DESCRIPTION
The AD79841 is an 18-bit, successive approximation, analog-todigital converter (ADC) that operates from a single power supply,
VDD. It contains a low power, high speed, 18-bit sampling ADC
and a versatile serial interface port. On the CNV rising edge,
the AD7984 samples the voltage difference between the IN+
and IN− pins. The voltages on these pins usually swing in
opposite phases between 0 V and VREF. The reference voltage,
REF, is applied externally and can be set independent of the
supply voltage, VDD.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single
3-wire bus and provides an optional busy indicator. It is
compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the separate
VIO supply.
The AD7984 is available in a 10-lead MSOP or a 10-lead LFCSP
with operation specified from −40°C to +85°C.
1
Protected by U.S. Patent 6,703,961.
Table 1. MSOP, LFCSP 16-/18-/20-Bit Precision SAR ADCs and SAR ADC-Based µModule Data Acquisition Solutions
Type
Differential
20-Bit
18-Bit
16-Bit
Pseudo Differential
18-Bit
16-Bit
1
≤100 kSPS
≤250 kSPS
AD7989-1
AD7691
1
AD7684
AD7988-1
AD7680
AD7683
1
AD76871
1
AD7685
AD7694
1
≤500 kSPS
≤1000 kSPS
≤2000 kSPS
AD40221
AD40111
AD76901
AD7989-51
AD76881
AD76931
AD79161
AD40211
AD40071
AD79821
AD79841
AD40051
AD79151
AD40201
AD40031
AD40101
AD40081
AD7988-51
AD76861
AD40061
AD40041
AD79801
AD79831
AD40021
AD40001
µModule Data Acquisition Solutions
AD40011
ADAQ7980
ADAQ7988
Pin for pin compatible.
Rev. C
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2007–2020 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD7984
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Driver Amplifier Choice ........................................................... 15
Applications ...................................................................................... 1
Single-to-Differential Driver .................................................... 16
Application Diagram ....................................................................... 1
Voltage Reference Input............................................................ 16
General Description ......................................................................... 1
Power Supply .............................................................................. 16
Revision History ............................................................................... 2
Digital Interface .......................................................................... 17
Specifications .................................................................................... 3
CS Mode, 3-Wire Without Busy Indicator............................. 18
Timing Specifications .................................................................. 5
CS Mode, 3-Wire with Busy Indicator .................................... 19
Absolute Maximum Ratings ........................................................... 7
CS Mode, 4-Wire Without Busy Indicator............................. 20
Thermal Resistance ...................................................................... 7
CS Mode, 4-Wire with Busy Indicator .................................... 21
ESD Caution.................................................................................. 7
Chain Mode Without Busy Indicator ..................................... 22
Pin Configurations and Function Descriptions ........................... 8
Chain Mode with Busy Indicator............................................. 23
Typical Performance Characteristics ............................................. 9
Application Hints ........................................................................... 24
Terminology .................................................................................... 12
Layout .......................................................................................... 24
Theory of Operation ...................................................................... 13
Evaluating the AD7984 Performance...................................... 24
Circuit Information ................................................................... 13
Outline Dimensions ....................................................................... 25
Converter Operation.................................................................. 13
Ordering Guide .......................................................................... 25
Typical Connection Diagram ................................................... 14
Analog Inputs ............................................................................. 15
REVISION HISTORY
7/2020—Rev. B to Rev. C
Changes to Features Section, Applications Section, and
Table 1 ................................................................................................ 1
Changes to Specifications Section and Table 2 ............................ 3
Changes to Power Supplies Parameter, Table 3 ........................... 4
Changes to Timing Specifications Section and Table 4 .............. 5
Added Table 5; Renumbered Sequentially .................................... 6
Deleted Figure 3; Renumbered Sequentially ................................ 6
Changes to Table 6 ........................................................................... 7
Added Thermal Resistance Section and Table 7 .......................... 7
Changes to Figure 22 ..................................................................... 14
Changes to Driver Amplifier Choice Section and Table 10 ..... 15
Changes to Single-to-Differential Driver Section, Voltage
Reference Input Section, and Power Supply Section................. 16
7/2014—Rev. A to Rev. B
Changed QFN (LFCSP) to LFCSP .............................. Throughout
Changes to Features Section and Table 1 ......................................1
Added Patent Note, Note 1 ..............................................................1
Changes to Power Supply Section................................................ 15
Changes to Evaluating the AD7984 Performance Section ....... 23
Updated Outline Dimensions ...................................................... 24
Changes to Ordering Guide .......................................................... 24
8/2010—Rev. 0 to Rev. A
Updated Outline Dimensions ...................................................... 24
Changes to Ordering Guide .......................................................... 24
11/2007—Revision 0: Initial Version
Rev. C | Page 2 of 25
Data Sheet
AD7984
SPECIFICATIONS
VDD = 2.5 V, VIO = 1.71 V to 5.5 V, REF = 5 V, TA = −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Absolute Input Voltage
Common-Mode Input Range
Analog Input CMRR
Leakage Current at 25°C
Input Impedance
ACCURACY
No Missing Codes
Differential Linearity Error
Integral Linearity Error
Transition Noise
Gain Error, TMIN to TMAX 3
Gain Error Temperature Drift
Zero Error, TMIN to TMAX3
Zero Temperature Drift
Power Supply Sensitivity
THROUGHPUT
Conversion Rate
Transient Response
AC ACCURACY
Dynamic Range
Signal-to-Noise, SNR
Spurious-Free Dynamic Range, SFDR
Total Harmonic Distortion 4, THD
Signal-to-(Noise + Distortion), SINAD
Test Conditions/Comments
Min
18
IN+ − IN−
IN+, IN−
IN+, IN−
fIN = 450 kHz
Acquisition phase
Typ
Max
Unit
Bits
−VREF
−0.1
VREF × 0.475
+VREF
VREF + 0.1
VREF × 0.525
V
V
V
dB 1
nA
18
−1
−2.25
+1.5
+2.25
VREF × 0.5
67
200
See the Analog Inputs section
−0.075
−700
VDD = 2.5 V ± 5%
VIO > 2.3 V
VIO ≤ 2.3 V
Full-scale step
0.95
±0.022
−0.6
±100
0.3
90
0
0
VREF = 5 V
fIN = 1 kHz, VREF = 5 V, TA = 25°C
fIN = 10 kHz
fIN = 10 kHz
fIN = 10 kHz, VREF = 5 V, TA = 25°C
96.5
+0.075
+700
1.33
833
290
99.7
98.5
112.5
−110.5
98
Bits
LSB 2
LSB2
LSB2
% of FS
ppm/°C
µV
ppm/°C
dB1
MSPS
kSPS
ns
dB1
dB1
dB1
dB1
dB1
All specifications expressed in decibels are referred to a full-scale range (FSR) and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
LSB means least significant bit. With the ±5 V input range, one LSB is 38.15 µV.
3
See Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.
4
Tested fully in production at fIN = 1 kHz.
1
2
Rev. C | Page 3 of 25
AD7984
Data Sheet
VDD = 2.5 V, VIO = 1.71 V to 5.5 V, REF = 5 V, TA = −40°C to +85°C, unless otherwise noted.
Table 3.
Parameter
REFERENCE
Voltage Range
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
DIGITAL INPUTS
Logic Levels
VIL
VIH
VIL
VIH
IIL
IIH
DIGITAL OUTPUTS
Data Format
Pipeline Delay
VOL
VOH
POWER SUPPLIES
VDD
VIO
Standby Current 1, 2
Power Dissipation
Energy per Conversion
TEMPERATURE RANGE 3
Specified Performance
Test Conditions/Comments
Min
Typ
Max
Unit
5.1
520
V
µA
10
2
MHz
ns
2.9
1.33 MSPS
VIO > 3 V
VIO > 3 V
VIO ≤ 3 V
VIO ≤ 3 V
–0.3
0.7 × VIO
–0.3
0.9 × VIO
−1
−1
+0.3 × VIO
VIO + 0.3
+0.1 × VIO
VIO + 0.3
+1
+1
Serial 18 bits, twos complement
Conversion results available immediately
after completed conversion
0.4
VIO − 0.3
ISINK = +500 µA
ISOURCE = −500 µA
2.375
1.71
VDD and VIO = 2.5 V
1.33 MSPS throughput
2.5
1.1
10.5
7.9
TMIN to TMAX
−40
With all digital inputs forced to VIO or GND as required.
During acquisition phase.
3
Contact an Analog Devices, Inc., sales representative for the extended temperature range.
1
2
Rev. C | Page 4 of 25
2.625
5.5
14
+85
V
V
V
V
µA
µA
V
V
V
V
mA
mW
nJ/sample
°C
Data Sheet
AD7984
TIMING SPECIFICATIONS
VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, TA = −40°C to +85°C, unless otherwise noted. See Figure 2 for load conditions.
Table 4.
Parameter 1
Throughput Rate
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Period (Chain Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 3 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (Chain Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
1
Symbol
Min
tCONV
tACQ
tCYC
tCNVH
tSCK
300
250
750
10
Typ
Max
1.33
500
Unit
MSPS
ns
ns
ns
ns
10.5
12
13
15
ns
ns
ns
ns
11.5
13
14
16
4.5
4.5
3
ns
ns
ns
ns
ns
ns
ns
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
9.5
11
12
14
ns
ns
ns
ns
10
15
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tEN
tDIS
tSSDICNV
tHSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
5
2
0
5
5
2
3
15
Timing parameters measured with respect to a falling edge are defined as triggered at x% VIO. Timing parameters measured with respect to a rising edge are defined
as triggered at y% VIO. For VIO ≤ 3 V, x = 90 and y = 10. For VIO > 3 V, x = 70 and y = 30. The minimum VIH and maximum VIL are used. See the Digital Inputs
Specifications in Table 2.
Rev. C | Page 5 of 25
AD7984
Data Sheet
VDD = 2.37 V to 2.63 V, VIO = 1.71 to 2.3 V, TA = −40°C to +125°C, unless otherwise stated. See Figure 2 for load conditions.
Table 5.
Parameter 1
Throughput Rate
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions 2
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (Chain Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
Symbol
Min
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
tDIS
tSSDICNV
tHSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
300
250
1.2
10
22
23
6
6
3
Typ
Max
833
500
14
18
21
40
20
5
10
0
5
5
2
3
22
Unit
kSPS
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Timing parameters measured with respect to a falling edge are defined as triggered at x% VIO. Timing parameters measured with respect to a rising edge are defined
as triggered at y% VIO. For VIO ≤ 3 V, x = 90 and y = 10. For VIO > 3 V, x = 70 and y = 30. The minimum VIH and maximum VIL are used. See the Digital Inputs
Specifications in Table 2.
2
The time required to clock out N bits of data, tREAD, may be greater than tACQ, depending on the magnitude of VIO. If tREAD is greater than tACQ, the throughput must be
limited to ensure that all N bits are read back from the device.
1
500µA
IOL
1.4V
TO SDO
500µA
IOH
06973-002
CL
20pF
Figure 2. Load Circuit for Digital Interface Timing
Rev. C | Page 6 of 25
Data Sheet
AD7984
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Analog Inputs
IN+, IN− to GND 1
Supply Voltage
REF, VIO to GND
VDD to GND
VDD to VIO
Digital Inputs to GND
Digital Outputs to GND
Storage Temperature Range
Junction Temperature
Lead Temperatures
Vapor Phase (60 sec)
Infrared (15 sec)
1
Rating
−0.3 V to VREF + 0.3 V or ±130 mA
−0.3 V to +6.0 V
−0.3 V to +3.0 V
+3 V to −6 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
215°C
220°C
See the Analog Inputs section for an explanation of IN+ and IN−.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC
is the junction to case thermal resistance.
Table 7. Thermal Resistance
Package Type1
RM-10
CP-10-9
1
θJA
200
48.7
θJC
44
2.96
Unit
°C/W
°C/W
Test Condition 1: thermal impedance simulated values are based on use of a
2S2P JEDEC PCB. Refer to the Ordering Guide for more information.
ESD CAUTION
Rev. C | Page 7 of 25
AD7984
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
10
VIO
VDD 2
AD7984
9
SDI
IN+ 3
TOP VIEW
(Not to Scale)
8
SCK
7
SDO
6
CNV
IN– 4
GND 5
IN+ 3
IN– 4
GND 5
06973-004
REF 1
AD7984
(EXPOSED
PAD)*
9
SDI
8
SCK
7
SDO
6
CNV
*EXPOSED PADDLE CAN BE CONNECTED
TO GROUND.
Figure 3. 10-Lead MSOP Pin Configuration
06973-005
10 VIO
REF 1
VDD 2
Figure 4. 10-Lead LFCSP Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
1
Mnemonic
REF
Type 1
AI
2
3
4
5
6
VDD
IN+
IN−
GND
CNV
P
AI
AI
P
DI
7
8
9
SDO
SCK
SDI
DO
DI
DI
10
VIO
P
1
Description
Reference Input Voltage. The REF range is 2.9 V to 5.1 V. This pin is referred to the GND pin and
should be decoupled closely to the GND pin with a 10 µF capacitor.
Power Supply.
Differential Positive Analog Input.
Differential Negative Analog Input.
Power Supply Ground.
Convert Input. This input has multiple functions. On its rising edge, it initiates the conversions
and selects the interface mode of the part: chain mode or CS mode. In CS mode, the SDO pin is
enabled when CNV is low. In chain mode, the data should be read when CNV is high.
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as
follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a
data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The
digital data level on SDI is output on SDO with a delay of 18 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can
enable the serial output signals when low. If SDI or CNV is low when the conversion is complete,
the busy indicator feature is enabled.
Input/Output Interface Digital Power. Nominally at the same supply as the host interface
(1.8 V, 2.5 V, 3 V, or 5 V).
AI = analog input, DI = digital input, DO = digital output, and P = power.
Rev. C | Page 8 of 25
Data Sheet
AD7984
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 2.5 V, REF = 5.0 V, VIO = 3.3 V.
2.0
2.0
POSITIVE DNL: +0.63LSB
NEGATIVE DNL: –0.34LSB
1.5
1.0
1.0
0.5
0.5
0
0
–0.5
–0.5
–1.0
–1.0
–1.5
–1.5
–2.0
0
65536
131072
–2.0
262144
196608
06973-038
DNL (LSB)
1.5
06973-032
INL (LSB)
POSITIVE INL: +1.07LSB
NEGATIVE INL: –0.73LSB
0
65536
131072
CODE
262144
196608
CODE
Figure 5. Integral Nonlinearity vs. Code
Figure 8. Differential Nonlinearity vs. Code
60k
60k
55354
COUNTS
32350
31003
30k
30k
20k
20k
16593
14653
0
0
0
7
326
1C
1D
1E
1F
5708
326
20
21
22
23
24
25
6
0
0
26
27
28
06973-041
5992
0
0
2
69
1D
1E
1F
20
0
1801
21
1378 37
22
23
24
25
26
27
0
0
28
29
06973-042
10k
10k
CODE IN HEX
CODE IN HEX
Figure 6. Histogram of a DC Input at the Code Center
Figure 9. Histogram of a DC Input at the Code Transition
0
100
fS = 1.33MSPS
fIN = 10kHz
–20
99
SNR = 98.2dB
THD = –110.6dB
SFDR = 112.5dB
SINAD = 98.0dB
–40
98
97
SNR (dB)
–60
–80
–100
–120
96
95
94
93
–140
–160
–180
0
100
200
300
400
500
06973-039
92
06973-033
AMPLITUDE (dB of Full Scale)
48266
40k
40k
COUNTS
48273
50k
50k
91
90
–10
600
FREQUENCY (kHz)
–9
–8
–7
–6
–5
–4
–3
INPUT LEVEL (dB of Full Scale)
Figure 7. FFT Plot
Figure 10. SNR vs. Input Level
Rev. C | Page 9 of 25
–2
–1
0
AD7984
Data Sheet
100
18
–100
17
–105
SNR
95
16
THD (dB)
90
ENOB (Bits)
SNR, SINAD (dB)
SINAD
–110
ENOB
–115
15
3.0
3.5
4.0
4.5
14
5.5
5.0
–120
2.5
06973-043
80
2.5
REFERENCE VOLTAGE (V)
06973-045
85
3.0
3.5
4.0
4.5
5.5
5.0
REFERENCE VOLTAGE (V)
Figure 11. SNR, SINAD, and ENOB vs. Reference Voltage
Figure 14. THD vs. Reference Voltage
100
–100
98
96
THD (dB)
SNR (dB)
–105
94
–110
–115
–35
–15
5
25
45
65
85
–120
–55
105
06973-046
90
–55
06973-044
92
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. SNR vs. Temperature
Figure 15. THD vs. Temperature
100
–80
–85
THD (dB)
–90
90
–95
–100
–105
85
80
1
10
100
06973-040
–110
06973-034
SINAD (dB)
95
–115
1
1000
FREQUENCY (kHz)
10
100
FREQUENCY (kHz)
Figure 13. SINAD vs. Frequency
Figure 16. THD vs. Frequency
Rev. C | Page 10 of 25
1000
Data Sheet
AD7984
2.5
2.5
IVDD
OPERATING CURRENTS (mA)
1.5
1.0
IREF
0.5
0
2.375
2.425
2.475
2.525
VDD VOLTAGE (V)
1.5
1.2
IVDD + IVIO
1.1
1.0
0.9
0.8
0.7
06973-036
STANDBY CURRENTS (mA)
1.3
0.6
–15
5
25
45
0.5
–35
–15
5
25
45
65
85
105
Figure 19. Operating Currents vs. Temperature
1.4
–35
IREF
TEMPERATURE (°C)
Figure 17. Operating Currents vs. Supply
0.5
–55
1.0
0
–55
2.625
2.575
1.5
IVIO
06973-035
IVIO
2.0
06973-037
OPERATING CURRENTS (mA)
IVDD
2.0
65
85
105
125
TEMPERATURE (°C)
Figure 18. Standby Currents vs. Temperature
Rev. C | Page 11 of 25
125
AD7984
Data Sheet
TERMINOLOGY
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 21).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified
in terms of resolution for which no missing codes are
guaranteed.
Zero Error
Zero error is the difference between the ideal midscale voltage,
that is, 0 V, from the actual voltage producing the midscale
output code, that is, 0 LSB.
Gain Error
The first transition (from 100 ... 00 to 100 ... 01) should occur at
a level ½ LSB above nominal negative full scale (−4.999981 V
for the ±5 V range). The last transition (from 011 … 10 to
011 … 11) should occur for an analog voltage 1½ LSB below
the nominal full scale (+4.999943 V for the ±5 V range). The
gain error is the deviation of the difference between the actual
level of the last transition and the actual level of the first
transition from the difference between the ideal levels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD as follows:
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
Noise-Free Code Resolution
Noise-free code resolution is the number of bits beyond which it is
impossible to distinctly resolve individual codes. It is calculated as
Noise-Free Code Resolution = log2(2N/Peak-to-Peak Noise)
and is expressed in bits.
Effective Resolution
Effective resolution is calculated as
Effective Resolution = log2(2N/RMS Input Noise)
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels. It is
measured with a signal at −60 dBF so that it includes all noise
sources and DNL artifacts.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the
Nyquist frequency, excluding harmonics and dc. The value for
SNR is expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components that are less than
the Nyquist frequency, including harmonics but excluding dc.
The value of SINAD is expressed in decibels.
Aperture Delay
Aperture delay is the measurement of the acquisition
performance and is the time between the rising edge of the
CNV input and when the input signal is held for a conversion.
Transient Response
Transient response is the time required for the ADC to accurately
acquire its input after a full-scale step function is applied.
Rev. C | Page 12 of 25
Data Sheet
AD7984
THEORY OF OPERATION
IN+
SWITCHES CONTROL
LSB
MSB
REF
131,072C
65,536C
2C
4C
SW+
C
C
BUSY
COMP
GND
131,072C
65,536C
2C
4C
CONTROL
LOGIC
C
C
MSB
OUTPUT CODE
LSB
SW–
06973-011
CNV
IN–
Figure 20. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7984 is a fast, low power, single-supply, precise, 18-bit
ADC using a successive approximation architecture and is
capable of converting 1,330,000 samples per second (1.33 MSPS).
The AD7984 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
The AD7984 can be interfaced to any 1.8 V to 5 V digital logic
family. It is available in a 10-lead MSOP or a tiny 10-lead
LFCSP that allows space savings and flexible configurations.
It is pin-for-pin-compatible with the 18-bit AD7982.
CONVERTER OPERATION
The AD7984 is a successive approximation ADC based on a
charge redistribution DAC. Figure 20 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 18 binary-weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
input of the comparator are connected to GND via SW+ and
SW−. All independent switches are connected to the analog
inputs. Therefore, the capacitor arrays are used as sampling
capacitors and acquire the analog signal on the IN+ and IN−
inputs. When the acquisition phase is complete and the CNV
input goes high, a conversion phase is initiated. When the
conversion phase begins, SW+ and SW− are opened first. The
two capacitor arrays are then disconnected from the inputs and
connected to the GND input. Therefore, the differential voltage
between the inputs IN+ and IN− captured at the end of the
acquisition phase is applied to the comparator inputs, causing
the comparator to become unbalanced. By switching each
element of the capacitor array between GND and REF, the
comparator input varies by binary-weighted voltage steps
(VREF/2, VREF/4 ... VREF/262,144). The control logic toggles these
switches, starting with the MSB, to bring the comparator back
into a balanced condition. After the completion of this process,
the part returns to the acquisition phase, and the control logic
generates the ADC output code and a busy signal indicator.
Because the AD7984 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Rev. C | Page 13 of 25
AD7984
Data Sheet
Transfer Functions
Table 9. Output Codes and Ideal Input Voltages
Analog Input
VREF = 5 V
+4.999962 V
+38.15 µV
0V
−38.15 µV
−4.999962 V
−5 V
Description
FSR − 1 LSB
Midscale + 1 LSB
Midscale
Midscale − 1 LSB
−FSR + 1 LSB
−FSR
011 ... 111
011 ... 110
011 ... 101
1
2
Digital Output
Code (Hex)
0x1FFFF1
0x00001
0x00000
0x3FFFF
0x20001
0x200002
This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
TYPICAL CONNECTION DIAGRAM
100 ... 010
100 ... 001
100 ... 000
–FSR
–FSR + 1 LSB
–FSR + 0.5 LSB
+FSR – 1 LSB
+FSR – 1.5 LSB
ANALOG INPUT
Figure 22 shows an example of the recommended connection
diagram for the AD7984 when multiple supplies are available.
06973-012
Figure 21. ADC Ideal Transfer Function
V+
REF1
2.5V
10µF2
100nF
V+
1.8V TO 5V
15Ω
0 TO VREF
100nF
REF
2.7nF
VDD
V–
AD7984
4
V+
15Ω
ADA48413
SCK
SDO
IN–
VREF TO 0
VIO
SDI
IN+
GND
3-WIRE INTERFACE
CNV
2.7nF
V–
4
NOTES
1 SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
2C
REF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
SEE RECOMMENDED LAYOUT IN FIGURE 40 AND FIGURE 41.
3 SEE DRIVER AMPLIFIER CHOICE SECTION.
4 RECOMMENDED FILTER CONFIGURATION. SEE THE ANALOG INPUTS SECTION.
Figure 22. Typical Application Diagram with Multiple Supplies
Rev. C | Page 14 of 25
06973-013
ADC CODE (TWOS COMPLEMENT)
The ideal transfer characteristic for the AD7984 is shown in
Figure 21 and Table 9.
Data Sheet
AD7984
ANALOG INPUTS
Figure 23 shows an equivalent circuit of the input structure of
the AD7984.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN−. Care must be taken to ensure that
the analog input signal does not exceed the reference input
voltage (REF) by more than 0.3 V. If the analog input signal
exceeds this level, the diodes become forward-biased and start
conducting current. These diodes can handle a forward-biased
current of 130 mA maximum. However, if the supplies of the
input buffer (for example, the supplies of the ADA4841 in
Figure 22) are different from those of REF, the analog input
signal may eventually exceed the supply rails by more than
0.3 V. In such a case (for example, an input buffer with a shortcircuit), the current limitation can be used to protect the part.
significantly affect the ac performance, especially THD. The
dc performances are less sensitive to the input impedance. The
maximum source impedance depends on the amount of THD
that can be tolerated. The THD degrades as a function of the
source impedance and the maximum input frequency.
DRIVER AMPLIFIER CHOICE
Although the AD7984 is easy to drive, the driver amplifier must
meet the following requirements:
•
The noise generated by the driver amplifier must be kept
as low as possible to preserve the SNR and transition noise
performance of the AD7984. The noise from the driver is
filtered by the AD7984 analog input circuit’s 1-pole, lowpass filter made by RIN and CIN or by the external filter, if
one is used. Because the typical noise of the AD7984 is
36.24 µV rms, the SNR degradation due to the amplifier is
REF
D1
RIN
CIN
SNR LOSS
IN+ OR IN–
D2
06973-014
CPIN
GND
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.
90
85
•
CMRR (dB)
•
75
70
1
10
100
FREQUENCY (kHz)
1000
10000
06973-015
65
60
Figure 24. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog
inputs (IN+ or IN−) can be modeled as a parallel combination
of capacitor, CPIN, and the network formed by the series connection
of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically
400 Ω and is a lumped component composed of serial resistors
and the on resistance of the switches. CIN is typically 30 pF and
is mainly the ADC sampling capacitor.
During the sampling phase, where the switches are closed, the
input impedance is limited to CPIN. RIN and CIN make a 1-pole,
low-pass filter that reduces undesirable aliasing effects and
limits noise.
When the source impedance of the driving circuit is low, the
AD7984 can be driven directly. Large source impedances
where:
f–3dB is the input bandwidth, in megahertz, of the AD7984
(10 MHz) or the cutoff frequency of the input filter, if
one is used.
N is the noise gain of the amplifier (for example, 1 in
buffer configuration).
eN is the equivalent input noise voltage of the op amp, in
nV/√Hz.
Figure 23. Equivalent Analog Input Circuit
80
36.24
= 20 log
π
36.24 2 + f −3dB (Ne N ) 2
2
For ac applications, the driver should have a THD performance commensurate with the AD7984.
For multichannel multiplexed applications, the driver
amplifier and the AD7984 analog input circuit must settle
for a full-scale step onto the capacitor array at an 18-bit level
(0.0004%, 4 ppm). In the data sheet of the amplifier, settling at
0.1% to 0.01% is more commonly specified. This may differ
significantly from the settling time at an 18-bit level and
should be verified prior to driver selection.
The Precision ADC Driver Tool can be used to model the
settling behavior and to estimate the ac performance of the
AD7984 with a selected driver and RC filter.
Table 10. Recommended Driver Amplifiers
Amplifier
ADA4805-1/
ADA4805-2
ADA4807-1/
ADA4807-2
ADA4841-1/
ADA4841-2
ADA4941-1
ADA4945-1
LTC6363
Rev. C | Page 15 of 25
Typical Application
Low noise, small size, and low power
Very low noise and high frequency
Low noise, low distortion and low power
Very low noise, low power single-to-differential
Low noise, low distortion, fully differential
Low power, low noise, fully differential
AD7984
Data Sheet
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 µF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift reference such as
the ADR435, ADR445, LTC6655, or ADR4550.
SINGLE-TO-DIFFERENTIAL DRIVER
For applications using a single-ended analog signal, either
bipolar or unipolar, the ADA4941-1 single-ended-todifferential driver allows for a differential input into the part.
The schematic is shown in Figure 25.
If desired, a reference-decoupling capacitor with values as small
as 2.2 µF can be used with a minimal impact on performance,
especially DNL.
R1 and R2 set the attenuation ratio between the input range
and the ADC range (VREF). R1, R2, and CF are chosen
depending on the desired input resistance, signal bandwidth,
antialiasing, and noise contribution. For example, for the ±10 V
range with a 4 kΩ impedance, R2 = 1 kΩ and R1 = 4 kΩ.
R3 and R4 set the common mode on the IN− input, and R5 and R6
set the common mode on the IN+ input of the ADC. The common
mode should be close to VREF/2. For example, for the ±10 V range
with a single supply, R3 = 8.45 kΩ, R4 = 11.8 kΩ, R5 = 10.5 kΩ,
and R6 = 9.76 kΩ.
R5
R6
R3
R4
+5V REF
10µF
+5.2V
100nF
REF
OUTN
15Ω
2.7nF
15Ω
IN
IN+
REF
VDD
AD7984
2.7nF
OUTP
100nF
+2.5V
IN–
Regardless, there is no need for an additional lower value
ceramic decoupling capacitor (for example, 100 nF) between
the REF and GND pins.
POWER SUPPLY
The AD7984 uses two power supply pins: a core supply (VDD)
and a digital input/output interface supply (VIO). VIO allows
direct interface with any logic between 1.8 V and 5.5 V. To
reduce the number of supplies needed, VIO and VDD can be
tied together. When VIO is greater than or equal to VDD, the
AD7984 is insensitive to power supply sequencing. In normal
operation, if the magnitude of VIO is less than the magnitude
of VDD, VIO must be applied before VDD. Additionally, it is
very insensitive to power supply variations over a wide frequency
range, as shown in Figure 26.
95
GND
FB
ADA4941
–0.2V
85
R2
Figure 25. Single-Ended-to-Differential Driver Circuit
VOLTAGE REFERENCE INPUT
80
75
70
The AD7984 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source (for
example, a reference buffer using the AD8031, the ADA4805-1,
or the ADA4807-1), a ceramic chip capacitor is appropriate for
optimum performance.
Rev. C | Page 16 of 25
65
60
1
10
100
FREQUENCY (kHz)
Figure 26. PSRR vs. Frequency
1000
06973-017
CF
PSRR (dB)
R1
06973-016
±10V,
±5V, ..
90
Data Sheet
AD7984
DIGITAL INTERFACE
Although the AD7984 has a reduced number of pins, it offers
flexibility in its serial interface modes.
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high, and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected,
the chain mode is always selected.
When in CS mode, the AD7984 is compatible with SPI, QSPI™,
digital hosts, and DSPs. In this mode, the AD7984 can use
either a 3-wire or 4-wire interface. A 3-wire interface using the
CNV, SCK, and SDO signals minimizes wiring connections
useful, for instance, in isolated applications. A 4-wire interface
using the SDI, CNV, SCK, and SDO signals allows CNV, which
initiates the conversions, to be independent of the readback
timing (SDI). This is useful in low jitter sampling or
simultaneous sampling applications.
In either mode, the AD7984 offers the option of forcing a start
bit in front of the data bits. This start bit can be used as a busy
signal indicator to interrupt the digital host and trigger the data
reading. Otherwise, without a busy indicator, the user must
timeout the maximum conversion time prior to readback.
When in chain mode, the AD7984 provides a daisy-chain feature
using the SDI input for cascading multiple ADCs on a single
data line similar to a shift register.
•
The busy indicator feature is enabled
•
Rev. C | Page 17 of 25
In CS mode if CNV or SDI is low when the ADC
conversion ends (see Figure 30 and Figure 34).
In chain mode if SCK is high during the CNV rising edge
(see Figure 38).
AD7984
Data Sheet
high for the maximum possible conversion time to avoid the
generation of the busy signal indicator. When the conversion is
complete, the AD7984 enters the acquisition phase and goes
into standby mode. When CNV goes low, the MSB is output
onto SDO. The remaining data bits are clocked by subsequent
SCK falling edges. The data is valid on both SCK edges. Although
the rising edge can be used to capture the data, a digital host using
the SCK falling edge allows a faster reading rate, provided it has
an acceptable hold time. After the 18th SCK falling edge or when
CNV goes high (whichever occurs first), SDO returns to high
impedance.
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7984 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 27, and the corresponding timing is given in
Figure 28.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. When a conversion is initiated, it continues until
completion irrespective of the state of CNV. This can be useful,
for example, to bring CNV low to select other SPI devices, such
as analog multiplexers; however, CNV must be returned high
before the minimum conversion time elapses and then held
CONVERT
DIGITAL HOST
CNV
VIO
SDI
AD7984
DATA IN
SDO
06973-018
SCK
CLK
Figure 27. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
1
2
3
16
tHSDO
18
tSCKH
tDSDO
tEN
SDO
17
D17
D16
D15
tDIS
D1
D0
Figure 28. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)
Rev. C | Page 18 of 25
06973-019
SCK
Data Sheet
AD7984
When the conversion is complete, SDO goes from high
impedance to low impedance. With a pull-up on the SDO line,
this transition can be used as an interrupt signal to initiate the
data reading controlled by the digital host. The AD7984 then
enters the acquisition phase and goes into standby mode. The
data bits are then clocked out, MSB first, by subsequent SCK
falling edges. The data is valid on both SCK edges. Although
the rising edge can be used to capture the data, a digital host
using the SCK falling edge allows a faster reading rate, provided
it has an acceptable hold time. After the optional 19th SCK
falling edge or when CNV goes high (whichever occurs first),
SDO returns to high impedance.
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7984 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 29, and the
corresponding timing is given in Figure 30.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time
elapses and then held low for the maximum possible
conversion time to guarantee the generation of the busy signal
indicator.
If multiple AD7984s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this
contention as short as possible to limit extra power dissipation.
CONVERT
VIO
CNV
AD7984
DATA IN
SDO
IRQ
SCK
06973-020
SDI
DIGITAL HOST
47kΩ
VIO
CLK
Figure 29. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
1
2
3
17
tHSDO
18
19
tSCKH
tDSDO
SDO
D17
D16
tDIS
D1
D0
Figure 30. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High)
Rev. C | Page 19 of 25
06973-021
SCK
AD7984
Data Sheet
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator. When the conversion is complete, the AD7984
enters the acquisition phase and goes into standby mode. Each
ADC result can be read by bringing its SDI input low, which
consequently outputs the MSB onto SDO. The remaining data
bits are then clocked by subsequent SCK falling edges. The data
is valid on both SCK edges. Although the rising edge can be
used to capture the data, a digital host using the SCK falling
edge allows a faster reading rate, provided it has an acceptable
hold time. After the 18th SCK falling edge or when SDI goes
high (whichever occurs first), SDO returns to high impedance
and another AD7984 can be read.
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7984s are connected
to an SPI-compatible digital host.
A connection diagram example using two AD7984s is shown in
Figure 31, and the corresponding timing is given in Figure 32.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase
and the subsequent data readback (if SDI and CNV are low,
SDO is driven low). Prior to the minimum conversion time,
SDI can be used to select other SPI devices, such as analog
multiplexers,
CS2
CS1
CONVERT
CNV
AD7984
SDO
SDI
AD7984
SCK
DIGITAL HOST
SDO
SCK
06973-022
SDI
CNV
DATA IN
CLK
Figure 31. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSSDICNV
SDI(CS1)
tHSDICNV
SDI(CS2)
tSCK
tSCKL
1
2
3
16
tHSDO
18
19
20
34
35
36
tDIS
tDSDO
tEN
SDO
17
tSCKH
D17
D16
D15
D1
D0
D17
D16
Figure 32. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing
Rev. C | Page 20 of 25
D1
D0
06973-023
SCK
Data Sheet
AD7984
multiplexers, but SDI must be returned low before the
minimum conversion time elapses and then held low for the
maximum possible conversion time to guarantee the generation
of the busy signal indicator. When the conversion is complete,
SDO goes from high impedance to low impedance. With a pullup on the SDO line, this transition can be used as an interrupt
signal to initiate the data readback controlled by the digital
host. The AD7984 then enters the acquisition phase and goes
into standby mode. The data bits are then clocked out, MSB
first, by subsequent SCK falling edges. The data is valid on both
SCK edges. Although the rising edge can be used to capture the
data, a digital host using the SCK falling edge allows a faster
reading rate, provided it has an acceptable hold time. After the
optional 19th SCK falling edge or SDI going high (whichever
occurs first), SDO returns to high impedance.
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7984 is connected
to an SPI-compatible digital host with an interrupt input and
when it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This independence is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 33, and the
corresponding timing is given in Figure 34.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase
and the subsequent data readback. (If SDI and CNV are low,
SDO is driven low.) Prior to the minimum conversion time,
SDI can be used to select other SPI devices, such as analog
CS1
CONVERT
VIO
CNV
AD7984
DATA IN
SDO
IRQ
SCK
06973-024
SDI
DIGITAL HOST
47kΩ
CLK
Figure 33. CS Mode, 4-Wire with Busy Indicator Connection Diagram
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSSDICNV
SDI
tSCK
tHSDICNV
tSCKL
1
2
3
tHSDO
17
18
19
tSCKH
tDSDO
tDIS
tEN
SDO
D17
D16
D1
Figure 34. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing
Rev. C | Page 21 of 25
D0
06973-025
SCK
AD7984
Data Sheet
subsequent data readback. When the conversion is complete,
the MSB is output onto SDO and the AD7984 enters the
acquisition phase and goes into standby mode. The remaining
data bits stored in the internal shift register are clocked by
subsequent SCK falling edges. For each ADC, SDI feeds the
input of the internal shift register and is clocked by the SCK
falling edge. Each ADC in the chain outputs its data MSB first,
and 18 × N clocks are required to read back the N ADCs. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge will allow a faster reading rate and consequently more
AD7984s in the chain, provided the digital host has an
acceptable hold time. The maximum conversion rate may be
reduced due to the total readback time.
CHAIN MODE WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7984s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7984s is shown in
Figure 35, and the corresponding timing is given in Figure 36.
When SDI and CNV are low, SDO is driven low. With SCK
low, a rising edge on CNV initiates a conversion, selects the
chain mode, and disables the busy indicator. In this mode,
CNV is held high during the conversion phase and the
CONVERT
CNV
AD7984
SDO
SDI
DIGITAL HOST
AD7984
A
DATA IN
SDO
B
SCK
SCK
06973-026
SDI
CNV
CLK
Figure 35. Chain Mode Without Busy Indicator Connection Diagram
SDIA = 0
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
tSSCKCNV
SCK
1
tHSCKCNV
2
3
16
18
17
tSSDISCK
19
20
DA17
DA16
34
35
36
D A1
DA0
tSCKH
tHSDISCK
tEN
SDOA = SDIB
DA17
DA16
DA15
DA1
DA0
DB17
DB16
DB15
DB1
DB0
SDOB
Figure 36. Chain Mode Without Busy Indicator Serial Interface Timing
Rev. C | Page 22 of 25
06973-027
tHSDO
tDSDO
Data Sheet
AD7984
completed their conversions, the SDO pin of the ADC closest
to the digital host (see the AD7984 ADC labeled C in Figure 37)
is driven high. This transition on SDO can be used as a busy
indicator to trigger the data readback controlled by the digital
host. The AD7984 then enters the acquisition phase and goes
into standby mode. The data bits stored in the internal shift
register are clocked out, MSB first, by subsequent SCK falling
edges. For each ADC, SDI feeds the input of the internal shift
register and is clocked by the SCK falling edge. Each ADC in
the chain outputs its data MSB first, and 18 × N + 1 clocks are
required to read back the N ADCs. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge allows a faster reading rate and, consequently, more
AD7984s in the chain, provided the digital host has an
acceptable hold time.
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7984s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications
or for systems with a limited interfacing capacity. Data readback
is analogous to clocking a shift register.
A connection diagram example using three AD7984s is shown
in Figure 37, and the corresponding timing is given in Figure 38.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
CONVERT
SDI
CNV
AD7984
SDO
SDI
CNV
AD7984
SDO
SDI
AD7984
B
A
SCK
DIGITAL HOST
SDO
DATA IN
C
SCK
SCK
IRQ
06973-028
CNV
CLK
Figure 37. Chain Mode with Busy Indicator Connection Diagram
tCYC
ACQUISITION
tCONV
tACQ
ACQUISITION
CONVERSION
tSSCKCNV
SCK
tSCKH
1
2
tSSDISCK
tHSCKCNV
tEN
SDOA = SDIB
3
4
tSCK
17
18
20
21
35
36
37
38
39
tSCKL
tHSDISCK
DA17 DA16 DA15
19
D A1
SDOB = SDIC
55
tDSDOSDI
tDSDOSDI
DB17 DB16 DB15
DB1
DB0 DA17 DA16
DA1
DA0
DC17 DC16 DC15
DC1
DC0 DB17 DB16
DB1
DB0 DA17 DA16
tDSDOSDI
SDOC
54
DA0
tHSDO
tDSDO
tDSDOSDI
53
tDSDOSDI
Figure 38. Chain Mode with Busy Indicator Serial Interface Timing
Rev. C | Page 23 of 25
DA 1
DA0
06973-029
CNV = SDIA
AD7984
Data Sheet
APPLICATION HINTS
LAYOUT
The printed circuit board (PCB) that houses the AD7984
should be designed so that the analog and digital sections are
separated and confined to certain areas of the board. The
pinout of the AD7984, with its analog signals on the left side
and its digital signals on the right side, eases this task.
AD7984
At least one ground plane should be used. The ground plane
can be common or split between the digital and analog sections.
In the latter case, the planes should be joined underneath the
AD7984.
06973-030
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7984 is used as a shield. Fast switching signals, such as CNV
or clocks, should not run near analog signal paths. Crossover of
digital and analog signals should be avoided.
Figure 39. Example Layout of the AD7984 (Top Layer)
The AD7984 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, ideally right up against, the REF and
GND pins and connecting them with wide, low impedance traces.
Finally, the power supplies VDD and VIO of the AD7984
should be decoupled with ceramic capacitors, typically 100 nF,
placed close to the AD7984 and connected using short, wide
traces to provide low impedance paths and to reduce the effect
of glitches on the power supply lines.
06973-031
An example of layout following these rules is shown in
Figure 39 and Figure 40.
EVALUATING THE AD7984 PERFORMANCE
Other recommended layouts for the AD7984 are outlined
in the documentation of the evaluation board for the AD7984
(EVAL-AD7984SDZ). The evaluation board package includes
a fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the
EVAL-SDP-CB1Z.
Rev. C | Page 24 of 25
Figure 40. Example Layout of the AD7984 (Bottom Layer)
Data Sheet
AD7984
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
5.15
4.90
4.65
6
1
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.30
0.15
0.70
0.55
0.40
0.23
0.13
6°
0°
091709-A
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 41. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
DETAIL A
(JEDEC 95)
2.48
2.38
2.23
3.10
3.00 SQ
2.90
0.50 BSC
10
6
PIN 1
INDICATOR
AREA
1.74
1.64
1.49
EXPOSED
PAD
0.50
0.40
0.30
1
5
BOTTOM VIE W
PKG-004362
0.80
0.75
0.70
SEATING
PLANE
SIDE VIEW
0.30
0.25
0.20
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 MIN
P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
08-20-2018-C
TOP VIEW
0.20 REF
Figure 42. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2, 3
AD7984BRMZ
AD7984BRMZ-RL7
AD7984BCPZ-RL7
AD7984BCPZ-RL
EVAL-AD7984SDZ
EVAL-SDP-CB1Z
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
10-Lead MSOP
10-Lead MSOP
10-Lead LFCSP_WD
10-Lead LFCSP_WD
Evaluation Board
Evaluation Board
Package Option
RM-10
RM-10
CP-10-9
CP-10-9
Ordering Quantity
Tube, 50
Reel, 1,000
Reel, 1,500
Reel, 5,000
Branding
C60
C60
C60
C60
Z = RoHS compliant part.
The EVAL-AD7984SDZ board can be used as a standalone evaluation board or in conjunction with the EVAL-SDP-CB1Z for evaluation/demonstration purposes.
3
The EVAL-SDP-CB1Z board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the SD designator.
1
2
©2007–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06973-7/20(C)
Rev. C | Page 25 of 25
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