AD8000

1.5 GHz Ultrahigh Speed Op Amp AD8000 FEATURES High speed 1.5 GHz, −3 dB bandwidth (G = +1) 650 MHz, full power bandwidth (G = +2, VO = 2 V p-p) Slew rate: 4100 V/µs 0.1% settling time: 12 ns Excellent video specifications 0.1 dB flatness: 170 MHz Differential gain: 0.02% Differential phase: 0.01° Output overdrive recovery: 22 ns Low noise: 1.6 nV/√Hz input voltage noise Low distortion over wide bandwidth 75 dBc SFDR @ 20 MHz 62 dBc SFDR @ 50 MHz Input offset voltage: 1 mV typ High output current: 100 mA Wide supply voltage range: 4.5 V to 12 V Supply current: 13.5 mA Power-down mode CONNECTION DIAGRAMS AD8000 POWER DOWN 1 FEEDBACK 2 –IN 3 +IN 4 8 +VS 7 OUTPUT 6 NC 5 –VS 05321-001 NC = NO CONNECT Figure 1. 8-Lead AD8000, 3 mm × 3 mm LFCSP (CP-8-2) FEEDBACK –IN +IN –VS 1 2 3 4 AD8000 8 7 6 5 POWER DOWN +VS OUTPUT NC 05321-002 NC = NO CONNECT Figure 2. 8-Lead AD8000 SOIC/EP (RD-8-1) APPLICATIONS Professional video High speed instrumentation Video switching IF/RF gain stage CCD imaging 3 2 1 VS = ±5V RL = 150Ω VOUT = 2V p-p NORMALIZED GAIN (dB) 0 –1 –2 –3 –4 –5 –6 05321-003 GENERAL DESCRIPTION The AD8000 is an ultrahigh speed, high performance, current feedback amplifier. Using ADI’s proprietar y eXtra Fast Complementar y Bipolar (XFCB) process, the amplifier can achieve a small signal bandwidth of 1.5 GHz and a slew rate of 4100 V/µs. The AD8000 has low spurious-free dynamic range (SFDR) of 75 dBc @ 20 MHz and input voltage noise of 1.6 nV/√Hz. The AD8000 can drive over 100 mA of load current with minimal distortion. The amplifier can operate on +5 V to ±6 V. These specifications make the AD8000 ideal for a variety of applications, including high speed instrumentation. With a differential gain of 0.02%, differential phase of 0.01°, and 0.1 dB flatness out to 170 MHz, the AD8000 has excellent video specifications, which ensure that even the most demanding video systems maintain excellent fidelity. G = +2, RF = 432Ω –7 1 10 100 FREQUENCY (MHz) 1000 Figure 3. Large Signal Frequency Response The AD8000 power-down mode reduces the supply current to 1.3 mA. The amplifier is available in a tiny 8-lead LFCSP package, as well as in an 8-lead SOIC package. The AD8000 is rated to work over the extended industrial temperature range (−40°C to +125°C). A triple version of the AD8000 (AD8003) is underdevelopment. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved. AD8000 TABLE OF CONTENTS Specifications with ±5 V Supply ..................................................... 3 Specifications with +5 V Supply ..................................................... 4 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution .................................................................................. 5 Typical Performance Characteristics ............................................. 6 Test Circuits ..................................................................................... 13 Applications ..................................................................................... 14 Circuit Configurations ............................................................... 14 Video Line Driver ....................................................................... 14 Low Distortion Pinout ............................................................... 15 Exposed Paddle........................................................................... 15 Printed Circuit Board Layout ................................................... 15 Signal Routing............................................................................. 15 Power Supply Bypassing ............................................................ 15 Grounding ................................................................................... 16 Outline Dimensions ....................................................................... 17 Ordering Guide .......................................................................... 17 REVISION HISTORY 1/05—Rev. 0: Initial Version Rev. 0 | Page 2 of 20 AD8000 SPECIFICATIONS WITH ±5 V SUPPLY At TA = 25°C, VS = ±5 V, RL = 150 Ω, Gain = +2, RF = RG = 432 Ω, unless otherwise noted. Exposed paddle should be connected to ground. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE Second/Third Harmonic Second/Third Harmonic Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current (Enabled) Transimpedance INPUT CHARACTERISTICS Noninverting Input Impedance Input Common-Mode Voltage Range Common-Mode Rejection Ratio Overdrive Recovery POWER DOWN PIN Power-Down Input Voltage Turn-Off Time Turn-On Time Input Bias Current Enabled Power-Down OUTPUT CHARACTERISTICS Output Voltage Swing Output Voltage Swing Linear Output Current Overdrive Recovery POWER SUPPLY Operating Range Quiescent Current Quiescent Current (Power-Down) Power Supply Rejection Ratio Conditions G = +1, VO = 0.2 V p-p, SOIC/LFCSP G = +2, VO = 2 V p-p, SOIC/LFCSP VO = 2 V p-p, SOIC/LFCSP G = +2, VO = 4 V step G = +2, VO = 2 V step VO = 2 V p-p, f = 5 MHz, LFCSP only VO = 2 V p-p, f = 20 MHz, LFCSP only f = 100 kHz f = 100 kHz, −IN f = 100 kHz, +IN NTSC, G = +2 NTSC, G = +2 Min Typ 1580/1350 650/610 190/170 4100 12 86/89 75/79 1.6 26 3.4 0.02 0.01 1 11 −5 −3 890 2/3.6 −3.5 to +3.5 −54 30 < +VS – 3.1 > +VS – 1.9 150 300 10 +4 +45 1600 Max Unit MHz MHz MHz V/µs ns dBc dBc nV/√Hz pA/√Hz pA/√Hz % Degree mV µV/°C µA µA kΩ MΩ/pF V dB ns V V ns ns +IB −IB 570 VCM = ±2.5 V G = +1, f = 1 MHz, triangle wave Power-down Enabled 50% of power-down voltage to 10% of VOUT final, VIN = 0.3 V p-p 50% of power-down voltage to 90% of VOUT final, VIN = 0.3 V p-p −52 −56 −1.1 −300 RL = 100 Ω RL = 1 kΩ VO = 2 V p-p, second HD < −50 dBc G = + 2, f = 1 MHz, triangle wave G = +2, VIN = 2.5 V to 0 V step ±3.7 ±3.9 +0.17 −235 ±3.9 ±4.1 100 45 22 +1.4 −160 µA µA V V mA ns ns −PSRR/+PSRR 4.5 12.7 1.1 −56/−61 13.5 1.3 −59/−63 12 14.3 1.65 V mA mA dB Rev. 0 | Page 3 of 20 AD8000 SPECIFICATIONS WITH +5 V SUPPLY At TA = 25°C, VS = +5 V, RL = 150 Ω, Gain = +2, RF = RG = 432 Ω, unless otherwise noted. Exposed paddle should be connected to ground. Table 2. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Conditions G = +1, VO = 0.2 V p-p G = +2, VO = 2 V p-p G = +10, VO = 0.2 V p-p VO = 0.2 V p-p VO = 2 V p-p G = +2, VO = 2 V step G = +2, VO = 2 V step VO = 2 V p-p, 5 MHz, LFCSP only VO = 2 V p-p, 20 MHz, LFCSP only f = 100 kHz f = 100 kHz, −IN f = 100 kHz, +IN NTSC, G = +2 NTSC, G = +2 Min Typ 980 477 328 136 136 2700 16 71/71 60/62 1.6 26 3.4 0.01 0.06 1.3 18 −5 −1 800 2/3.6 1.5 to 3.6 −52 60 < +VS − 3.1 > +VS − 1.9 200 300 10 +3 +45 1500 Max Unit MHz MHz MHz MHz MHz V/µs ns dBc dBc nV/√Hz pA/√Hz pA/√Hz % Degree mV µV/°C µA µA kΩ MΩ/pF V dB ns V V ns ns Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE Second/Third Harmonic Second/Third Harmonic Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current (Enabled) Transimpedance INPUT CHARACTERISTICS Noninverting Input Impedance Input Common-Mode Voltage Range Common-Mode Rejection Ratio Overdrive Recovery POWER DOWN PIN Power-Down Input Voltage Turn-Off Time Turn-On Time Input Current Enabled Power-Down OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Overdrive Recovery POWER SUPPLY Operating Range Quiescent Current Quiescent Current (Power-Down) Power Supply Rejection Ratio +IB −IB 440 VCM = ±2.5 V G = +1, f = 1 MHz, triangle wave Power-down Enable 50% of power-down voltage to 10% of VOUT final, VIN = 0.3 V p-p 50% of power-down voltage to 90% of VOUT final, VIN = 0.3 V p-p −51 −54 −1.1 −50 RL = 100 Ω R L = 1 kΩ VO = 2 V p-p, second HD < −50 dBc G = +2, f = 100 kHz, triangle wave 1.1 to 3.9 1 to 3.1 +0.17 −40 1.05 to 4.1 0.85 to 4.15 70 65 +1.4 −30 µA µA V V mA ns −PSRR/+PSRR 4.5 11 0.7 −55/−60 12 0.95 −57/−62 12 13 1.25 V mA mA dB Rev. 0 | Page 4 of 20 AD8000 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage Power Dissipation Common-Mode Input Voltage Differential Input Voltage Exposed Paddle Voltage Storage Temperature Operating Temperature Range Lead Temperature Range (Soldering, 10 sec) Junction Temperature Rating 12.6 V See Figure 4 −VS − 0.7 V to +VS + 0.7 V ±VS −VS −65°C to +125°C −40°C to +125°C 300°C 150°C The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the die due to the AD8000 drive at the output. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). PD = Quiescent Power + (Total Drive Power – Load Power) ⎛V V PD = (VS × I S ) + ⎜ S × OUT ⎜2 RL ⎝ ⎞ VOUT 2 ⎟– ⎟ RL ⎠ Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only ; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RMS output voltages should be considered. If RL is referenced to −VS, as in single-supply operation, the total drive power is VS × IOUT. If the rms signal levels are indeterminate, consider the worst case, when VOUT = VS/4 for RL to midsupply. PD = (VS × I S ) + (VS / 4 )2 RL THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, θJA is specified for device soldered in the circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type SOIC-8 3 mm × 3 mm LFCSP θJA 80 93 θJC 30 35 Unit °C/W °C/W In single-supply operation with RL referenced to −VS, worst case is VOUT = VS/2. Airflow increases heat dissipation, effectively reducing θJA. Also, more metal directly in contact with the package leads and exposed paddle from metal traces, through holes, ground, and power planes reduces θJA. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the exposed paddle SOIC (80°C/W) and the LFCSP (93°C/W) package on a JEDEC standard 4-layer board. θJA values are approximations. 3.0 Maximum Power Dissipation The maximum safe power dissipation for the AD8000 is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the glass transition temperature, the properties of the plastic change. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8000. Exceeding a junction temperature of 175°C for an extended period of time can result in changes in silicon devices, potentially causing degradation or loss of functionality. MAXIMUM POWER DISSIPATION (W) 2.5 2.0 SOIC 1.5 LFCSP 1.0 0.5 05321-063 0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120 AMBIENT TEMPERATURE (°C) Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation and loss of functionality. Rev. 0 | Page 5 of 20 AD8000 TYPICAL PERFORMANCE CHARACTERISTICS 3 2 1 VS = ±5V RL = 150Ω VOUT = 200mV p-p 9 G = +1, RF = 432Ω RF = 392Ω 6 NORMALIZED GAIN (dB) 0 G = +2, RF = 432Ω, RG = 432Ω GAIN (dB) –1 –2 –3 –4 3 RF = 432Ω RF = 487Ω G = +10, RF = 357Ω, RG = 40.2Ω 0 VS = ±5V G = +2 RL = 150Ω VOUT = 200mV p-p LFCSP 1 10 100 FREQUENCY (MHz) 1000 –5 –6 –7 1 10 100 FREQUENCY (MHz) 1000 05321-006 –3 Figure 5. Small Signal Frequency Response vs. Various Gains 3 2 1 NORMALIZED GAIN (dB) 9 Figure 8. Small Signal Frequency Response vs. RF VS = ±5V RL = 150Ω VOUT = 200mV p-p G = –1, RF = RG = 249Ω RF = 392Ω 6 0 –2 –3 –4 G = –10, RF = 432Ω, RG = 43.2Ω GAIN (dB) –1 RF = 432Ω 3 RF = 487Ω 0 –5 –6 –7 1 10 100 FREQUENCY (MHz) 1000 05321-007 –3 1 10 100 FREQUENCY (MHz) 1000 Figure 6. Small Signal Frequency Response vs. Various Gains Figure 9. Large Signal Frequency Response vs. RF 3 2 1 NORMALIZED GAIN (dB) 1000 VS = ±5V RL = 150Ω VOUT = 2V p-p G = +1, RF = 432Ω VS = ±5V RL = 100Ω 200 150 TRANSIMPEDANCE (kΩ) 100 PHASE (Degrees) 05321-027 0 –1 –2 –3 –4 –5 –6 –7 1 10 100 FREQUENCY (MHz) 05321-008 100 G = +4, RF = 357Ω, RG = 121Ω G = +10, RF = 357Ω, RG = 40.2Ω G = +2, RF = RG = 432Ω 10 TZ PHASE 50 0 1 50 1000 0.1 0.1 1 10 100 1000 100 10000 FREQUENCY (MHz) Figure 7. Large Signal Frequency Response vs. Various Gains Figure 10. Transimpedance and Phase vs. Frequency Rev. 0 | Page 6 of 20 05321-012 G = –2, RF = 432Ω, RG = 215Ω VS = ±5V G = +2 RL = 150Ω VOUT = 2V p-p LFCSP 05321-011 AD8000 3 2 1 0 9 RL = 1kΩ G = +1 RF = 432Ω VOUT = 200mV p-p LFCSP VS = +5V, RS = 0Ω 6 VS = ±5V, RS = 0Ω GAIN (dB) –1 –2 –3 –4 –5 –6 –7 0.1 GAIN (dB) 3 –40°C VS = ±5V G = +2 RL = 150Ω VOUT = 200mV p-p LFCSP 1 10 100 FREQUENCY (MHz) VS = +5V, RS = 50Ω 0 VS = ±5V, RS = 50Ω 05321-010 +25°C 1000 –3 1 10 FREQUENCY (MHz) 100 1000 Figure 11. Small Signal Frequency Response vs. Supply Voltage Figure 14. Small Signal Frequency Response vs. Temperature 9 RL = 150Ω G = +1 RF = 432Ω VOUT = 200mV p-p LFCSP 9 6 3 VS = ±5V 6 +25°C GAIN (dB) GAIN (dB) –40°C 3 0 VS = +5V –3 0 –6 05321-009 –9 1 10 100 FREQUENCY (MHz) 1000 –3 1 10 100 FREQUENCY (MHz) 1000 Figure 12. Small Signal Frequency Response vs. Supply Voltage Figure 15. Small Signal Frequency Response vs. Temperature 6.5 6.4 6.3 6.2 VS = ±5V RL = 150Ω VOUT = 2V p-p G = +2 RF = 432Ω 9 6 GAIN (dB) SOIC 6.0 5.9 LFCSP 5.8 GAIN (dB) 6.1 3 –40°C +25°C 0 VS = ±5V G = +2 RL = 150Ω VOUT = 2V p-p LFCSP 1 10 5.7 5.6 5.5 1 10 FREQUENCY (MHz) 100 05321-013 –3 100 FREQUENCY (MHz) 1000 Figure 13. 0.1 dB Flatness Figure 16. Large Signal Frequency Response vs. Temperature Rev. 0 | Page 7 of 20 05321-016 +125°C 05321-015 VS = ±5V G = +2 RL = 1kΩ VOUT = 200mV p-p LFCSP +125°C 05321-014 +125°C AD8000 9 VOUT = 1V p-p 6 –40 –50 –60 DISTORTION (dBc) –70 SECOND HD –80 –90 –100 05321-017 05321-042 VS = ±5V VOUT = 2V p-p G = +1 RL = 1kΩ LFCSP GAIN (dB) 3 VOUT = 2V p-p THIRD HD 0 VS = ±5V G = +2 RL = 150Ω LFCSP 1 10 VOUT = 4V p-p –110 –120 1 10 FREQUENCY (MHz) –3 100 FREQUENCY (MHz) 1000 100 Figure 17. Large Signal Frequency Response vs. Various Outputs Figure 20. Harmonic Distortion vs. Frequency –40 –50 –60 VS = ±5V VOUT = 2V p-p G = +1 RL = 150Ω LFCSP DISTORTION (dBc) –20 –30 –40 SECOND HD –50 –60 –70 THIRD HD –80 05321-040 05321-041 VS = ±5V VOUT = 4V p-p G = +1 RL = 1kΩ LFCSP DISTORTION (dBc) –70 THIRD HD –80 –90 –100 –110 –120 1 10 FREQUENCY (MHz) SECOND HD –90 –100 1 10 FREQUENCY (MHz) 100 100 Figure 18. Harmonic Distortion vs. Frequency –40 –50 –60 –40 Figure 21. Harmonic Distortion vs. Frequency VS = ±5V G = +10 VOUT = 2V p-p RL = 1kΩ LFCSP DISTORTION (dBc) –50 VS = ±5V VOUT = 2V p-p G = +2 RL = 150Ω LFCSP SECOND HD DISTORTION (dBc) –60 –70 –80 –90 –100 SECOND HD THIRD HD SOIC SECOND HD –70 –80 –90 05321-039 LFCSP THIRD HD SOIC THIRD HD 05321-043 –110 –120 1 10 FREQUENCY (MHz) –100 1 10 FREQUENCY (MHz) 100 100 Figure 19. Harmonic Distortion vs. Frequency Figure 22. Harmonic Distortion vs. Frequency Rev. 0 | Page 8 of 20 AD8000 –20 –30 –40 DISTORTION (dBc) –20 VS = 5V VOUT = 2V p-p G = +2 RL = 150Ω LFCSP –30 –40 SECOND HD DISTORTION (dBc) VS = ±2.5V VOUT = 2V p-p G = –1 RL = 150Ω LFCSP –50 –60 –70 –80 –90 –100 –110 1 10 FREQUENCY (MHz) 05321-044 –50 –60 –70 –80 –90 –100 –110 –120 1 10 FREQUENCY (MHz) 05321-048 THIRD HD SECOND HD THIRD HD 100 100 Figure 23. Harmonic Distortion vs. Frequency Figure 26. Harmonic Distortion vs. Frequency –20 –30 –40 DISTORTION (dBc) –20 VS = 5V VOUT = 2V p-p G = +2 RL = 1kΩ LFCSP DISTORTION (dBc) –30 –40 –50 VS = 5V VOUT = 2V p-p G = –1 RL = 1kΩ LFCSP THIRD HD –50 –60 –70 –80 THIRD HD –60 –70 –80 –90 –100 SECOND HD SECOND HD 05321-045 –110 –120 1 10 FREQUENCY (MHz) –100 1 10 FREQUENCY (MHz) 100 100 Figure 24. Harmonic Distortion vs. Frequency –20 –30 –40 DISTORTION (dBc) –40 –50 Figure 27. Harmonic Distortion vs. Frequency VS = ±5V VOUT = 2V p-p G = +2 RL = 1kΩ LFCSP DISTORTION (dBc) –50 –60 –70 –80 –90 –100 –110 –120 1 10 FREQUENCY (MHz) 05321-047 –60 VS = ±5V VOUT = 2V p-p G = –1 RL = 150Ω LFCSP SECOND HD SECOND HD –70 –80 –90 THIRD HD THIRD HD –110 1 10 FREQUENCY (MHz) 100 100 Figure 25. Harmonic Distortion vs. Frequency Figure 28. Harmonic Distortion vs. Frequency Rev. 0 | Page 9 of 20 05321-050 –100 05321-049 –90 AD8000 –40 –50 –60 DISTORTION (dBc) –70 –80 THIRD HD –90 –100 05321-051 VS = ±5V VOUT = 2V p-p G = –1 RL = 1kΩ LFCSP SECOND HD –10 –15 –20 –25 –30 VS = ±5V VIN = 2V p-p RL = 100Ω G = +1 RF = 432Ω –PSRR PSRR (dB) –35 –40 –45 –50 –55 –60 –65 –70 –75 05321-021 +PSRR –110 –120 1 10 FREQUENCY (MHz) 100 0.1 1 10 FREQUENCY (MHz) 100 Figure 29. Harmonic Distortion vs. Frequency 1k VS = ±5V VIN = 0.2V p-p RF = 432Ω LFCSP Figure 32. Power Supply Rejection Ratio (PSRR) vs. Frequency –25 –30 –35 100 VS = ±5V VIN = 1V p-p RL = 100Ω LFCSP IMPEDANCE (Ω) CMRR (dB) G = +1 OR G = +2 05321-023 10 –40 –45 –50 –55 05321-031 1 0.1 –60 –65 0.1 0.01 0.1 1 10 FREQUENCY (MHz) 100 1000 1 10 FREQUENCY (MHz) 100 1000 Figure 30. Output Impedance vs. Frequency 2.65 G = +1 2.60 G = +2 Figure 33. Common-Mode Rejection Ratio vs. Frequency 0.175 0.150 0.125 0.100 0.075 RESPONSE (V) G = +1 RESPONSE (V) 2.55 0.050 0.025 0 –0.025 –0.050 –0.075 G = +2 2.50 2.45 VS = 5V RF = 432Ω RS = 0Ω RL = 100Ω 0 5 10 15 20 25 TIME (ns) 30 35 40 45 –0.100 05321-072 2.40 2.35 –0.150 –0.175 0 5 10 15 20 25 TIME (ns) 30 35 50 40 45 50 Figure 31. Small Signal Transient Response Figure 34. Small Signal Transient Response Rev. 0 | Page 10 of 20 05321-066 –0.125 VS = ±5V RF = 432Ω RS = 0Ω RL = 100Ω AD8000 1.75 1.50 1.25 1.00 G = +1 5 VS = ±5V, VIN 4 3 VS = ±5V, VOUT OUTPUT VOLTAGE (V) 0.75 RESPONSE (V) 2 1 0 –1 –2 –3 VS = ±2.5V, VIN VS = ±2.5V, VOUT 0.50 0.25 0 –0.25 –0.50 –0.75 –1.00 –1.25 –1.50 –1.75 0 5 10 15 20 25 TIME (ns) 30 35 VS = ±5V RF = 432Ω RS = 0Ω RL = 100Ω 40 45 G = +2 05321-067 –4 –5 0 50 200 400 600 800 1000 TIME (ns) Figure 35. Large Signal Transient Response Figure 38. Input Overdrive 0.5 0.4 0.3 VIN 6 G = +2 5 4 3 VS = ±5V, 2 × VIN VS = ±5V, VOUT SETTLING TIME (%) 0.2 0.1 0 –0.1 –0.2 –0.3 1V OUTPUT VOLTAGE (V) 2 1 0 –1 –2 –3 –4 VS = ±2.5V, VOUT G = +2 RL = 150Ω RF = 432Ω 0 200 400 600 800 VS = ±2.5V, 2 × VIN 05321-068 –0.4 t = 0s –0.5 –5 –4 –3 –2 –1 VCM (V) 0 1 5ns/DIV 2 3 –5 –6 1000 TIME (ns) Figure 36. Settling Time 6k G = +2 RF = 432Ω RL = 150Ω SOIC, VS = ±5V Figure 39. Output Overdrive 100 VS = ±5V G = +10 RF = 432Ω RN = 47.5Ω 10 4k 3k LFCSP, VS = ±5V SOIC, VS = +5V LFCSP, VS = +5V 2k INPUT VOLTAGE NOISE (nV/ Hz) 5k SR (V/µs) 1 1k 05321-018 0 0 1 2 3 4 5 6 7 VOUT (V p-p) 0.1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 37. Slew Rate vs. Output Level Figure 40. Input Voltage Noise Rev. 0 | Page 11 of 20 05321-058 05321-020 05321-019 G = +1 RL = 150Ω RF = 432Ω AD8000 1000 VS = ±5V 0 –5 INPUT CURRENT NOISE (pA/ Hz) –10 100 INVERTING CURRENT NOISE, RF = 1kΩ –15 –20 10 VS = ±5V VS = +5V IB (µA) NONINVERTING CURRENT NOISE, RF = 432Ω 05321-055 –25 –30 –35 1 –40 –45 –50 –5 –4 –3 –2 –1 0 VCM (V) 1 2 3 4 5 05321-070 0.1 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) Figure 41. Input Current Noise 20 15 10 5 VS = ±5V Figure 44. Input Bias Current vs. Common-Mode Voltage –5 –10 –15 –20 S22 (dB) RBACK TERM = 50 VS = ±5V G = +2 POUT = –10dBm SOIC VOS (mV) –25 –30 –35 0 –5 –10 05321-024 –40 VS = +5V –5 –4 –3 –2 –1 0 VCM (V) 1 2 3 4 5 –45 –50 10 100 FREQUENCY (MHz) –20 1000 Figure 42. Input VOS vs. Common-Mode Voltage 25 20 15 10 S11 (dB) Figure 45. Output Voltage Standing Wave Ratio (S22) –5 –10 –15 G = +2 –20 –25 G = +1 –30 –35 G = +10 5 IB (µA) 0 –5 –10 –15 –20 –25 –5 VS = ±5V VS = +5V 05321-069 –40 –45 –50 10 100 –4 –3 –2 –1 0 VOUT (V) 1 2 3 4 5 1000 FREQUENCY (MHz) Figure 43. Input Bias Current vs. Output Voltage Figure 46. Input Voltage Standing Wave Ratio (S11) Rev. 0 | Page 12 of 20 05321-064 INPUT RS = 0Ω VS = ±5V POUT = –10dBm SOIC 05321-065 –15 AD8000 TEST CIRCUITS +VS 10µF RF 432Ω 50Ω TRANSMISSION LINE VIN 60.4Ω 200Ω 200Ω 0.1µF 10µF –VS 05321-028 0.1µF 432Ω AD8000 49.9Ω 50Ω TRANSMISSION LINE 49.9Ω Figure 47. CMRR VP = VS + VIN 50Ω TRANSMISSION LINE TERMINATION 50Ω 49.9Ω AD8000 49.9Ω 50Ω TRANSMISSION LINE 49.9Ω TERMINATION 50Ω 0.1µF RF 432Ω RG 432Ω 10µF 05321-029 –VS Figure 48. Positive PSRR +VS 10µF 0.1µF 50Ω TRANSMISSION LINE TERMINATION 50Ω AD8000 49.9Ω 50Ω TRANSMISSION LINE 49.9Ω TERMINATION 50Ω RF 432Ω RG 432Ω 49.9Ω VN = –VS + VIN Figure 49. Negative PSRR Rev. 0 | Page 13 of 20 05321-030 AD8000 APPLICATIONS All current feedback amplifier operational amplifiers are affected by stray capacitance at the inverting input pin. As a practical consideration, the higher the stray capacitance on the inverting input to ground, the higher RF needs to be to minimize peaking and ringing. +VS RF FB – +V VO VO RL 10µF + 0.1µF VIN RG AD8000 + –V 0.1µF CIRCUIT CONFIGURATIONS Figure 50 and Figure 51 show typical schematics for noninverting and inverting configurations. For current feedback amplifiers, the value of feedback resistance determines the stability and bandwidth of the amplifier. The optimum performance values are shown in Table 5 and should not be deviated from by more than ±10% to ensure stable operation. Figure 8 shows the influence var ying RF has on bandwidth. In noninverting unity-gain configurations, it is recommended that an RS of 50 Ω be used, as shown in Figure 50. Table 5 provides a quick reference for the circuit values, gain, and output voltage noise. +VS RF FB – +V VO 0.1µF VO RL 10µF + 0.1µF RG RS 10µF + 05321-036 –VS Figure 51. Inverting Configuration VIDEO LINE DRIVER The AD8000 is designed to offer outstanding performance as a video line driver. The important specifications of differential gain (0.02%), differential phase (0.01°), and 650 MHz bandwidth at 2 V p-p meet the most exacting video demands. Figure 52 shows a typical noninverting video driver with a gain of +2. 432Ω 432Ω +VS 4.7µF + FB 0.1µF 75Ω 75Ω CABLE VOUT 0.1µF 75Ω AD8000 + –V VIN AD8000 + 75Ω CABLE VIN 75Ω –VS 10µF + 4.7µF 05321-071 + –VS NONINVERTING 05321-035 Figure 52. Video Line Driver Figure 50. Noninverting Configuration Table 5. Typical Values (LFCSP/SOIC) Component Values (Ω) RG RF 432 --432 432 357 120 357 40 −3 dB SS Bandwidth (MHz) LFCSP SOIC 1380 1580 600 650 550 550 350 365 −3 dB LS Bandwidth (MHz) LFCSP SOIC 550 600 610 650 350 350 370 370 Slew Rate (V/µsec) 2200 3700 3800 3200 Output Noise (nV/√Hz) 10.9 11.3 10 18.4 Total Output Noise Including Resistors (nV/√Hz) 11.2 11.9 12 19.9 Gain 1 2 4 10 Rev. 0 | Page 14 of 20 AD8000 LOW DISTORTION PINOUT The AD8000 LFCSP features ADI’s new low distortion pinout. The new pinout lowers the second harmonic distortion and simplifies the circuit layout. The close proximity of the noninverting input and the negative supply pin creates a source of second harmonic distortion. Physical separation of the noninverting input pin and the negative power supply pin reduces this distortion significantly, as seen in Figure 22. By providing an additional output pin, the feedback resistor can be connected directly across Pin 2 and Pin 3. This greatly simplifies the routing of the feedback resistor and allows a more compact circuit layout, which reduces its size and helps to minimize parasitics and increase stability. The SOIC also features a dedicated feedback pin. The feedback pin is brought out on Pin 1, which is typically a No Connect on standard SOIC pinouts. Existing applications that use the standard SOIC pinout can take full advantage of the performance offered by the AD8000. For drop-in replacements, ensure that Pin 1 is not connected to ground or to any other potential because this pin is connected internally to the output of the amplifier. For existing designs, Pin 6 can still be used for the feedback resistor. PRINTED CIRCUIT BOARD LAYOUT Laying out the printed circuit board (PCB) is usually the last step in the design process and often proves to be one of the most critical. A brilliant design can be rendered useless because of a poor or sloppy layout. Since the AD8000 can operate into the RF frequency spectrum, high frequency board layout considerations must be taken into account. The PCB layout, signal routing, power supply bypassing, and grounding all must be addressed to ensure optimal performance. SIGNAL ROUTING The AD8000 LFCSP features the new low distortion pinout with a dedicated feedback pin and allows a compact layout. The dedicated feedback pin reduces the distance from the output to the inverting input, which greatly simplifies the routing of the feedback network. To minimize parasitic inductances, ground planes should be used under high frequency signal traces. However, the ground plane should be removed from under the input and output pins to minimize the formation of parasitic capacitors, which degrades phase margin. Signals that are susceptible to noise pickup should be run on the internal layers of the PCB, which can provide maximum shielding. EXPOSED PADDLE The AD8000 features an exposed paddle, which can lower the thermal resistance by 25% compared to a standard SOIC plastic package. The paddle can be soldered directly to the ground plane of the board. Figure 53 shows a typical pad geometry for the LFCSP, the same type of pad geometry can be applied to the SOIC package. Thermal vias or “heat pipes” can also be incorporated into the design of the mounting pad for the exposed paddle. These additional vias improve the thermal transfer from the package to the PCB. Using a heavier weight copper on the surface to which the amplifier’s exposed paddle is soldered also reduces the overall thermal resistance “seen” by the AD8000. POWER SUPPLY BYPASSING Power supply bypassing is a critical aspect of the PCB design process. For best performance, the AD8000 power supply pins need to be properly bypassed. A parallel connection of capacitors from each of the power supply pins to ground works best. Paralleling different values and sizes of capacitors helps to ensure that the power supply pins “see” a low ac impedance across a wide band of frequencies. This is important for minimizing the coupling of noise into the amplifier. Starting directly at the power supply pins, the smallest value and sized component should be placed on the same side of the board as the amplifier, and as close as possible to the amplifier, and connected to the ground plane. This process should be repeated for the next larger value capacitor. It is recommended for the AD8000 that a 0.1 µF ceramic 0508 case be used. The 0508 offers low series inductance and excellent high frequency performance. The 0.1 µF case provides low impedance at high frequencies. A 10 µF electrolytic capacitor should be placed in parallel with the 0.1 µF. The 10 µf capacitor provides low ac impedance at low frequencies. Smaller values of electrolytic capacitors can be used, depending on the circuit requirements. Additional smaller value capacitors help to provide a low impedance path for unwanted noise out to higher frequencies but are not always necessar y. Figure 53. LFCSP Exposed Paddle Layout 05321-034 Rev. 0 | Page 15 of 20 AD8000 Placement of the capacitor returns (grounds), where the capacitors enter into the ground plane, is also important. Returning the capacitors grounds close to the amplifier load is critical for distortion performance. Keeping the capacitors distance short, but equal from the load, is optimal for performance. In some cases, bypassing between the two supplies can help to improve PSRR and to maintain distortion performance in crowded or difficult layouts. This is as another option to improve performance. Minimizing the trace length and widening the trace from the capacitors to the amplifier reduce the trace inductance. A series inductance with the parallel capacitance can form a tank circuit, which can introduce high frequency ringing at the output. This additional inductance can also contribute to increased distortion due to high frequency compression at the output. The use of vias should be minimized in the direct path to the amplifier power supply pins since vias can introduce parasitic inductance, which can lead to instability. When required, use multiple large diameter vias because this lowers the equivalent parasitic inductance. GROUNDING The use of ground and power planes is encouraged as a method of proving low impedance returns for power supply and signal currents. Ground and power planes can also help to reduce stray trace inductance and to provide a low thermal path for the amplifier. Ground and power planes should not be used under any of the pins of the AD8000. The mounting pads and the ground or power planes can form a parasitic capacitance at the amplifiers input. Stray capacitance on the inverting input and the feedback resistor form a pole, which degrades the phase margin, leading to instability. Excessive stray capacitance on the output also forms a pole, which degrades phase margin. Rev. 0 | Page 16 of 20 AD8000 OUTLINE DIMENSIONS 5.00 (0.197) 4.90 (0.193) 4.80 (0.189) 8 1 5 4 BOTTOM VIEW (PINS UP) 4.00 (0.157) 3.90 (0.154) 3.80 (0.150) 2.29 (0.092) 6.20 (0.244) 6.00 (0.236) 5.80 (0.228) 2.29 (0.092) TOP VIEW 1.27 (0.05) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY SEATING 0.10 PLANE 1.75 (0.069) 1.35 (0.053) 0.50 (0.020) × 45° 0.25 (0.010) 0.51 (0.020) 0.31 (0.012) 8° 0.25 (0.0098) 0° 1.27 (0.050) 0.40 (0.016) 0.17 (0.0068) COMPLIANT TO JEDEC STANDARDS MS-012 CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 54. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP] Narrow Body (RD-8-1) Dimensions shown in millimeters and (inches) 3.00 BSC SQ 0.45 0.60 MAX 0.50 0.40 0.30 PIN 1 INDICATOR 8 1 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 5 (BOTTOM VIEW) EXPOSED PAD 1.50 REF 4 1.90 1.75 1.60 0.90 0.85 0.80 12° MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF 0.25 MIN 1.60 1.45 1.30 SEATING PLANE Figure 55. 8-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body (CP-8-2) Dimensions shown in millimeters ORDERING GUIDE Model AD8000YRDZ1 AD8000YRDZ-REEL1 AD8000YRDZ-REEL71 AD8000YCPZ-R21 AD8000YCPZ-REEL1 AD8000YCPZ-REEL71 Minimum Ordering Quantity 1 2,500 1,000 250 5,000 1,500 Temperature Range –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C Package Description 8-Lead SOIC/EP 8-Lead SOIC/EP 8-Lead SOIC/EP 8-Lead LFCSP 8-Lead LFCSP 8-Lead LFCSP Branding Package Option RD-8-1 RD-8-1 RD-8-1 CP-8-2 CP-8-2 CP-8-2 HNB HNB HNB 1 Z = Pb-free part. Rev. 0 | Page 17 of 20 AD8000 NOTES Rev. 0 | Page 18 of 20 AD8000 NOTES Rev. 0 | Page 19 of 20 AD8000 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05321–0–1/05(0) Rev. 0 | Page 20 of 20