AD8010

a FEATURES 200 mA of Output Current 9 Load SFDR –54 dBc @ 1 MHz Differential Gain Error 0.04%, f = 4.43 MHz Differential Phase Error 0.06 , f = 4.43 MHz Maintains Video Specifications Driving Eight Parallel 75 Loads 0.02% Differential Gain 0.03 Differential Phase 0.1 dB Gain Flatness to 60 MHz THD –72 dBc @ 1 MHz, RL = 18.75 IP3 42 dBm @ 5 MHz, RL = 18.75 1 dB Gain Compression 21 dBm @ 5 MHz, RL = 100 230 MHz –3 dB Bandwidth, G = +1, RL = 18.75 800 V/ s Slew Rate, RL = 18.75 25 ns Settling Time to 0.1% Available in 8-Lead DIP, 16-Lead Wide Body SOIC and Thermally Enhanced 8-Lead SOIC APPLICATIONS Video Distribution Amplifier VDSL, xDSL Line Driver Communications ATE Instrumentation 200 mA Output Current High-Speed Amplifier AD8010 CONNECTION DIAGRAMS 8-Lead DIP and SOIC NC 1 –IN 2 +IN 3 –VS 4 AD8010 8 7 6 5 NC +VS OUT NC NC = NO CONNECT 16-Lead Wide Body SOIC NC 1 NC 2 –IN 3 NC 4 +IN 5 NC 6 –VS 7 NC 8 AD8010 16 15 14 13 12 11 10 9 NC NC +VS NC OUT NC NC NC NC = NO CONNECT PRODUCT DESCRIPTION 75 RF RG +5V VOUT1 VOUT2 VOUT3 VOUT4 The AD8010 is a low power, high current amplifier capable of delivering a minimum load drive of 175 mA. Signal performance such as 0.02% and 0.03° differential gain and phase error is maintained while driving eight 75 Ω back terminated video lines. The current feedback amplifier features gain flatness to 60 MHz and –3 dB (G = +1) signal bandwidth of 230 MHz and only requires a typical of 15.5 mA supply current from ± 5 V supplies. These features make the AD8010 an ideal component for Video Distribution Amplifiers or as the drive amplifier within high data rate Digital Subscriber Line (VDSL and xDSL) systems. The AD8010 is an ideal component choice for any application that needs a driver that will maintain signal quality when driving low impedance loads. The AD8010 is offered in three package options: an 8-lead DIP, 16-lead wide body SOIC and a low thermal resistance 8-lead SOIC, and operates over the industrial temperature range of –40°C to +85°C. VIN RT RS AD8010 VOUT5 –5V VOUT6 VOUT7 VOUT8 75 Figure 1. Video Distribution Amplifier R EV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 RF = RG = 562 Model , G = +2, R = AD8010–SPECIFICATIONS–40(@C,25 C,=V +=85 C5 uVnless otherwise18.75 , R (N-8), R = R = 499 (R-8). T = T noted) S L F G MIN MAX S+ = 150 , RF = RG = 604 Max (R-16), Unit MHz MHz MHz MHz dB V/µs ns ns Conditions G = +1, VOUT = 0.2 V p-p G = +2, VOUT = 0.2 V p-p VOUT = 0.2 V p-p VOUT = 4 V p-p VOUT = 0.2 V p-p, < 5 MHz VOUT = 2 V p-p VOUT = 2 V p-p 0.1%, VOUT = 2 V p-p VOUT = 2 V p-p 1 MHz 5 MHz 10 MHz 10 MHz, RL = 39 Ω 20 MHz 1 MHz 5 MHz 10 MHz 10 MHz, RL = 39 Ω 20 MHz 5 MHz ∆f = 10 kHz 5 MHz 5 MHz f = 10 kHz f = 10 kHz, +In f = 20 kHz, –In f = 4.43 MHz, RL = 150 Ω f = 4.43 MHz, RL = 18.75 Ω f = 4.43 MHz, RL = 150 Ω f = 4.43 MHz, RL =18.75 Ω Min 180 130 30 Typ 230 190 60 90 0.02 800 2.0 25 DYNAMIC PERFORMANCE –3 dB Bandwidth 0.1 dB Bandwidth Large Signal Bandwidth Peaking Slew Rise and Fall Time Settling Time NOISE/HARMONIC PERFORMANCE Distortion 2nd Harmonic 3rd Harmonic IMD IP3 1 dB Gain Compression Input Noise Voltage Input Noise Current Differential Gain Differential Phase DC PERFORMANCE Input Offset Voltage –73 –58 –53 –67 –44 –77 –63 –57 –63 –50 –73 42 21 2 3 20 0.02 0.02 0.02 0.03 5 12 15 135 200 12 20 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBm dBm nV√Hz pA√Hz pA√Hz % % Degrees Degrees mV mV µV/°C µA µA µA µA kΩ Ω pF dB V kΩ kΩ TMIN–TMAX Offset Drift Input Bias Current (–) TMIN–TMAX Input Bias Current (+) TMIN–TMAX INPUT CHARACTERISTICS Input Resistance Input Capacitance Common-Mode Rejection Ratio Input Common-Mode Voltage Range Open Loop Transresistance OUTPUT CHARACTERISTICS Output Voltage Swing RL = 18.75 Ω RL = 150 Ω Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio Specifications subject to change without notice. 10 10 6 +Input –Input VCM = ± 2.5 V VOUT = ± 2.5 V TMIN–TMAX 50 300 250 125 12.5 2.75 54 ± 2.5 500 RL = 9 Ω ± 2.1 ± 2.7 175 ± 2.5 ± 3.0 200 240 40 ± 6.0 17 20 V V mA mA pF V mA mA dB dB ± 4.5 15.5 TMIN to TMAX +VS = +4 V to +6 V, –VS = +5 V +VS = +5 V, –VS = –4 V to –6 V 60 50 66 56 – 2– REV. B AD8010 ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V Internal Power Dissipation2 Plastic Package (N) . . . . . . Observe Power Derating Curves Small Outline Package (R) . Observe Power Derating Curves Wide Body SOIC (R-16) . . . Observe Power Derating Curves Input Voltage (Common-Mode) . . . . . . . . . . . . . . . . . . . ± VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . ± 1.2 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range N, R . . . . . . . . –65°C to +125°C Operating Temperature Range (A Grade) . . –40°C to +85°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-Lead Plastic Package: θJA = 90°C/W 8-Lead SOIC Package: θJA = 122°C/W 16-Lead SOIC Package: θJA = 73°C/W 3.0 MAXIMUM POWER DISSIPATION – Watts The maximum power that can be safely dissipated by the AD8010 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175°C for an extended period can result in device failure. While the AD8010 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (+150°C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves. TJ = 150 C 2.5 8-LEAD MINI-DIP PACKAGE 2.0 16-LEAD SOIC PACKAGE (WIDEBODY) 1.5 1.0 8-LEAD SOIC PACKAGE 0.5 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE – C Figure 2. Plot of Maximum Power Dissipation vs. Temperature ORDERING GUIDE Model AD8010AN AD8010AR AD8010AR-16 AD8010AR-REEL AD8010AR-REEL7 AD8010AR-16-REEL AD8010AR-16-REEL7 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 8-Lead Plastic DIP 8-Lead Plastic SOIC 16-Lead Wide Body SOIC REEL SOIC REEL SOIC REEL SOIC REEL SOIC Package Options N-8 SO-8 R-16 13" REEL 7" REEL 13" REEL 7" REEL CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8010 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. B –3– AD8010–Typical Performance Characteristics 60 dG 50 PERCENTAGE OF UNITS 0.05 0.10 0.04 0.08 DIFFERENTIAL GAIN 0.03 DIFFERENTIAL PHASE 0.02 0.04 0.06 40 dG d d DIFFERENTIAL GAIN dG IN % DIFFERENTIAL PHASE d IN Degrees 30 20 dG d d 10 d dG 0 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0.11 0.12 0.13 dG (%)/d – Degrees d d d d d d 0.01 0.02 0 1 2 4 6 8 10 12 NUMBER OF VIDEO LOADS 14 16 0 Figure 3. Distribution of Differential Gain (dG) and Differential Phase (dφ); RL = 18.75 Ω Figure 6. Differential Gain and Phase vs. Number of Video Loads Over Temperature (–40 °C to +85 °C); f = 4.43 MHz –45 –50 G = +2 VO = 2V p-p RL AS SHOWN 2ND RL = 18.75 3RD INTERCEPT POINT – dBm 45 40 35 30 25 20 15 10 5 1 10 FREQUENCY – MHz 100 G = +2 RL = 18.75 HARMONIC DISTORTION – dBc –55 –60 –65 –70 –75 –80 –85 –90 –95 1 3RD RL = 100 2ND 2 3 4 5 6 7 8 9 10 FREQUENCY – MHz 20 Figure 4. Harmonic Distortion vs. Frequency; G = +2 Figure 7. Two-Tone, 3rd Order IMD Intercept vs. Frequency; G = +2, RL = 18.75 Ω 6.5 6.20 6.15 G = +2 RL = 18.75 VO = 0.2V p-p +85 C 4 G = +2 VO = 0.2V p-p NUMBER OF VIDEO LOADS AS SHOWN 6.4 6.3 GAIN FLATNESS – dB 2 6 8 +25 C GAIN FLATNESS – dB 6.10 6.05 6.0 5.95 5.90 5.85 5.80 0.1 1 10 FREQUENCY – MHz 100 500 –40 C 6.2 6.1 6.0 5.9 1 5.8 5.7 5.6 5.5 1 10 10 12 14 100 1000 FREQUENCY – MHz Figure 5. Gain Flatness vs. Frequency Over Temperature (–40 °C to +85 °C) Figure 8. Gain Flatness vs. Frequency vs. Number of Video Loads –4– REV. B DIFFERENTIAL PHASE – Degrees SAMPLE SIZE = 300 G = +2 f = 4.43MHz (PAL) RL = 18.75 DIFFERENTIAL GAIN – % AD8010 5 POUT INTERMODULATION DISTORTION – dBm 0 4dBm 4dBm –10 PMEASURE = 10dBm (FULL SCALE) –5 –15 –25 –35 –45 –55 –65 –75 –85 4.965 4.985 5.0 5.015 FREQUENCY – MHz 5.035 –69dBm –69dBm G = +2 RL = 18.75 fO = 5MHz f = 10kHz –20 PMEASURE – dBm –30 –40 –50 –60 –70 –80 –90 0 1 2 3 RG GAIN = 6.6 RF 50 150 50 50 500kHz TONE SPACING FROM 500kHz TO 5.5MHz WITH 4 MISSING TONES 4 5 6 7 FREQUENCY – MHz 8 9 10 Figure 9. Intermodulation Distortion Figure 12. Multitone Distortion; RL = 100 Ω –35 TOTAL HARMONIC DISTORTION – dBc –55 FREQUENCY = 5MHz G = +2 RL = AS SHOWN (SEE SCHEMATIC) –60 HARMONIC DISTORTION – dBc –45 G = +2 VO = 2V p-p f = 5MHz –55 RL = 18.75 –65 –75 RF –85 –95 RL = 100 RG 150 PIN RL1 = FOR RL = 100 RL1 = 23.1 FOR RL = 18.75 –8 –6 –4 –2 50 RL1 50 POUT 50 –65 –70 –75 –80 2ND 3RD –85 –90 –105 –10 0 2 POUT – dBm 4 6 8 10 12 15 100 200 300 LOAD – 400 500 Figure 10. Total Harmonic Distortion vs. POUT; G = +2 Figure 13. Harmonic Distortion vs. Load 2 G = +1 1 G = +2 0 8.0 7.0 6.0 GAIN – dB 5.0 4.0 12 3.0 8 2.0 1.0 0.0 1 10 100 FREQUENCY – MHz 1000 G = +2 VO = 0.2V p-p NUMBER OF VIDEO LOADS AS SHOWN 4 1 NORMALIZED GAIN – dB –1 –2 –3 –4 –5 –6 –7 0.1 GAIN AS SHOWN VO = 0.2V p-p RL = 18.75 G = +3 1 10 FREQUENCY – MHz 100 1000 Figure 11. Small Signal Closed-Loop Frequency Response; RL = 18.75 Ω Figure 14. Closed-Loop Frequency Response vs. Number of Video Loads REV. B –5– AD8010 –10 –20 –20 0 –10 –30 –40 –50 –PSRR –60 +PSRR –70 –30 CMRR – dB PSRR – dB –40 –50 –60 –70 –80 –90 –80 0.03 0.1 1 10 100 500 –100 0.1 1 FREQUENCY – MHz 10 FREQUENCY – MHz 100 500 Figure 15. PSRR vs. Frequency Figure 18. CMRR vs. Frequency 1000 CLOSED-LOOP OUTPUT RESISTANCE – 310 G = +2 100 31 10 3.1 1 0.31 0.1 1 0.031 0.1 1 10 FREQUENCY – MHz 100 0.316 10k 100k 1M 10M FREQUENCY – Hz 100M 1G 225 316 100 PHASE 31.6 10 TRANSRESISTANCE 3.16 180 90 0 TRANSRESISTANCE – k 45 135 500 Figure 16. Closed-Loop Output Resistance vs. Frequency Figure 19. Transresistance and Phase vs. Frequency; RL = 18.75 Ω 2 1 0 NORMALIZED GAIN – dB 3.0 G = +1 2.0 1.0 NORMALIZED GAIN – dB G = +2 –1 –2 –3 GAIN AS SHOWN VO = 2V p-p RL = 18.75 G = +2 0.0 –1.0 –2.0 –3.0 –4.0 –5.0 –6.0 GAIN AS SHOWN VO = 4V p-p RL = 18.75 G = +10 G = +10 –4 –5 –6 –7 0.1 1 10 FREQUENCY – MHz 100 1000 –7.0 0.1 0 10 FREQUENCY – MHz 100 1000 Figure 17. Large Signal Frequency Response; VO = 2 V p-p Figure 20. Large Signal Frequency Response; VO = 4 V p-p –6– REV. B PHASE – Degrees AD8010 5 0.2 0.15 0.1 0.05 G = +1 RL = 18.75 VO = 0.2V p-p 4 3 2 1 G = +1 RL = 18.75 VO = 4V p-p VOLTS 0 –0.05 –0.1 –0.15 –0.2 50mV 20ns VOLTS 0 –1 –2 –3 –4 1V –5 20ns Figure 21. Small-Signal Pulse Response; G = +1 Figure 24. Large-Signal Pulse Response; G = +1 0.2 0.15 0.1 G = +2, –1 RL = 18.75 VO = 0.2V p-p 4 3 2 1 VOLTS G = +2, –1 RL = 18.75 VO = 4V p-p VOLTS 0.05 0 –0.05 –0.1 –0.15 –0.2 50mV 20ns 0 –1 –2 –3 –4 1V 20ns Figure 22. Small-Signal Pulse Response; G = +2, –1 Figure 25. Large-Signal Pulse Response; G = +2, –1 100 1000 INPUT VOLTAGE NOISE – nV/ Hz INPUT CURRENT NOISE – pA/ Hz 100 INVERTING CURRENT 10 10 NONINVERTING CURRENT 1 10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M 10M FREQUENCY – Hz FREQUENCY – Hz Figure 23. Input Voltage Noise vs. Frequency Figure 26. Input Current Noise vs. Frequency REV. B –7– AD8010 G = +6 RF = 604 RL = 18.75 INPUT VOLTS Driving Capacitance Loads OUTPUT 0 The AD8010 was designed primarily to drive nonreactive loads. If driving loads with a capacitive component is desired, best frequency response is obtained by the addition of a small series resistance as shown in Figure 28. The inset figure shows the optimum value for RSERIES vs. capacitive load. It is worth noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll-off of RSERIES and CL. LAYOUT CONSIDERATIONS INPUT (500mV/DIV) OUTPUT (1V/DIV) 100ns Figure 27. Overdrive Recovery; G = +6 OVERDRIVE RECOVERY The specified high speed performance of the AD8010 requires careful attention to board layout and component selection. Proper RF design techniques and low-pass parasitic component selection are necessary. The PCB should have a ground plane covering all unused portions of the component side of the board to provide low impedance path. The ground plane should be removed from the area near the input pins to reduce the parasitic capacitance. +VS –VS Overdrive of an amplifier occurs when the output and/or input range are exceeded. The amplifier must recover from this overdrive condition. As shown in Figure 27, the AD8010 recovers within 35 ns from negative overdrive and within 75 ns from positive overdrive. THEORY OF OPERATION The AD8010 is a current feedback amplifier optimized for high current output while maintaining excellent performance with respect to flatness, distortion and differential gain/phase. As a video distribution amplifier, the AD8010 will drive up to 12 parallel video loads (12.5 Ω) from a single output with 0.04% differential gain and 0.04° differential phase errors. This means that, unlike designs with one driver per output, any output is a true reflection of the signal on all other outputs. The high output current capability of the AD8010 also make it useful in xDSL applications. The AD8010 can drive a 12.5 Ω single-ended or 25 Ω differential load with low harmonic distortion. This makes it useful in designs that utilize a step-up transformer to drive a twisted-pair transmission line. To achieve these levels of performance special precautions with respect to supply bypassing are recommended (Figure 29). This configuration minimizes the contribution from high frequency supply rejection to differential gain and phase errors as well as reducing distortion due to harmonic energy in the power supplies. 200 100 G = +5 GAIN AS SHOWN VO = 0.2V p-p w/ 30% OVERSHOOT RF RG RS 150 10 VIN 50 CL VOUT FB C1 + 150 VIN RBT RT ZO AD8010 RF C2 + RL RG Figure 29. Standard Noninverting Closed-Loop Configuration with Recommended Bypassing Technique CAPACITIVE LOAD – pF The standard noninverting closed-loop configuration with the recommended power supply bypassing technique is shown in Figure 29. Ferrite beads (Amidon Associates, Torrance CA, Part Number 43101) are used to suppress high frequency power supply energy on the DUT supply lines at the DUT. C1 and C2 each represent the parallel combination of a 47 µF (16 V) tantalum electrolytic capacitor, a 10 µF (10 V) tantalum electrolytic capacitor and a 0.1 µF ceramic chip capacitor. Connect C1 from the +VS pin to the –VS pin. Connect C2 from the –VS pin to signal ground. The feedback resistor should be located close to the inverting input pin in order to keep the parasitic capacitance at this node to a minimum. Parasitic capacitances of less than 1 pF at the inverting input can significantly affect high speed performance. G = +2 G = +1 1 0 5 10 RS – 15 20 Figure 28. Capacitive Load Drive vs. Series Resistor for Various Gains Stripline design techniques should be used for long traces (greater than about 3 cm). These should be designed with a characteristic impedance (ZO) of 50 Ω or 75 Ω and be properly terminated at each end. –8– REV. B AD8010 APPLICATIONS Video Distribution Amplifier The AD8010 is optimized for the specific function of providing excellent video performance when driving multiple video loads in parallel. Significant power is saved and heat sinking is greatly simplified because of the ability of the AD8010 to obtain this performance when running on a ± 5 V supply. However, due to the high currents that flow when driving many parallel video loads, special layout and bypassing techniques are required to assure optimal performance. When designing a video distribution amplifier with the AD8010, it is very important to keep in mind where the high (ac) currents will flow. These paths include the power supply pins of the chip along with the bypass capacitors and the return path for these capacitors, the output circuits and the return path of the output current from the loads. In general, any loops that are formed by any of the above paths should be made as small as possible. Large loops are both generators and receivers of magnetic fields and can cause undesired coupling of signals that lowers the performance of the amplifier. Effects that have not been seen before in other op amp circuits might arise because of the high currents. Most op amp circuits output, at most, tens of milliamps and do not require extremely tight video specifications, while a video distribution amplifier can output hundreds of milliamps and require extremely low differential gain and phase errors. The bypassing scheme that is used for the AD8010 requires special attention. It was found that the conventional technique of bypassing each power pin individually to ground can have an adverse effect on the differential phase error of the circuit. The cause of this is attributed to the fact that there is an internal compensation capacitor in the AD8010 that is referenced to the negative supply. The recommended technique is to connect parallel bypass capacitors from the positive supply to the negative supply and then to bypass the negative supply to ground. For high frequency bypassing, 0.1 µF ceramic capacitors are recommended. These should be placed within a few millimeters of the power pins and should preferably be chip type capacitors. The high currents that can potentially flow through the power supply pins require large bypassing capacitors. These should be low inductance tantalum types and at least 47 µF. The ground side of the capacitor that bypasses the negative supply should be brought to a single point ground that is the common for the returns of the outputs. Figure 30 shows a circuit for making an N-channel video distribution amplifier. As a practical matter, the AD8010 can readily drive eight standard 150 Ω video loads. When driving up to 12 video loads, there is minimal degradation in video performance. Another important consideration when driving multiple cables is the high frequency isolation between the outputs of the cables. Due to its low output impedance, the AD8010 achieves better than 46 dB of output-to-output isolation at 5 MHz driving back terminated 75 Ω cables. +5V FB 499 499 75 AD8010 VIN 75 C2 FB 150 C1 75 75 RL2 75 RL1 –5V 75 75 RLN Figure 30. An N-Channel Video Distribution Amplifier Using An AD8010. NOTE: Please see Figure 29 for Recommended Bypassing Technique. REV. B –9– AD8010 Differential Line Driver Twisted pair transmission lines are more often being used for high frequency analog and digital signals. Over long distances, however, the attenuation characteristics of these lines can degrade the performance of the transmission system. To compensate for this, larger signals are transmitted, which after the attenuation, will still have useful signal strength. The high output current of two AD8010s can be used along with a transformer to create a high power differential line driver. The differential configuration effectively doubles the output swing, while the step-up transformer further increases the output voltage. In the circuit in Figure 31 the A device is configured as a gainof-two follower, while the B device is a gain-of-two inverter. These will produce a differential output signal whose maximum value is twice the peak-to-peak value of the maximum output of one device. For this circuit a 12 V peak-to-peak output can be obtained. The op amps drive a 1:2 step-up transformer that drives a 100 Ω transmission line. Since the impedance reflected back to the primary varies as the square of the turns ratio, it will appear as 25 Ω at the primary. This source terminating resistor is split as a 12.4 Ω resistor at the output of each device. The circuit shown is capable of delivering 12 V p-p to the line and operates with a –3 dB bandwidth of 40 MHz. The peak current output of either op amp is 100 mA. 499 499 12.4 +6 AD8010 150 VIN 402 806 100 AD8010 150 12.4 1:2 – 6 Figure 31. High Output Differential Line Driver Using Two AD8010s. NOTE: Please see Figure 29 for Recommended Bypassing Technique. –10– REV. B AD8010 Closed-Loop Gain and Bandwidth The AD8010 is a current feedback amplifier optimized for use in high performance video and data acquisition applications. Since it uses a current feedback architecture, its closed-loop –3 dB bandwidth is dependent on the magnitude of the feedback resistor. The desired closed-loop bandwidth and gain are obtained by varying the feedback resistor (RF) to set the bandwidth, and varying the gain resistor (RG) to set the desired gain. The characteristic curves and specifications for this data sheet reflect the performance of the AD8010 using the values of RF noted at the top of the specifications table. If a greater –3 dB bandwidth and/or slew rate is required (at the expense of video performance), Table I provides the recommended resistor values. Figure 32 shows the test circuit and conditions used to produce Table I. Effect of Feedback Resistor Tolerance on Gain Flatness Table I. –3 dB Bandwidth and Slew Rate vs. Closed-Loop Gain and Resistor Values Package: N-8 Closed-Loop Gain +1 +2 +5 +10 Package: R-16 RF ( ) 453 374 348 562 RG ( ) –3 dB BW (MHz) 285 255 200 120 Slew Rate (V/ s) 900 900 800 550 ∞ 374 86.6 61.9 Closed-Loop Gain +1 +2 +5 +10 Package: SO-8 RF ( ) 412 392 392 604 RG ( ) –3 dB BW (MHz) 245 220 160 95 Slew Rate (V/ s) 900 900 800 550 Because of the relationship between the 3 dB bandwidth and the feedback resistor, the fine scale gain flatness will, to some extent, vary with feedback resistor tolerance. It is therefore recommended that resistors with a 1% tolerance be used if it is desired to maintain flatness over a wide range of production lots. In addition, resistors of different construction have different associated parasitic capacitance and inductance. Metal-film resistors were used for the bulk of the characterization for this data sheet. It is possible that values other than those indicated will be optimal for other resistor types. Quality of Coaxial Cable ∞ 392 97.6 66.5 Closed-Loop Gain +1 +2 +5 +10 RF ( ) 392 374 348 499 RG ( ) –3 dB BW (MHz) 345 305 220 135 Slew Rate (V/ s) 950 1000 1000 650 ∞ 374 86.6 54.9 Optimum flatness when driving a coax cable is possible only when the driven cable is terminated at each end with a resistor matching its characteristic impedance. If the coax was ideal, then the resulting flatness would not be affected by the length of the cable. While outstanding results can be achieved using inexpensive cables, it should be noted that some variation in flatness due to varying cable lengths may be experienced. 1. VO = 0.2 V p-p for –3 dB Bandwidth. 2. VO = 2 V p-p for Slew Rate. 3. Bypassing per Figure 29. VIN 50 RF RG 18.75 150 VOUT Figure 32. Test Circuit for Table I REV. B –11– AD8010 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Plastic Mini-DIP (N-8) C01047a–0–12/00 (rev. B) 45 0.430 (10.92) 0.348 (8.84) 8 5 0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 1 4 PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.130 (3.30) MIN 0.022 (0.558) 0.100 0.070 (1.77) SEATING PLANE 0.014 (0.356) (2.54) 0.045 (1.15) BSC 0.015 (0.381) 0.008 (0.204) 8-Lead SOIC (SO-8) 0.1968 (5.00) 0.1890 (4.80) 8 1 5 4 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) 0.0099 (0.25) 45 0.0500 0.0192 (0.49) SEATING (1.27) 0.0098 (0.25) PLANE BSC 0.0138 (0.35) 0.0075 (0.19) 8 0 0.0500 (1.27) 0.0160 (0.41) 16-Lead Wide Body SOIC (R-16) 0.4133 (10.50) 0.3977 (10.00) 16 9 1 8 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) PIN 1 0.0118 (0.30) 0.0040 (0.10) 0.1043 (2.65) 0.0926 (2.35) 0.0291 (0.74) 0.0098 (0.25) 0.0500 (1.27) BSC 8 0.0192 (0.49) 0 SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) – 12– REV. B PRINTED IN U.S.A.