AD8015ACHIPS

a FEATURES Low Cost, Wide Bandwidth, Low Noise Bandwidth: 240 MHz Pulse Width Modulation: 500 ps Rise Time/Fall Time: 1.5 ns Input Current Noise: 3.0 pA/√ Hz @ 100 MHz Total Input RMS Noise: 26.5 nA to 100 MHz Wide Dynamic Range Optical Sensitivity: –36 dBm @ 155.52 Mbps Peak Input Current: 350 A Differential Outputs Low Power: 5 V @ 25 mA Wide Operating Temperature Range: –40 C to +85 C APPLICATIONS Fiber Optic Receivers: SONET/SDH, FDDI, Fibre Channel Stable Operation with High Capacitance Detectors Low Noise Preamplifiers Single-Ended to Differential Conversion I-to-V Converters Wideband/Differential Output Transimpedance Amplifier AD8015 FUNCTIONAL BLOCK DIAGRAM AD8015 NC 1 IIN 2 G = 30 G=3 NC 3 +1 VBYP 4 –+ 1.7V NC = NO CONNECT +VS 5 –VS 50Ω 6 –OUTPUT 10kΩ 50Ω +1 8 +VS 7 +OUTPUT 25.0E+3 DIFFERENTIAL 20.0E+3 X-RESISTANCE – Ω 15.0E+3 SINGLE-ENDED 10.0E+3 PRODUCT DESCRIPTION 5.0E+3 The AD8015 is a wide bandwidth, single supply transimpedance amplifier optimized for use in a fiber optic receiver circuit. It is a complete, single chip solution for converting photodiode current into a differential voltage output. The 240 MHz bandwidth enables AD8015 application in FDDI receivers and SONET/SDH receivers with data rates up to 155 Mbps. This high bandwidth supports data rates beyond 300 Mbps. The differential outputs drive ECL directly, or can drive a comparator/ fiber optic post amplifier. In addition to fiber optic applications, this low cost, silicon alternative to GaAs-based transimpedance amplifiers is ideal for systems requiring a wide dynamic range preamplifier or singleended to differential conversion. The IC can be used with a standard ECL power supply (–5.2 V) or a PECL (+5 V) power supply; the common mode at the output is ECL compatible. The AD8015 is available in die form, or in an 8-pin SOIC package. 000.E+0 10.0E+6 100.0E+6 FREQUENCY – Hz 1.0E+9 Figure 1. Differential/Single-Ended Transimpedance vs. Frequency 5.0 EQUIVALENT INPUT CURRENT NOISE – pA√ Hz 4.5 2.0pF 4.0 1.5pF 3.5 3.0pF 3.0 2.5 0.5pF 2.0 000.0E+0 20.0E+6 40.0E+6 60.0E+6 1.0pF 80.0E+6 100.0E+6 FREQUENCY – Hz REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Figure 2. Noise vs. Frequency (SO-8 Package with Added Capacitance) © Analog Devices, Inc., 1996 One Technology Way, P.O. Box 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD8015–SPECIFICATIONS (SO Package @ T = +25 C and V A S = +5 V, unless otherwise noted) AD8015AR Typ 240 500 1.5 3 ± 30 ± 350 –36 0.2 0.4 1.8 Parameter DYNAMIC PERFORMANCE Bandwidth Pulse Width Modulation Rise and Fall Time Settling Time1 INPUT Linear Input Current Range Max Input Current Range Optical Sensitivity Input Stray Capacitance Input Bias Voltage NOISE Input Current Noise Total Input RMS Noise TRANSFER CHARACTERISTICS Transresistance Power Supply Rejection Ratio OUTPUT Differential Offset Output Common-Mode Voltage Voltage Swing (Differential) Output Impedance POWER SUPPLY Operating Range Current Conditions 3 dB 10 µA to 200 µA Peak 10% to 90% to 3%, 0.5 V Diff Output Step ± 2.5%, Nonlinearity Saturation 155 Mbps, Avg Power Die, by Design SOIC, by Design +VS to IIN and VBYP Die, Single Ended at POUT, or Differential (POUT–NOUT), CSTRAY = 0.3 pF f = 100 MHz DC to 100 MHz Single Ended Differential Single Ended Differential Min 180 Max Units MHz ps ns ns µA µA dBm pF pF V ± 25 ± 200 1.6 2.0 3.0 26.5 8 16 10 20 37.0 40 6 –1.3 1.0 600 50 +5 25 12 24 pA/√Hz nA kΩ kΩ dB dB mV V V p-p mV p-p Ω V V mA From Positive Supply Positive Input Current, RL = ∞ Positive Input Current, RL = 50 Ω TMIN to TMAX Single Supply Dual Supply –1.5 40 +4.5 ± 2.25 20 –1.1 60 +11 ± 5.5 26 NOTES 1 Settling Time is defined as the time elapsed from the application of a perfect step input to the time when the output has entered and remained within a specified error band symmetrical about the final value. This parameter includes propagation delay, slew time, overload recovery, and linear settling times. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage (+VS to –VS). . . . . . . . . . . . . . . . . . . . . . . 12 V Internal Power Dissipation2 Small Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 Watts Output Short Circuit Duration . . . . . . . . . . . . . . . Indefinite Maximum Input Current . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C Operating Temperature Range (TMIN to TMAX) AD8015ACHIP/AR . . . . . . . . . . . . . . . . . . –40°C to +85°C Maximum Junction Temperature . . . . . . . . . . . . . . . . . +165°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C NOTES 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-pin SOIC package: θJA = 155°C/W. ORDERING GUIDE Temperature Range Package Description Package Option Model AD8015AR –40°C to +85°C 8-Pin Plastic SOIC SO-8 AD8015ACHIPS –40°C to +85°C Die Form CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8015 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE –2– REV. A AD8015 PIN CONFIGURATION AD8015 NC 1 IIN 2 G = 30 G=3 NC 3 +1 VBYP 4 –+ 1.7V C1 +VS +VS 1.7V AD8015 8 +VS 50Ω +1 1 10kΩ +1 G = 30 3 G=3 +1 4 –+ 1.7V 50Ω 6 50Ω 7 8 LPF: R 3dB@ 0.7 x F LPF: 3dB@ 0.7 x F V1 R CLOCK RECOVERY QUANTIZER R > 40Ω C1 >100pF 4.5V < VS < 11V CLK DATA 10kΩ 7 +OUTPUT 2 50Ω +VS 6 –OUTPUT . 5 –VS +VS 5 NC = NO CONNECT METALIZATION PHOTOGRAPH Dimensions shown in microns. Not to scale. OPTIONAL +VS CONNECTION +VS Figure 3. Fiber Optic Receiver Application: Photodiode Referred to Positive Supply PHOTODIODE REFERRED TO NEGATIVE SUPPLY IIN +OUTPUT 838µ 998µ –OUTPUT Figure 4 shows the AD8015 used in a circuit where the photodiode is referred to the negative supply. This results in a larger back bias voltage than when referring the photodiode to the positive supply. The larger back bias voltage on the photodiode decreases the photodiode’s capacitance thereby increasing its bandwidth. The R2, C2 network shown in Figure 4 is added to decouple the photodiode to the positive supply. This improves PSRR. +VS +VS AD8015 1 C2 2 +VS 1.7V 3 R2 G = 30 G=3 +1 4 –+ 1.7V C1 50Ω 6 +1 10kΩ 50Ω 7 8 LPF: 3dB@ 0.7 x F LPF: 3dB@ 0.7 x F V1 R R CLOCK RECOVERY QUANTIZER CLK DATA VBYP 813µ 973µ –VS +VS 5 R > 40Ω C1 >100pF 4.5V < VS < 11V R2 AND C2 OPTIONAL FOR IMPROVED PSRR NOTE: FOR BEST PERFORMANCE ATTACH PACKAGE SUBSTRATE TO +VS. MATERIAL AT BACK OF DIE IS SILICON. USE OF +VS OR –VS FOR DIE ATTACH IS ACCEPTABLE. Figure 4. Fiber Optic Receiver Application: Photodiode Referred to Negative Supply FIBER OPTIC SYSTEM NOISE PERFORMANCE FIBER OPTIC RECEIVER APPLICATIONS In a fiber optic receiver, the photodiode can be placed from the IIN pin to either the positive or negative supply. The AD8015 converts the current from the photodiode to a differential voltage in these applications. The voltage at the VBYP pin is ≈1.8 V below the positive supply. This node must be bypassed with a capacitor (C1 in Figures 3 and 4 below) to the signal ground. If large levels of power supply noise exist, then connecting C1 to +VS is recommended for improved noise immunity. For optimum performance, choose C1 such that C1 > 1/(2 π × 1000 × fMIN); where fMIN is the minimum useful frequency in Hz. PHOTODIODE REFERRED TO POSITIVE SUPPLY The AD8015 maintains 26.5 nA referred to input (RTI) to 100 MHz. Calculations below translate this specification into minimum power level and bit error rate specifications for SONET and FDDI systems. The dominant sources of noise are: 10 kΩ feedback resistor current noise, input bipolar transistor base current noise, and input voltage noise. The AD8015 has dielectrically isolated devices and bond pads that minimize stray capacitance at the IIN pin. Input voltage noise is negligible at lower frequencies, but can become the dominant noise source at high frequencies due to IIN pin stray capacitance. Minimizing the stray capacitance at the IIN pin is critical to maintaining low noise levels at high frequencies. The pins surrounding the IIN pin (Pins 1 and 3) have no internal connection and should be left unconnected in an application. This minimizes IIN pin package capacitance. It is best to have no ground plane or metal runs near Pins 1, 2, and 3 and to minimize capacitance at the IIN pin. The AD8015AR (8-pin SOIC) IIN pin total stray capacitance is 0.4 pF without the photodiode. Photodiodes used for SONET or FDDI systems typically add 0.3 pF, resulting in roughly 0.7 pF total stray capacitance. –3– Figure 3 shows the AD8015 used in a circuit where the photodiode is referred to the positive supply. The back bias voltage on the photodiode is ≈1.8 V. This method of referring the photodiode provides greater power supply noise immunity (PSRR) than referring the photodiode to the negative supply. The signal path is referred to the positive rail, and the photodiode capacitance is not modulated by high frequency noise that may exist on the negative rail. REV. A AD8015 SONET OC-3 SENSITIVITY ANALYSIS OC-3 Minimum Bandwidth = 0.7 × 155 MHz ≈ 110 MHz Total Current Noise = (π/2) × 26.5 nA = 42 nA (assuming single pole response) Sensitivity (minimum power level) = 492/0.85 nW = 579 nW (peak) = –32.4 dBm (peak) = –35.4 dBm (average) The FDDI specification allows for a minimum power level of –28 dBm peak, or –31 dBm average. Using the AD8015 provides 4.4 dB margin. THEORY OF OPERATION To maintain a BER < 1 × 10–10 (1 error per 10 billion bits): Minimum current level needs to be > 13 × Total Current Noise = 541 nA (peak) Assume a typical photodiode current/power conversion ratio = 0.85 A/W Sensitivity (minimum power level) = 541/0.85 nW = 637 nW (peak) = –32.0 dBm (peak) = –35.0 dBm (average) The SONET OC-3 specification allows for a minimum power level of –31 dBm peak, or –34 dBm average. Using the AD8015 provides 1 dB margin. FDDI SENSITIVITY ANALYSIS FDDI Minimum Bandwidth = 0.7 × 125 MHz ≈ 88 MHz Total Current Noise = ( π / 2 ) × 88 MHz 100 MHz × 26 . 5 nA The simplified schematic is shown in Figure 5. Q1 and Q3 make up the input stage, with Q3 running at 300 µA and Q1 running at 2.7 mA. Q3 runs essentially as a grounded emitter. A large capacitor (0.01 µF) placed from VBYP to the positive supply shorts out the noise of R17, R21, and Q16. The first stage of the amplifier (Q3, R2, Q4, and C1) functions as an integrator, integrating current into the IIN pin. The integrator drives a differential stage (Q5, Q6, R5, R3, and R4) with gains of +3 and –3. The differential stage then drives emitter followers (Q41, Q42, Q60 and Q61). The positive output of the differential stage provides the feedback by driving RFB. The differential outputs are buffered using Q7 and Q8. The bandwidth of the AD8015 is set to within +20% of the nominal value, 240 MHz, by factory trimming R5 to 60 Ω. The following formula describes the AD8015 bandwidth: Bandwidth = 1/(2 π × C1 × RFB × (R5 + 2 re)/R4) where re (of Q5 and Q6) = 9 Ω each, constant over temperature, and RFB/R4 = 43.5, constant over temperature. The bandwidth equation simplifies, and the bandwidth depends only on the value of C1: Bandwidth = 1/(2 π × 3393 × C1). = 39 nA (assuming single pole response) To maintain a BER < 2.5 × 10 –10 (1 error per 4 billion bits): Minimum current level needs to be > 12.6 × Total Current Noise = 492 nA (peak) Assume a typical photodiode current/power conversion ratio = 0.85 A/W +VS R17 635 R21 1.8k VBYP R1 300 R2 3k Q4 Q16 Q1 Q3 INPUT CLAMPS IIN Q5 C1 0.2pF +VS I10 0.75MA Q56 R5 60 Q61 Q6 330 –OUTPUT R43 50 Q41 Q8 Q7 R44 50 Q60 R3 230 R4 230 Q42 330 +OUTPUT RFB 10k I1 1.5MA I2 3MA I3 1MA I4 3MA I5 3MA I6 1MA I7 1MA I8 1MA I9 1MA –VS Figure 5. AD8015 Simplified Schematiic –4– REV. A AD8015 1.5 +85°C 1.0 OUTPUT VOLTAGE – Volts 9 +85°C 0.5 + 25°C – 40°C –40°C AND 0°C 5 0 GAIN – dB 4k VOUT 0 IN AD8015 50Ω –0.5 –1.0 –1.5 –100 –80 –60 –40 –20 0 20 40 60 80 100 1 10 100 FREQUENCY – MHz 1000 INPUT CURRENT – µA Figure 6. Differential Output vs. Input Current Figure 9. Gain vs. Frequency 0 10 –0.5 OUTPUT VOLTAGE – Volts PIN 7 –1.0 +25°C +85°C –40°C –40°C PIN 6 GROUP DELAY – ns 5V, +25°C 0 –1.5 –2.0 +25°C +85°C –2.5 –100 –80 –60 –40 –20 0 20 40 60 80 100 10 100 FREQUENCY – MHz 1000 INPUT CURRENT – µA Figure 7. Single-Ended Output vs. Input Current Figure 10. Group Delay vs. Frequency 300 290 280 9.0 8.5 11.0V 8.0 270 BANDWIDTH – MHz GAIN – dB 260 250 240 230 220 210 200 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 7.5 5.0V 7.0 6.5 6.0 5.5 5.0 10.0E+6 4.5V TEMPERATURE – °C 100.0E+6 FREQUENCY – Hz 1.0E+9 Figure 8. Bandwidth vs. Temperature Figure 11. Differential Gain vs. Supply REV. A –5– AD8015 100 5V, +25°C APPLICATION 155 Mbps Fiber Optic Receiver IMPEDANCE – Ω PIN 7 The AD8015 and AD807 can be used together for a complete 155 Mbps Fiber Optic Receiver (Transimpedance Amplifier, Post Amplifier with Signal Detect Output, and Clock Recovery and Data Retiming) as shown in Figure 16. The PIN diode front end is connected to a single mode, 1300 nm laser source. The PIN diode has 3.3 V reverse bias, 0.8 A/W responsivity, 0.7 pF capacitance, and 2.5 GHz bandwidth. The AD8015 outputs (POUT and NOUT) drive a differential, constant impedance (50 Ω) low-pass π filter with a 3 dB cutoff of 100 MHz. The outputs of the low-pass filter are ac coupled to the AD807 inputs (PIN and NIN). The AD807 PLL damping factor is set at 10 using a 0.22 µF capacitor. The entire circuit was enclosed in a shielded box. Table I summarizes results of tests performed using a 223–1 PRN sequence, and varying the average power at the PIN diode. The circuit acquires and maintains lock with an average input power as low as –39.25 dBm. 30 DEVICES, 2 LOTS: (+OUT, –OUT) × (25°C, –40°C, 85°C) × (5V, 4.5V, 11.0V) 100 90 80 POPULATION – Parts 50 PIN 6 0 1 10 100 FREQUENCY – MHz 1000 Figure 12. Output Impedance vs. Frequency 100 80 VOLTAGE – mV 70 0 60 70 50 40 30 20 20 10 10 0 200.000E+6 205.000E+6 210.000E+6 215.000E+6 220.000E+6 225.000E+6 230.000E+6 235.000E+6 240.000E+6 245.000E+6 250.000E+6 255.000E+6 260.000E+6 265.000E+6 270.000E+6 275.000E+6 280.000E+6 285.000E+6 290.000E+6 295.000E+6 300.000E+6 CUMULATIVE – % 60 50 40 30 –100 0 10 TIME – ns 20 Figure 13. Small Signal Pulse Response 2 0 0 –2 1pF FREQUENCY – Hz Figure 15. Bandwidth Distribution Matrix GAIN – dB –4 5pF –6 8pF –8 –10 3pF 0pF –12 10.0E+6 100.0E+6 FREQUENCY – Hz 1.0E+9 Figure 14. Differential Gain vs. Input Capacitance –6– REV. A AD8015 C1 0.1µF TP8 C2 R1 R2 0.1µF 100 100 C3 0.1µF C4 0.1µF CLKOUTN R8 100 CLKOUTP C5 0.1µF R3 100 C6 0.1µF R4 100 C8 R11 154 R12 154 TP1 R5 100 R6 100 R11 R10 154 154 SDOUT TP7 C1 100pF 1 2 3 R7 100 C7 4 5 6 7 CD DATAOUTN DATAOUTP VCC2 CLKOUTN CLKOUTP VCC1 CF1 CF2 VEE 16 R17 3.65k C11 R14 50 R15 50 C12 2.2µF R16 301 C13 0.1µF DATAOUTN DATAOUTP SDOUT 15 AVCC PIN NIN AVCC THRADJ 14 13 12 11 10 9 C10 TP6 100 pF R13 THRADJ TP5 C15 0.1µF C14 0.1µF 8 TP2 DAMPING CAP,0.22µF AD807 AVEE GND TP4 C9 10µF 5V TP3 1 NC 2 IIN 3 NC 4 0.1µF VBYP +VS +OUT –OUT –VS 8 7 0.1µF 10µF 50Ω LINE 50Ω LINE ABB HAFO 1A227 FC HOUSING NOTES 1. ALL CAPS ARE CHIP, 15pF ARE MICA. 2. 150 nH ARE SMT NC = NO CONNECT 0.8 A/W, 0.7pF 2.5GHz 150nH 15pF 6 5 150nH 15pF AD8015 0.01µF Figure 16. 155 Mbps Fiber Optic Receiver Schematic Table I. AD8015, AD807 Fiber Optic Receiver Circuit: Output Bit Error Rate & Output Jitter vs. Average Input Power Average Optical Input Power (dBm) –6.4 –6.45 –6.50 –6.60 –6.70 –7.0 to –35.50 –36.00 –36.50 –37.00 –37.50 –38.00 –38.50 –39.00 –39.1 –39.20 –39.25 –39.30 Output Bit Error Rate Loses Lock 1.2 × 10–2 7.5 × 10–3 9.4 × 10–4 1 × 10–14 1 × 10–14 3.0 × 10–12 4.8 × 10–10 2.8 × 10–8 8.2 × 10–7 1.3 × 10–5 1.1 × 10–4 1.0 × 10–3 1.3 × 10–3 1.9 × 10–3 2.2 × 10–3 Loses Lock Output Jitter (ps rms) < 40 < 40 REV. A –7– AD8015 AC COUPLED PHOTODIODE APPLICATION FOR IMPROVED DYNAMIC RANGE and typical sensitivity of –35 dBm. AC coupling the input also results in improved pulse width modulation performance. Careful attention to minimize parasitic capacitance at the AD8015 input (from the photodetector input), RAC and CAC are critical for sensitivity performance in this application. Note that CAC of 0.01 µF was chosen for a low frequency cutoff equal to 2.2 kHz. +VS AC coupling the photodiode current input to the AD8015 (Figure 17) extends fiber optic receiver overload by 3 dB while sacrificing only 1 dB of sensitivity (increasing receiver dynamic range by 2 dB). This application results in typical overload of –4 dBm, +VS AD8015 1 10kΩ +1 G = 30 3 G=3 +1 4 –+ 1.7V C1 50Ω 6 50Ω 7 8 LPF: R 3dB@ 0.7 x F LPF: 3dB@ 0.7 x F V1 R CLOCK RECOVERY QUANTIZER R > 40Ω C1 >100pF 4.5V < VS < 11V CLK DATA CAC 2 RAC 7k 0.01µF +VS 5 Figure 17. AC Coupled Photodiode Application for Improved Dynamic Range OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Small Outline IC Package (SO-8) 0.1968 (5.00) 0.1890 (4.80) 8 1 5 4 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) 0.0099 (0.25) x 45° SEATING PLANE 0.0500 0.020 (0.51) (1.27) 0.013 (0.33) BSC 0.0098 (0.25) 0.0075 (0.19) 8° 0° 0.0500 (1.27) 0.0160 (0.41) –8– REV. A PRINTED IN U.S.A. C1973–6–1/96