AD8016AREZ-REEL

xDSL line driver that features full ADSL central office (CO) Performance on ±12 V supplies Low power operation ±5 V to ±12 V voltage supply 12.5 mA/amp (typical) total supply current Power reduced keep alive current of 4.5 mA/amp High output voltage and current drive IOUT = 600 mA 40 V p-p differential output voltage RL = 50 Ω, VS = ±12 V Low single-tone distortion –75 dBc @ 1 MHz SFDR, RL = 100 Ω, VOUT = 2 V p-p MTPR = –75 dBc, 26 kHz to 1.1 MHz, ZLINE = 100 Ω, PLINE = 20.4 dBm High Speed 78 MHz bandwidth (–3 dB), G = +5 40 MHz gain flatness 1000 V/μs slew rate PIN CONFIGURATIONS +V1 1 24 VOUT1 2 23 VOUT2 VINN1 3 22 VINN2 VINP1 4 21 VINP2 AGND 5 20 AGND – + + – AD8016 AGND 6 +V2 AGND TOP VIEW (Not to Scale) 18 AGND 17 AGND AGND 7 AGND 8 19 PWDN0 9 16 PWDN1 DGND 10 15 BIAS –V1 11 14 –V2 NC 12 13 NC NC = NO CONNECT 01019-002 FEATURES Figure 1. 24-Lead SOIC_W_BAT (RB-24) NC 1 28 NC NC 2 27 NC NC 3 26 NC +VIN2 4 25 NC –VIN2 5 24 PWDN1 VOUT2 6 23 BIAS +V2 7 AD8016ARE 22 –V2 +V1 8 TOP VIEW (Not to Scale) 21 –V1 VOUT1 9 20 DGND –VIN1 10 19 NC +VIN1 11 18 PWDN0 NC 12 17 NC NC 13 16 NC NC 14 15 NC NOTES 1. THE EXPOSED PADDLE IS FLOATING, NOT ELECTRICALLY CONNECTED INTERNALLY. 2. NC = NO CONNECT. 01019-003 Data Sheet Low Power, High Output Current xDSL Line Driver AD8016 Figure 2. 28-Lead TSSOP_EP (RE-28-1) GENERAL DESCRIPTION The AD8016 high output current dual amplifier is designed for the line drive interface in Digital Subscriber Line systems such as ADSL, HDSL2, and proprietary xDSL systems. The drivers are capable, in full-bias operation, of providing 24.4 dBm output power into low resistance loads, enough to power a 20.4 dBm line, including hybrid insertion loss. the xDSL hybrid in Figure 35 and Figure 36. Two digital bits (PWDN0, PWDN1) allow the driver to be capable of full performance, an output keep-alive state, or two intermediate bias states. The keep-alive state biases the output transistors enough to provide a low impedance at the amplifier outputs for back termination. The AD8016 is available in a low cost 24-lead SOIC_W_BAT and a 28-lead TSSOP_EP with an exposed lead frame (ePAD). Operating from ±12 V supplies, the AD8016 requires only 1.5 W of total power dissipation (refer to the Power Dissipation section for details) while driving 20.4 dBm of power downstream using The low power dissipation, high output current, high output voltage swing, flexible power-down, and robust thermal packaging enable the AD8016 to be used as the central office (CO) terminal driver in ADSL, HDSL2, VDSL, and proprietary xDSL systems. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved. AD8016 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Feedback Resistor Selection ...................................................... 14 Pin Configurations ........................................................................... 1 Bias Pin and PWDN Features ................................................... 14 General Description ......................................................................... 1 Thermal Shutdown .................................................................... 15 Revision History ............................................................................... 2 Applications Information .............................................................. 16 Specifications..................................................................................... 3 Multitone Power Ratio (MTPR) ............................................... 16 Logic Inputs (CMOS Compatible Logic) .................................. 4 Generating DMT ........................................................................ 17 Absolute Maximum Ratings ............................................................ 5 Power Dissipation....................................................................... 17 Maximum Power Dissipation ..................................................... 5 Thermal Enhancements and PCB Layout ............................... 18 ESD Caution .................................................................................. 5 Thermal Testing.......................................................................... 18 Pin Configurations and Function Descriptions ........................... 6 Air Flow Test Conditions .......................................................... 18 Typical Performance Characteristics ............................................. 7 Experimental Results ................................................................. 19 Test Circuts ...................................................................................... 13 Outline Dimensions ....................................................................... 20 Theory of Operation ...................................................................... 14 Ordering Guide .......................................................................... 20 Power Supply and Decoupling .................................................. 14 REVISION HISTORY 3/12—Rev. B to Rev. C Updated Format .................................................................. Universal Deleted PSOP Package and Evaluation Boards (Throughout) ... 1 Added Pin Configurations and Function Descriptions Sections .. 7 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 19 11/03—Rev. A to Rev. B Changes to Ordering Guide ............................................................ 4 Changes to TPC 21 ........................................................................... 8 Updated Outline Dimensions ..................................................19-20 Rev. C | Page 2 of 20 Data Sheet AD8016 SPECIFICATIONS @ 25°C, VS = ±12 V, RL = 100 Ω, PWDN0, PWDN1 = (1, 1), TMIN = −40°C, TMAX = +85°C, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Large Signal Bandwidth Peaking Slew Rate Rise and Fall Time Settling Time Input Overdrive Recovery Time NOISE/DISTORTION PERFORMANCE Distortion, Single-Ended Second Harmonic Third Harmonic Multitone Power Ratio 1 IMD IP3 Voltage Noise (RTI) Input Current Noise INPUT CHARACTERISTICS RTI Offset Voltage +Input Bias Current –Input Bias Current Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current Recovery Time Shutdown Current Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE 1 Test Conditions/Comments G = +1, RF = 1.5 kΩ, VOUT = 0.2 V p-p G = +5, RF = 499 Ω, VOUT < 0.5 V p-p G = +5, RF = 499 Ω, VOUT = 0.2 V p-p VOUT = 4 V p-p VOUT = 0.2 V p-p < 50 MHz VOUT = 4 V p-p, G = +2 VOUT = 2 V p-p 0.1%, VOUT = 2 V p-p VOUT = 12.5 V p-p VOUT = 2 V p-p, G = +5, RF = 499 Ω fC = 1 MHz, RL = 100 Ω/25 Ω fC = 1 MHz, RL = 100 Ω/25 Ω 26 kHz to 1.1 MHz, ZLINE = 100 Ω, PLINE = 20.4 dBm 500 kHz, Δf = 10 kHz, RL = 100 Ω/25 Ω 500 kHz, RL = 100 Ω/25 Ω f = 10 kHz f = 10 kHz Min 69 16 −75/−62 −88/−74 −84/−80 42/40 −3.0 −45 −75 −10 58 Single-ended, RL = 100 Ω G = 5, RL = 10 Ω, f1 = 100 kHz, −60 dBc SFDR −11 400 Typ See Figure 48, R20, R21 = 0 Ω, R1 = open. Rev. C | Page 3 of 20 63 −40 Unit 380 78 38 90 0.1 1000 2 23 350 MHz MHz MHz MHz dB V/μs ns ns ns −77/−64 −93/−76 –75 −88/−85 43/41 2.6 18 dBc dBc dBc dBc dBm nV/√Hz pA√Hz 1.0 4 400 2 4.5 21 +3.0 +45 +75 +10 64 12.5 8 5 4 25 1.5 75 mV μA μA kΩ pF V dB +11 V mA mA pF ±13 13.2 10 8 6 V mA/Amp mA/Amp mA/Amp mA/Amp μs mA/Amp dB °C 600 2000 80 ±3 PWDN1, PWDN0 = (1, 1) PWDN1, PWDN0 = (1, 0) PWDN1, PWDN0 = (0, 1) PWDN1, PWDN0 = (0, 0) To 95% of IQ 250 μA out of bias pin ΔVS = ±1 V Max 4.0 +85 AD8016 Data Sheet @ 25°C, VS = ±6 V, RL = 100 Ω, PWDN0, PWDN1 = (1, 1), TMIN = –40°C, TMAX = +85°C, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth Test Conditions/Comments Bandwidth for 0.1 dB Flatness Large Signal Bandwidth Peaking Slew Rate Rise and Fall Time Settling Time Input Overdrive Recovery Time NOISE/DISTORTION PERFORMANCE Distortion, Single-Ended Second Harmonic Third Harmonic Multitone Power Ratio 1 IMD IP3 Voltage Noise (RTI) Input Current Noise INPUT CHARACTERISTICS RTI Offset Voltage +Input Bias Current −Input Bias Current Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Quiescent Current Recovery Time Shutdown Current Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE Min G = +1, RF = 1.5 kΩ, VOUT = 0.2 V p-p G = +5, RF = 499 Ω, VOUT < 0.5 V p-p G = +5, RF = 499 Ω, VOUT = 0.2 V p-p VOUT = 1 V rms VOUT = 0.2 V p-p < 50 MHz VOUT = 4 V p-p, G = +2 VOUT = 2 V p-p 0.1%, VOUT = 2 V p-p VOUT = 6.5 V p-p 70 10 G = +5, VOUT = 2 V p-p, RF = 499 Ω fC = 1 MHz, RL = 100 Ω/25 Ω fC = 1 MHz, RL = 100 Ω/25 Ω 26 kHz to 138 kHz, ZLINE = 100 Ω, PLINE = 13 dBm 500 kHz, Δf = 110 kHz, RL = 100 Ω/25 Ω 500 kHz f = 10 kHz f = 10 kHz −73/61 −80/−68 −87/−82 42/39 −3.0 −25 −30 −4 60 Single-Ended, RL = 100 Ω G = +5, RL = 5 Ω, f = 100 kHz, −60 dBc SFDR −5 300 Typ 320 71 15 80 0.7 300 2 39 350 −75/−63 −82/−70 −68 −88/−83 42/39 4 17 +4 66 RS = 10 Ω PWDN1, PWDN0 = (1, 1) PWDN1, PWDN0 = (1, 0) PWDN1, PWDN0 = (0, 1) PWDN1, PWDN0 = (0, 0) To 95% of IQ 250 μA out of bias pin ΔVS = ±1 V 8 6 4 3 23 1.0 80 PWDN0, PWDN1, VCC = ±12 V or ±6 V; full temperature range. Table 3. Typ Max VCC 0.8 Rev. C | Page 4 of 20 Unit V V mV μA μA kΩ pF V dB V mA mA pF 9.7 6.9 5.0 4.1 mA/Amp mA/Amp mA/Amp mA/Amp μs mA/Amp dB °C +85 LOGIC INPUTS (CMOS COMPATIBLE LOGIC) dBc dBc dBc dBc dBm nV/√Hz pA√Hz +5 2.0 See Figure 48, R20, R21 = 0 Ω, R1 = open. Min 2.2 0 1.0 MHz MHz MHz MHz dB V/μs ns ns ns +3.0 +25 +30 1 Parameter Logic 1 Voltage Logic 0 Voltage Unit 5 20 0.2 10 10 400 2 420 830 50 63 −40 Max Data Sheet AD8016 ABSOLUTE MAXIMUM RATINGS Storage Temperature Range Operating Temperature Range Lead Temperature Range (Soldering 10 sec) Rating 26.4 V 1.4 W 1.4 W ±VS ±VS Observe power derating curves −65°C to +125°C −40°C to +85°C 300°C 1 Specification is for device on a 4-layer board with 10 inches2 of 1 oz copper at 85°C 24-lead SOIC_W_BAT package: θJA = 28°C/W. 2 Specification is for device on a 4-layer board with 9 inches2 of 1 oz copper at 85°C 28-lead (TSSOP_EP) package: θJA = 29°C/W. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 8 7 6 5 4 SOIC_W_BAT 3 TSSOP-EP 2 1 0 0 10 20 30 40 50 60 AMBIENT TEMPERATURE (°C) 70 80 90 01019-005 Parameter Supply Voltage Internal Power Dissipation SOIC_W_BAT Package1 TSSOP_EP Package2 Input Voltage (Common-Mode) Differential Input Voltage Output Short-Circuit Duration The output stage of the AD8016 is designed for maximum load current capability. As a result, shorting the output to common can cause the AD8016 to source or sink 2000 mA. To ensure proper operation, it is necessary to observe the maximum power derating curves. Direct connection of the output to either power supply rail can destroy the device. MAXIMUM POWER DISSIPATION (W) Table 4. Figure 3. Maximum Power Dissipation vs. Temperature for AD8016 for TJ = 125 °C ESD CAUTION MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD8016 is limited by the associated rise in junction temperature. The maximum safe junction temperature for a plastic encapsulated device is determined by the glass transition temperature of the plastic, approximately 150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Rev. C | Page 5 of 20 AD8016 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS NC 1 24 +V2 VOUT1 2 23 VOUT2 VINN1 3 – + + – VINP1 4 21 AGND 5 AGND 7 AGND 8 AD8016 VINN2 VINP2 25 NC –VIN2 5 24 PWDN1 23 BIAS +V2 7 AD8016ARE 22 –V2 +V1 8 TOP VIEW (Not to Scale) 21 –V1 20 AGND 19 AGND –VIN1 10 19 NC +VIN1 11 18 16 PWDN1 DGND 10 15 BIAS –V1 11 14 –V2 NC 12 13 NC NC = NO CONNECT +VIN2 4 VOUT1 9 TOP VIEW (Not to Scale) 18 AGND 17 AGND PWDN0 9 26 NC VOUT2 6 20 DGND PWDN0 NC 12 17 NC NC 13 16 NC NC 14 15 NC NOTES 1. THE EXPOSED PADDLE IS FLOATING, NOT ELECTRICALLY CONNECTED INTERNALLY. 2. NC = NO CONNECT. 01019-002 AGND 6 22 27 NC NC 3 Figure 4. 24-Lead SOIC_W_BAT (RB-24) 01019-003 +V1 1 28 NC NC 2 Figure 5. 28-Lead TSSOP_EP (RE-28-1) Table 5. Pin Function Descriptions SOIC_W_BAT 1 2 3 4 5 to 8, 17 to 20 9 10 11 12, 13 14 15 16 21 22 23 24 Pin No. TSSOP_EP 8 9 18 20 21 1 to 3, 12 to 17, 19, 25 to 28 22 23 24 6 7 4 5 10 11 EP Mnemonic +V1 VOUT1 VINN1 VINP1 AGND PWDN0 DGND −V1 NC Description Positive Power Supply, Amp 1. Output Signal, Amp 1. Negative Input Signal, Amp 1. Positive Input Signal, Amp1. Analog Ground. Power-Down Input 0. Digital Ground. Negative Power Supply, Amp1. This pin is not connected internally (see Figure 4 and Figure 5). −V2 BIAS PWDN1 VINP2 VINN2 VOUT2 +V2 +VIN2 −VIN2 −VIN1 +VIN1 EPAD −V Power Supply, Amp 2. Quiescent Current Adjust. Power-Down Input 1. Positive Input Signal, Amp 2. Negative Input Signal, Amp 2. Output Signal, Amp 2. Positive Power Supply, Amp 2. Positive Input Signal, Amp 2. Negative Input Signal, Amp 2. Negative Input Signal, Amp 1. Positive Input Signal, Amp 1. Exposed Pad. The exposed paddle is floating, not electrically connected internally. Rev. C | Page 6 of 20 Data Sheet AD8016 TYPICAL PERFORMANCE CHARACTERISTICS 549.3 550.3 551.3 552.3 553.3 554.3 555.3 556.3 557.3 558.3 559.3 FREQUENCY (kHz) TIME (100ns/DIV) Figure 6. Multitone Power Ratio; VS = ±12 V, 20.4 dBm Output Power into 100 Ω, Downstream Figure 9. 100 mV Step Response; G = +5, VS = ±12 V, RL = 25 Ω, Single-Ended VOLTS VOUT = 4V VIN = 20mV 01019-011 VIN = 800mV 01019-008 VOLTS VOUT = 100mV TIME (100ns/DIV) VIN = 20mV 01019-010 VOLTS –75dBc 01019-004 10dB/DIV VOUT = 100mV TIME (100ns/DIV) Figure 7. 100 mV Step Response; G = +5, VS = ±6 V, RL = 25 Ω, Single-Ended Figure 10. 4 V Step Response; G = +5, VS = ±12 V, RL = 25 Ω, Single-Ended –30 RF = 499Ω G = +10 –40 VOUT = 4V p-p VOUT = 5V (0,0) VOLTS DISTORTION (dBc) –50 VIN = 800mV (0,1) (1,0) –60 –70 –80 PWDN1, PWDN0 = (1,1) –90 –110 0.01 Figure 8. 4 V Step Response; G = +5, VS = ±6 V, RL = 25 Ω, Single-Ended 0.1 1 FREQUENCY (MHz) 10 20 01019-012 01019-009 TIME (100ns/DIV) –100 Figure 11. Distortion vs. Frequency; Second Harmonic, VS = ±12 V, RL = 50 Ω, Differential Rev. C | Page 7 of 20 AD8016 Data Sheet –30 (0,0) RF = 499Ω G = +10 V –40 OUT = 4V p-p (0,1) –50 DISTORTION (dBc) (1,0) –60 –70 –80 PWDN1, PWDN0 = (1,1) –100 10 20 Figure 12. Distortion vs. Frequency; Second Harmonic, VS = ±6 V, RL = 50 Ω –30 –110 0.01 –30 10 20 RF = 499Ω G = +5 (1,0) (0,0) –45 DISTORTION (dBc) –50 –55 (0,0) (0,1) (1,0) –60 –65 –70 –50 (0,1) –60 –70 –80 0 100 300 400 500 600 200 PEAK OUTPUT CURRENT (mA) 700 800 01019-014 PWDN1, PWDN0 = (1,1) –75 Figure 13. Distortion vs. Peak Output Current; Second Harmonic, VS = ±12 V, RL = 10 Ω, f = 100 kHz, Single-Ended –30 –90 0 100 300 400 500 200 PEAK OUTPUT CURRENT (mA) 600 700 Figure 16. Distortion vs. Peak Output Current, Third Harmonic; VS = ±12 V, RL = 10 Ω, G = +5, f = 100 kHz, Single-Ended –30 (0,0) RF = 499Ω G = +10 –40 VOUT = 4V p-p PWDN1, PWDN0 = (1,1) 01019-017 DISTORTION (dBc) 1 FREQUENCY (MHz) –40 –40 –80 0.1 Figure 15. Distortion vs. Frequency; Third Harmonic, VS = ±6 V, RL = 50 Ω, Differential RF = 499Ω G = +5 –35 PWDN1, PWDN0 = (1,1) –80 –100 1 FREQUENCY (MHz) (1,0) –70 –90 0.1 (0,1) –60 –90 –110 0.01 (0,0) –50 01019-013 DISTORTION (dBc) RF = 499Ω G = +10 –40 VOUT = 4V p-p 01019-016 –30 RF = 499Ω G = +5 –35 (0,1) –40 –60 DISTORTION (dBc) DISTORTION (dBc) –50 (1,0) –70 PWDN1, PWDN0 = (1,1) –80 –45 (0,0) –50 (0,1) –55 (1,0) –60 –65 –90 –70 0.1 1 FREQUENCY (MHz) 10 20 –80 01019-015 –110 0.01 –75 Figure 14. Distortion vs. Frequency; Third Harmonic, VS = ±12 V, RL = 50 Ω, Differential PWDN1, PWDN0 = (1,1) 0 100 200 300 400 PEAK OUTPUT CURRENT (mA) 500 600 01019-018 –100 Figure 17. Distortion vs. Peak Output Current; Second Harmonic, VS = ±6 V, RL = 5 Ω, f = 100 kHz, Single-Ended Rev. C | Page 8 of 20 AD8016 –30 –30 –40 –40 –50 –50 DISTORTION (dBc) (0,0) –60 (0,1) –70 (1,0) (0,0) (0,1) –60 (1,0) –70 –80 –80 PWDN1, PWDN0 = (1,1) 0 5 15 20 25 30 10 DIFFERENTIAL OUTPUT (V p-p) 35 –100 01019-020 –100 PWDN1, PWDN0 = (1,1) –90 –90 40 0 5 10 15 20 25 30 DIFFERENTIAL OUTPUT (V p-p) 35 01019-023 DISTORTION (dBc) Data Sheet 40 Figure 21. Distortion vs. Output Voltage; Third Harmonic, VS = ±12 V, G = +10, f = 1 MHz, RL = 50 Ω, Differential Figure 18. Distortion vs. Output Voltage; Second Harmonic, VS = ±12 V, G = +10, f = 1 MHz, RL = 50 Ω, Differential –30 –30 –40 –40 DISTORTION (dBc) DISTORTION (dBc) (0,0) –50 –60 (0,0) (0,1) –70 –50 (0,1) –60 (1,0) –70 (1,0) 10 15 5 DIFFERENTIAL OUTPUT (V p-p) 0 20 –90 Figure 19. Distortion vs. Output Voltage; Second Harmonic, VS = ±6 V, G = +10, f = 1 MHz, RL = 50 Ω, Differential 20 3 –40 –45 –50 (0,0) –55 (0,1) –60 (1,0) –65 –70 –75 0 100 300 400 200 PEAK OUTPUT CURRENT (mA) 500 600 Figure 20. Distortion vs. Peak Output Current; Third Harmonic, VS = ±6 V, G = +5, RL = 5 Ω, f = 100 kHz, Single-Ended –3 (1,1) –6 (1,0) –9 –12 (0,1) –15 –18 (0,0) –21 VIN = 40mV p-p G = +5 RL = 100Ω –24 –27 01019-022 PWDN1, PWDN0 = (1,1) 0 1 10 FREQUENCY (MHz) 100 500 01019-025 NORMALIZED FREQUENCY RESPONSE (dB) –35 DISTORTION (dBc) 5 10 15 DIFFERENTIAL OUTPUT (V p-p) Figure 22. Distortion vs. Output Voltage, Third Harmonic, VS = ±6 V, G = +10, f = 1 MHz, RL = 50 Ω, Differential –30 –80 0 01019-024 PWDN1, PWDN0 = (1,1) 01019-021 –90 PWDN1, PWDN0 = (1,1) –80 –80 Figure 23. Frequency Response; VS = ±12 V, @ PWDN1, PWDN0 Codes Rev. C | Page 9 of 20 AD8016 11 Data Sheet 11 G = +5 RL = 100Ω RF = 499Ω 8 –1 –4 –7 –10 2 –1 –4 –7 –10 –13 –13 –16 –16 1 10 FREQUENCY (MHz) 100 500 –19 10 FREQUENCY (MHz) 1 Figure 24. Output Voltage vs. Frequency; VS = ±12 V 20 10 500 Figure 27. Output Voltage vs. Frequency; VS = ±6 V –10 VIN = 2V rms RF = 602Ω RF = 499Ω –20 (1,1) 0 100 01019-029 OUTPUT VOLTAGE (dBV) 5 2 01019-026 OUTPUT VOLTAGE (dBV) 5 –19 G = +5 RL = 100Ω RF = 499Ω 8 (1,0) –30 +PSRR –20 –30 PSRR (dB) CMRR (dB) –10 (0,1) –40 –40 –50 –PSRR –60 (0,0) –50 –70 –60 100 500 –90 0.01 10 1 FREQUENCY (MHz) 100 500 Figure 28. PSRR vs. Frequency; VS = ±12 V Figure 25. CMRR vs. Frequency; VS = ±12 V @ PWDN1, PWDN0 Codes 180 90 3 160 80 140 70 120 60 100 50 80 40 + INPUT CURRENT NOISE (pA/ Hz) 6 0 (1,1) –3 –6 (1,0) –9 –12 (0,1) –15 –18 –21 VIN = 40mV p-p G = +5 RL = 100Ω –24 1 (0,0) 60 30 +INOISE 40 20 VIN NOISE 10 20 10 FREQUENCY (MHz) 100 500 01019-028 NORMALIZED FREQUENCY RESPONSE (dB) 0.1 Figure 26. Frequency Response; VS = ±6 V, @ PWDN1, PWDN0 Codes Rev. C | Page 10 of 20 0 10 INPUT VOLTAGE NOISE (nV/ Hz) 10 1 FREQUENCY (MHz) 100 100k 1k 10k FREQUENCY (MHz) Figure 29. Noise vs. Frequency 1M 0 10M 01019-031 0.1 01019-027 –80 0.03 01019-030 –80 –70 G = +2 RF = 1kΩ VOUT = 2VSTEP RL = 100Ω +2mV (–0.1%) 0 –2mV (–0.1%) VOUT VIN –5 0 5 10 VOUT – VIN 15 20 25 30 35 40 G = +2 RF = 1kΩ VOUT = 2VSTEP RL = 100Ω +2mV (–0.1%) 0 –2mV (–0.1%) 45 TIME (ns) VIN VOUT –5 0 10 5 15 20 25 30 35 40 45 TIME (ns) Figure 30. Settling Time 0.1%; VS = ±12 V Figure 33. Settling Time 0.1%; VS = ±6 V 1000 –20 VOUT = 2V p-p RF = 499Ω G = +5 –30 R = 100Ω L OUTPUT IMPEDANCE (Ω) 100 –40 CROSSTALK (dB) VOUT – VIN 01019-035 OUTPUT VOLTAGE ERROR (2mV/DIV (0.1%/DIV)) AD8016 01019-032 OUTPUT VOLTAGE ERROR (2mV/DIV (0.1%/DIV)) Data Sheet –50 –60 –70 (0,0) (0,1) 10 (1,0) 1 (1,1) 0.1 0.1 1 10 FREQUENCY (MHz) 100 500 0.01 0.03 01019-033 –90 0.03 Figure 31. Output Crosstalk vs. Frequency 0.1 1 10 FREQUENCY (MHz) 100 01019-036 –80 500 Figure 34. Output Impedance vs. Frequency @ PWDN1, PWDN0 Codes 1M 360 100k 320 10k 280 VIN = 2V/DIV VOUT = 5V/DIV 240 100 200 TRANSIMPEDANCE 10 160 120 1 0.1 80 0.01 40 PHASE (Degrees) PHASE 1k 0V VIN 0.001 0.0001 0.001 0.01 0.1 1 10 FREQUENCY (MHz) 100 1k 0 10k Figure 32. Open-Loop Transimpedance and Phase vs. Frequency –100 0 100 200 300 400 500 TIME (ns) 600 700 800 900 01019-037 0V 01019-034 TRANSIMPEDANCE (k Ω) VOUT Figure 35. Positive Overdrive Recovery; VS = ±12 V, G = +5, RL = 100 Ω Rev. C | Page 11 of 20 AD8016 Data Sheet 18 VIN = 2V/DIV VOUT = 5V/DIV 16 PWDN1, PWDN0 = (1,1) 14 0V VOUT 12 IQ (mA) (1,0) 0V 10 (0,1) 8 (0,0) VIN 6 4 100 200 300 400 500 TIME (ns) 600 700 800 900 0 0 50 100 IBIAS (µA) 150 200 01019-040 0 01019-038 2 –100 Figure 38. IQ vs. IBIAS Current; VS = ±6 V Figure 36. Negative Overdrive Recovery; VS = ±12 V, G = +5, RL = 100 Ω 12 25 +VOUT, VS = ±12V PWDN1, PWDN0 = (1,1) 8 20 OUTPUT SWING (V) +VOUT, VS = ±6V (1,0) IQ (mA) 15 (0,1) 10 4 0 –4 (0,0) –VOUT, VS = ±6V 5 –8 50 100 IBIAS (µA) 150 200 Figure 37. IQ vs. IBIAS Current; VS = ±12 V –12 10 100 1k RLOAD (Ω) Figure 39. Output Voltage vs. RLOAD Rev. C | Page 12 of 20 10k 01019-041 0 01019-039 –VOUT, VS = ±12V 0 Data Sheet AD8016 TEST CIRCUTS 10µF +VS 124Ω 499Ω + 0.1µF +VIN VOUT +VO 49.9Ω RL 499Ω 111Ω VIN 49.9Ω 499Ω RL +VS 0.1µF + 10µF 0.1µF + 10µF 0.1µF –VIN –VO –VS Figure 40. Single-Ended Test Circuit; G = +5 10µF + Figure 41. Differential Test Circuit; G = +10 Rev. C | Page 13 of 20 01019-007 –VS 01019-006 49.9Ω AD8016 Data Sheet THEORY OF OPERATION The AD8016 is a current feedback amplifier with high (500 mA) output current capability. With a current feedback amplifier, the current into the inverting input is the feedback signal and the open-loop behavior is that of a transimpedance, dVOUT/dIIN or TZ. The open-loop transimpedance is analogous to the open-loop voltage gain of a voltage feedback amplifier. Figure 42 shows a simplified model of a current feedback amplifier. Because RIN is proportional to 1/gm, the equivalent voltage gain is just TZ × gm, where gm is the transconductance of the input stage. Basic analysis of the follower with gain circuit yields TZ (S) VOUT =G× TZ (S) + G × RIN + RF VIN RIN = RF RG 1 ≈ 25 Ω gm Recognizing that G × RIN