AD8061ARTZ-REEL7

Low Cost, 300 MHz Rail-to-Rail Amplifiers AD8061/AD8062/AD8063 FEATURES Low cost Single (AD8061), dual (AD8062) Single with disable (AD8063) Rail-to-rail output swing Low offset voltage: 6 mV High speed 300 MHz, −3 dB bandwidth (G = 1) 650 V/μs slew rate 8.5 nV/√Hz at 5 V 35 ns settling time to 0.1% with 1 V step Operates on 2.7 V to 8 V supplies Input voltage range = −0.2 V to +3.2 V with VS = 5 V Excellent video specifications (RL = 150 Ω, G = 2) Gain flatness: 0.1 dB to 30 MHz 0.01% differential gain error 0.04° differential phase error 35 ns overload recovery Low power 6.8 mA/amplifier typical supply current AD8063 400 μA when disabled AD8061/ AD8063 CONNECTION DIAGRAMS VOUT1 8 7 6 1 2 3 4 AD8062 8 7 6 5 +VS VOUT2 –IN2 01065-003 NC 1 –IN 2 +IN 3 –VS 4 DISABLE +VS VOUT (AD8063 ONLY) –IN1 +IN1 01065-001 (Not to Scale) 5 NC – VS +IN2 NC = NO CONNECT (Not to Scale) Figure 1. 8-Lead SOIC (R) VOUT 1 –VS 2 Figure 2. 8-Lead SOIC (R)/MSOP (RM) AD8061 5 AD8063 6 +VS 5 DISABLE 4 VOUT 1 –VS 2 01065-002 +VS +IN 3 (Not to Scale) –IN +IN 3 4 –IN (Not to Scale) Figure 3. 6-Lead SOT-23 (RJ) Figure 4. 5-Lead SOT-23 (RJ) 3 RF = 50Ω 0 NORMALIZED GAIN (dB) APPLICATIONS Imaging Photodiode preamps Professional video and cameras Handsets DVDs/CDs Base stations Filters ADC drivers Clock buffers –3 VO = 0.2V p-p RL = 1kΩ VBIAS = 1V RF RF = 0Ω –6 IN –9 50Ω VBIAS –12 OUT RL 1 10 100 1k FREQUENCY (MHz) Figure 5. Small Signal Response, RF = 0 Ω, 50 Ω GENERAL DESCRIPTION The AD8061/AD8062/AD8063 are rail-to-rail output voltage feedback amplifiers offering ease of use and low cost. They have a bandwidth and slew rate typically found in current feedback amplifiers. All have a wide input common-mode voltage range and output voltage swing, making them easy to use on single supplies as low as 2.7 V. Despite being low cost, the AD8061/AD8062/AD8063 provide excellent overall performance. For video applications, their differential gain and phase errors are 0.01% and 0.04° into a 150 Ω load, along with 0.1 dB flatness out to 30 MHz. Additionally, they offer wide bandwidth to 300 MHz along with 650 V/μs slew rate. The AD8061/AD8062/AD8063 offer a typical low power of 6.8 mA/amplifier, while being capable of delivering up to 50 mA of load current. The AD8063 has a power-down disable feature that reduces the supply current to 400 μA. These features make the AD8063 ideal for portable and battery-powered applications where size and power are critical. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1999–2007 Analog Devices, Inc. All rights reserved. 01065-005 01065-004 AD8061/AD8062/AD8063 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Connection Diagrams...................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 6 Maximum Power Dissipation ..................................................... 6 ESD Caution.................................................................................. 6 Typical Performance Characteristics ............................................. 7 Circuit Description......................................................................... 14 Headroom Considerations........................................................ 14 Overload Behavior and Recovery ............................................ 15 Capacitive Load Drive ............................................................... 16 Disable Operation ...................................................................... 16 Board Layout Considerations ................................................... 16 Applications Information .............................................................. 17 Single-Supply Sync Stripper...................................................... 17 RGB Amplifier ............................................................................ 17 Multiplexer .................................................................................. 18 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 20 REVISION HISTORY 10/07—Rev. D to Rev. E Changes to Applications .................................................................. 1 Updated Outline Dimensions ....................................................... 19 12/05—Rev. C to Rev. D Updated Format..................................................................Universal Change to Features and General Description............................... 1 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 5/01—Rev. B to Rev. C Replaced TPC 9 with new graph .................................................... 7 11/00—Rev. A to Rev. B 2/00—Rev. 0 to Rev. A 11/99—Revision 0: Initial Version Rev. E | Page 2 of 20 AD8061/AD8062/AD8063 SPECIFICATIONS TA = 25°C, VS = 5 V, RL = 1 kΩ, VO = 1 V, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth −3 dB Large Signal Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion Crosstalk, Output to Output Input Voltage Noise Input Current Noise Differential Gain Error (NTSC) Differential Phase Error (NTSC) Third-Order Intercept SFDR DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current TMIN to TMAX Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing (Load Resistance Is Terminated at Midsupply) Output Current Capacitive Load Drive, VOUT = 0.8 V POWER-DOWN DISABLE Turn-On Time Turn-Off Time DISABLE Voltage (Off) DISABLE Voltage (On) POWER SUPPLY Operating Range Quiescent Current per Amplifier Supply Current when Disabled (AD8063 Only) Power Supply Rejection Ratio 2.7 VCM = –0.2 V to +3.2 V RL = 150 Ω RL = 2 kΩ VO = 0.5 V to 4.5 V 30% overshoot: G = 1, RS = 0 Ω G = 2, RS = 4.7 Ω 62 0.3 0.25 25 VO = 0.5 V to 4.5 V, RL = 150 Ω VO = 0.5 V to 4.5 V, RL = 2 kΩ 68 74 Conditions G = 1, VO = 0.2 V p-p G = –1, +2, VO = 0.2 V p-p G = 1, VO = 1 V p-p G = 1, VO = 0.2 V p-p G = 1, VO = 2 V step, RL = 2 kΩ G = 2, VO = 2 V step, RL = 2 kΩ G = 2, VO = 2 V step fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ f = 5 MHz, G = 2, AD8062 f = 100 kHz f = 100 kHz G = 2, RL = 150 Ω G = 2, RL = 150 Ω f = 10 MHz f = 5 MHz Min 150 60 Typ 320 115 280 30 650 500 35 −77 −50 −90 8.5 1.2 0.01 0.04 28 62 1 2 3.5 3.5 4 ±0.3 70 90 13 1 −0.2 to +3.2 80 0.1 to 4.5 0.1 to 4.9 50 25 300 40 300 2.8 3.2 5 6.8 0.4 80 8 9.5 4.75 4.85 6 6 9 9 ±4.5 Max Unit MHz MHz MHz MHz V/μs V/μs ns dBc dBc dBc nV/√Hz pA/√Hz % Degrees dBc dB mV mV μV/°C μA μA μA dB dB MΩ pF V dB V V mA pF pF ns ns V V V mA mA dB 500 300 TMIN to TMAX ∆VS = 2.7 V to 5 V 72 Rev. E | Page 3 of 20 AD8061/AD8062/AD8063 TA = 25°C, VS = 3 V, RL = 1 kΩ, VO = 1 V, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE –3 dB Small Signal Bandwidth –3 dB Large Signal Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion Crosstalk, Output to Output Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current TMIN to TMAX Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing (Load Resistance Is Terminated at Midsupply) Output Current Capacitive Load Drive, VOUT = 0.8 V POWER-DOWN DISABLE Turn-On Time Turn-Off Time DISABLE Voltage—Off DISABLE Voltage—On POWER SUPPLY Operating Range Quiescent Current per Amplifier Supply Current when Disabled (AD8063 Only) Power Supply Rejection Ratio 2.7 6.8 0.4 80 VO = 0.5 V to 2.5 V, RL = 150 Ω VO = 0.5 V to 2.5 V, RL = 2 kΩ 66 74 Conditions G = 1, VO = 0.2 V p-p G = –1, +2, VO = 0.2 V p-p G = 1, VO = 1 V p-p G = 1, VO = 0.2 V p-p G = 1, VO = 1 V step, RL = 2 kΩ G = 2, VO = 1.5 V step, RL = 2 kΩ G = 2, VO = 1 V step fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ f = 5 MHz, G = 2 f = 100 kHz f = 100 kHz Min 150 60 Typ 300 115 250 30 280 230 40 −60 −44 −90 8.5 1.2 1 2 3.5 3.5 4 ±0.3 70 90 13 1 −0.2 to +12 80 0.3 0.3 0.1 to 2.87 0.1 to 2.9 25 25 300 40 300 0.8 1.2 3 9 2.85 2.90 6 6 8.5 8.5 ±4.5 Max Unit MHz MHz MHz MHz V/μs V/μs ns dBc dBc dBc nV/√Hz pA/√Hz mV mV μV/°C μA μA μA dB dB MΩ pF V dB V V mA pF pF ns ns V V V mA mA dB 190 180 TMIN to TMAX VCM = –0.2 V to +1.2 V RL = 150 Ω RL = 2 kΩ VO = 0.5 V to 2.5 V 30% overshoot, G = 1, RS = 0 Ω G = 2, RS = 4.7 Ω 72 Rev. E | Page 4 of 20 AD8061/AD8062/AD8063 TA = 25°C, VS = 2.7 V, RL = 1 kΩ, VO = 1 V, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE –3 dB Small Signal Bandwidth Conditions G = 1, VO = 0.2 V p-p G = –1, +2, VO = 0.2 V p-p G = 1, VO = 1 V p-p G = 1, VO = 0.2 V p-p, VO dc = 1 V G = 1, VO = 0.7 V step, RL = 2 kΩ G = 2, VO = 1.5 V step, RL = 2 kΩ G = 2, VO = 1 V step fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ f = 5 MHz, G = 2 f = 100 kHz f = 100 kHz Min 150 60 Typ 300 115 230 30 150 130 40 –60 –44 –90 8.5 1.2 1 2 3.5 3.5 4 ±0.3 70 90 13 1 –0.2 to +0.9 0.8 0.3 0.25 0.1 to 2.55 0.1 to 2.6 25 25 2.55 2.6 6 6 Max Unit MHz MHz MHz MHz V/μs V/μs ns dBc dBc dBc nV/√Hz pA/√Hz mV mV μV/°C μA μA μA dB dB MΩ pF V dB V V mA pF pF ns ns V V 8 8.5 V mA mA dB Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion Crosstalk, Output to Output Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current 110 95 TMIN to TMAX TMIN to TMAX Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing (Load Resistance Is Terminated at Midsupply) Output Current Capacitive Load Drive, VOUT = 0.8 V POWER-DOWN DISABLE Turn-On Time Turn-Off Time DISABLE Voltage (Off) DISABLE Voltage (On) POWER SUPPLY Operating Range Quiescent Current per Amplifier Supply Current when Disabled (AD8063 Only) Power Supply Rejection Ratio VO = 0.5 V to 2.2 V, RL = 150 Ω VO = 0.5 V to 2.2 V, RL = 2 kΩ 63 74 8.5 ±4.5 VCM = –0.2 V to +0.9 V RL = 150 Ω RL = 2 kΩ VO = 0.5 V to 2.2 V 30% overshoot: G = 1, RS = 0 Ω G = 2, RS = 4.7 Ω 300 40 300 0.5 0.9 2.7 6.8 0.4 80 Rev. E | Page 5 of 20 AD8061/AD8062/AD8063 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Supply Voltage Internal Power Dissipation1 8-lead SOIC (R) 5-lead SOT-23 (RJ) 6-lead SOT-23 (RJ) 8-lead MSOP (RM) Input Voltage (Common-Mode) Differential Input Voltage Output Short-Circuit Duration Storage Temperature Range R-8, RM-8, SOT-23-5, SOT-23-6 Operating Temperature Range Lead Temperature (Soldering, 10 sec) 1 MAXIMUM POWER DISSIPATION Rating 8V 0.8 W 0.5 W 0.5 W 0.6 W (−VS − 0.2 V) to (+VS − 1.8 V) ±VS Observe power derating curves −65°C to +125°C −40°C to +85°C 300°C The maximum power that can be safely dissipated by the AD8061/AD8062/AD8063 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure. While the AD8061/AD8062/AD8063 is internally short-circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150°C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves. 2.0 8-LEAD SOIC PACKAGE 1.5 TJ = 150°C 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE (°C) Figure 6. Maximum Power Dissipation vs. Temperature for AD8061/AD8062/AD8063 ESD CAUTION Rev. E | Page 6 of 20 01065-006 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. MAXIMUM POWER DISSIPATION (W) Specification is for device in free air. 8-Lead SOIC_N: θJA = 160°C/W; θJC = 56°C/W. 5-Lead SOT-23: θJA = 240°C/W; θJC = 92°C/W. 6-Lead SOT-23: θJA = 230°C/W; θJC = 92°C/W. 8-Lead MSOP: θJA = 200°C/W; θJC = 44°C/W. 1.0 0.5 MSOP SOT-23-5, SOT-23-6 AD8061/AD8062/AD8063 TYPICAL PERFORMANCE CHARACTERISTICS 1.2 3 VOLTAGE DIFFERENTIAL FROM VS (Unit) 1.0 +VOUT @ +85°C +VOUT @ +25°C G = +1 0 0.8 NORMALIZED GAIN (dB) –3 G = +2 0.6 +VOUT @ –40°C –VOUT @ –40°C 0.4 –6 G = +5 –9 VO = 0.2V p-p RL = 1kΩ VBIAS = 1V 1 0.2 –VOUT @ +25°C 0 0 10 20 30 40 50 60 –VOUT @ +85°C 01065-007 70 80 90 –12 10 100 1k LOAD CURRENT (mA) FREQUENCY (MHz) Figure 7. Output Saturation Voltage vs. Load Current 18 16 AD8062 Figure 10. Small Signal Frequency Response 3 VO = 1.0V p-p RL = 1kΩ VBIAS = 1V G = +1 G = +2 POWER SUPPLY CURRENT (mA) 14 12 10 AD8061 8 6 4 01065-008 0 NORMALIZED GAIN (dB) –3 –6 G = +5 –9 01065-011 2 0 2 3 4 5 6 7 8 –12 1 10 100 1k SINGLE POWER SUPPLY (V) FREQUENCY (MHz) Figure 8. ISUPPLY vs. VSUPPLY 3 RF = 50Ω 0 Figure 11. Large Signal Frequency Response 3 VS = 5V VO = 0.2V p-p RL = 1kΩ VBIAS = 1V G = –1 –3 RF –6 IN 50Ω –9 01065-009 01065-012 NORMALIZED GAIN (dB) RF = 0Ω –3 NORMALIZED GAIN (dB) VO = 0.2V p-p RL = 1kΩ VBIAS = 1V RF 0 G = –5 G = –2 –6 IN –9 50Ω VBIAS –12 OUT RL OUT RL VBIAS –12 1 10 100 1k 1 10 100 1k FREQUENCY (MHz) FREQUENCY (MHz) Figure 9. Small Signal Response, RF = 0 Ω, 50 Ω Figure 12. Small Signal Frequency Response Rev. E | Page 7 of 20 01065-010 AD8061/AD8062/AD8063 3 VS = 5V VO = 1V p-p RL = 1kΩ VBIAS = 1V G = –1 –3 G = –2 –6 G = –5 –9 01065-013 0 –10 VS = 5V RL = 1kΩ G = +1 HARMONIC DISTORTION (dBc) 0 NORMALIZED GAIN (dB) –20 –30 2ND @ 1MHz –40 –50 –60 –70 –80 –90 –100 0.5 2ND @ 10MHz 1.0 1.5 2.0 3RD @ 10MHz –12 3RD @ 1MHz 2.5 3.0 1 10 100 1k 3.5 FREQUENCY (MHz) INPUT SIGNAL DC BIAS (V) Figure 13. Large Signal Frequency Response Figure 16. Harmonic Distortion for a 1 V p-p Signal vs. Input Signal DC Bias 0.1 VS = 2.7V 0 NORMALIZED GAIN (dB) VO = 0.2V p-p RL = 1kΩ VBIAS = 1V G = +1 DISTORTION (dB) –40 5V 604Ω –50 1kΩ 10µF + 0.1µF 50Ω –60 –0.1 VS = 5V –0.2 VS = 3V 52.3Ω 1MΩ INPUT –70 –80 –90 0.1µF 1.25Vdc + – 1kΩ (RLOAD) 2ND H –0.3 –0.4 01065-014 –0.5 1 10 100 1k FREQUENCY (MHz) –110 0.01 3RD H 0.1 1 10 50 FREQUENCY (MHz, START = 10kHz, STOP = 30MHz) Figure 14. 0.1 dB Flatness 80 200 150 60 SERIES 1 100 Figure 17. Harmonic Distortion for a 1 V p-p Output Signal vs. Input Signal DC Bias –30 –40 –50 PHASE (Degrees) DISTORTION (dB) 2ND 3RD 10MHz VS = 5V RL = 1kΩ G = +5 VO = 1V p-p OPEN-LOOP GAIN (dB) 40 50 SERIES 2 0 –50 –100 –60 –70 –80 –90 –100 2ND 3RD 20 0 –150 –200 –250 5MHz 1MHz – 20 01065-015 –110 –120 2ND 0 1 2 3 4 3RD 5 – 40 0.01 0.1 1 10 100 –300 1k FREQUENCY (MHz) OUTPUT SIGNAL DC BIAS (V) Figure 15. AD8062 Open-Loop Gain and Phase vs. Frequency, VS = 5 V, RL = 1 kΩ Figure 18. Harmonic Distortion vs. Output Signal DC Bias Rev. E | Page 8 of 20 01065-018 01065-017 –100 01065-016 AD8061/AD8062/AD8063 –40 –50 –60 DISTORTION (dB) –70 –80 –90 –100 3RD @ 500kHz –110 1.0 1.5 2.0 2.5 3.0 3.5 4.0 50Ω 1kΩ DIFFERENTIAL GAIN (%) VS = 5V RF = RL = 1kΩ G = +2 5V 2ND @ 10MHz 0.01 0 –0.01 –0.02 –0.04 –0.06 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH 0.02 0 –0.02 –0.04 –0.06 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH 01065-022 + 10µF 0.1µF 1MΩ INPUT TO 3589A 1kΩ 50Ω 1kΩ 2ND @ 2MHz 2ND @ 500kHz 3RD @ 2MHz 4.5 RTO OUTPUT (V p-p) Figure 19. Harmonic Distortion vs. Output Signal Amplitude –30 –40 –50 DISTORTION (dB) DIFFERENTIAL PHASE (Degrees) 01065-019 Figure 22. Differential Gain and Phase Error, G = 2, NTSC Input Signal, RL = 1 kΩ, VS = 5 V DIFFERENTIAL GAIN (%) VS = 5V RI = RL = 1kΩ VO = 2V p-p G=2 S1 3RD HARMONIC/ DUAL ±2.5V SUPPLY S1 2ND HARMONIC/ DUAL ±2.5V SUPPLY S1 2ND HARMONIC/ SINGLE +5V SUPPLY 0.010 0.005 0 –0.005 –0.010 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH –60 –70 –80 –90 DIFFERENTIAL PHASE (Degrees) –110 0.01 0.1 1 10 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH FREQUENCY (MHz, START = 10kHz, STOP = 30MHz) Figure 20. Harmonic Distortion vs. Frequency 1.0 0.9 0.8 1000 Figure 23. Differential Gain and Phase Error, G = 2, NTSC Input Signal, RL = 150 Ω, VS = 5 V VS = 5V RL = 1kΩ G = +1 900 800 VS = 5V RL = 1kΩ G = +1 FALLING EDGE OUTPUT VOLTAGE (V) SLEW RATE (V/µs) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.1 0.2 TIME (µs) 0.3 0.4 01065-021 700 600 500 400 300 200 100 0 1.0 1.5 2.0 RISING EDGE 0.5 2.5 3.0 OUTPUT STEP AMPLITUDE (V) Figure 21. 400 mV Pulse Response Figure 24. Slew Rate vs. Output Step Amplitude Rev. E | Page 9 of 20 01065-024 01065-023 S1 3RD HARMONIC/ SINGLE +5V SUPPLY 01065-020 –100 0.04 0.03 0.02 0.01 0 –0.01 –0.02 AD8061/AD8062/AD8063 1400 1200 1000 SLEW RATE (V/µs) FALLING EDGE VS = ±4V FALLING EDGE VS = +5V VOLTS VIN 2.5V VS = ±2.5V G = +1 RL = 1kΩ 800 600 400 200 0 RISING EDGE VS = ±4V RISING EDGE VS = +5V 01065-025 VOUT 0V 500mV/DIV 0 20 40 60 80 100 120 140 160 180 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 200 OUTPUT STEP (V) TIME (ns) Figure 25. Slew Rate vs. Output Step Amplitude, G = 2, RL = 1 kΩ, VS = 5 V 1k VS = 5V RL = 1kΩ VOLTAGE NOISE (nV/ Hz) Figure 28. Input Overload Recovery, Input Step = 0 V to 2 V VS = ±2.5V G = +5 RL = 1kΩ VOUT 100 VOLTS 2.5V 1.0V VIN 10 0V 01065-026 500mV/DIV 1 10 100 1k 10k 100k 1M 10M 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (Hz) TIME (ns) Figure 26. Voltage Noise vs. Frequency 100 VS = 5V RL = 1kΩ CURRENT NOISE (pA/ Hz) 10 CMRR (dB) Figure 29. Output Overload Recovery, Input Step = 0 V to 1 V 0 –10 –20 –30 –40 –50 –60 –70 –80 01065-027 VCM = 0.2V p-p RL = 100Ω VS = ±2.5V SIDE 2 SIDE 1 1 604Ω 604Ω VIN 200mV p-p 154 Ω 57.6Ω 154 Ω 50Ω –90 –100 0.01 0.1 1 0 10 100 1k 10k 100k 1M 10M 10 100 500 FREQUENCY (Hz) FREQUENCY (MHz) Figure 27. Current Noise vs. Frequency Figure 30. CMRR vs. Frequency Rev. E | Page 10 of 20 01065-030 01065-029 01065-028 AD8061/AD8062/AD8063 0 –10 –20 –30 7 ΔVS = 0.2V p-p RL = 1kΩ VS = 5V –PSRR VS = 5V 6 5 ISUPPLY (mA) PSRR (dB) –40 –50 –60 –70 –80 –90 –100 0.01 0.1 1 10 100 01065-031 4 3 2 1 0 1.0 +PSRR 500 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (MHz) DISABLE VOLTAGE Figure 31. ±PSRR vs. Frequency Delta –20 OUTPUT TO OUTPUT CROSSTALK (dB) Figure 34. AD8063 DISABLE Voltage vs. Supply Current 6 –30 –40 1kΩ 1kΩ +2.5V 5 VDISABLE –60 –70 –80 –90 –100 –110 –120 0.01 50Ω 1kΩ –2.5V OUTPUT VOLTAGE (V) –50 IN OUT 4 3 2 1 0 –1 VOUT VS = 5V G = +2 fIN = 10MHz @ 1.3VBIAS RL = 100Ω INPUT = SIDE 2 INPUT = SIDE 1 01065-032 0.1 1 10 100 500 0 0.4 0.8 TIME (µs) 1.2 1.6 2.0 FREQUENCY (MHz) Figure 32. AD8062 Crosstalk, VOUT = 2.0 V p-p, RL = 1 kΩ, G = 2, VS = 5 V Figure 35. AD8063 DISABLE Function, Voltage = 0 V to 5 V 0 –10 DISABLED ISOLATION (dB) –20 –30 –40 –50 –60 –70 VS = 5V VO = 0.2V p-p RL = 1kΩ VBIAS = 1V 1k VS = 5V VO = 0.2V p-p RL = 1kΩ VBIAS = 1V 100 IMPEDANCE (Ω) 10 1 0.1 01065-033 01065-036 –80 –90 1 10 100 1k 0.01 0.1 1 10 FREQUENCY (MHz) 100 1k FREQUENCY (MHz) Figure 33. AD8063 Disabled Output Isolation Frequency Response Figure 36. Output Impedance vs. Frequency, VOUT = 0.2 V p-p, RL = 1 kΩ, VS = 5 V Rev. E | Page 11 of 20 01065-035 VS = 5V VIN = 400mV rms RL = 1kΩ G = +2 01065-034 AD8061/AD8062/AD8063 VS = 5V RL = 1kΩ VS = 5V G = +2 RL = 1kΩ VIN = 1V p-p 3.5V SETTLING TIME TO 0.1% +0.1% VOLTS 1kΩ 1kΩ 01065-037 –0.1% 2.5V 1.5V RL = 1kΩ t=0 20ns/DIV 500mV/DIV 0 10 20 30 40 50 TIME (ns) 60 70 80 90 100 Figure 37. Output Settling Time to 0.1% 50 45 40 FALLING EDGE Figure 40. 1 V Step Response 2.6V VS = 5V G = +2 RL = 1kΩ VIN = 100mV SETTLING TIME (ns) 35 VOLTS 30 25 20 15 10 5 0 0.5 1.0 RISING EDGE 2.5V 2.4V VS = 5V RL = 1kΩ G = +1 01065-038 20mV/DIV 0 10 20 30 40 50 60 TIME (ns) 70 80 90 1.5 OUTPUT VOLTAGE STEP 2.0 2.5 100 Figure 38. Settling Time vs. VOUT VS = 5V G = –1 RF = 1kΩ RL = 1kΩ 4.86V Figure 41. 100 mV Step Response VS = 5V G = +2 RF = RL = 1kΩ VIN = 4V p-p VOLTS 2.43V 0V 2µs/DIV 1V/DIV Figure 39. Output Swing Figure 42. Output Rail-to-Rail Swing Rev. E | Page 12 of 20 01065-042 1V 2µs 01065-039 VOLTS 0V 01065-041 01065-040 50Ω AD8061/AD8062/AD8063 VS = 5V G = +1 RL = 1kΩ 2.6V 4.5V VS = 5V G = +2 RL = RF = 1kΩ VIN = 2V p-p VOLTS 2.5V VOLTS 01065-043 2.5V 2.4V 0.5V 50mV/DIV 0 5 10 15 20 25 TIME (ns) 30 35 40 45 50 1V/DIV 0 5 10 15 20 25 TIME (ns) 30 35 40 45 50 Figure 43. 200 mV Step Response Figure 44. 2 V Step Response Rev. E | Page 13 of 20 01065-044 AD8061/AD8062/AD8063 CIRCUIT DESCRIPTION The AD8061/AD8062/AD8063 family is comprised of high speed voltage feedback op amps. The high slew rate input stage is a true, single-supply topology, capable of sensing signals at or below the minus supply rail. The rail-to-rail output stage can pull within 30 mV of either supply rail when driving light loads and within 0.3 V when driving 150 Ω. High speed performance is maintained at supply voltages as low as 2.7 V. –0.4 –0.8 –1.2 –1.6 VOS (mV) –2.0 –2.4 –2.8 –3.2 –3.6 –4.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 01065-045 HEADROOM CONSIDERATIONS These amplifiers are designed for use in low voltage systems. To obtain optimum performance, it is useful to understand the behavior of the amplifier as input and output signals approach the amplifier’s headroom limits. The AD8061/AD8062/AD8063 input common-mode voltage range extends from the negative supply voltage (actually 200 mV below this), or ground for single-supply operation, to within 1.8 V of the positive supply voltage. Thus, at a gain of 2, the AD8061/AD8062/AD8063 can provide full rail-to-rail output swing for supply voltage as low as 3.6 V, assuming the input signal swings from −VS (or ground) to +VS/2. At a gain of 3, the AD8061/AD8062/AD8063 can provide a rail-to-rail output range down to 2.7 V total supply voltage. Exceeding the headroom limit is not a concern for any inverting gain on any supply voltage, as long as the reference voltage at the amplifier’s positive input lies within the amplifier’s input common-mode range. The input stage is the headroom limit for signals when the amplifier is used in a gain of 1 for signals approaching the positive rail. Figure 45 shows a typical offset voltage vs. input common-mode voltage for the AD8061/AD8062/AD8063 amplifier on a 5 V supply. Accurate dc performance is maintained from approximately 200 mV below the minus supply to within 1.8 V of the positive supply. For high speed signals, however, there are other considerations. Figure 46 shows −3 dB bandwidth vs. dc input voltage for a unity-gain follower. As the common-mode voltage approaches the positive supply, the amplifier holds together well, but the bandwidth begins to drop at 1.9 V within +VS. This manifests itself in increased distortion or settling time. Figure 16 plots the distortion of a 1 V p-p signal with the AD8061/AD8062/AD8063 amplifier used as a follower on a 5 V supply vs. signal common-mode voltage. Distortion performance is maintained until the input signal center voltage gets beyond 2.5 V, as the peak of the input sine wave begins to run into the upper common-mode voltage limit. 4.0 VCM (V) Figure 45. VOS vs. Common-Mode Voltage, VS = 5 V 2 0 VCM = 3.0 VCM = 3.1 VCM = 3.2 VCM = 3.3 VCM = 3.4 GAIN (dB) –2 –4 –6 01065-046 –8 0.1 1 10 100 1k 10k FREQUENCY (MHz) Figure 46. Unity-Gain Follower Bandwidth vs. Input Common Mode, VS = 5 V Higher frequency signals require more headroom than lower frequencies to maintain distortion performance. Figure 47 illustrates how the rising edge settling time for the amplifier configured as a unity-gain follower stretches out as the top of a 1 V step input approaches and exceeds the specified input common-mode voltage limit. For signals approaching the minus supply and inverting gain and high positive gain configurations, the headroom limit is the output stage. The AD8061/AD8062/AD8063 amplifiers use a common emitter style output stage. This output stage maximizes the available output range, limited by the saturation voltage of the output transistors. The saturation voltage increases with the drive current the output transistor is required to supply, due to the output transistors’ collector resistance. The saturation voltage is estimated using the equation VSAT = 25 mV + IO × 8 Ω where: IO is the output current. 8 Ω is a typical value for the output transistors’ collector resistance. Rev. E | Page 14 of 20 AD8061/AD8062/AD8063 3.6 3.4 3.2 3.7 3.5 OUTPUT VOLTAGE (V) 3.0 2V TO 3V STEP 2.8 2.6 2.4 2.2 2.0 0 4 8 12 16 20 24 28 32 01065-047 OUTPUT VOLTAGE (V) 3.3 3.1 2.9 2.7 2.5 2.3 2.1 VOLTAGE STEP FROM 2.4V TO 3.4V VOLTAGE STEP FROM 2.4V TO 3.6V VOLTAGE STEP FROM 2.4V TO 3.8V, 4V AND 5V 2.1V TO 3.1V STEP 2.2V TO 3.2V STEP 2.3V TO 3.3V STEP 2.4V TO 3.4V STEP 0 100 200 300 TIME (ns) 400 500 600 TIME (ns) Figure 47. Output Rising Edge for 1 V Step at Input Headroom Limits, G = 1, VS = 5 V, 0 V Figure 48. Pulse Response for G = 1 Follower, Input Step Overloading the Input Stage As the saturation point of the output stage is approached, the output signal shows increasing amounts of compression and clipping. As in the input headroom case, the higher frequency signals require a bit more headroom than lower frequency signals. Figure 16, Figure 17, and Figure 18 illustrate this point, plotting typical distortion vs. output amplitude and bias for gains of 2 and 5. Output Output overload recovery is typically within 40 ns after the amplifier’s input is brought to a nonoverloading value. Figure 49 shows output recovery transients for the amplifier recovering from a saturated output from the top and bottom supplies to a point at midsupply. 5.0 4.6 OUTPUT VOLTAGE 5V TO 2.5V OUTPUT VOLTAGE 0V TO 2.5V INPUT VOLTAGE EDGES R R VIN – 2.5V 5V OVERLOAD BEHAVIOR AND RECOVERY Input The specified input common-mode voltage of the AD8061/ AD8062/AD8063 is −200 mV below the negative supply to within 1.8 V of the positive supply. Exceeding the top limit results in lower bandwidth and increased settling time as seen in Figure 46 and Figure 47. Pushing the input voltage of a unitygain follower beyond 1.6 V within the positive supply leads to the behavior shown in Figure 48—an increasing amount of output error and much increased settling time. Recovery time from input voltages 1.6 V or closer to the positive supply is approximately 35 ns, which is limited by the settling artifacts caused by transistors in the input stage coming out of saturation. The AD8061/AD8062/AD8063 family does not exhibit phase reversal, even for input voltages beyond the voltage supply rails. Going more than 0.6 V beyond the power supplies turns on protection diodes at the input stage, which greatly increases the current draw of the device. INPUT AND OUTPUT VOLTAGE (V) 4.2 3.8 3.4 3.0 2.6 2.2 1.8 1.4 1.0 0.6 0.2 –0.2 0 10 20 30 40 TIME (ns) 50 60 70 Figure 49. Overload Recovery, G = −1, VS = 5 V Rev. E | Page 15 of 20 01065-049 VO – 01065-048 AD8061/AD8062/AD8063 CAPACITIVE LOAD DRIVE The AD8061/AD8062/AD8063 family is optimized for bandwidth and speed, not for driving capacitive loads. Output capacitance creates a pole in the amplifier’s feedback path, leading to excessive peaking and potential oscillation. If dealing with load capacitance is a requirement of the application, the two strategies to consider are as follows: • • Use a small resistor in series with the amplifier’s output and the load capacitance. Reduce the bandwidth of the amplifier’s feedback loop by increasing the overall noise gain. DISABLE OPERATION The internal circuit for the AD8063 disable function is shown in Figure 52. When the DISABLE node is pulled below 2 V from the positive supply, the supply current decreases from typically 6.5 mA to under 400 μA, and the AD8063 output enters a high impedance state. If the DISABLE node is not connected and allowed to float, the AD8063 stays biased at full power. VCC 2V DISABLE TO AMPLIFIER BIAS VEE AD8061 VIN RSERIES CLOAD Figure 52. Disable Circuit of the AD8063 VO 01065-050 Figure 50. Series Resistor Isolating Capacitive Load Voltage feedback amplifiers like those in the AD8061/AD8062/ AD8063 family are able to drive more capacitive load without excessive peaking when used in higher gain configurations because the increased noise gain reduces the bandwidth of the overall feedback loop. Figure 51 plots the capacitance that produces 30% overshoot vs. noise gain for a typical amplifier. 10k Figure 34 shows the AD8063 supply current vs. DISABLE voltage. Figure 35 plots the output seen when the AD8063 input is driven with a 10 MHz sine wave, and DISABLE is toggled from 0 V to 5 V, illustrating the part’s turn-on and turn-off time. Figure 33 shows the input/output isolation response with the AD8063 shut off. BOARD LAYOUT CONSIDERATIONS Maintaining the high speed performance of the AD8061/AD8062/ AD8063 family requires the use of high speed board layout techniques and low parasitic components. The PCB should have a ground plane covering unused portions of the component side of the board to provide a low impedance path. Remove the ground plane near the package to reduce parasitic capacitance. CAPACITIVE LOAD (pF) 1k RS = 4.7 RS = 0 100 01065-051 Proper bypassing is critical. Use a ceramic 0.1 μF chip capacitor to bypass both supplies. Locate the chip capacitor within 3 mm of each power pin. Additionally, connect in parallel a 4.7 μF to 10 μF tantalum electrolytic capacitor to provide charge for fast, large signal changes at the output. Minimizing parasitic capacitance at the amplifier’s inverting input pin is very important. Locate the feedback resistor close to the inverting input pin. The value of the feedback resistor may come into play—for instance, 1 kΩ interacting with 1 pF of parasitic capacitance creates a pole at 159 MHz. Use stripline design techniques for signal traces longer than 25 mm. Design them with either 50 Ω or 75 Ω characteristic impedance and proper termination at each end. 10 1 2 3 CLOSED-LOOP GAIN 4 5 Figure 51. Capacitive Load vs. Closed-Loop Gain Rev. E | Page 16 of 20 01065-052 Figure 50 shows a unity-gain follower using the series resistor strategy. The resistor isolates the output from the capacitance and, more importantly, creates a zero in the feedback path that compensates for the pole created by the output capacitance. AD8061/AD8062/AD8063 APPLICATIONS INFORMATION SINGLE-SUPPLY SYNC STRIPPER When a video signal contains synchronization pulses, it is sometimes desirable to remove them prior to performing certain operations. In the case of analog-to-digital conversion, the sync pulses consume some of the dynamic range, so removing them increases the converter’s available dynamic range for the video information. Figure 53 shows a basic circuit for creating a sync stripper using the AD8061 powered by a single supply. When the negative supply is at ground potential, the lowest potential to which the output can go is ground. This feature is exploited to create a waveform whose lowest amplitude is the black level of the video and does not include the sync level. 3V 0.1µF 6 RF 1kΩ 10µF 75Ω VIDEO OUT 75Ω 3V 0.1µF 6 10µF 75Ω RED 75Ω 1kΩ 3V 0.1µF 8 1kΩ 2 3 5 AD8062 1 75Ω GREEN 75Ω 75Ω BLUE 75Ω 4 01065-055 The circuit can be modified to provide the sync stripping function for such a waveform. Instead of connecting RG to ground, connect it to a dc voltage that is two times the black level of the input signal. The gain from the noninverting input to the output is 2, which means the black level is amplified by 2 to the output. However, the gain through RG is −1 to the output. It takes a dc level of twice the input black level to shift the black level to ground at the output. When this occurs, the sync is stripped, and the active video is passed as in the groundreferenced case. RED DAC GREEN DAC BLUE DAC 75Ω 75Ω MONITOR #1 75Ω 75Ω 75Ω 75Ω VIDEO IN 75Ω 3 2 7 1kΩ AD8061 4 RG 1kΩ 01065-053 PIN NUMBERS ARE FOR 8-LEAD PACKAGE 1kΩ 2 3 7 AD8061 4 Figure 53. Single 3 V Sync Stripper Using AD8061 In this case, the input video signal has its black level at ground, so it comes out at ground at the input. Because the sync level is below the black level, it does not show up at the output. However, all of the active video portion of the waveform is amplified by a gain of 2 and then normalized to unity gain by the backterminated transmission line. Figure 54 is an oscilloscope plot of the input and output waveforms. 1 INPUT MONITOR #2 10µF 1kΩ 6 AD8062 7 1kΩ Figure 55. RGB Cable Driver Using AD8061 and AD8062 2 OUTPUT RGB AMPLIFIER Most RGB graphics signals are created by video DAC outputs that drive a current through a resistor to ground. At the video black level, the current goes to zero, and the voltage of the video is also zero. Before the availability of high speed rail-to-rail op amps, it was essential that an amplifier have a negative supply to amplify such a signal. Such an amplifier is necessary if one wants to drive a second monitor from the same DAC outputs. However, high speed, rail-to-rail output amplifiers like the AD8061 and AD8062 accept ground-level input signals and output ground-level signals. They are used as RGB signal amplifiers. A combination of the AD8061 (single) and the AD8062 (dual) amplifies the three video channels of an RGB system. Figure 55 shows a circuit that performs this function. 500mV 10µs Figure 54. Input and Output Waveforms for a Single-Supply Video Sync Stripper Using an AD8061 Some video signals with sync are derived from single-supply devices, such as video DACs. These signals can contain sync, but the whole waveform is positive, and the black level is not at ground but at a positive voltage. 01065-054 Rev. E | Page 17 of 20 AD8061/AD8062/AD8063 MULTIPLEXER The AD8063 has a disable pin used to power down the amplifier to save power or to create a mux circuit. If two (or more) AD8063 outputs are connected together, and only one is enabled, then only the signal of the enabled amplifier will appear at the output. This configuration is used to select from various input signal sources. Additionally, the same input signal is applied to different gain stages, or differently tuned filters, to make a gainstep amplifier or a selectable frequency amplifier. Figure 56 shows a schematic of two AD8063 devices used to create a mux that selects between two inputs. One of these is a 1 V p-p, 3 MHz sine wave; the other is a 2 V p-p, 1 MHz sine wave. +4V 01065-057 The select signal and the output waveforms for this circuit are shown in Figure 57. For synchronization clarity, two different frequency synthesizers, whose time bases are locked to each other, generate the signals. 2µs OUTPUT SELECT 0.1µF TIME BASE OUT 49.9Ω AD8063 1 10µF 1V 2V Figure 57. AD8063 Mux Output 0.1µF 10µF 1V p-p 3MHz –4V 1kΩ +4V 1kΩ 49.9Ω VOUT 49.9Ω 0.1µF 10µF 2V p-p 1MHz TIME BASE IN 49.9Ω AD8063 1 0.1µF –4V 1kΩ 10µF 1kΩ SELECT Figure 56. Two-to-One Multiplexer Using Two AD8063s Rev. E | Page 18 of 20 01065-056 HCO4 AD8061/AD8062/AD8063 OUTLINE DIMENSIONS 2.90 BSC 5.00 (0.1968) 4.80 (0.1890) 4 5 1.60 BSC 1 2 3 2.80 BSC 8 5 4 4.00 (0.1574) 3.80 (0.1497) 1 6.20 (0.2441) 5.80 (0.2284) PIN 1 0.95 BSC 1.30 1.15 0.90 1.90 BSC 0.25 (0.0098) 0.10 (0.0040) 1.27 (0.0500) BSC 1.75 (0.0688) 1.35 (0.0532) 0.50 (0.0196) 0.25 (0.0099) 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 45° 1.45 MAX 0.22 0.08 10° 5° 0° 0.60 0.45 0.30 COPLANARITY 0.10 SEATING PLANE 0.51 (0.0201) 0.31 (0.0122) 0.15 MAX COMPLIANT TO JEDEC STANDARDS MO-178-A A Figure 58. 5-Lead Small Outline Transistor Package [SOT-23] (RJ-5) Dimensions shown in millimeters Figure 59. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 2.90 BSC 3.20 3.00 2.80 4 6 5 1.60 BSC 1 2 3 2.80 BSC PIN 1 INDICATOR 0.95 BSC 1.30 1.15 0.90 1.90 BSC 0.95 0.85 0.75 3.20 3.00 2.80 8 5 1 5.15 4.90 4.65 4 PIN 1 0.65 BSC 1.10 MAX 8° 0° 0.80 0.60 0.40 1.45 MAX 0.22 0.08 10° 4° 0° 0.60 0.45 0.30 0.15 MAX 0.50 0.30 0.15 0.00 0.38 0.22 SEATING PLANE 0.23 0.08 SEATING PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-178-AB COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 60. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6) Dimensions shown in millimeters Figure 61. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. E | Page 19 of 20 012407-A 0.50 0.30 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. AD8061/AD8062/AD8063 ORDERING GUIDE Model AD8061AR AD8061AR-REEL AD8061AR-REEL7 AD8061ARZ 1 AD8061ARZ-REEL1 AD8061ARZ-REEL71 AD8061ART-R2 AD8061ART-REEL AD8061ART-REEL7 AD8061ARTZ-R21 AD8061ARTZ-REEL1 AD8061ARTZ-REEL71 AD8062AR AD8062AR-REEL AD8062AR-REEL7 AD8062ARZ1 AD8062ARZ-RL1 AD8062ARZ-R71 AD8062ARM AD8062ARM-REEL AD8062ARM-REEL7 AD8062ARMZ1 AD8062ARMZ-RL1 AD8062ARMZ-R71 AD8063AR AD8063AR-REEL AD8063AR-REEL7 AD8063ARZ1 AD8063ARZ-REEL1 AD8063ARZ-REEL71 AD8063ART-R2 AD8063ART-REEL AD8063ART-REEL7 AD8063ARTZ-R21 AD8063ARTZ-REEL1 AD8063ARTZ-REEL71 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C –40°C to +85°C −40°C to +85°C −40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 8-Lead SOIC_N 8-Lead SOIC_N, 13-Inch Tape and Reel 8-Lead SOIC_N, 7-Inch Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N, 13-Inch Tape and Reel 8-Lead SOIC_N, 7-Inch Tape and Reel 5-Lead SOT-23, 250 Piece Tape and Reel 5-Lead SOT-23, 13-Inch Tape and Reel 5-Lead SOT-23, 7-Inch Tape and Reel 5-Lead SOT-23, 250 Piece Tape and Reel 5-Lead SOT-23, 13-Inch Tape and Reel 5-Lead SOT-23, 7-Inch Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N, 13-Inch Tape and Reel 8-Lead SOIC_N, 7-Inch Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N, 13-Inch Tape and Reel 8-Lead SOIC_N, 7-Inch Tape and Reel 8-Lead MSOP 8-Lead MSOP, 13-Inch Tape and Reel 8-Lead MSOP, 7-Inch Tape and Reel 8-Lead MSOP 8-Lead MSOP, 13-Inch Tape and Reel 8-Lead MSOP, 7-Inch Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N, 13-Inch Tape and Reel 8-Lead SOIC_N, 7-Inch Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N, 13-Inch Tape and Reel 8-Lead SOIC_N, 7-Inch Tape and Reel 6-Lead SOT-23, 250 Piece Tape and Reel 6-Lead SOT-23, 13-Inch Tape and Reel 6-Lead SOT-23, 7-Inch Tape and Reel 6-Lead SOT-23, 250 Piece Tape and Reel 6-Lead SOT-23, 13-Inch Tape and Reel 6-Lead SOT-23, 7-Inch Tape and Reel Package Option R-8 R-8 R-8 R-8 R-8 R-8 RJ-5 RJ-5 RJ-5 RJ-5 RJ-5 RJ-5 R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 R-8 R-8 R-8 R-8 R-8 R-8 RJ-6 RJ-6 RJ-6 RJ-6 RJ-6 RJ-6 Branding HGA HGA HGA H0D 2 H0D2 H0D2 HCA HCA HCA #HCA #HCA #HCA HHA HHA HHA H0E 3 H0E3 H0E3 Z = RoHS Compliant Part, # denotes RoHS product may be top or bottom marked. New branding after data code 0542, previously branded HGA. 3 New branding after data code 0542, previously branded HHA. ©1999–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01065-0-10/07(E) Rev. E | Page 20 of 20