AD8073JR

a FEATURES Very Low Cost Good Video Specifications (RL = 150 ) Gain Flatness of 0.1 dB to 10 MHz 0.05% Differential Gain Error 0.1 Differential Phase Error Low Power 3.5 mA/Amplifier Supply Current Operates on Single +5 V to +12 V Supply High Speed 100 MHz, –3 dB Bandwidth (G = +2) 500 V/ s Slew Rate Fast Settling Time of 25 ns (0.1%) Easy to Use 30 mA Output Current Output Swing to 1.3 V of Rails on Single +5 V Supply APPLICATIONS Video Line Driver Computer Video Plug-In Boards RGB or S-Video Amplifier in Component Systems PRODUCT DESCRIPTION Low Cost, Dual/Triple Video Amplifiers AD8072/AD8073 FUNCTIONAL BLOCK DIAGRAMS 8-Lead Plastic (N), SOIC (R), and SOIC (RM) Packages OUT1 1 –IN1 2 IN1 3 –VS 4 8 VS 7 OUT2 6 –IN2 AD8072 5 IN2 14-Lead Plastic (N), and SOIC (R) Packages NC NC NC VS IN1 –IN1 OUT1 1 2 3 4 5 6 7 NC = NO CONNECT 14 OUT2 13 –IN2 12 IN2 The AD8072 (dual) and AD8073 (triple) are low cost, current feedback amplifiers intended for high volume, cost sensitive applications. In addition to being low cost, these amplifiers deliver solid video performance into a 150 Ω load while consuming only 3.5 mA per amplifier of supply current. Furthermore, the AD8073 is three amplifiers in a single 14-lead narrow-body SOIC package. This makes it ideal for applications where small size is essential. Each amplifier’s inputs and output are accessible providing added gain setting flexibility. These devices provide 30 mA of output current per amplifier, and are optimized for driving one back terminated video load (150 Ω) each. These current feedback amplifiers feature gain flatness of 0.1 dB to 10 MHz while offering differential gain and phase error of 0.05% and 0.1°. This makes the AD8072 and AD8073 ideal for business and consumer video electronics. Both will operate from a single +5 V to +12 V power supply. The outputs of each amplifier swing to within 1.3 volts of either supply rail to accommodate video signals on a single +5 V supply. The high bandwidth of 100 MHz, 500 V/µs of slew rate, along with settling to 0.1% in 25 ns, make the AD8072 and AD8073 useful in many general purpose, high speed applications where a single +5 V or dual power supplies up to ± 6 V are needed. The AD8072 is available in 8-lead plastic DIP, SOIC, and µSOIC packages while the AD8073 is available in 14-lead plastic DIP and SOIC packages. Both operate over the commercial temperature range of 0°C to +70°C. Additionally, the AD8072ARM operates over the industrial temperature range of –40°C to +85°C. R EV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 6.1 6.0 5.9 AD8073 AD8072 11 –VS 10 IN3 9 –IN3 8 OUT3 7 6 5.8 5.7 5.6 5.5 5.4 5.3 0.1 4 3 1 dB DIV 0.1 dB DIV 2 1 0 –1 500 VS = 5V VO = 2V p-p RF = RG = 1k RL = 150 AV = 2 1 10 FREQUENCY – MHz 100 Figure 1. Large Signal Frequency Response One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 CLOSED-LOOP GAIN – dB 5 GAIN FLATNESS – dB AD8072/AD8073–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (@ T = +25 C, V A S = 5 V, RL = 150 Min 80 8 , unless otherwise noted) AD8072/AD8073 Typ Max 100 10 500 25 0.05 0.1 60 3 6 0.3 2 0.15 0.3 Units MHz MHz V/µs ns % Degrees dB nV/√Hz pA/√Hz MΩ mV mV µV/°C µA nA/°C Ω MΩ pF dB V V V mA mA V dB mA °C Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth, Small Signal 0.1 dB Bandwidth, Small Signal Slew Rate Settling Time to 0.1% DISTORTION/NOISE PERFORMANCE Differential Gain Differential Phase Crosstalk Input Voltage Noise Input Current Noise DC PERFORMANCE Transimpedance Input Offset Voltage Conditions RF = 1 kΩ No Peaking, G = +2 No Peaking, G = +2 VO = 4 V Step VO = 2 V Step RF = 1 kΩ f = 3.58 MHz, G = +2 f = 3.58 MHz, G = +2 f = 5 MHz f = 10 kHz f = 10 kHz (± IIN) TMIN to TMAX Offset Drift Input Bias Current (± ) Input Bias Current Drift (± ) INPUT CHARACTERISTICS –Input Resistance +Input Resistance Input Capacitance Common-Mode Rejection Ratio Input Common-Mode Voltage Range OUTPUT CHARACTERISTICS +Output Voltage Swing –Output Voltage Swing Output Current Short Circuit Current POWER SUPPLY Operating Range Power Supply Rejection Ratio Quiescent Current per Amplifier OPERATING TEMPERATURE RANGE Specifications subject to change without notice. 6 8 12 11 4 12 120 1 1.6 56 ± 3.8 3 2.25 RL = 10 Ω 3.3 3 30 80 ± 2.5 to ± 6 70 3.5 0 VCM = –3.8 V to +3.8 V VS = ± 4 V to ± 6 V 5 +70 –2– REV. A AD8072/AD8073 ELECTRICAL CHARACTERISTICS (@ T = +25 C, V = +5 V, R = 150 A S L to 2.5 V, unless otherwise noted) Min 78 7.8 AD8072/AD8073 Typ 100 10 350 25 0.1 0.1 60 3 6 0.25 1.5 Max Units MHz MHz V/µs ns % Degrees dB nV/√Hz pA/√Hz MΩ mV mV µV/°C µA nA/°C Ω MΩ pF dB V V mA mA V dB mA °C Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth, Small Signal 0.1 dB Bandwidth, Small Signal Slew Rate Settling Time to 0.1% DISTORTION/NOISE PERFORMANCE Differential Gain Differential Phase Crosstalk Input Voltage Noise Input Current Noise DC PERFORMANCE Transimpedance Input Offset Voltage Conditions RF = 1 kΩ No Peaking, G = +2 No Peaking, G = +2 VO = 2 V Step VO = 2 V Step RF = 1 kΩ f = 3.58 MHz, G = +2, RL to 1.5 V f = 3.58 MHz, G = +2, RL to 1.5 V f = 5 MHz f = 10 kHz f = 10 kHz (± IIN) TMIN to TMAX Offset Drift Input Bias Current (± ) Input Bias Current Drift (± ) INPUT CHARACTERISTICS –Input Resistance +Input Resistance Input Capacitance Common-Mode Rejection Ratio Input Common-Mode Voltage Range OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short Circuit Current POWER SUPPLY Operating Range Power Supply Rejection Ratio Quiescent Current per Amplifier OPERATING TEMPERATURE RANGE 9 3 10 120 1 1.6 54 +1.2 to +3.8 +1.5 to +3.5 RL = 10 Ω +1.3 to +3.7 20 60 4 6 10 VCM = +1.2 V to +3.8 V VS = +4 V to +6 V 0 ± 2.5 to ± 6 64 3 4.5 +70 REV. A –3– AD8072/AD8073 ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13.2 V Internal Power Dissipation2 AD8072 8-Lead Plastic (N) . . . . . . . . . . . . . . . . . 1.3 Watts AD8072 8-Lead Small Outline (SO-8) . . . . . . . . . 0.9 Watts AD8072 8-Lead µSOIC (RM) . . . . . . . . . . . . . . . 0.6 Watts AD8073 14-Lead Plastic (N) . . . . . . . . . . . . . . . . 1.6 Watts AD8073 14-Lead Small Outline (R) . . . . . . . . . . . 1.0 Watts Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ± VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . ± 1.25 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range N, R, RM Packages . . . . . . . . . . . . . . . . . –65°C to +125°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-Lead Plastic Package: θJA = 90°C/W 8-Lead SOIC Package: θJA = 140°C/W 8-Lead µSOIC Package: θJA = 214°C/W 14-Lead Plastic Package: θJA = 75°C/W 14-Lead SOIC Package: θJA = 120°C/W The maximum power that can be safely dissipated by the AD8072 and AD8073 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150° C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175°C for an extended period can result in device failure. While the AD8072 and AD8073 are internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (+150°C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves shown in Figures 2 and 3. 2.0 MAXIMUM POWER DISSIPATION – Watts 8-LEAD MINI-DIP PACKAGE TJ = 150 C 1.5 8-LEAD SOIC PACKAGE 1.0 ORDERING GUIDE Model AD8072ARM AD8072ARM-REEL AD8072ARM-REEL7 AD8072JN AD8072JR AD8072JR-REEL AD8072JR-REEL7 AD8073JN AD8073JR AD8073JR-REEL AD8073JR-REEL7 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C Package Description 8-Lead µSOIC 13" Reel 8-Lead µSOIC 7" Reel 8-Lead µSOIC 8-Lead Plastic DIP 8-Lead SOIC 13" Reel 8-Lead SOIC 7" Reel 8-Lead SOIC 14-Lead Plastic DIP 14-Lead Narrow SOIC 13" Reel 14-Lead SOIC 7" Reel 14-Lead SOIC Package Option RM-8 RM-8 RM-8 N-8 SO-8 SO-8 SO-8 N-14 R-14 R-14 R-14 0.5 SOIC 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE – C Figure 2. AD8072 Maximum Power Dissipation vs. Temperature 2.5 MAXIMUM POWER DISSIPATION – Watts TJ = 150 C 2.0 14-LEAD DIP PACKAGE 1.5 14-LEAD SOIC 1.0 0.5 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE – C Figure 3. AD8073 Maximum Power Dissipation vs. Temperature CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8072 and AD8073 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE –4– REV. A AD8072/AD8073 7 6 5 4 3 2 1 0 0.1 0.1 VS = 5V RF = 1k RL = 150 TO 2.5V AV = 2 VIN = 100mV p-p GAIN FLATNESS – dB 6.1 6.0 5.9 5.8 0 C, 25 C 5.7 5.6 5.5 5.4 25 C 1.0 10 FREQUENCY – MHz 100 1000 5.3 0.1 1.0 10 FREQUENCY – MHz 100 500 VS = 5V 70 C RF = 1k RL = 150 AV = 2 VIN = 100mV p-p CLOSED-LOOP GAIN – dB 0C 70 C Figure 4. Frequency Response Over Temperature; VS = +5 V Figure 7. 0.1 dB Flatness vs. Frequency Over Temperature; VS = ± 5 V DIFFERENTIAL PHASE – deg DIFFERENTIAL GAIN – % 7 6 5 4 3 2 1 0 0.1 0.1 VS = 5V RF = 1k RL = 150 AV = 2 VIN = 100mV p-p 0C 70 C 25 C 0.00 0.12 0.10 0.08 0.06 0.04 0.02 0.00 –0.02 VS = 0.03 0.07 0.08 MIN = 0.00 0.08 0.08 MAX = 0.09 p-p/MAX = 0.09 0.09 0.08 0.08 0.07 0.06 2 5V, RF = 1k , RL = 150 TO 1.5V, AV = CLOSED-LOOP GAIN – dB MIN = 0.00 0.00 0.12 0.10 0.08 0.06 0.04 0.02 0.00 –0.02 VS = 0.05 0.09 0.10 0.09 0.08 0.06 MAX = 0.10 0.06 2 0.05 p-p = 0.10 0.04 0.02 5V, RF = 1k , RL = 150 TO 1.5V, AV = 1.0 10 FREQUENCY – MHz 100 1000 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH MODULATING RAMP LEVEL – IRE 10TH 11TH Figure 5. Frequency Response Over Temperature; VS = ±5 V Figure 8. Differential Gain and Phase, VS = +5 V DIFFERENTIAL PHASE – deg DIFFERENTIAL GAIN – % 6.1 6.0 5.9 GAIN FLATNESS – dB 5.8 5.7 5.6 5.5 5.4 5.3 0.1 VS = 5V RF = 1k RL = 150 TO 2.5V AV = 2 VIN = 100mV p-p 70 C MIN = –0.03 0.00 0.00 –0.01 –0.02 –0.03 VS = 5V, RF = 1k RL = 150 AV = 2 0.00 0.00 –0.00 MAX = 0.00 p-p/MAX = 0.03 0.00 –0.01 –0.01 –0.02 –0.03 –0.03 –0.03 MIN = –0.10 0.00 0.02 0.00 –0.02 –0.04 –0.06 –0.08 –0.10 –0.12 MAX = 0.00 p-p = 0.10 0.00 –0.00 –0.02 –0.03 –0.05 –0.07 –0.08 –0.10 –0.10 –0.10 0 C, 25 C VS = 5V, RF = 1k RL = 150 AV = 1ST 2 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH MODULATING RAMP LEVEL – IRE 10TH 11TH 1.0 10 FREQUENCY – MHz 100 500 Figure 6. 0.1 dB Flatness vs. Frequency Over Temperature; VS = +5 V Figure 9. Differential Gain and Phase, VS = ± 5 V REV. A –5– AD8072/AD8073 0 –10 –20 SOIC PACKAGE DRIVE AMP 2 RECEIVE AMPS 1, 3 AD8073 RECEIVE AMP 1 AD8072 VS = 5V, 5V RF = 1k , RL = 150 AV = 2 VIN = 1V p-p AMP 2 OUTPUT 1M 0 –20 100k OHMS ( ) –40 DEGREES –60 –80 DEGREES CROSSTALK – dB –30 –40 –50 –60 –70 –80 –90 0.1 0.1 10k TZ – –100 1k –120 100 –140 –160 10 1k –180 10k 100k 1M 10M 100M 1G FREQUENCY – Hz 1.0 10 FREQUENCY – MHz 100 500 Figure 10. Crosstalk vs. Frequency Figure 13. Open-Loop Transimpedance vs. Frequency –40 NORMALIZED CLOSED-LOOP GAIN – dB 3 –50 DISTORTION – dBc –60 VS = 5V RF = 1k RL = 150 AV = 2 VOUT = 2V p-p 2 AV = 1 0 –1 –2 –3 –4 –5 –6 0.1 1 10 FREQUENCY – MHz 100 1k VS = 5V AV = 10 1 3RD HARMONIC –70 –80 2ND HARMONIC RF = 1k RL = 150 VOUT = 200mV p-p AV = 2 –90 AV = 5 –100 0.1 1 FREQUENCY – MHz 10 Figure 11. Distortion vs. Frequency; VS = ± 5 V Figure 14. Normalized Frequency Response; VS = ± 5 V –40 VS = 5V RF = 1k RL = 150 TO 2.5V AV = 2 VOUT = 2V p-p 6.1 6.0 3RD HARMONIC 7 6 –50 –60 5.8 5.7 5.6 5.5 4 3 1 dB DIV 0.1 dB DIV 2 1 0 –1 500 –70 VS = 5V VO = 2V p-p RF = RG = 1k RL = 150 AV = 2 TO 2.5V –80 2ND HARMONIC –90 5.4 –100 0.1 1 FREQUENCY – MHz 10 5.3 0.1 1 10 FREQUENCY – MHz 100 Figure 12. Distortion vs. Frequency; VS = +5 V Figure 15. Large Signal Frequency Response –6– REV. A CLOSED-LOOP GAIN – dB 5.9 5 GAIN FLATNESS – dB DISTORTION – dBc AD8072/AD8073 100 VS = 100 AV = OUTPUT RESISTANCE – 5V INPUT CURRENT NOISE – pA/ Hz RF = 1k 2 80 10 60 40 1 20 0.1 0.1 0 1 10 FREQUENCY – MHz 100 500 1 10 100 1k FREQUENCY – Hz 10k 100k Figure 16. Output Resistance vs. Frequency; VS = ± 5 V Figure 18. Noise vs. Frequency; VS = ± 5 V 50 10 0 VS = 5V RF = 1k RL = 150 AV = 2 100mV p-p ON TOP OF VS INPUT VOLTAGE NOISE – nV/ Hz 40 –10 –20 –30 –40 –PSRR 20 PSRR – dB 30 PSRR –50 10 –60 0 1 10 100 1k FREQUENCY – Hz 10k 100k –70 0.02 0.1 1 10 FREQUENCY – MHz 100 500 Figure 17. Noise vs. Frequency; VS = ± 5 V Figure 19. PSRR vs. Frequency –5 –10 –15 –20 CMRR – dB VIN 2V p-p 1k 1k 154 60.4 154 VOUT 150 –25 –30 –35 –40 –45 –50 –55 0.02 0.1 1 10 FREQUENCY – MHz 100 500 Figure 20. CMRR vs. Frequency; VS = ± 5 V REV. A –7– AD8072/AD8073 1k 1k RL 150 VIN 50 0.1 F 0.1 F 0.001 F 0.001 F + + 10 F –VS 10 F VOUT VS Figure 21. Test Circuit; Gain = +2 250mV 20ns 250mV 10ns Figure 22. 2 V Step Response; G = +2, VS = ± 5 V Figure 25. 2 V Step Response; G = +2, VS = ± 2.5 V 50mV 20ns 50mV 20ns Figure 23. 200 mV Step Response; G = +2, VS = ± 5 V Figure 26. 200 mV Step Response; G = +2, VS = ± 2.5 V 1V 20ns 250mV 20ns Figure 24. Sine Response; G = +2, VS = ± 5 V Figure 27. Sine Response; G = +2, VS = ± 2.5 V Note: VS = ± 2.5 V operation is identical to VS = +5 V single supply operation. –8– REV. A AD8072/AD8073 APPLICATIONS Overdrive Recovery Capacitive Load Drive Overdrive of an amplifier occurs when the output and/or input range are exceeded. The amplifier must recover from this overdrive condition and resume normal operation. As shown in Figure 28, the AD8072 and AD8073 recover within 75 ns from positive overdrive and 30 ns from negative overdrive. When an op amp output drives a capacitive load, extra phase shift due to the pole formed by the op amp’s output impedance and the capacitor can cause peaking or even oscillation. The top trace of Figure 30, RS = 0 Ω, shows the output of one of the amplifiers of the AD8072/AD8073 when driving a 50 pF capacitor as shown in the schematic of Figure 31. The amount of peaking can be significantly reduced by adding a resistor in series with the capacitor. The lower trace of Figure 30 shows the same capacitor being driven with a 25 Ω resistor in series with it. In general, the resistor value will have to be experimentally determined, but from 10 Ω to 50 Ω is a practical range of values to experiment with for capacitive loads of up to a few hundred pF. VIN VOUT RS = 0Ω RS = 25Ω 1V 25ns Figure 28. Overload Recovery; VS = ± 5 V, VIN = 8 V p-p, RF = 1 kΩ, RL = 150 Ω, G = +2 Bandwidth vs. Feedback Resistor Value The closed-loop frequency response of a current feedback amplifier is a function of the feedback resistor. A smaller feedback resistor will produce a wider bandwidth response. However, if the feedback resistance becomes too small, the gain flatness can be affected. As a practical consideration, the minimum value of feedback resistance for the AD8072/AD8073 was found to be 649 Ω. For resistances below this value, the gain flatness will be affected and more significant lot to lot variations in device performance will be noticed. Figure 29 shows a plot of the frequency response of an AD8072/AD8073 at a gain of two with both feedback and gain resistors equal to 649 Ω. On the other hand, the bandwidth of a current feedback amplifier can be decreased by increasing the feedback resistance. This can sometimes be useful where it is desired to reduce the noise bandwidth of a system. As a practical matter, the maximum value of feedback resistor was found to be 2 kΩ. Figure 29 shows the frequency response of an AD8072/AD8073 at a gain of two with both feedback and gain resistors equal to 2 kΩ. 6.1 6.0 5.9 5.8 0.1 dB DIV 5.7 VS = 5.6 5.5 5.4 0.1 RF = 2k 1 10 FREQUENCY – MHz 100 AV = 5V 2 1 dB DIV 2 3 7 6 CLOSED-LOOP GAIN – dB 50mV 20ns Figure 30. Capacitive Low Drive 1k 1k RS VIN = 100mV p-p 50 CL 50pF RL 1k Figure 31. Capacitive Load Drive Circuit GAIN FLATNESS – dB RF = 649 5 4 RL = 150 VO = 0.2V p-p 1 0 500 Figure 29. Frequency Response vs. RF REV. A –9– AD8072/AD8073 Crosstalk Layout Considerations Crosstalk between internal amplifiers may vary depending on which amplifier is being driven and how many amplifiers are being driven. This variation typically stems from pin location on the package and the internal layout of the IC itself. Table I illustrates the typical crosstalk results for a combination of conditions. Table I. AD8073JR Crosstalk Table (dB) The specified high speed performance of the AD8072 and AD8073 require careful attention to board layout and component selection. Proper RF design techniques and low parasitic component selection are mandatory. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance ground path. The ground plane should be removed from the area near the input pins to reduce stray capacitance. Chip capacitors should be used for supply bypassing. One end of the capacitor should be connected to the ground plane and the other within 1/8 inches of each power pin. An additional large (4.7 µF–10 µF) tantalum electrolytic capacitor should be connected in parallel, but not necessarily as close to the supply pins, to provide current for fast large-signal changes at the device’s output. The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. Capacitance variations of less than 1 pF at the inverting input will affect high speed performance. Stripline design techniques should be used for long signal traces (greater than about 1 inch). These should be designed with a characteristic impedance of 50 Ω or 75 Ω and be properly terminated at each end. AD8073JR 1 Drive Amplifier 2 3 All Hostile CONDITIONS Receive Amplifier 1 2 3 X –60 –56 –60 –54 –53 X –60 –55 –60 X –54 VS = ± 5 V RF = 1 kΩ, RL = 150 Ω AV = +2 VOUT = 2 V p-p on Drive Amplifier –10– REV. A AD8072/AD8073 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Plastic DIP (N-8) 0.430 (10.92) 0.348 (8.84) 8 5 14-Lead Plastic DIP (N-14) 0.795 (20.19) 0.725 (18.42) 14 8 7 1 4 0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN SEATING PLANE 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 1 0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.022 (0.558) 0.100 0.070 (1.77) 0.014 (0.356) (2.54) 0.045 (1.15) BSC 0.015 (0.381) 0.008 (0.204) 0.100 0.070 (1.77) (2.54) 0.045 (1.15) BSC SEATING PLANE 0.015 (0.381) 0.008 (0.204) 8-Lead Plastic SOIC (SO-8) 0.1968 (5.00) 0.1890 (4.80) 8 1 5 4 14 1 14-Lead SOIC (R-14) 0.3444 (8.75) 0.3367 (8.55) 8 7 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) x 45° 0.0099 (0.25) PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) x 45° 0.0099 (0.25) SEATING PLANE 0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) BSC 0.0098 (0.25) 0.0075 (0.19) 8° 0° 0.0500 (1.27) 0.0160 (0.41) SEATING PLANE 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 0.0099 (0.25) 0.0075 (0.19) 8° 0° 0.0500 (1.27) 0.0160 (0.41) 8-Lead SOIC (RM-8) 0.122 (3.10) 0.114 (2.90) 8 5 0.122 (3.10) 0.114 (2.90) 1 4 0.199 (5.05) 0.187 (4.75) PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) SEATING 0.008 (0.20) PLANE 0.043 (1.09) 0.037 (0.94) 0.011 (0.28) 0.003 (0.08) 0.120 (3.05) 0.112 (2.84) 33 27 0.028 (0.71) 0.016 (0.41) REV. A –11– PRINTED IN U.S.A. C2126–0–3/00 (rev. A)