AD8075-EVAL

a FEATURES Dual Supply 5 V High-Speed Fully Buffered Inputs and Outputs 600 MHz Bandwidth (–3 dB) 200 mV p-p 500 MHz Bandwidth (–3 dB) 2 V p-p 1600 V/ s Slew Rate, G = +1 1350 V/ s Slew Rate, G = +2 Fast Settling Time: 4 ns Low Supply Current: V DGND + ~2.0 V and enabled for VOE < VDGND + 0.8 V. TTL logic levels are expected. The following restrictions are placed upon the digital ground potential: 3.5 V ≤ VAVCC – VDGND ≤ 12 V VDGND ≥ VAVEE Full Power Bandwidth = Peak Slew Rate 2 × π × Sinusoidal Amplitude Peak slew rate is not the same as average slew rate (25% to 75%) which is typically specified. For a natural response, peak slew rate may be 2.7 times larger than average slew rate. Therefore, calculating a full power bandwidth with a specified average slew rate will give a pessimistic result. The primary cause of overshoot in these amplifiers is the presence of large reactive loads at the output and insufficient series isolation of the load. However, it is possible to overdrive these amplifiers with 1 V, subnanosecond input-pulse edges. The ensuing dynamics may give rise to subnanosecond overshoot. To reduce these effects, an edge-rate limiting network at the input should be considered for input transition times less than 0.5 ns. The architecture of the output buffer is such that the output voltage can swing to within ~2.3 V of either rail. For example, if the output need swing only 2 V, then the buffers could be operated on dual 3.5 V or single 7 V supplies. It is cautioned that saturation effects may become noticeable when the output swings within 2.6 V of either rail. The system designer may opt to use this characteristic to his or her advantage by using the soft-saturation regime, (2.2 V–2.6 V from the supply rails), to tame excessive overshoot. The designer is cautioned that a charge storage associated time delay of several nanoseconds is incurred when recovering from soft-saturation. This effect results in longer settling tails. REV. A –9– AD8074/AD8075 RGB Buffer for Second Monitor The RGB signals for PC monitors are driven through coax cables whose characteristic impedance is 75 Ω. The graphics chip will generally have current-source output drivers that should be double terminated with a 75 Ω shunt termination at each end. On the transmit end, the shunt terminations are provided to ground close to the graphics IC, while the monitor terminates its end via internal termination resistors. While this scheme works well and is virtually foolproof for a single monitor, it leaves no means for passively connecting a second monitor to the same source. A second monitor that is connected simply in parallel will provide an extra set of terminations that will upset the signal levels. To keep costs low, most computer monitors do not have the ability to open-circuit the terminations in order that an additional monitor can be connected to the same signal, as is done in some studiotype TV monitors. A way around this problem is to connect the first monitor to the RGB channels in the standard fashion, and then to provide a triple gain-of-two buffer to drive the second monitor. The AD8075 is designed to provide this function and also provide excellent high-frequency performance for high-resolution graphics signals. Figure 3 shows a schematic of this circuit. The outputs of the AD8075 are low impedance voltage sources and are therefore series-terminated with 75 Ω resistors. The internal resistors in Monitor #2 provide the terminations at its end. The overall effect of this type of termination scheme is to divide the signal amplitude by two. This is compensated by the gain of two provided by the AD8075. PC GRAPHICS IC R 75 75 MONITOR #1 CURRENT SOURCE OUTPUT DRIVERS G 75 75 INTERNAL TERMINATIONS B 75 75 +5V +5V +5V 25 F + 0.1 F 0.1 F 0.1 F MONITOR #2 75 75 AD8075 75 75 INTERNAL TERMINATIONS 75 75 25 F + 0.1 F 0.1 F 0.1 F –5V –5V –5V Figure 3. Buffer –10– REV. A AD8074/AD8075 Triple Video Multiplexer The AD8074 and AD8075 each have an output-enable function that can be used to disable the outputs and put them in a highimpedance state. Usually, for a unity-gain device, it is relatively easy to provide high disabled impedance, because the feedback path is from the output to a high-impedance input. However, for a non-unity-gain part, the feedback provides a resistive path to ground. This will usually dominate the disabled output impedance, and make it a much lower value than the unity-gain device. The AD8075 has an internal buffer that provides a low-impedance, ground level output that terminates the feedback path during enabled operation. In the disabled state, both this buffer output +5V +5V and the amplifier output are disabled to a high impedance to provide a high-impedance disabled state. To construct a multiplexer, the outputs from one or more devices are connected in parallel and only one device is enabled at a time while all of the others are disabled. The two sets of inputs are applied individually to each of the separate device inputs. Figure 4 shows the circuit details for this function. The first RGB Source 1 is input to the first AD8075. Each of the individual signals is terminated to ground with 75 Ω to provide proper termination for the input cables. In a similar fashion, the Source 2 signals are input to the second AD8075. +5V 25 F + 0.1 F 0.1 F 0.1 F 75 R 75 R AD8075 75 SOURCE 1 G 75 G OUTPUT 75 B 75 OE B 25 F + 0.1 F 0.1 F 0.1 F –5V –5V –5V SEL1/SEL2 +5V +5V +5V 25 F + 0.1 F 0.1 F 0.1 F OE 75 R 75 AD8075 75 SOURCE 2 G 75 75 B 75 25 F + 0.1 F 0.1 F 0.1 F –5V –5V –5V Figure 4. Mux REV. A –11– AD8074/AD8075 Each of the six outputs has a 75 Ω series resistor that is used to reverse-terminate the output transmission line. The corresponding outputs are then wired in parallel and delivered to the output cable. The termination resistors in this position help to isolate the off capacitance of the disabled device’s outputs from loading the enabled device’s outputs. The gain-of-two of the AD8075 compensates for the signal halving that occurs as a result of the output terminations. A select signal is provided directly to the OE of the second AD8075 and an inverted version is used to drive the other device’s OE. This will ensure that only one device is active at a time. Since there is a total of 150 Ω in series between any two outputs, it is not essential to be overly concerned about the exact timing of the making and breaking of the enable signals. Additional inputs can easily be added to the circuit shown to make wider multiplexers. The outputs of all of the devices will be wired in parallel, and the logic must allow that only one output be enabled at a time. If it is desired to make a triple 3:1 multiplexer, a triple 2:1 multiplexer, like the AD8185 can be used along with the AD8075. The same general guidelines for input and output treatment should be followed and the logic must perform the proper function. If it is desired to design such a multiplexer at unity gain, the AD8074 should be used. For a triple 3:1 multiplexer, an AD8183 (triple 2:1 mux) can be combined with an AD8074 to provide this function. Layout and Grounding A major area of focus should be the power distribution system. There should be a full ground plane that provides the reference and return paths for both the inputs and outputs. The ground also provides isolation between the input signals to minimize the crosstalk. This ground plane should cover as wide an area as possible and be minimally interrupted in order to keep its impedance to a minimum. The power planes should also be as broad as possible to provide minimal inductance, which is required for high-slew-rate signals. These power planes layers should be spaced closely to the ground plane to increase the interplane capacitance between the supplies and ground. Each supply pin should be bypassed with a low inductance 0.1 µF ceramic capacitance with minimal excess circuit length to minimize the series impedance. A 25 µF tantalum electrolytic capacitor will supply a charge reservoir for lower frequency, high-amplitude transitions. The input and output signals should be run as directly as possible in order to minimize the effects of parasitics. If they must run over a longer distance of more than a few centimeters, controlled impedance PCB traces should be used to minimize the effect of reflections due to mismatches in impedance and the proper termination should be provided. To avoid excess crosstalk, the above recommendations should be followed carefully. The power system and signal routing are the most important aspects of preventing excess crosstalk. Beyond these techniques, shielding can be provided by ground traces between adjacent signals, especially those that travel parallel over long distances. The AD8074 and AD8075 are extreme bandwidth, high-slew-rate devices that are designed to drive up to the highest resolution monitors and provide excellent resolution. To realize their full performance potential, it is essential to adhere to the best practices of high-speed PCB layout. –12– REV. A AD8074/AD8075 TP2 VEE P1 1 VEE DO NOT INSTALL VEE IMPEDANCE LINE + C2 10 F 50 AGND VCC R16 20k W2 VCC TP5 DISOUT DISOUT 50 AGND IMPEDANCE LINE AGND R11 50 DO NOT INSTALL AGND IN2 IN2 75 IMPEDANCE LINE DO NOT INSTALL R1 75 AGND IN1 IN1 75 IMPEDANCE LINE AGND AGND AGND 75 IMPEDANCE LINE VEE R3 75 AGND C6 0.1 F AGND C8 0.01 F AGND 1 OE 2 DGND 3 IN2 4 AGND 5 IN1 6 AGND 7 IN0 8 VEE VCC 16 VCC 15 OUT2 14 VEE 13 OUT1 12 VCC 11 OUT0 10 VEE 9 C11 0.01 F AGND VEE VCC C12 0.01 F AGND AGND DUT C7 0.1 F C3 0.1 F C15 0.01 F AGND P1 3 AGND P1 2 TP1 VCC AGND AGND TP3 TP4 AGND DO NOT INSTALL VCC IMPEDANCE LINE AGND + C1 10 F 50 VCC C14 0.01 F AGND R7 75 VEE C13 0.01 F AGND R8 75 75 IMPEDANCE LINE OUT2 OUT2 R6 150 DO NOT INSTALL AGND AGND R2 75 AGND IN0 IN0 75 IMPEDANCE LINE OUT1 OUT1 R10 150 DO NOT INSTALL AGND AGND AD8074 R9 75 75 IMPEDANCE LINE OUT0 OUT0 R12 150 DO NOT INSTALL AGND AGND Figure 5. Evaluation Board Schematic REV. A –13– AD8074/AD8075 Figure 6. Component Side Figure 8. Silkscreen Top Figure 7. Circuit Side Figure 9. Silkscreen Bottom Figure 10. Internal 2 –14– REV. A AD8074/AD8075 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Controlling Dimension: Metric, shown in parentheses. 16-Lead TSSOP (RU-16) 0.201 (5.10) 0.193 (4.90) 16 9 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 8 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX SEATING PLANE 0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 8 0 0.028 (0.70) 0.020 (0.50) REV. A –15– AD8074/AD8075 Revision History Location Data Sheet changed from REV. 0 to REV. A. Page Addition to equation in SINGLE SUPPLY OPERATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 C02391–0–10/01(A) –16– REV. A PRINTED IN U.S.A.