AD8079ARZ-REEL

Dual 260 MHz Gain = +2.0 & +2.2 Buffer AD8079 a APPLICATIONS Differential A-to-D Driver Video Line Driver Differential Line Driver Professional Cameras Video Switchers Special Effects RF Receivers FUNCTIONAL BLOCK DIAGRAM 8-Pin Plastic SOIC +IN1 1 GND 2 8 OUT1 7 +VS AD8079 GND 3 6 –VS +IN2 4 5 OUT2 cables and transformers. Its low distortion and fast settling are ideal for buffering high speed dual or differential A-to-D converters. The AD8079 features a unique transimpedance linearization circuitry. This allows it to drive video loads with excellent differential gain and phase performance of 0.01% and 0.02° on only 50 mW of power per amplifier. It features gain flatness of 0.1 dB to 50 MHz. This makes the AD8079 ideal for professional video electronics such as cameras and video switchers. The AD8079 offers low power of 5 mA/amplifier (VS = ± 5 V) and can run on a single +12 V power supply while delivering over 70 mA of load current. All of this is offered in a small 8-pin SOIC package. These features make this amplifier ideal for portable and battery powered applications where size and power are critical. The outstanding bandwidth of 260 MHz along with 800 V/µs of slew rate make the AD8079 useful in many general purpose high speed applications where dual power supplies of ± 3 V to ± 6 V are required. The AD8079 is available in the industrial temperature range of –40°C to +85°C. PRODUCT DESCRIPTION Additionally, the AD8079 contains gain setting resistors factory set at G = +2.0 (A grade) or Gain = +2.2 (B grade) allowing circuit configurations with minimal external components. The B grade gain of +2.2 compensates for gain loss through a system by providing a single-point trim. Using active laser trimming of these resistors, the AD8079 guarantees tight control of gain and channel-channel gain matching. With its performance and configuration, the AD8079 is well suited for driving differential REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 1 0 RL = 100Ω SIDE 2 VIN = 50mV rms –1 SIDE 1 –2 NORMALIZED FLATNESS – dB The AD8079 is a dual, low power, high speed buffer designed to operate on ± 5 V supplies. The AD8079’s pinout offers excellent input and output isolation compared to the traditional dual amplifier pin configuration. With two ac ground pins separating both the inputs and outputs, the AD8079 achieves very low crosstalk of less than –70 dB at 5 MHz. 0.1 –3 0 –4 –0.1 –5 –0.2 –0.3 –6 SIDE 2 50Ω SIDE 1 –7 50Ω –0.4 –8 –0.5 1M –9 10M 100M FREQUENCY – Hz NORMALIZED FREQUENCY RESPONSE – dB FEATURES Factory Set Gain AD8079A: Gain = +2.0 (Also +1.0 & –1.0) AD8079B: Gain = +2.2 (Also +1 & –1.2) Gain of 2.2 Compensates for System Gain Loss Minimizes External Components Tight Control of Gain and Gain Matching (0.1%) Optimum Dual Pinout Simplifies PCB Layout Low Crosstalk of –70 dB @ 5 MHz Excellent Video Specifications (RL = 150 V) Gain Flatness 0.1 dB to 50 MHz 0.01% Differential Gain Error 0.028 Differential Phase Error Low Power of 50 mW/Amplifier (5 mA) High Speed and Fast Settling 260 MHz, –3 dB Bandwidth 750 V/ms Slew Rate (2 V Step), 800 V/ms (4 V Step) 40 ns Settling Time to 0.1% (2 V Step) Low Distortion of –65 dBc THD, fC = 5 MHz High Output Drive of Over 70 mA Drives Up to 8 Back-Terminated 75 V Loads (4 Loads/ Side) While Maintaining Good Differential Gain/ Phase Performance (0.01%/0.178) High ESD Tolerance (5 kV) Available in Small 8-Pin SOIC 1G Figure 1. Frequency Response and Flatness One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1996 AD8079–SPECIFICATIONS (@ T = +258C, V = 65 V, R = 100 V, unless otherwise noted) A Parameter DYNAMIC PERFORMANCE –3 dB Small Signal Bandwidth Bandwidth for 0.1 dB Flatness Large Signal Bandwidth Slew Rate Settling Time to 0.1% Rise & Fall Time NOISE/HARMONIC PERFORMANCE Total Harmonic Distortion Crosstalk, Output to Output Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error S L Conditions Min AD8079A/AD8079B Typ Max VIN = 50 mV rms VIN = 50 mV rms VIN = 1 V rms VO = 2 V Step VO = 4 V Step VO = 2 V Step VO = 2 V Step 260 50 100 750 800 40 2.5 MHz MHz MHz V/µs V/µs ns ns fC = 5 MHz, VO = 2 V p-p f = 5 MHz f = 10 kHz f = 10 kHz, +In NTSC, R L = 150 Ω NTSC, RL = 75 Ω NTSC, R L = 150 Ω RL = 75 Ω –65 –70 2.0 2.0 0.01 0.01 0.02 0.07 dBc dB nV/√Hz pA/√Hz % % Degree Degree DC PERFORMANCE Offset Voltage, RTO 10 10 20 3.0 TMIN–TMAX Offset Drift, RTO +Input Bias Current Gain Gain Matching INPUT CHARACTERISTICS +Input Resistance +Input Capacitance OUTPUT CHARACTERISTICS Output Voltage Swing Output Current1 Short Circuit Current1 POWER SUPPLY Operating Range Quiescent Current/Both Amplifiers Power Supply Rejection Ratio, RTO +Input Current Units TMIN–TMAX No Load RL = 150 Ω Channel-to-Channel, No Load Channel-to-Channel, RL = 150 Ω 1.998/2.198 1.995/2.195 +Input +Input R L = 150 Ω RL = 75 Ω 2.7 85 2.0/2.2 2.0/2.2 0.1 0.5 49 40 6.0 10 2.002/2.202 2.005/2.205 mV mV µV/°C ±µA ±µA V/V V/V % % 10 1.5 MΩ pF 3.1 2.8 70 110 ±V ±V mA mA ± 3.0 TMIN–TMAX +VS = +4 V to +6 V, –VS = –5 V –VS = – 4 V to –6 V, +VS = +5 V TMIN–TMAX 15 20 10.0 69 50 0.1 ± 6.0 11.5 0.5 V mA dB dB µA/V NOTES 1 Output current is limited by the maximum power dissipation in the package. See the power derating curves. Specifications subject to change without notice. –2– REV. A AD8079 ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V Internal Power Dissipation2 Small Outline Package (R) . . . . . . . . . . . . . . . . . . 0.9 Watts Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range . . . . . . . . . . . . . –65°C to +125°C Operating Temperature Range (A Grade) . . . –40°C to +85°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C The maximum power that can be safely dissipated by the AD8079 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150°C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175°C for an extended period can result in device failure. NOTES 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-Pin SOIC Package: θJA = 160°C/Watt While the AD8079 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (+150°C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves. 2.0 MAXIMUM POWER DISSIPATION – Watts TJ = +150°C 1.5 9 1.0 8-PIN SOIC PACKAGE 0.5 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE – °C Figure 2. Plot of Maximum Power Dissipation vs. Temperature ORDERING GUIDE Model Gain Temperature Range Package Description Package Option AD8079AR AD8079AR-REEL AD8079AR-REEL7 AD8079BR AD8079BR-REEL AD8079BR-REEL7 G = +2.0 G = +2.0 G = +2.0 G = +2.2 G = +2.2 G = +2.2 –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 8-Pin Plastic SOIC REEL SOIC REEL 7 SOIC 8-Pin Plastic SOIC REEL SOIC REEL 7 SOIC SO-8 SO-8 SO-8 SO-8 SO-8 SO-8 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8079 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. A –3– WARNING! ESD SENSITIVE DEVICE AD8079 0 +5V RL = 100Ω VIN = 50mV rms 10µF SIDE 2 –1 SIDE 1 –2 2 7 AD8079 VIN 1 PULSE GENERATOR NORMALIZED FLATNESS – dB 0.1µF 8 0.1µF RL = 100Ω 6 50Ω 10µF –5V TR/TF = 250ps 0.1 –3 0 –4 –0.1 –5 –0.2 –6 SIDE 2 50Ω –0.3 SIDE 1 –7 50Ω –0.4 –8 –0.5 1M –9 10M 100M FREQUENCY – Hz NORMALIZED FREQUENCY RESPONSE – dB 1 1G Figure 6. Frequency Response and Flatness Figure 3. Test Circuit –50 RL = 100Ω 100mV STEP –60 DISTORTION – dBc SIDE 1 –70 2ND HARMONIC –80 3RD HARMONIC –90 –100 SIDE 2 20mV 5ns –110 10k 100k 1M FREQUENCY – Hz 10M 100M Figure 7. Distortion vs. Frequency, RL = 100 Ω Figure 4. 100 mV Step Response –60 RL = 1kΩ VOUT = 2Vp-p 1V STEP –70 DISTORTION – dBc SIDE 1 SIDE 2 200mV –80 2ND HARMONIC –90 3RD HARMONIC –100 –110 5ns –120 10k 100k 1M FREQUENCY – Hz 10M 100M Figure 8. Distortion vs. Frequency, RL = 1 kΩ Figure 5. 1 V Step Response –4– REV. A AD8079 –30 VS = ±5V –3 –40 CROSSTALK – dB VS = ±5V RL = 100Ω V IN = 1.0V rms 0 INPUT LEVEL – dBV –20 VIN = 2V p-p RL = 100Ω –50 –60 –70 3 0 –3 V IN = 0.5V rms –6 –6 –9 –9 V IN = 0.25V rms –12 –12 –15 –15 V IN = 125mV rms –18 –18 –80 –21 –21 –90 V IN = 62.5mV rms –24 –100 –110 100k –27 1M 0.1M 1M 10M FREQUENCY – Hz Figure 9. Crosstalk (Output-to-Output) vs. Frequency 100M 5 2 BACK TERMINATED LOADS (75Ω) NTSC 0.01 2V STEP RC = 100Ω RL = 150Ω 4 3 0.00 –0.01 –0.02 1 2 3 4 5 6 IRE 7 8 9 10 11 0.08 2 BACK TERMINATED LOADS (75Ω) 0.06 0.04 1 0 –1 –2 1 BACK TERMINATED LOAD (150Ω) NTSC 9 2 1 BACK TERMINATED LOAD (150Ω) 0.1%/DIV DIFF GAIN – % –24 –27 500M Figure 12. Large Signal Frequency Response 0.02 DIFF PHASE – Degrees 10M FREQUENCY – Hz 100M 200M –3 –4 0.02 –5 0.00 1 2 3 4 5 6 IRE 7 8 9 10 0 11 20 40 60 TIME – ns 80 100 Figure 13. Short-Term Settling Time Figure 10. Differential Gain and Differential Phase (per Amplifier) RL = 100Ω 2V STEP RL = 100Ω SIDE 1 ERROR, (0.05%/DIV) SIDE 2 OUTPUT INPUT 400mV 5ns 2µs NOTES: SIDE 1: VIN = 0V; 8mV/div RTO SIDE 2: 1V STEP RTO; 400mV/div Figure 14. Long-Term Settling Time Figure 11. Pulse Crosstalk, Worst Case, 1 V Step REV. A NORMALIZED OUTPUT LEVEL – dBV 3 –10 –5– 120 AD8079 3.4 11.5 3.3 OUTPUT SWING – Volts TOTAL SUPPLY CURRENT – mA RL = 150Ω VS = ±5V 3.2 3.1 +VOUT |–VOUT| 3.0 2.9 2.8 2.7 11.0 10.5 VS = ±5V 10.0 9.5 2.6 2.5 –55 –35 –15 5 25 45 65 85 JUNCTION TEMPERATURE – °C 105 9.0 –55 125 –15 5 25 45 65 85 JUNCTION TEMPERATURE – °C 105 125 Figure 18. Total Supply Current vs. Temperature 7 120 6 115 SHORT CIRCUIT CURRENT – mA INPUT BIAS CURRENT – µA Figure 15. Output Swing vs. Temperature –35 5 4 3 +IN 2 1 0 110 105 100 |SINK ISC| SOURCE ISC 95 90 85 80 75 –1 –55 –35 –15 5 25 45 65 85 105 125 70 –55 JUNCTION TEMPERATURE – °C Figure 16. Input Bias Current vs. Temperature –35 –15 5 25 45 65 85 JUNCTION TEMPERATURE – °C 125 105 Figure 19. Short Circuit Current vs. Temperature 100 8 100 2 DEVICE #2 0 DEVICE #3 –2 10 10 NONINVERTING CURRENT VS = ±5V VOLTAGE NOISE VS = ±5V NOISE CURRENT – pA/ 4 Hz Hz 6 NOISE VOLTAGE, RTI – nV/ INPUT OFFSET VOLTAGE RTO – mV DEVICE #1 –4 –6 –55 1 10 –35 –15 5 25 45 65 85 JUNCTION TEMPERATURE – °C 105 125 100 1k FREQUENCY – Hz 10k 1 100k Figure 20. Noise vs. Frequency Figure 17. Input Offset Voltage vs. Temperature –6– REV. A AD8079 THEORY OF OPERATION 100 RESISTANCE – Ω 10 The AD8079, a dual current feedback amplifier, is internally configured for a gain of either +2 (AD8079A) or +2.2 (AD8079B). The internal gain-setting resistors effectively eliminate any parasitic capacitance associated with the inverting input pin, accounting for the AD8079’s excellent gain flatness response. The carefully chosen pinout greatly reduces the crosstalk between each amplifier. Up to four back-terminated 75 Ω video loads can be driven by each amplifier, with a typical differential gain and phase performance of 0.01%/0.17°, respectively. The AD8079B, with a gain of +2.2, can be employed as a single gain-trimming element in a video signal chain. Finally, the AD8079A/B used in conjunction with our AD8116 crosspoint matrix, provides a complete turn-key solution to video distribution. RbT = 50Ω VS = ±5.0V POWER = 0dBm (223.6mV rms) RbT = 0Ω 1 0.1 0.01 10k 100k 1M 10M FREQUENCY – Hz 100M 1G Printed Circuit Board Layout Considerations Figure 21. Output Resistance vs. Frequency As to be expected for a wideband amplifier, PC board parasitics can affect the overall closed-loop performance. If a ground plane is to be used on the same side of the board as the signal traces, a space (5 mm min) should be left around the signal lines to minimize coupling. Line lengths on the order of less than 5 mm are recommended. If long runs of coaxial cable are being driven, dispersion and loss must be considered. –44.0 –46.5 –PSRR –49.0 –51.5 Power Supply Bypassing PSRR – dB 2V SPAN –54.0 Adequate power supply bypassing can be critical when optimizing the performance of a high frequency circuit. Inductance in the power supply leads can form resonant circuits that produce peaking in the amplifier’s response. In addition, if large current transients must be delivered to the load, then bypass capacitors (typically greater than 1 µF) will be required to provide the best settling time and lowest distortion. A parallel combination of 4.7 µF and 0.1 µF is recommended. Some brands of electrolytic capacitors will require a small series damping resistor ≈ 4.7 Ω for optimum results. CURVES ARE FOR WORST CASE CONDITION WHERE ONE SUPPLY IS VARIED WHILE THE OTHER IS HELD CONSTANT. –56.5 –59.0 –61.5 –64.0 +PSRR –66.5 –69.0 –55 –35 –15 5 25 45 65 85 JUNCTION TEMPERATURE – °C 105 125 DC Errors and Noise Figure 22. PSRR vs. Temperature There are three major noise and offset terms to consider in a current feedback amplifier. For offset errors refer to the equation below. For noise error the terms are root-sum-squared to give a net output error. In the circuit below (Figure 24) they are input offset (VIO) which appears at the output multiplied by the noise gain of the circuit (1 + R F/RI), noninverting input current (IBN × RN) also multiplied by the noise gain, and the inverting input current, which when divided between RF and RI and subsequently multiplied by the noise gain always appears at the output as IBN × RF. The input voltage noise of the AD8079 is a low 2 nV/√Hz. At low gains though the inverting input current noise times RF is the dominant noise source. Careful layout and device matching contribute to better offset and drift specifications for the AD8079 compared to many other current feedback amplifiers. The typical performance curves in conjunction with the equations below can be used to predict the performance of the AD8079 in any application. 0 VIN = 200mV –4 –14 PSRR – dB –24 –PSRR –34 –44 +PSRR –54 –64 –74 –84 30k 100k 1M 10M FREQUENCY – Hz 100M 500M  V OUT =V IO ×  1+ Figure 23. PSRR vs. Frequency   RF  RF   ± I BN × RN ×  1 +  ± I BI × RF   RI  R I   where: RF = RI = 750 Ω for AD8079A RF = 750 Ω, RI = 625 Ω for AD8079B REV. A –7– 9 AD8079 RF (INTERNAL) RI (INTERNAL) RN 75Ω 75Ω CABLE VOUT #1 I BI +VS 4.7µF 75Ω RSERIES I BN VOUT 0.1µF CL 7 2 1/2 AD8079 1 Figure 24. Output Offset Voltage 6 75Ω CABLE Driving Capacitive Loads 75Ω CABLE VOUT #2 8 0.1µF 75Ω 4.7µF V IN The AD8079 was designed primarily to drive nonreactive loads. If driving loads with a capacitive component is desired, best frequency response is obtained by the addition of a small series output resistance (RSERIES). The graph in Figure 25 shows the optimum value for RSERIES vs. capacitive load. It is worth noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll-off of RSERIES and CL. 75Ω –VS 75Ω 4 1/2 AD8079 75Ω 75Ω CABLE VOUT #3 5 3 75Ω 75Ω 75Ω CABLE VOUT #4 40 75Ω 30 RSERIES – Ω Figure 26. Video Line Driver Single-Ended to Differential Driver Using an AD8079 20 10 0 0 5 10 15 20 25 C L – pF Figure 25. Recommended RSERIES vs. Capacitive Load The two halves of an AD8079 can be configured to create a single-ended to differential high speed driver with a –3 dB bandwidth in excess of 110 MHz as shown in Figure 27. Although the individual op amps are each current feedback with internal feedback resistors, the overall architecture yields a circuit with attributes normally associated with voltage feedback amplifiers, while offering the speed advantages inherent in current feedback amplifiers. In addition, the gain of the circuit can be changed by varying a single resistor, RF, which is often not possible in a dual op amp differential driver. CC = 1.5pF Operation as a Video Line Driver The AD8079 has been designed to offer outstanding performance as a video line driver. The important specifications of differential gain (0.01%) and differential phase (0.02°) meet the most exacting HDTV demands for driving one video load with each amplifier. The AD8079 also drives four back terminated loads (two each), as shown in Figure 26, with equally impressive performance (0.01%, 0.07°). Another important consideration is isolation between loads in a multiple load application. The AD8079 has more than 40 dB of isolation at 5 MHz when driving two 75 Ω back terminated loads. RF 750Ω RG 750Ω VIN OP AMP #1 50Ω 1/2 AD8079 OUTPUT #1 50Ω 1/2 AD8079 OUTPUT #2 OP AMP #2 Figure 27. Differential Line Driver –8– REV. A AD8079 The circuit consists of the two op amps each configured as a unity gain follower by the 750 Ω feedback resistors between each op amp’s output and inverting input. The output of each op amp has a 750 Ω resistor to the inverting input of the other op amp. Thus, each output drives the other op amp through a unity gain inverter configuration. By connecting the two amplifiers as cross-coupled inverters, their outputs are free to be equal and opposite, assuring zero-output common-mode voltage. 4 CC = 1.3pF VIN = 10dBm 2 0 –2 –4 –6 –8 OUT+ –10 OUT– –12 –14 0.1M With this circuit configuration, the common-mode signal of the outputs is reduced. If one output moves slightly higher, the negative input to the other op amp drives its output to go slightly lower and thus preserves the symmetry of the complementary outputs which reduces the common-mode signal. 1M 10M FREQUENCY – Hz 100M 1G Figure 28. Differential Driver Frequency Response Layout Considerations The specified high speed performance of the AD8079 requires careful attention to board layout and component selection. Proper RF design techniques and low parasitic component selection are mandatory. The resulting architecture offers several advantages. First, the gain can be changed by changing a single resistor. Changing either RF or RG will change the gain as in an inverting op amp circuit. For most types of differential circuits, more than one resistor must be changed to change gain and still maintain good CMR. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance ground path. The ground plane should be removed from the area near the input pins to reduce stray capacitance. Reactive elements can be used in the feedback network. This is in contrast to current feedback amplifiers that restrict the use of reactive elements in the feedback. The circuit described requires about 1.3 pF of capacitance in shunt across RF in order to optimize peaking and realize a –3 dB bandwidth of more than 110 MHz. Chip capacitors should be used for supply bypassing (see Figure 29). One end should be connected to the ground plane and the other within 1/8 in. of each power pin. An additional large (4.7 µF–10 µF) tantalum electrolytic capacitor should be connected in parallel, but not necessarily so close, to supply current for fast, large-signal changes at the output. The peaking exhibited by the circuit is very sensitive to the value of this capacitor. Parasitics in the board layout on the order of tenths of picofarads will influence the frequency response and the value required for the feedback capacitor, so a good layout is essential. Stripline design techniques should be used for long signal traces (greater than about 1 in.). These should be designed with a characteristic impedance of 50 Ω or 75 Ω and be properly terminated at each end. The shunt capacitor type selection is also critical. Good microwave type chip capacitors with high Q were found to yield best performance. REV. A 6 OUTPUT – dB The current feedback nature of the op amps, in addition to enabling the wide bandwidth, provides an output drive of more than 3 V p-p into a 20 Ω load for each output at 20 MHz. On the other hand, the voltage feedback nature provides symmetrical high impedance inputs and allows the use of reactive components in the feedback network. –9– 9 AD8079 +VS IN 50Ω OUT RT –VS Inverting Configuration +VS C1 0.1µF C3 10µF C2 0.1µF C4 10µF –VS Supply Bypassing Figure 30. Board Layout (Silkscreen) +VS 50Ω OUT IN RT –VS *SEE TABLE I Noninverting Configuration (G = +2) TRIM 200Ω OUT AD8079B IN RT Figure 31. Board Layout (Component Layer) Optional Gain Trim (G = +2 → +2.2) TIE INPUT PINS TOGETHER TO MINIMIZE PEAKING +VS OUT IN RT –VS Noninverting Configuration (G = +1) Figure 29. Inverting and Noninverting Configurations Table I. Recommended Component Values Component –1 +1 +2/+2.2 RT (Nominal) (Ω) Small Signal BW (MHz) 0.1 dB Flatness (MHz) 53.6 220 50 49.9 750 100 49.9 260 50 Figure 32. Board Layout (Solder Side; Looking Through the Board) –10– REV. A AD8079 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead SOIC (SO-8) 0.1968 (5.00) 0.1890 (4.80) 0.1574 (4.00) 0.1497 (3.80) 8 5 1 4 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.0098 (0.25) 0.0688 (1.75) 0.0196 (0.50) 0.0532 (1.35) 0.0099 (0.25) x 45° 0.0040 (0.10) SEATING PLANE 0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) BSC 0.0098 (0.25) 8° 0° 0.0500 (1.27) 0.0075 (0.19) 0.0160 (0.41) 9 REV. A –11– –12– PRINTED IN U.S.A. C2185a–xx–11/96