AD8112

Audio/Video, 60 MHz, 16 × 8, Gain of +2 Crosspoint Switch AD8112 FEATURES Low cost, 16 × 8, high speed, nonblocking switch array Pin-compatible 16 × 16 version available (AD8113) Serial or parallel programming of switch array Serial data out allows daisy chaining control of multiple 16 × 8 arrays to create larger switch arrays Output disable allows connection of multiple devices without loading the output bus Complete solution Buffered inputs 8 output amplifiers Operates on ±5 V or ±12 V supplies Low supply current of 54 mA Excellent audio performance VS = ±12 V ±10 V output swing 0.002% THD at 20 kHz maximum 20 V p-p (RL = 600 Ω) Excellent video performance VS = ±5 V 0.1 dB gain flatness of 10 MHz 0.1% differential gain error (RL = 1 kΩ) 0.1° differential phase error (RL = 1 kΩ) Excellent ac performance −3 dB bandwidth 60 MHz Low all-hostile crosstalk of −83 dB at 20 kHz Reset pin allows disabling of all outputs (connected to a capacitor to ground provides power-on reset capability) 100-lead LQFP (14 mm × 14 mm) FUNCTIONAL BLOCK DIAGRAM SER/PAR D0 D1 D2 D3 D4 A0 A1 A2 80-BIT SHIFT REGISTER WITH 5-BIT PARALLEL LOADING 40 PARALLEL LATCH 40 DECODE 8 × 5:16 DECODERS 40 CLK DATA IN UPDATE CE RESET DATA OUT 8 AD8112 128 OUTPUT BUFFER G = +2 ENABLE/DISABLE SET INDIVIDUAL OR RESET ALL OUTPUTS TO OFF 8 OUTPUTS 06523-001 NO CONNECT 16 INPUTS SWITCH MATRIX APPLICATIONS CCTV surveillance/DVR Analog/digital audio routers Video routers (NTSC, PAL, S-Video, SECAM) Multimedia systems Video conferencing Figure 1. GENERAL DESCRIPTION The AD8112 is a low cost, fully buffered crosspoint switch matrix that operates on ±12 V for audio applications and ±5 V for video applications. It offers a −3 dB signal bandwidth greater than 60 MHz and channel switch times of less than 60 ns with 0.1% settling for use in both analog and digital audio. The AD8112 operated at 20 kHz has a crosstalk performance of −83 dB and isolation of 90 dB. In addition, ground/power pins surround all inputs and outputs to provide extra shielding for operation in the most demanding audio routing applications. With a differential gain and differential phase better than 0.1% and 0.1°, respectively, and a 0.1 dB flatness output of up to 10 MHz, the AD8112 is suitable for many video applications. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. The AD8112 includes eight independent output buffers that can be placed into a disabled state for paralleling crosspoint outputs so that off channel loading is minimized. The AD8112 has a gain of +2. It operates on voltage supplies of ±5 V or ±12 V while consuming only 34 mA or 31 mA of current, respectively. The channel switching is performed via a serial digital control (which can accommodate the daisy chaining of several devices) or via a parallel control, allowing updating of an individual output without reprogramming the entire array. The AD8112 is packaged in a 100-lead LQFP and is available over the commercial temperature range of 0°C to 70°C. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. AD8112 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics (Serial) .................................................. 5 Timing Characteristics (Parallel) ............................................... 6 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Power Dissipation......................................................................... 7 Pin Configuration and Function Descriptions............................. 9 I/O Schematics............................................................................ 11 Typical Performance Characteristics ........................................... 12 Theory of Operation ...................................................................... 17 Calculation of Power Dissipation............................................. 17 Short-Circuit Output Conditions............................................. 18 Application Notes ........................................................................... 19 Serial Programming ................................................................... 19 Parallel Programming................................................................ 19 Power-On Reset.......................................................................... 20 Specifying Audio Levels ............................................................ 20 Creating Unity-Gain Channels................................................. 20 Video Signals............................................................................... 20 Creating Larger Crosspoint Arrays.......................................... 21 Multichannel Video and Audio ................................................ 23 Crosstalk ...................................................................................... 23 PCB Layout...................................................................................... 26 Outline Dimensions ....................................................................... 28 Ordering Guide .......................................................................... 28 REVISION HISTORY 2/07—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD8112 SPECIFICATIONS TA = 25°C, VS = ±12 V, RL = 600 Ω, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Conditions VOUT = 200 mV p-p, RL = 600 Ω, VS = ±12 V VOUT = 200 mV p-p, RL = 150 Ω, VS = ±5 V VOUT = 8 V p-p, RL = 600 Ω, VS = ±12 V VOUT = 2 V p-p, RL = 150 Ω, VS = ±5 V 0.1 dB, VOUT = 200 mV p-p, RL = 150 Ω, VS = ±5 V VOUT = 2 V p-p, RL = 150 Ω 0.1%, 2 V Step, RL = 150 Ω, VS = ±5 V 2 V step, RL = 150 Ω, VS = ±5 V 20 V step, RL = 600 Ω, VS = ±12 V NTSC, RL = 1 kΩ, VS = ±5 V NTSC, RL = 1 kΩ, VS = ±5 V 20 kHz, RL = 600 Ω, 20 V p-p f = 5 MHz, RL = 150 Ω, VS = ±5 V f = 20 kHz f = 5 MHz, RL = 150 Ω, VS = ±5 V, one channel f = 20 kHz, one channel 20 kHz 0.1 MHz to 10 MHz No load, VS = ±12 V, VOUT = ±8 V RL = 600 Ω, VS = ±12 V RL = 150 Ω, VS = ±5 V No load, channel-to-channel RL = 600 Ω, channel-to-channel RL = 150 Ω, channel-to-channel Min 46 41 Typ 60 60 10 25 10 20 23 100 120 0.1 0.1 0.002 −67 −83 −100 −83 14 12 0.3 0.5 0.5 0.7 0.7 0.7 20 0.3 4 5 ±3.5 ±10.5 ±3 ±10 55 ±4.5 10 ±1.5 ±5.0 4 50 ±1.6 ±8.5 2.5 Max Unit MHz MHz MHz MHz MHz ns ns V/μs V/μs % Degrees % dB dB dB dB nV/√Hz nV/√Hz % % % % % % ppm/°C Ω kΩ pF V V V V mA mV μV/°C V V pF MΩ μA Gain Flatness Propagation Delay Settling Time Slew Rate NOISE/DISTORTION PERFORMANCE Differential Gain Error Differential Phase Error Total Harmonic Distortion Crosstalk, All Hostile Off Isolation Input Voltage Noise DC PERFORMANCE Gain Error Gain Matching 3.5 Gain Temperature Coefficient OUTPUT CHARACTERISTICS Output Resistance Output Capacitance Output Voltage Swing Short-Circuit Current INPUT CHARACTERISTICS Input Offset Voltage Input Voltage Range Input Capacitance Input Resistance Input Bias Current Enabled Disabled Disabled VS = ±5 V, no load VS = ±12 V, no load IOUT = 20 mA, VS = ±5 V IOUT = 20 mA, VS = ±12 V RL = 0 Ω All configurations Temperature coefficient No load, VS = ±5 V VS = ±12 V Any switch configuration Any number of enabled inputs 3.4 ±3.2 ±10.3 ±2.7 ±9.8 +1 Rev. 0 | Page 3 of 28 AD8112 Parameter SWITCHING CHARACTERISTICS Enable On Time Switching Time, 2 V Step Switching Transient (Glitch) POWER SUPPLIES Supply Current Conditions Min Typ 80 50 20 50 34 45 31 50 34 45 31 8 4.5 −12.6 4.5 75 54 38 50 35 54 38 50 35 13 12.6 −4.5 5.5 80 60 40 0 to 70 40 Max Unit ns ns mV p-p mA mA mA mA mA mA mA mA mA V V V dB dB dB °C °C/W 50% update to 1% settling AVCC outputs enabled, no load, VS = ±12 V AVCC outputs disabled, VS = ±12 V AVCC outputs enabled, no load, VS = ±5 V AVCC outputs disabled, VS = ±5 V AVEE outputs enabled, no load, VS = ±12 V AVEE outputs disabled, VS = ±12 V AVEE outputs enabled, no load, VS = ±5 V AVEE outputs disabled, VS = ±5 V DVCC outputs enabled, no load AVCC AVEE DVCC DC f = 100 kHz f = 1 MHz Operating (still air) Operating (still air) DYNAMIC PERFORMANCE Supply Voltage Range PSRR OPERATING TEMPERATURE RANGE Temperature Range θJA Rev. 0 | Page 4 of 28 AD8112 TIMING CHARACTERISTICS (SERIAL) Table 2. Parameter Serial Data Setup Time CLK Pulse Width Serial Data Hold Time CLK Pulse Separation, Serial Mode CLK to UPDATE Delay UPDATE Pulse Width CLK to DATA OUT Valid, Serial Mode Propagation Delay, UPDATE to Switch On or Off Data Load Time, CLK = 5 MHz, Serial Mode CLK, UPDATE Rise and Fall Times RESET Time 1 CLK 0 1 DATA IN 0 1 = LATCHED UPDATE 0 = TRANSPARENT Symbol t1 t2 t3 t4 t5 t6 t7 Min 20 100 20 100 0 50 Limit Typ Max 200 50 16 100 200 Unit ns ns ns ns ns ns ns ns μs ns ns t2 t4 LOAD DATA INTO SERIAL REGISTER ON FALLING EDGE OUT07 (D3) OUT00 (D0) t1 t3 OUT07 (D4) t5 TRANSFER DATA FROM SERIAL REGISTER TO PARALLEL LATCHES DURING LOW LEVEL t6 t7 DATA OUT Figure 2. Timing Diagram, Serial Mode Table 3. Logic Levels Pins RESET, SER/PAR, CLK, DATA IN, CE, UPDATE DATA OUT VIH 2.0 V min VIL 0.8 V max VOH VOL IIH 20 μA max IIL −400 μA min IOH IOL 2.7 V min 0.5 V max −400 μA max 06523-002 3.0 mA min Rev. 0 | Page 5 of 28 AD8112 TIMING CHARACTERISTICS (PARALLEL) Table 4. Parameter Data Setup Time CLK Pulse Width Data Hold Time CLK Pulse Separation CLK to UPDATE Delay UPDATE Pulse Width Propagation Delay, UPDATE to Switch On or Off CLK, UPDATE Rise and Fall Times RESET Time Symbol t1 t2 t3 t4 t5 t6 Min 20 100 20 100 0 50 Limit Max Unit ns ns ns ns ns ns ns ns ns 50 100 200 t2 1 CLK 0 t4 t1 D0 TO D4 A0 TO A2 1 0 t3 t5 1 = LATCHED UPDATE 0 = TRANSPARENT t6 06523-003 Figure 3. Timing Diagram, Parallel Mode Table 5. Logic Levels Pins RESET, SER/PAR, CLK, D0, D1, D2, D3, D4, A0, A1, A2, CE, UPDATE DATA OUT VIH 2.0 V min VIL 0.8 V max VOH VOL IIH 20 μA max IIL −400 μA min IOH IOL 2.7 V min 0.5 V max −400 μA max 3.0 mA min Rev. 0 | Page 6 of 28 AD8112 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Analog Supply Voltage (AVCC to AVEE) Digital Supply Voltage (DVCC to DGND) Ground Potential Difference (AGND to DGND) Internal Power Dissipation1 Analog Input Voltage2 Digital Input Voltage Output Voltage (Disabled Output) Output Short-Circuit Duration Storage Temperature Range Lead Temperature (Soldering 10 sec) 1 POWER DISSIPATION Rating 26.0 V 6V ±0.5 V 3.1 W Maintain linear output DVCC (AVCC − 1.5 V) to (AVEE + 1.5 V) Momentary −65°C to +125°C 300°C The AD8112 is operated with ±5 V to ±12 V supplies and can drive loads down to 150 Ω (±5 V) or 600 Ω (±12 V), resulting in a large range of possible power dissipations. For this reason, extra care must be taken when derating the operating conditions based on ambient temperature. Packaged in a 100-lead LQFP, the AD8112 junction-to-ambient thermal impedance (θJA) is 40°C/W. For long-term reliability, the maximum allowed junction temperature of the plastic encapsulated die should not exceed 150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure. The curve in Figure 4 shows the range of allowed power dissipations that meet these conditions over the commercial range of ambient temperatures. 4.0 TJ = 150°C 3.5 Specification is for device in free air (TA = 25°C): 100-lead plastic LQFP (ST): θJA = 40°C/W. 2 To avoid differential input breakdown, ensure that one-half the output voltage (1/2 VOUT) and any input voltage is less than 10 V of the potential differential. See Output Voltage Swing specification for linear output range. MAXIMUM POWER (W) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3.0 ESD CAUTION 2.5 06523-004 2.0 0 10 20 30 40 50 AMBIENT TEMPERATURE (°C) 60 70 Figure 4. Maximum Power Dissipation vs. Ambient Temperature Rev. 0 | Page 7 of 28 AD8112 Table 7. Operation Truth Table CE 1 0 UPDATE X 1 CLK X DATA IN X Data i DATA OUT X Data i-80 RESET X 1 SER/PAR X 0 Operation/Comment No change in logic. The data on the serial DATA IN line is loaded into serial register. The first bit clocked into the serial register appears at DATA OUT 80 clocks later. The data on the parallel data lines, D0 to D4, is loaded into the 80-bit serial shift register location addressed by A0 to A2. Data in the 80-bit shift register transfers into the parallel latches that control the switch array. Latches are transparent. Asynchronous operation. All outputs are disabled. Remainder of logic is unchanged. 0 1 D0 ... D4, A0 ... A2 X X X X 0 X 0 X N/A in Parallel Mode X X 1 1 1 0 X X PARALLEL DATA (OUTPUT ENABLE) SER/PAR D0 D1 D2 D3 D4 S D1 S D1 DQ CLK Q D0 DQ CLK DATA IN (SERIAL) Q D0 S D1 Q D0 S D1 DQ CLK Q DQ D0 CLK S D1 Q DQ D0 CLK S D1 Q D0 DQ CLK S D1 Q DQ D0 CLK S D1 Q D0 DQ CLK S D1 Q D0 DQ CLK S D1 Q D0 DQ CLK S D1 Q D0 DQ CLK S D1 Q DQ D0 CLK DATA OUT CLK CE UPDATE OUT00 EN OUTPUT ADDRESS OUT01 EN 3-TO-16 DECODER OUT02 EN OUT03 EN OUT04 EN OUT05 EN OUT06 EN OUT07 EN A0 A1 A2 LE D OUT00 B0 Q LE D OUT00 B1 Q LE D OUT00 B2 Q LE D OUT00 B3 Q LE D OUT00 EN CLR Q LE D OUT01 B0 Q LE D OUT06 EN CLR Q LE D OUT07 B0 Q LE D OUT07 B1 Q LE D OUT07 B2 Q LE D OUT07 B3 Q LE D OUT07 EN CLR Q RESET (OUTPUT ENABLE) DECODE 06523-005 128 SWITCH MATRIX 8 OUTPUT ENABLE Figure 5. Logic Diagram Rev. 0 | Page 8 of 28 AD8112 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DATA OUT SER/PAR UPDATE DATA IN RESET DGND CLK NC NC NC NC NC NC NC NC NC CE A0 A1 A2 D0 D1 D2 78 D3 77 100 99 97 96 95 93 92 91 90 89 87 86 85 79 81 98 94 83 DVCC DGND AGND IN08 AGND IN09 AGND IN10 AGND IN11 AGND IN12 AGND IN13 AGND IN14 AGND IN15 AGND AVEE AVCC AVCC NC AVEE NC 82 80 88 84 76 D4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIN 1 75 74 73 72 71 70 69 68 67 66 65 DVCC DGND AGND IN07 AGND IN06 AGND IN05 AGND IN04 AGND IN03 AGND IN02 AGND IN01 AGND IN00 AGND AVEE AVCC AVCC00 OUT00 AVEE00/01 OUT01 TOP VIEW (Not to Scale) AD8112 64 63 62 61 60 59 58 57 56 55 54 53 52 51 27 40 41 42 46 47 48 45 26 28 29 34 37 38 39 43 30 31 32 36 33 44 49 NC = NO CONNECT 35 OUT06 OUT05 OUT07 OUT04 AVCC AVCC NC NC NC NC OUT03 AVEE06/07 AVEE04/05 AVCC03/04 AVCC05/06 AVEE02/03 OUT02 AVEE AVEE AVCC AVEE NC NC AVCC AVCC01/02 50 Figure 6. Pin Configuration Table 8. Pin Function Descriptions Pin No. 58, 60, 62, 64, 66, 68, 70, 72, 4, 6, 8, 10, 12, 14, 16, 18 96 97 98 95 100 99 94 53, 51, 49, 47, 45, 43, 41, 39 3, 5, 7, 9, 11, 13, 15, 17, 19, 57, 59, 61, 63, 65, 67, 69, 71, 73 1, 75 2, 74, 81 20, 24, 28, 32, 36, 56 Mnemonic IN00 to IN15 1 DATA IN CLK DATA OUT UPDATE RESET CE SER/PAR OUT00 to OUT071 AGND DVCC DGND AVEE Description Analog Inputs for Channel Numbers 00 through 15. Serial Data Input, TTL-compatible. Clock, TTL-compatible. Falling edge triggered. Serial Data Output, TTL-compatible. Enable (Transparent) Low. Allows serial register to connect directly to switch matrix. Data latched when high. Disable Outputs, Active Low. Chip Enable, Enable Low. Must be low to clock in and latch data. Serial Data/Parallel Data. When low, this pin selects serial data mode; when high, this pin selects parallel data mode, high. Must be connected. Analog Outputs for Channel Numbers 00 Through 07. Analog Ground for Inputs and Switch Matrix. Must be connected. 5 V for Digital Circuitry. Ground for Digital Circuitry. −5 V for Inputs and Switch Matrix. Rev. 0 | Page 9 of 28 06523-006 AD8112 Pin No. 21, 22, 26, 30, 34, 38, 55 54 50, 46, 42 52, 48, 44, 40 84 83 82 80 79 78 77 76 23, 25, 27, 29, 31, 33, 35, 37, 85 to 93 1 Mnemonic AVCC AVCCxx AVCCxx/yy1 AVEExx/yy1 A0 A1 A2 D0 D1 D2 D3 D4 NC Description 5 V for Inputs and Switch Matrix. 5 V for Output Amplifier. This pin is shared by Channel Numbers xx and yy. Must be connected. 5 V for Output Amplifier. This pin is shared by Channel Numbers xx and yy. Must be connected. −5 V for Output Amplifier. This pin is shared by Channel Numbers xx and yy. Must be connected. Parallel Data Input, TTL-compatible (Output Select LSB). Parallel Data Input, TTL-compatible (Output Select). Parallel Data Input, TTL-compatible (Output Select). Parallel Data Input, TTL-compatible (Input Select LSB). Parallel Data Input, TTL-compatible (Input Select). Parallel Data Input, TTL-compatible (Input Select). Parallel Data Input, TTL-compatible (Input Select MSB). Parallel Data Input, TTL-compatible (Output Enable). No Connect. xx = Chanel numbers 00 through 15 for analog inputs; yy = channel numbers 00 through 07 for analog outputs. Rev. 0 | Page 10 of 28 AD8112 I/O SCHEMATICS VCC ESD INPUT ESD 06523-007 VCC ESD INPUT ESD DGND 06523-010 AVEE Figure 7. Analog Input Figure 10. Logic Input VCC ESD OUTPUT ESD 06523-008 VCC 2kΩ ESD OUTPUT ESD DGND 06523-011 AVEE Figure 8. Analog Output VCC ESD RESET ESD DGND 06523-009 Figure 11. Logic Output 20kΩ Figure 9. Reset Input Rev. 0 | Page 11 of 28 AD8112 TYPICAL PERFORMANCE CHARACTERISTICS 3 3 0 GAIN (dB) 0 GAIN (dB) –3 –3 06523-013 –6 0.01 0.1 1 FREQUENCY (MHz) 10 100 –6 0.1 1 10 FREQUENCY (MHz) 100 Figure 12. Small-Signal Bandwidth, VS = ±5 V, RL = 150 Ω, VOUT = 200 mV p-p Figure 15. Small-Signal Bandwidth, VS = ±12 V, RL = 600 Ω, VOUT = 200 mV p-p 0.3 0.3 0.2 0.2 GAIN FLATNESS (dB) 0.1 GAIN FLATNESS (dB) 0.1 0 0 –0.1 –0.1 –0.2 –0.2 06523-014 06523-048 –0.3 0.1 –0.3 0.1 1 1 10 FREQUENCY (MHz) 100 10 FREQUENCY (MHz) 100 Figure 13. Small-Signal Gain Flatness, VS = ±5 V, RL = 150 Ω, VOUT = 200 mV p-p Figure 16. Small-Signal Gain Flatness, VS = ±12 V, RL = 600 Ω, VOUT = 200 mV p-p 3 3 0 GAIN (dB) GAIN (dB) 0 –3 –3 06523-015 –6 0.1 1 10 FREQUENCY (MHz) 100 –6 0.1 1 10 FREQUENCY (MHz) 100 Figure 14. Large-Signal Bandwidth, VS = ±5 V, RL = 150 Ω, VOUT = 2 V p-p Figure 17. Large-Signal Bandwidth, VS = ±12 V, RL = 600 Ω, VOUT = 8 V p-p Rev. 0 | Page 12 of 28 06523-049 06523-047 AD8112 0.3 0.3 0.2 GAIN FLATNESS (dB) GAIN FLATNESS (dB) 0.2 0.1 0.1 0 0 –0.1 –0.1 06523-016 –0.3 0.1 1 10 FREQUENCY (MHz) 100 –0.3 0.1 1 FREQUENCY (MHz) 10 Figure 18. Large-Signal Gain Flatness, VS = ±5 V, RL = 150 Ω, VOUT = 2 V p-p Figure 21. Large-Signal Gain Flatness, VS = ±12 V, RL = 600 Ω, VOUT = 8 V p-p –40 ALL HOSTILE –50 –30 –40 ALL HOSTILE CROSSTALK (dB) ADJACENT –70 CROSSTALK (dB) –60 –50 –60 ADJACENT –70 –80 –90 06523-017 –80 06523-051 –100 0.1 1 10 FREQUENCY (MHz) 100 –90 0.01 0.1 1 FREQUENCY (MHz) 10 100 Figure 19. Crosstalk vs. Frequency, VS = ±5 V, RL = 150 Ω, VOUT = 2 V p-p Figure 22. Crosstalk vs. Frequency, VS = ±12 V, RL = 600 Ω, VOUT = 20 V p-p –50 –70 –75 –80 –60 DISTORTION (dBc) –70 SECOND HARMONIC –80 DISTORTION (dBc) –85 –90 –95 –100 THIRD HARMONIC –105 0.001 0.01 0.1 FREQUENCY (MHz) 1 SECOND HARMONIC –90 –100 06523-018 –110 0.001 0.01 0.1 1 FREQUENCY (MHz) 10 100 Figure 20. Distortion vs. Frequency, VS = ±5 V, RL = 150 Ω, VOUT = 2 V p-p Figure 23. Distortion vs. Frequency, VS = ±12 V, RL = 600 Ω, VOUT = 20 V p-p Rev. 0 | Page 13 of 28 06523-052 THIRD HARMONIC 06523-050 –0.2 –0.2 AD8112 300 250 CAPACITIVE LOAD (pF) INPUT 200 150 VS = ±12V RL = 600Ω VS = ±5V RL = 150Ω 0.1%/DIV OUTPUT – INPUT 2 OUTPUT 100 50 06523-019 0 0 5 10 15 20 25 SERIES RESISTANCE (Ω) 30 35 0 5 10 15 20 25 5ns/DIV 30 35 40 45 50 Figure 24. Capacitive Load vs. Series Resistance for Less than 30% Overshoot 10k Figure 27. Settling Time to 0.1%, 2 V Step, VS = ±5 V, RL = 150 Ω 10k 1k 1k IMPEDANCE (Ω) IMPEDANCE (Ω) 100 100 10 06523-020 10 06523-053 1 0.1 1 10 FREQUENCY (MHz) 100 1k 1 0.1 1 10 FREQUENCY (MHz) 100 1k Figure 25. Disabled Output Impedance vs. Frequency, VS = ±5 V 1k Figure 28. Disabled Output Impedance vs. Frequency, VS = ±12 V 1k 100 IMPEDANCE (Ω) IMPEDANCE (Ω) 100 10 10 1 06523-021 1 06523-054 0.1 0.1 1 10 FREQUENCY (MHz) 100 1k 0.1 0.1 1 10 FREQUENCY (MHz) 100 1k Figure 26. Enabled Output Impedance vs. Frequency, VS = ±5 V Figure 29. Enabled Output Impedance vs. Frequency, VS = ±12 V Rev. 0 | Page 14 of 28 06523-022 AD8112 0 –10 –20 –30 PSRR (dB) 0 –20 –40 –50 –60 –70 PSRR (dB) –40 +PSRR –60 –PSRR –80 +PSRR –PSRR 06523-023 –90 0.01 0.1 1 FREQUENCY (MHz) 10 –100 0.01 0.1 1 FREQUENCY (MHz) 10 Figure 30. PSRR vs. Frequency, VS = ±5 V Figure 33. PSRR vs. Frequency, VS = ±12 V 160 140 0 –20 120 OFF ISOLATION (dB) NOISE (nV/ Hz) 100 80 60 40 06523-024 –40 VS = ±12V RL = 600Ω VOUT = 8V p-p –60 –80 VS = ±5V RL = 150Ω VOUT = 2V p-p 1 10 FREQUENCY (MHz) 0 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M –120 0.1 100 Figure 31. Noise vs. Frequency Figure 34. Off Isolation vs. Frequency 50mV/DIV 50mV/DIV 06523-025 50ns/DIV 100ns/DIV Figure 32. Small-Signal Pulse Response, VS = ±5 V, RL = 150 Ω Figure 35. Small-Signal Pulse Response, VS = ±12 V, RL = 600 Ω Rev. 0 | Page 15 of 28 06523-056 06523-026 20 –100 06523-055 –80 AD8112 500mV/DIV 5V/DIV 06523-027 100ns/DIV 100ns/DIV Figure 36. Large-Signal Pulse Response, VS = ±5 V, RL = 150 Ω Figure 39. Large-Signal Pulse Response, VS = ±12 V, RL = 600 Ω UPDATE UPDATE 2V/DIV 2V/DIV VOUT VOUT INPUT 0 INPUT 1 06523-028 10V/DIV INPUT 0 INPUT 1 06523-058 100ns/DIV 100ns/DIV Figure 37. Switching Time, VS = ±5 V, RL = 150 Ω Figure 40. Switching Time, VS = ±12 V, RL = 600 Ω UPDATE UPDATE 1V/DIV 1V/DIV OUTPUT 20mV/DIV OUTPUT 20mV/DIV 06523-029 06523-057 100ns/DIV 100ns/DIV Figure 38. Switching Transient, VS = ±5 V, RL = 150 Ω Figure 41. Switching Transient, VS = ±12 V, RL = 600 Ω Rev. 0 | Page 16 of 28 06523-059 AD8112 THEORY OF OPERATION The AD8112 has a gain of +2 and is a crosspoint array with eight outputs, each of which can be connected to any one of 16 inputs. Organized by output row, 16 switchable transconductance stages are connected to each output buffer in the form of a 16-to-1 multiplexer. Each of the 16 rows of transconductance stages are wired in parallel to the 16 input pins, for a total array of 256 transconductance stages. Decoding logic for each output selects one (or none) of the transconductance stages to drive the output stage. The transconductance stages are NPN input differential pairs, sourcing current into the folded cascode output stage. The compensation networks and emitter follower output buffers are in the output stage. Voltage feedback sets the gain at +2. When operated with ±12 V supplies, this architecture provides ±10 V drive for 600 Ω audio loads with extremely low distortion (> 0.5 V). PDQ, OUTPUT = (AVCC − AVEE) × IO, QUIESCENT PDQ, OUTPUT = (12 V − (−12 V)) × 0.67 mA = 16 mW For nonsinusoidal output, the power dissipation is calculated by integrating the on-chip voltage drop multiplied by the load current over one period. The user can subtract the quiescent current for the Class AB output stage when calculating the loaded power dissipation. For each output stage driving a load, subtract a quiescent power according to PD, OUTPUT = (AVCC − AVEE) × IO, QUIESCENT There are eight outputs, thus nPDQ, OUTPUT = 8 × 16 mW = 0.13 W 4. Verify that power dissipation does not exceed the maximum allowed value. PD, ON-CHIP = PD, QUIESCENT + nPD, OUTPUT − nPDQ, OUTPUT PD, ON-CHIP = 1.3 W + 0.55 W − 0.13 W = 1.7 W where: IO, QUIESCENT = 0.67 mA. For each disabled output, the quiescent power supply current in AVCC and AVEE drops by approximately 1.25 mA, although there is a power dissipation in the on-chip feedback resistors if the disabled output is being driven from an external source. AVCC IO, QUIESCENT QNPN RF 4kΩ VOUTPUT IOUTPUT AGND IO, QUIESCENT 06523-031 This power dissipation is below the maximum allowed dissipation for all ambient temperatures approaching 70°C. It can be shown that for a dual supply of ±a, a Class AB output stage dissipates maximum power into a grounded load when the output voltage is a/2. Therefore, for a ±12 V supply, the previous example demonstrates the worst-case power dissipation into 600 Ω. It can be seen from this example that the minimum load resistance for ±12 V operation is 600 Ω for full rated operating temperature range. For larger safety margins when the output signal is unknown, loads of 1 kΩ and greater are recommended. When operating with ±5 V supplies, this load resistance can be lowered to 150 Ω. QPNP SHORT-CIRCUIT OUTPUT CONDITIONS Although there is short-circuit current protection on the AD8112 outputs, the output current can reach values of 55 mA into a grounded output. Sustained operation with even one shorted output will exceed the maximum die temperature and may result in device failure (see the Absolute Maximum Ratings section). AVEE Figure 43. Simplified Output Stage Example The power supplies of the AD8112 with an ambient temperature of 70°C and all eight outputs driving 6 V rms into 600 Ω loads are ±12 V. 1. Calculate the power dissipation of the AD8112 using quiescent currents (see the Specifications section). PD, QUIESCENT = (AVCC + IAVCC) + (AVEE × IAVEE) + (DVCC × IDVCC) PD, QUIESCENT = (12 V × 54 mA) + (−12 V × −54 mA) + (5 V × 13 mA) = 1.3 W Rev. 0 | Page 18 of 28 AD8112 APPLICATION NOTES The AD8112 has two options for changing the programming of the crosspoint matrix. In the first option, a serial word of 80 bits is provided to update the entire matrix. The serial data needs to be prefixed with 40 zeros because there are 40 unconnected bits. The second option allows for changing a single output’s programming via a parallel interface. The serial option requires fewer signals but more time (clock cycles) for changing the programming, whereas the parallel programming technique requires more signals but can change outputs individually and requires fewer clock cycles to complete programming. PARALLEL PROGRAMMING When using the parallel programming mode, it is not necessary to reprogram the entire device when making changes to the matrix. In fact, parallel programming allows the modification of a single output. Because this requires only one CLK/UPDATE cycle, significant time is saved by using parallel programming. One important consideration when using parallel programming is that the RESET signal does not reset all registers in the AD8112. When taken low, the RESET signal only sets each output to the disabled state. This is helpful during power-up to ensure that two parallel outputs will not be active at the same time. After initial power-up, the internal registers in the device generally have random data, even though the RESET signal has been asserted. If parallel programming is used to program one output, then that output is properly programmed, but the rest of the device has a random program state depending on the internal register content at power-up. Therefore, when using parallel programming, it is essential that all outputs be programmed to a desired state after power-up to ensure that the programming matrix is always in a known state. Then, parallel programming can be used to modify a single output or multiple outputs. Similarly, if both CE and UPDATE are taken low after initial power-up, the random power-up data in the shift register is programmed into the matrix. Therefore, to prevent the crosspoint from being programmed into an unknown state, do not apply low logic levels to both CE and UPDATE after power is initially applied. Programming the full shift register one time to a desired state, by either serial or parallel programming after initial power-up, eliminates the possibility of programming the matrix to an unknown state. To change an output programming via parallel programming, SER/PAR and UPDATE should be taken high and CE should be taken low. The CLK signal should be in the high state. The 3-bit address of the output to be programmed should be put on A0 to A2. The first four data bits (D0 to D3) should contain the information identifying the input that is programmed to the addressed output. The fifth data bit (D4) determines the enabled state of the output. If D4 is low (output disabled), the data on D0 to D3 does not matter. After the desired address and data signals have been established, the data can be latched into the shift register by a high to low transition of the CLK signal. The matrix will not be programmed, however, until the UPDATE signal is taken low. It is therefore possible to latch in new data for several or all outputs via successive negative transitions of CLK while UPDATE is held high, and then for the new data to take effect when UPDATE goes SERIAL PROGRAMMING The serial programming mode uses the device pins: CE, CLK, DATA IN, UPDATE, and SER/PAR. The first step is to assert a low on SER/PAR to enable the serial programming mode. The CE pin for the chip must be low to allow data to be clocked into the device. The CE signal can be used to address an individual device when devices are connected in parallel. The UPDATE signal should be high during the time that data is shifted into the device’s serial port. Although the data shifts in when UPDATE is low, the transparent asynchronous latches allow the shifting data to reach the matrix. This causes the matrix to try to update to every intermediate state as defined by the shifting data. The data at DATA IN is clocked in upon each falling edge of CLK. A total of 80 bits must be shifted in to complete the programming because there are 40 unconnected bits. For each of the eight outputs, there are four bits (D0 to D3) that determine the source of the input followed by one bit (D4) that determines the enabled state of the output. If D4 is low (output disabled), the four associated bits (D0 to D3) do not matter, because no input will be switched to that output. The most significant output address data is shifted in first, and then followed in sequence until the least significant output address data is shifted in. At this point UPDATE can be taken low, which programs the device with the data that was just shifted in. The UPDATE registers are asynchronous, and when UPDATE is low (and CE is low), they are transparent. If more than one AD8112 device is to be serially programmed in a system, the DATA OUT signal from one device can be connected to the DATA IN of the next device to form a serial chain. All of the CLK, CE, UPDATE, and SER/PAR pins should be connected in parallel and operated as described previously. The serial data is input into the DATA IN pin of the first device of the chain, and it ripples through to the last device. Therefore, the data for the last device in the chain should come at the beginning of the programming sequence. The length of the programming sequence is 80 bits times the number of devices in the chain. Rev. 0 | Page 19 of 28 AD8112 low. This technique should be used when programming the device for the first time after power-up when using parallel programming. Because P = V2/R, the voltage required to create 1 mW into 600 Ω is 0.775 V rms. This is the voltage reference (0 dB) used for dBu measurements without regard to the impedance. The AD8112 operates as a voltage-in/voltage-out device. Therefore, all parameters are specified in volts, but users can convert the values to other power units or decibel-type measurements as required by a particular application. POWER-ON RESET When powering up the AD8112, it is usually desirable to have the outputs in the disabled state. The RESET pin, when taken low, causes all outputs to be in the disabled state. However, the RESET signal does not reset all registers in the AD8112. This is important when operating in the parallel programming mode. (Please refer to the Parallel Programming section for information about programming internal registers after power-up.) Serial programming updates the entire matrix, therefore no special considerations apply. Because the data in the shift register is random after power-up, it should not be used to program the matrix; otherwise the matrix can enter an unknown state. To prevent this, do not apply logic low signals to both CE and UPDATE immediately after powerup. The shift register should first be loaded with the desired data, and then UPDATE can be taken low to program the device. The RESET pin has a 20 kΩ pull-up resistor to DVCC that can be used to create a simple power-up reset circuit. A capacitor from RESET to ground holds RESET low until the device stabilizes. The low condition causes all the outputs to be disabled. The capacitor then charges through the pull-up resistor to the high state, thus allowing full programming capability of the device. CREATING UNITY-GAIN CHANNELS The channels in the AD8112 each have a gain of +2. This gain is necessary, as opposed to a gain of unity, to restrict the voltage on internal nodes to less than the breakdown voltage. If it is desired to create channels with an overall gain of unity, a resistive divider can be used at the input to divide the signals by 2. After passing through any input/output channel combination of the AD8112, the overall gain of unity is achieved. +12V AUDIO SOURCE 1kΩ TYPICAL INPUT UNITY GAIN AUDIO OUT 06523-032 AD8112 G = +2 –12V 1kΩ TYPICAL OUTPUT Figure 44. Input Divide Circuit SPECIFYING AUDIO LEVELS Several methods are used to specify audio levels. A level is actually a power measurement, which requires not just a voltage measurement, but also a reference impedance. Traditionally both 150 Ω and 600 Ω have been used as references for audio level measurements. The typical reference power level is 1 mW. Power levels that are measured relative to this reference level are given the designation dBm. However, it is necessary to be sure of the reference impedance used for such measurements. This can be either explicit (for example, 0 dBm (600 Ω)) or implicit (if there is an agreement on what the reference impedance is). Because modern voltmeters have high input impedances, measurements can be made that do not terminate the signal. Therefore, it is not proper to consider this type of measurement a dBm, or power measurement. However, a measurement scale that is designated dBu is used to measure unterminated voltages. This scale has a voltage reference for 0 dBu that is the same as the voltage required to produce 0 dBm (600 Ω). Figure 44 shows a typical input with a divide-by-2 input divider that creates a unity gain channel. The circuit uses 1 kΩ resistors to form the divider. These resistors need to be high enough so they do not overload the drive circuit. But if they are too high, they generate an offset voltage due to the input bias current that flows through them. Larger resistors also increase the thermal noise of the channel. The circuit shown in Figure 44 can handle inputs that swing up to ±10 V when the AD8112 operates on analog supplies of ±12 V. After passing through the divider, the maximum voltage is ±5 V at the input. This maximum input amplitude is ±10 V at the output after the gain of +2 of the channels. VIDEO SIGNALS Unlike audio signals, which have lower bandwidths and longer wavelengths, video signals often use controlled-impedance transmission lines that are terminated in their characteristic impedance. Although this is not always the case, there are some considerations when using the AD8112 to route video signals with controlled-impedance transmission lines. Figure 45 shows a schematic of an input and output treatment of a typical video channel. +5V OR +12V TYPICAL INPUT 75Ω VIDEO SOURCE 75Ω TYPICAL OUTPUT 75Ω 75Ω TRANSMISSION LINE 75Ω 06523-033 AD8112 G = +2 –5V OR –12V Figure 45. Video Signal Circuit Rev. 0 | Page 20 of 28 AD8112 Video signals usually use 75 Ω transmission lines that need to be terminated with this value of resistance at each end. When such a source is delivered to one of the AD8112 inputs, the high input impedance does not properly terminate these signals. Therefore, the line should be terminated with a 75 Ω shunt resistor to ground. Because video signals are limited in their peak-to-peak amplitude, there is no need to attenuate video signals before they pass through the AD8112. The AD8112 outputs are very low impedance and do not properly terminate the source end of a 75 Ω transmission line. In these cases, a series 75 Ω resistor should be inserted at an output that drives a video signal. Then the transmission line should be terminated with 75 Ω at its far end. This overall termination scheme divides the amplitude of the AD8112 output by 2. An overall unity gain channel is produced as a result of the AD8112’s channel gain of +2. The basic concept in constructing larger crosspoint arrays is to connect inputs in parallel in a horizontal direction and to wire-OR the outputs together in the vertical direction. The meaning of horizontal and vertical can best be understood by looking at Figure 46, which illustrates this concept for a 32 × 16 crosspoint array that uses four AD8112s. 16 1kΩ 1kΩ 8 8 16 IN00 TO IN15 AD8112 AD8112 IN16 TO IN31 16 1kΩ AD8112 8 8 16 AD8112 8 8 06523-035 1kΩ CREATING LARGER CROSSPOINT ARRAYS The AD8112 is a high density building block for creating crosspoint arrays of dimensions larger than 16 × 8. Various features, such as output disable and chip enable, are useful for creating larger arrays. The first consideration in constructing a larger crosspoint is to determine the minimum number of devices required. The 16 × 8 architecture of the AD8112 contains 128 points, which is a factor of 32 greater than a 4 × 1 crosspoint (or multiplexer). The PC board area, power consumption, and design effort savings are readily apparent when compared with using these smaller devices. For a nonblocking crosspoint, the number of points required is the product of the number of inputs multiplied by the number of outputs. Nonblocking requires that the programming of a given input to one or more outputs does not restrict the availability of that input to be a source for any other outputs. Some nonblocking crosspoint architectures require more than this minimum as previously calculated. Also, there are blocking architectures that can be constructed with fewer devices than this minimum. These systems have connectivity available on a statistical basis that is determined when designing the overall system. Figure 46. 32 x 16 Audio Crosspoint Array Using Four AD8112s The inputs are individually assigned to each of the 32 inputs of the two devices and a divider is used to normalize the channel gain. The outputs are wire-OR’ed together in pairs. The output from only one wire-OR’ed pair should be enabled at any given time. The device programming software must be properly written to for this to happen. Using additional crosspoint devices in the design can lower the number of outputs that must be wire-OR’ed together. Figure 47 shows a block diagram of a system using ten AD8112s to create a nonblocking, gain of +2, 128 × 8 crosspoint that restricts the wire-OR’ing at the output to only four outputs. Additionally, by using the lower eight outputs from each of the two Rank 2 AD8112s, a blocking 128 × 16 crosspoint array can be realized. There are, however, some drawbacks to this technique. The offset voltages of the various cascaded devices accumulate, and the bandwidth limitations of the devices compound. In addition, the extra devices consume more current and take up more board space. Consider the overall system design specifications when using the various trade-offs. Rev. 0 | Page 21 of 28 AD8112 RANK 1 (8 × AD8112) 128:16 IN00 TO IN15 1kΩ 16 RTERM IN16 TO IN31 1kΩ 16 RTERM IN32 TO IN47 1kΩ 16 RTERM IN48 TO IN63 1kΩ 16 RTERM IN64 TO IN79 1kΩ 16 RTERM IN80 TO IN95 1kΩ 16 RTERM IN96 TO IN111 1kΩ 16 RTERM IN112 TO IN127 1kΩ 16 RTERM 4 1kΩ 4 1kΩ 4 1kΩ 4 1kΩ 4 1kΩ 4 1kΩ 4 1kΩ 4 1kΩ 4 1kΩ 4 1kΩ AD8112 AD8112 4 1kΩ AD8112 4 1kΩ RANK 2 16:8 NONBLOCKING (16:16 BLOCKING) 4 4 1kΩ OUT00 TO OUT07 NONBLOCKING AD8112 4 1kΩ AD8112 4 AD8112 4 1kΩ 4 1kΩ 1kΩ 4 1kΩ 4 AD8112 AD8112 4 4 ADDITIONAL EIGHT OUTPUTS (SUBJECT TO BLOCKING) AD8112 4 1kΩ AD8112 4 1kΩ 06523-036 Figure 47. Nonblocking 128 × 8 Audio Array (128 × 16 Blocking) Rev. 0 | Page 22 of 28 AD8112 MULTICHANNEL VIDEO AND AUDIO The video specifications of the AD8112 make it an ideal candidate for creating composite video crosspoint switches. These can be made quite dense by taking advantage of the AD8112’s high level of integration and the fact that composite video requires only one crosspoint channel per system video channel. There are, however, other video formats that can be routed with the AD8112, requiring more than one crosspoint channel per video channel. Some systems use twisted pair cables to carry video or audio signals. These systems utilize differential signals and can lower costs because they use lower cost cables, connectors, and termination methods. They also have the ability to lower crosstalk and reject common-mode signals, which can be important for equipment that operates in noisy environments, or where common-mode voltages are present between transmitting and receiving equipment. In such systems, the audio or video signals are differential; there are positive and negative (or inverted) versions of the signals. These complementary signals are transmitted through each of the two cables of the twisted pair, yielding a first-order zero common-mode voltage. At the receive end, the signals are differentially received and converted back into a single-ended signal. When switching these differential signals, two channels are required in the switching element to handle the two differential signals that compose the video or audio channel. Thus, one differential video or audio channel is assigned to a pair of crosspoint channels, both input and output. For a single AD8112, eight differential video or audio channels can be assigned to the 16 inputs, and four differential video or audio channels can be assigned to the eight outputs. This effectively forms an 8 × 4 differential crosspoint switch. Programming such a device requires that inputs and outputs be programmed in pairs. This information can be deduced through inspection of the programming format of the AD8112 and the requirements of the system. There are other analog video formats requiring more than one analog circuit per video channel. One two-circuit format that is commonly being used in systems such as satellite TV, digital cable boxes, and higher quality VCRs is called S-video or Y/C video. This format carries the brightness (luminance or Y) portion of the video signal on one channel and the color (chrominance, chroma, or C) portion on a second channel. Because S-video also uses two separate circuits for one video channel, creating a crosspoint system requires assigning one video channel to two crosspoint channels, as in the case of a differential video system. Aside from the nature of the video format, other aspects of these two systems are the same. Stereo audio can also be routed in a paired-channel arrangement similar to a two-channel video system. There are yet other video formats using three channels to carry the video information. Video cameras produce RGB (red, green, blue) directly from the image sensors. RGB is also the usual format used internally by computers for graphics. RGB can also be converted to Y, R–Y, B–Y format, sometimes called YUV format. These three-circuit video standards are referred to as component analog video. The component video standards require three crosspoint channels per video channel to handle the switching function. Similar to the two-circuit video formats, the inputs and outputs are assigned in groups of three, and the appropriate logic programming is performed to route the video signals. CROSSTALK Many systems, such as studio audio or broadcast video, that handle numerous analog signal channels have strict requirements for keeping the various signals from influencing other signals in the system. Crosstalk is the term used to describe the coupling of the signals of other nearby channels to a given channel. When there are many signals in close proximity in a system, as undoubtedly is the case in a system that uses the AD8112, the crosstalk issues can be quite complex. A good understanding of the nature of crosstalk and some definition of terms is required in order to specify a system that uses one or more AD8112s. Types of Crosstalk Crosstalk can be propagated by one of three methods. These fall into the categories of electric field, magnetic field, and sharing of common impedances. This section explains these effects. Every conductor can be both a radiator of electric fields and a receiver of electric fields. The electric field crosstalk mechanism occurs when the electric field created by the transmitter propagates across a stray capacitance (for example, free space) and then couples with the receiver and induces a voltage. This voltage is an unwanted crosstalk signal in any channel that receives it. Currents flowing in conductors create magnetic fields that circulate around the currents. These magnetic fields then generate voltages in any other conductor whose paths is linked. The undesired induced voltages in these other channels are crosstalk signals. The channels with crosstalk have a mutual inductance that couples signals from one channel to another. The power supplies, grounds, and other signal return paths of a multichannel system are generally shared by the various channels. When a current from one channel flows into one of these paths, a voltage that is developed across the impedance becomes an input crosstalk signal for other channels that share the common impedance. Rev. 0 | Page 23 of 28 AD8112 All these sources of crosstalk are vector quantities; therefore the magnitudes cannot simply be added together to obtain the total crosstalk. In fact, there are conditions where driving additional circuits in parallel in a given configuration can reduce the crosstalk. To measure this crosstalk, use one of the following two methods. In the first method, the crosstalk terms associated with driving a test signal into each of the other 15 inputs is measured one at a time, while applying no signal to IN00. In the second method, the crosstalk terms associated with driving a parallel test signal into all 15 other inputs is measured two at a time in all possible combinations, then three at a time, and so on, until, finally, there is only one way to drive a test signal into all 15 other inputs in parallel. Each combination is legitimately different from the others and might yield a unique value, depending on the resolution of the measurement system. It is not practical to measure and then specify all these terms. Furthermore, this describes the crosstalk matrix for just one input channel. A similar crosstalk matrix can be proposed for every other input. In addition, if the possible combinations and permutations for connecting inputs to the other outputs (not used for measurement) are taken into consideration, the numbers of possibilities quickly grows to astronomical proportions. If a larger crosspoint array of multiple AD8112s is constructed, the numbers grow larger still. Obviously, a subset of all these cases must be selected to be used as a guide for a practical measure of crosstalk. One common method is to measure all hostile crosstalk; this means that the crosstalk to the selected channel is measured while all other system channels are driven in parallel. In general, this yields the worst crosstalk number, but this is not always the case, due to the vector nature of the crosstalk signal. Other useful crosstalk measurements are those created by the nearest neighbor or by the two nearest neighbors on either side. These crosstalk measurements are generally higher than those of more distant channels, and therefore can serve as a worstcase measure for any other 1-channel or 2-channel crosstalk measurements. Areas of Crosstalk A practical AD8112 circuit must be mounted to some sort of circuit board to connect it to power supplies and measurement equipment. Great care has been taken to create a characterization board (also available as an evaluation board) that adds minimum crosstalk to the intrinsic device. This, however, raises the issue that the crosstalk of a system is a combination of the intrinsic crosstalk of both the devices and the circuit board to which they are mounted. It is important to try to separate these two areas when attempting to minimize the effect of crosstalk. In addition, crosstalk can occur among the inputs as well as the outputs of a cross-point. It can also occur from input to output. The following sections describe techniques for measuring and identifying the source of crosstalk. Measuring Crosstalk Crosstalk is measured by applying a signal to one or more channels and measuring the relative strength of that signal on a desired selected channel. The measurement is usually expressed as decibels down from the magnitude of the test signal. The crosstalk is expressed by | XT | = 20 log 10 ( Asel ( s ) / Atest ( s )) where: s = jw is the Laplace transform variable. Asel(s) = the amplitude of the crosstalk induced signal in the selected channel. Atest(s) = the amplitude of the test signal. It can be seen that crosstalk is a function of frequency, but not a function of the magnitude of the test signal (to first order). In addition, the crosstalk signal has a phase relative to the test signal associated with it. A network analyzer is most commonly used to measure crosstalk over a frequency range of interest. It can provide both magnitude and phase information about the crosstalk signal. As a crosspoint system or device grows larger, the number of theoretical crosstalk combinations and permutations can become extremely large. For example, in the case of the 16 × 8 matrix of the AD8112, consider the number of possible sources of crosstalk terms for a single channel, for example the IN00 input. IN00 is programmed to connect to one of the AD8112 outputs where crosstalk can be measured. Input and Output Crosstalk The flexible programming capability of the AD8112 can be used to diagnose whether crosstalk is greater on the input side or the output side. For example, to identify the source of crosstalk, the IN07 input channel can be programmed to drive OUT07, with the input to IN07 terminated to ground (via 50 Ω or 75 Ω) and no signal applied. All the other inputs are driven in parallel with the same test signal (practically provided by a distribution amplifier), with all other outputs except OUT07 disabled. Because grounded IN07 is programmed to drive OUT07, no signal should be present. Any signal that is present can be attributed to the other 15 hostile input signals, because no other outputs are driven (they are all disabled). Therefore, this method measures the all-hostile input contribution to crosstalk into IN07. This method can be used for other input channels and combinations of hostile inputs. Rev. 0 | Page 24 of 28 AD8112 For output crosstalk measurement, a single input channel is driven (IN00, for example) and all outputs other than a given output (IN07 in the middle) are programmed to connect to IN00. OUT07 is programmed to connect to IN15 (not in close proximity to IN00), which is terminated to ground. Therefore, OUT07 should not have a signal present because it is listening to a quiet input. Any signal measured at the OUT07 can be attributed to the output crosstalk of the other seven hostile outputs. Again, this method can be modified to measure other channels and other crosspoint matrix combinations. From the equation, it can be observed that this crosstalk mechanism has a high-pass nature. It can also be minimized by reducing the coupling capacitance of the input circuits and lowering the output impedance of the drivers. If the input is driven from a 75 Ω terminated cable, the input crosstalk can be reduced by buffering this signal with a low output impedance buffer. On the output side, the crosstalk can be reduced by driving a lighter load. Although the AD8112 is specified with excellent differential gain and phase when driving a standard 150 Ω video load, the crosstalk is higher than the minimum obtainable crosstalk due to the high output currents. These currents induce crosstalk via the mutual inductance of the output pins and bond wires of the AD8112. From a circuit standpoint, this output crosstalk mechanism looks like a transformer with a mutual inductance between the windings that drive a load resistor. For low frequencies, the magnitude of the crosstalk is given by | XT | = 20 log 10 (Mxy × s / R L ) Effect of Impedances on Crosstalk The input side crosstalk can be influenced by the output impedance of the sources that drive the inputs. The lower the impedance of the drive source, the lower the magnitude of the crosstalk. The dominant crosstalk mechanism on the input side is capacitive coupling. The high impedance inputs do not have significant current flow to create magnetically induced crosstalk. However, significant current can flow through the input termination resistors and the loops that drive them. Therefore, the PC board on the input side can contribute to magnetically coupled crosstalk. From a circuit standpoint, the input crosstalk mechanism looks like a capacitor coupling to a resistive load. For low frequencies the magnitude of the crosstalk is given by |XT| = 20 log10[(RSCM) × s] where: RS is the source resistance. CM is the mutual capacitance between the test signal circuit and the selected circuit. s is the Laplace transform variable. where: Mxy is the mutual inductance of output x to output y. RL is the load resistance on the measured output. This crosstalk mechanism can be minimized by keeping the mutual inductance low and increasing RL. The mutual inductance can be kept low by increasing the spacing of the conductors and minimizing their parallel length. Rev. 0 | Page 25 of 28 AD8112 PCB LAYOUT Extreme care must be exercised to minimize additional crosstalk generated by the system circuit board(s). The areas that must be carefully designed are grounding, shielding, signal routing, and supply bypassing. The packaging of the AD8112 is designed to help minimize crosstalk. Each input is separated from each other input by an analog ground pin. All of these AGNDs should be directly connected to the ground plane of the circuit board. These ground pins provide shielding, low impedance return paths, and physical separation for the inputs. All of these help to reduce crosstalk. Each output is separated from its two neighboring outputs by an analog supply pin of one polarity or the other. Each of these analog supply pins provides power to the output stages of only the two nearest outputs. These supply pins provide shielding, physical separation, and a low impedance supply for the outputs. Individual bypassing of each of these supply pins with a 0.01 μF chip capacitor connected directly to the ground plane minimizes high frequency output crosstalk via the mechanism of sharing common impedances. In addition, each output has an on-chip compensation capacitor that is individually tied to the nearby analog ground pins (AGND00 through AGND07). This technique reduces crosstalk by preventing the currents that flow in these paths from sharing a common impedance on the IC and in the package pins. These AGNDxx signals should all be connected directly to the ground plane. The input and output signals have minimum crosstalk if they are located between ground planes on layers above and below, and separated by ground in between. Vias should be located as close to the IC as possible to carry the inputs and outputs to the inner layer. The input and output signals surface at the input termination resistors and at the output series back-termination resistors. To the extent possible, these signals should also be separated as soon as they emerge from the IC package. Rev. 0 | Page 26 of 28 AD8112 DVCC DGND P1-1 P1-2 + NC P1-3 AVEE AGND AVCC P1-4 P1-5 NC P1-6 P1-7 + DVCC 0.01µF 0.1µF 10µF 1, 75 INPUT 00 75Ω INPUT 01 75Ω INPUT 02 75Ω INPUT 03 75Ω INPUT 04 75Ω INPUT 05 75Ω INPUT 06 75Ω INPUT 07 75Ω INPUT 08 75Ω INPUT 09 75Ω INPUT 10 75Ω INPUT 11 75Ω INPUT 12 75Ω INPUT 13 75Ω INPUT 14 75Ω INPUT 15 75Ω 58 57, 59 60 61 62 63 64 65 66 67 68 69 70 71 72 3, 73 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 98 R R P2-5 P2-4 P2-2 P2-3 P2-1 P2-6 R R R C R R R R R R R R R R SERIAL MODE JUMP 96 IN00 AGND IN01 AGND OUT00 IN02 AGND IN03 AGND IN04 AGND IN05 AGND IN06 AGND IN07 AGND IN08 AGND IN09 AGND IN10 AGND IN11 AGND IN12 AGND IN13 AGND IN14 AGND IN15 AGND DATA OUT RESET DGND CLK JUMPER 0.1µF 10µF + AVCC 0.01µF 21, 55 AVCC AVEE 0.01µF 20, 56 AVEE 85 TO 93 NC AVCC AVCC 54 53 0.01µF AVEE 52 51 0.01µF AVCC 50 49 0.01µF AVEE 48 47 0.01µF AVCC 46 45 0.01µF AVEE 44 43 0.01µF AVCC 42 41 0.01µF AVEE AVEE06/07 OUT07 40 39 0.01µF 75Ω OUTPUT 07 75Ω OUTPUT 06 75Ω OUTPUT 05 75Ω OUTPUT 04 75Ω OUTPUT 02 75Ω OUTPUT 02 75Ω OUTPUT 01 75Ω OUTPUT 00 DVCC AVEE00/01 OUT01 AVCC01/02 OUT02 AVEE02/03 OUT03 AVCC03/04 OUT04 AVEE04/05 OUT05 AVCC05/06 OUT06 AD8112 AVCC UPDATE 22 CE A0 A1 A2 D0 D1 D2 D3 2, 74 100 99 97 95 84 83 82 81 80 79 78 77 76 D4 94 SER /PAR DATA IN DGND R33 20kΩ DVCC P3-10 P3-11 P3-12 P3-13 Figure 48. Evaluation Board Schematic Rev. 0 | Page 27 of 28 06523-037 NOTES 1. R = OPTIONAL 50Ω TERMINATOR RESISTORS. 2. C = OPTIONAL SMOOTHING CAPACITOR. 3. NC = NO CONNECT. P3-14 P3-1 P3-2 P3-3 P3-4 P3-5 P3-6 P3-7 P3-8 AD8112 OUTLINE DIMENSIONS 1.60 MAX 0.75 0.60 0.45 100 1 PIN 1 16.20 16.00 SQ 15.80 76 75 (PINS DOWN) TOP VIEW 14.20 14.00 SQ 13.80 1.45 1.40 1.35 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY 25 26 51 50 VIEW A 0.50 BSC LEAD PITCH VIEW A ROTATED 90° CCW 0.27 0.22 0.17 051706-A COMPLIANT TO JEDEC STANDARDS MS-026-BED Figure 49. 100-Lead Low Profile Quad Flat Package [LQFP] (ST-100) Dimensions shown in millimeters ORDERING GUIDE Model AD8112JSTZ 1 AD8112-EVALZ1 1 Temperature Range 0°C to 70°C Package Description 100-Lead Plastic LQFP Evaluation Board Package Option ST-100 Z = Pb-free part. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06523-0-2/07(0) Rev. 0 | Page 28 of 28