Low Cost, 225 MHz,
16 × 16 Crosspoint Switches
AD8114/AD8115
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
Routing of high speed signals, including
Video (NTSC, PAL, S, SECAM, YUV, RGB)
Compressed video (MPEG, wavelet)
3-level digital video (HDB3)
Data communications
Telecommunications
GENERAL DESCRIPTION
The AD8114/AD8115 are high speed, 16 × 16 video crosspoint
switch matrices. They offer a −3 dB signal bandwidth greater than
200 MHz and channel switch times of less than 50 ns with 1%
settling. With −70 dB of crosstalk and −98 dB isolation (at 5 MHz),
the AD8114/AD8115 are useful in many high speed applications.
Rev. C
SER/PAR D0 D1 D2 D3 D4
A0
A1
A2
A3
CLK
DATA IN
80-BIT SHIFT REGISTER
WITH 5-BIT
PARALLEL LOADING
UPDATE
CE
80
PARALLEL LATCH
RESET
80
DATA
OUT
SET
INDIVIDUAL
OR RESET
ALL OUTPUTS
TO "OFF"
DECODE
16 × 5:16 DECODERS
AD8114/AD8115
256
SWITCH
MATRIX
OUTPUT
BUFFER
G = +1,
G = +2
16
OUTPUTS
01070-001
16 INPUTS
16
ENABLE/DISABLE
16 × 16 high speed nonblocking switch arrays
AD8114; G = 1
AD8115; G = 2
Serial or parallel programming of switch array
Serial data out allows daisy-chaining of multiple
16 × 16 arrays to create larger switch arrays
High impedance output disable allows connection of
multiple devices without loading the output bus
For smaller arrays see the AD8108/AD8109 (8 × 8) or
AD8110/AD8111 (16 × 8) switch arrays
Complete solution
Buffered inputs
Programmable high impedance outputs
16 output amplifiers, AD8114 (G = 1), AD8115 (G = 2)
Drives 150 Ω loads
Excellent video performance
25 MHz, 0.1 dB gain flatness
0.05%/0.05° differential gain/differential phase error
(RL = 150 Ω)
Excellent ac performance
−3 dB bandwidth: 225 MHz
Slew rate: 375 V/µs
Low power of 700 mW (2.75 mW per point)
Low all hostile crosstalk of −70 dB at 5 MHz
Reset pin allows disabling of all outputs (connected through
a capacitor to ground provides power-on reset capability)
100-lead LQFP (14 mm × 14 mm)
Figure 1.
The differential gain and differential phase of better than 0.05%
and 0.05°, respectively, along with a 0.1 dB flatness out to 25 MHz
while driving a 75 Ω back-terminated load, make the AD8114/
AD8115 ideal for all types of signal switching.
The AD8114/AD8115 include 16 independent output buffers
that can be placed into a high impedance state for paralleling
crosspoint outputs so that off channels do not load the output bus.
The AD8114 has a gain of 1, while the AD8115 offers a gain of 2.
They operate on voltage supplies of ±5 V while consuming only
70 mA of idle current. The channel switching is performed via a
serial digital control (which can accommodate daisy-chaining of
several devices) or via a parallel control, allowing updating of an
individual output without reprogramming the entire array.
The AD8114/AD8115 is packaged in a 100-lead LQFP and is
available over the extended industrial temperature range of
−40°C to +85°C.
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Technical Support
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AD8114/AD8115
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ........................................... 11
Applications ....................................................................................... 1
Input/Output Schematics .............................................................. 17
General Description ......................................................................... 1
Theory of Operation ...................................................................... 18
Functional Block Diagram .............................................................. 1
Applications ................................................................................ 18
Revision History ............................................................................... 2
Power-On Reset .......................................................................... 19
Specifications..................................................................................... 3
Gain Selection ............................................................................. 19
Timing Characteristics (Serial) .................................................. 5
Creating Larger Crosspoint Arrays .......................................... 19
Timing Characteristics (Parallel) ............................................... 6
Multichannel Video ................................................................... 21
Absolute Maximum Ratings ............................................................ 8
Crosstalk ...................................................................................... 21
Maximum Power Dissipation ..................................................... 8
Outline Dimensions ....................................................................... 24
ESD Caution .................................................................................. 8
Ordering Guide .......................................................................... 24
Pin Configuration and Function Descriptions ............................. 9
REVISION HISTORY
7/2016—Rev. B to Rev. C
Changes to General Description Section ...................................... 1
Changes to Off Isolation, Input-to-Output Parameter, Table 1 ........ 3
Changes to Areas of Crosstalk Section ........................................ 22
Deleted PCB Layout Section and Figure 50; Renumbered
Sequentially ..................................................................................... 25
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 25
Deleted Figure 51 and Figure 52................................................... 26
Deleted Figure 53 and Figure 54................................................... 27
Deleted Figure 55 and Figure 56................................................... 28
Deleted Evaluation Board Section and Figure 57....................... 29
Deleted Control the Evaluation Board from a PC Section,
Figure 58, Overshoot of PC Printer Ports’ Data Lines Section,
and Figure 59 ................................................................................... 30
9/2005—Rev. A to Rev. B
Updated Format .................................................................. Universal
Change to Figure 3 ............................................................................6
Change to Absolute Maximum Ratings .........................................8
Changes to Maximum Power Dissipation Section........................8
Updated Outline Dimensions ....................................................... 31
Changes to Ordering Guide .......................................................... 31
11/2001—Rev. 0 to Rev. A
Changes to Ordering Guide .............................................................5
Updated Outline Dimensions ....................................................... 26
10/1998—Revision 0: Initial Version
Rev. C | Page 2 of 25
Data Sheet
AD8114/AD8115
SPECIFICATIONS
VS = ±5 V, TA = +25°C, RL = 1 kΩ, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Gain Flatness
Propagation Delay
Settling Time
Slew Rate
NOISE/DISTORTION PERFORMANCE
Differential Gain Error
Differential Phase Error
Crosstalk, All Hostile
Off Isolation, Input-to-Output
Input Voltage Noise
DC PERFORMANCE
Gain Error
Gain Matching
Gain Temperature Coefficient
OUTPUT CHARACTERISTICS
Output Impedance
Output Disable Capacitance
Output Leakage Current
Output Voltage Range
Voltage Range
INPUT CHARACTERISTICS
Input Offset Voltage
Input Voltage Range
Input Capacitance
Input Resistance
Input Bias Current
SWITCHING CHARACTERISTICS
Enable On Time
Switching Time, 2 V Step
Switching Transient (Glitch)
Test Conditions/Comments
Min
Typ
200 mV p-p, RL = 150 Ω
2 V p-p, RL = 150 Ω
0.1 dB, 200 mV p-p, RL = 150 Ω
0.1 dB, 2 V p-p, RL = 150 Ω
2 V p-p, RL = 150 Ω
0.1%, 2 V step, RL = 150 Ω
2 V step, RL = 150 Ω
150/125
225/200
100/125
25/40
20/40
5
40
375/450
MHz
MHz
MHz
MHz
ns
ns
V/µs
NTSC or PAL, RL = 1 kΩ
NTSC or PAL, RL = 150 Ω
NTSC or PAL, RL = 1 kΩ
NTSC or PAL, RL = 150 Ω
f = 5 MHz
f = 10 MHz
f = 5 MHz, RL = 150 Ω, one channel
0.01 MHz to 50 MHz
0.05
0.05
0.05
0.05
−70/−64
−60/−52
−98
16/18
%
%
Degrees
Degrees
dB
dB
dB
nV/√Hz
No load
RL = 1 kΩ
RL = 150 Ω
No load, channel-to-channel
RL = 1 kΩ channel-to-channel
0.05/0.2
0.05/0.2
0.2/0.35
0.01/0.5
0.01/0.5
0.75/1.5
DC, enabled
Disabled
Disabled
Disabled
No load
IOUT = 20 mA
Short-circuit current
0.2
10
5
1
±3.3
±3
65
Worst case (all configurations)
Temperature coefficient
No load
Any switch configuration
±3.0
±2.5
±3/±1.5
1
Per output selected
50% UPDATE to 1% settling
Rev. C | Page 3 of 25
3
10
±3.5
5
10
2
60
50
20/30
Max
0.08/0.6
0.04/1
Unit
%
%
%
%
%
ppm/°C
Ω
MΩ
pF
µA
V
V
mA
15
5
mV
µV/°C
V
pF
MΩ
µA
ns
ns
mV p-p
AD8114/AD8115
Parameter
POWER SUPPLIES
Supply Current
Supply Voltage Range
PSRR
OPERATING TEMPERATURE RANGE
Temperature Range
θJA
Data Sheet
Test Conditions/Comments
Min
AVCC, outputs enabled, no load
AVCC, outputs disabled
AVEE, outputs enabled, no load
AVEE, outputs disabled
DVCC, outputs enabled, no load
DC
f = 100 kHz
f = 1 MHz
64
Operating (still air)
Operating (still air)
Rev. C | Page 4 of 25
Typ
Max
Unit
70/80
27/30
70/80
27/30
16
±4.5 to ±5.5
80
66
46
mA
mA
mA
mA
mA
V
dB
dB
dB
−40 to +85
40
°C
°C/W
Data Sheet
AD8114/AD8115
TIMING CHARACTERISTICS (SERIAL)
Table 2. Timing Characteristics
Parameter
Serial Data Setup Time
CLK Pulse Width
Serial Data Hold Time
CLK Pulse Separation, Serial Mode
CLK to UPDATE Delay
UPDATE Pulse Width
CLK to DATA OUT Valid, Serial Mode
Propagation Delay, UPDATE to Switch On or Off
Data Load Time, CLK = 5 MHz, Serial Mode
CLK, UPDATE Rise and Fall Times
RESET Time
Symbol
t1
t2
t3
t4
t5
t6
t7
Min
20
100
20
100
0
50
Typ
Max
200
50
16
100
200
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
Table 3. Logic Levels
VIL
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
0.8 V max
VOH
DATA OUT
VOL
DATA OUT
2.7 V min
0.5 V max
t2
IIH
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
20 µA max
IIL
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
−400 µA min
IOH
DATA OUT
IOL
DATA OUT
−400 µA max
3.0 mA min
t4
1
CLK
0
t1
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
t3
1
DATA IN
OUT7 (D4)
OUT00 (D0)
OUT7 (D3)
0
t5
t6
1 = LATCHED
UPDATE
0 = TRANSPARENT
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
t7
01070-002
VIH
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
2.0 V min
DATA OUT
Figure 2. Timing Diagram, Serial Mode
Rev. C | Page 5 of 25
AD8114/AD8115
Data Sheet
TIMING CHARACTERISTICS (PARALLEL)
Table 4. Timing Characteristics
Parameter
Data Setup Time
CLK Pulse Width
Data Hold Time
CLK Pulse Separation
CLK to UPDATE Delay
UPDATE Pulse Width
Propagation Delay, UPDATE to Switch On or Off
CLK, UPDATE Rise and Fall Times
RESET Time
Symbol
t1
t2
t3
t4
t5
t6
Min
20
100
20
100
0
50
Typ
Max
50
100
200
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 5. Logic Levels
VIH
RESET, SER/PAR,
CLK, D0, D1, D2,
D3, D4, A0, A1, A2,
A3, CE, UPDATE
VIL
RESET, SER/PAR,
CLK, D0, D1, D2,
D3, D4, A0, A1, A2,
A3, CE, UPDATE
VOH
DATA OUT
VOL
DATA OUT
IIH
RESET, SER/PAR,
CLK, D0, D1, D2,
D3, D4, A0, A1, A2,
A3, CE, UPDATE
IIL
RESET, SER/PAR,
CLK, D0, D1, D2,
D3, D4, A0, A1, A2,
A3, CE, UPDATE
IOH
DATA OUT
IOL
DATA OUT
2.0 V min
0.8 V max
2.7 V min
0.5 V max
20 µA max
−400 µA min
−400 µA max
3.0 mA min
t2
t4
1
CLK
0
t1
D0–D3
A0–A2
t3
1
0
t5
01070-003
1 = LATCHED
t6
UPDATE
0 = TRANSPARENT
Figure 3. Timing Diagram, Parallel Mode
Rev. C | Page 6 of 25
Data Sheet
AD8114/AD8115
Table 6. Operation Truth Table
CE
1
0
UPDATE
X
1
CLK
X
f
DATA IN
X
Datai
DATA OUT
X
Datai-80
RESET
X
1
SER/ PAR
0
1
f
1
0
X
Not applicable in
parallel mode
X
1
0
D0…D4,
A0… A3
X
1
X
X
X
X
X
X
0
X
PARALLEL
DATA
(OUTPUT
ENABLE)
X
0
Operation/Comment
No change in logic.
The data on the serial DATA IN line is loaded into serial register.
The first bit clocked into the serial register appears at DATA
OUT 80 clocks later.
The data on the parallel data lines, D0 to D4, are loaded into
the 80 bit serial shift register location addressed by A0 to A3.
Data in the 80-bit shift register transfers into the parallel
latches that control the switch array. Latches are transparent.
Asynchronous operation. All outputs are disabled. Remainder
of logic is unchanged.
D0
D1
D2
D3
D4
SER/PAR
S
D1
Q
D0
DATA IN
(SERIAL)
S
D1
S
D1
D Q
Q
D0
CLK
D Q
Q
D0
CLK
S
D1
D Q
Q
D0
CLK
D Q
CLK
S
D1
S
D1
Q D Q
D0
CLK
Q
D0
D Q
CLK
S
D1
S
D1
Q D Q
D0 CLK
Q
D0
S
D1
D Q
Q
D0
CLK
S
D1
D Q
Q
D0
CLK
S
D1
D Q
Q
D0
CLK
S
D1
D Q
Q
D0
CLK
D Q
DATA
OUT
CLK
CLK
CE
UPDATE
OUTPUT
ADDRESS
OUT0 EN
OUT1 EN
OUT2 EN
OUT3 EN
OUT4 EN
A1
OUT5 EN
A2
A3
4 TO 16 DECODER
A0
OUT6 EN
OUT7 EN
OUT8 EN
OUT9 EN
OUT10 EN
OUT11 EN
OUT12 EN
OUT13 EN
OUT14 EN
OUT15 EN
LE D
LE D
LE D
LE D
LE D
LE D
LE D
LE D
LE D
LE D
LE D
LE D
OUT0
B0
OUT0
B1
OUT0
B2
OUT0
B3
OUT0
EN
OUT1
B0
OUT14
EN
OUT15
B0
OUT15
B1
OUT15
B2
OUT15
B3
OUT15
EN
Q
Q
Q
Q
Q
CLR Q
CLR Q
Q
Q
Q
Q
CLR Q
RESET
(OUTPUT ENABLE)
SWITCH MATRIX
Figure 4. Logic Diagram
Rev. C | Page 7 of 25
16
OUTPUT ENABLE
01070-011
DECODE
256
AD8114/AD8115
Data Sheet
ABSOLUTE MAXIMUM RATINGS
While the AD8114/AD8115 are internally short-circuit protected,
this may not be sufficient to guarantee that the maximum junction
temperature (125°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maximum
power derating curves shown in Figure 5.
Table 7.
Rating
12.0 V
2.6 W
5
TJ = 125°C
Specification is for device in free air (TA = 25°C). 100-lead plastic LQFP (ST):
θJA = 40°C/W.
2
Maximum reflow temperatures are to JEDEC industry standard J-STD-020.
1
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
MAXIMUM POWER DISSIPATION
4
3
2
1
0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60
AMBIENT TEMPERATURE (°C)
01070-004
±VS
Observe power derating curves
−65°C to +125°C
MAXIMUM POWER DISSIPATION (Ω)
Parameter
Supply Voltage
Internal Power Dissipation1
AD8114/AD8115 100-Lead
Plastic LQFP (ST)
Input Voltage
Output Short-Circuit Duration
Storage Temperature Range2
70
80
Figure 5. Maximum Power Dissipation vs. Temperature
ESD CAUTION
The maximum power that can be safely dissipated by the
AD8114/AD8115 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for
plastic encapsulated devices is determined by the glass transition
temperature of the plastic, approximately 125°C. Temporarily
exceeding this limit may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of 125°C for an extended
period can result in device failure.
Rev. C | Page 8 of 25
90
Data Sheet
AD8114/AD8115
CE
DATA OUT
CLK
DATA IN
UPDATE
SER/PAR
NC
NC
NC
NC
NC
NC
NC
NC
NC
A0
A1
A2
A3
D0
D1
D2
D3
D4
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
RESET
100
99
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
75
DVCC
74
DGND
DVCC
1
DGND
2
AGND
3
73
AGND
IN08
4
72
IN07
AGND
PIN 1
AGND
5
71
IN09
6
70
IN06
AGND
7
69
AGND
IN05
IN10
8
68
AGND
9
67
AGND
IN11
10
AD8114/AD8115
66
IN04
AGND
11
IN12
12
TOP VIEW
(Not to Scale)
65
AGND
64
IN03
AGND
13
63
AGND
IN13
14
62
IN02
AGND
15
61
AGND
IN14
16
60
IN01
AGND
AGND
17
59
IN15
18
58
IN00
AGND
19
57
AGND
AVEE
AVEE
20
56
AVCC
21
55
AVCC
AVCC15
22
54
AVCC00
OUT00
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
OUT11
AVEE10/11
OUT10
AVCC09/10
OUT09
AVEE08/09
OUT08
AVCC07/08
OUT07
AVEE06/07
OUT06
AVCC05/06
OUT05
AVEE04/05
OUT04
AVCC03/04
OUT03
AVEE02/03
OUT02
AVCC01/02
01070-005
30
AVCC11/12
NC = NO CONNECT
29
OUT01
OUT12
51
28
25
AVEE12/13
AVEE00/01
OUT14
27
52
26
53
24
OUT13
23
AVCC13/14
OUT15
AVEE14/15
Figure 6. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
58, 60, 62, 64, 66, 68, 70, 72,
4, 6, 8, 10, 12, 14, 16, 18
96
97
98
95
Mnemonic
INxx
Description
Analog Inputs. xx = Channel 00 through Channel 15.
DATA IN
CLK
DATA OUT
UPDATE
100
99
94
53, 51, 49, 47, 45, 43, 41, 39,
37, 35, 33, 31, 29, 27, 25, 23
3, 5, 7, 9, 11, 13, 15, 17, 19, 57,
59, 61, 63, 65, 67, 69, 71, 73
1, 75
2, 74
20, 56
21, 55
54, 50, 46, 42, 38, 34, 30, 26, 22
52, 48, 44, 40, 36, 32, 28, 24
84
83
82
RESET
CE
SER/PAR
OUTyy
Serial Data Input, TTL Compatible.
Clock, TTL Compatible. Falling edge triggered.
Serial Data Out, TTL Compatible.
Enable (Transparent) Low. Allows serial register to connect directly to switch matrix. Data
latched when high.
Disable Outputs, Active Low.
Chip Enable, Enable Low. Must be low to clock in and latch data.
Selects Serial Data Mode, Low or Parallel Data Mode, High. Must be connected.
Analog Outputs. yy = Channel 00 through Channel 15.
AGND
Analog Ground for Inputs and Switch Matrix. Must be connected.
DVCC
DGND
AVEE
AVCC
AVCCxx/yy
AVEExx/yy
A0
A1
A2
+5 V for Digital Circuitry.
Ground for Digital Circuitry.
−5 V for Inputs and Switch Matrix.
+5 V for Inputs and Switch Matrix.
+5 V for Output Amplifier that is Shared by Channels xx and yy. Must be connected.
−5 V for Output Amplifier that is Shared by Channels xx and yy. Must be connected.
Parallel Data Input, TTL Compatible (output select LSB).
Parallel Data Input, TTL Compatible (output select).
Parallel Data Input, TTL Compatible (output select).
Rev. C | Page 9 of 25
AD8114/AD8115
Pin No.
81
80
79
78
77
76
85 to 93
Data Sheet
Mnemonic
A3
D0
D1
D2
D3
D4
NC
Description
Parallel Data Input, TTL Compatible (output select MSB).
Parallel Data Input, TTL Compatible (input select LSB)
Parallel Data Input, TTL Compatible (input select).
Parallel Data Input, TTL Compatible (input select).
Parallel Data Input, TTL Compatible (input select MSB).
Parallel Data Input, TTL Compatible (output enable).
No Connect.
Rev. C | Page 10 of 25
Data Sheet
AD8114/AD8115
TYPICAL PERFORMANCE CHARACTERISTICS
2
0.2
GAIN
0.1
200mV p-p
0.3
0
FLATNESS
–1
0
–2
–0.1
–3
–0.2
GAIN
–0.4
–5
0.2
0.1
–2
FLATNESS
0
–3
–0.1
–4
200mV p-p
2V p-p
–5
–0.2
–7
0.1
–0.5
1
10
FREQUENCY (MHz)
–0.6
1000
100
01070-012
–6
VO AS SHOWN
RL = 150Ω
–6
–8
0.1
Figure 7. AD8114 Frequency Response, RL = 150 Ω
–0.4
1
10
FREQUENCY (MHz)
–0.5
1000
100
Figure 10. AD8115 Frequency Response, RL = 150 Ω
3
0.4
3
0.5
2
0.3
2
0.4
0.2
1
1
200mV p-p
GAIN
–0.1
2V p-p
GAIN (dB)
0
–2
FLATNESS (dB)
–1
FLATNESS
–4
–4
–5
–0.4
–5
1
10
FREQUENCY (MHz)
–0.6
1000
100
01070-013
–0.2
–0.5
0.1
–1
–0.3
0
–0.1
–3
200mV p-p
2V p-p
–7
0.1
Figure 8. AD8114 Frequency Response, RL = 1 kΩ
8
VO = 200mV p-p
RL AS SHOWN
CL = 18pF
RL = 1kΩ
6
4
0
2
–1
GAIN (dB)
1
RL = 150Ω
–2
10
FREQUENCY (MHz)
100
–4
–6
1
10
100
RL = 1kΩ
RL = 150Ω
–2
–4
–5
VO = 200mV p-p
RL AS SHOWN
CL = 18pF
0
–3
–6
0.1
1
10
01070-014
GAIN (dB)
2
–0.4
–0.5
1000
Figure 11. AD8115 Frequency Response, RL = 1 kΩ
4
3
–0.3
2V p-p
VO AS SHOWN
RL = 1kΩ
–6
–0.2
01070-017
–6
0.2
–2
–3
–7
0.1
0.3
0
FLATNESS
VO AS SHOWN
RL = 1kΩ
200mV p-p
GAIN
0.1
0
GAIN (dB)
–0.3
2V p-p
VO AS SHOWN
RL = 150Ω�
–7
FLATNESS (dB)
–0.3
GAIN (dB)
2V p-p
FLATNESS (dB)
GAIN (dB)
–1
–4
0.4
01070-015
200mV p-p
–8
–10
0.1
1000
FREQUENCY (MHz)
1
10
100
1000
FREQUENCY (MHz)
Figure 9. AD8114 Frequency Response vs. Load Impedance
Figure 12. AD8115 Frequency Response vs. Load Impedance
Rev. C | Page 11 of 25
FLATNESS (dB)
0
0.5
1
01070-016
1
AD8114/AD8115
Data Sheet
0
0
RL = 1kΩ
RT = 37.5Ω
–20
–20
–30
–30
–40
ALL HOSTILE
–50
RL = 1kΩ
RT = 37.5Ω
–10
CROSSTALK (dB)
–60
–70
–40
ALL HOSTILE
–50
ADJACENT
–60
–70
ADJACENT
–80
01070-018
–80
–90
–100
0.1
1
10
100
01070-021
CROSSTALK (dB)
–10
–90
–100
0.1
1000
1
FREQUENCY (MHz)
Figure 13. AD8114 Crosstalk vs. Frequency
100
1000
Figure 16. AD8115 Crosstalk vs. Frequency
0
0
VO = 2V p-p
RL = 150Ω
–10
–20
–20
–30
–30
–40
–50
2ND HARMONIC
–60
VO = 2V p-p
RL = 150Ω
–10
DISTORTION (dBC)
DISTORTION (dBc)
10
FREQUENCY (MHz)
–70
–40
–50
2ND HARMONIC
–60
–70
3RD HARMONIC
–80
01070-019
3RD HARMONIC
–90
–100
1
10
01070-022
–80
–90
–100
1
50
10
FUNDAMENTAL FREQUENCY (MHz)
50
FUNDAMENTAL FREQUENCY (MHz)
Figure 14. AD8114 Distortion vs. Frequency
Figure 17. AD8115 Distortion vs. Frequency
VO = 2V STEP
RL = 150Ω
0
5
10
15
20
25
5ns/DIV
30
35
40
01070-023
01070-020
0.1%/DIV
0.1%/DIV
VO = 2V STEP
RL = 150Ω
45
0
5
10
15
20
25
5ns/DIV
30
35
Figure 18. AD8115 Settling Time
Figure 15. AD8114 Settling Time
Rev. C | Page 12 of 25
40
45
Data Sheet
AD8114/AD8115
1M
1M
100k
1k
100
0.1
1
10
100
10k
1k
01070-027
INPUT IMPEDANCE (Ω)
10k
01070-024
INPUT IMPEDANCE (Ω)
100k
100
0.1
500
1
FREQUENCY (MHz)
100
100
10
01070-025
1
10
FREQUENCY (MHz)
100
500
10
1
0.1
0.1
1000
01070-028
OUTPUT IMPEDANCE (Ω)
1000
OUTPUT IMPEDANCE (Ω)
1000
1
100
Figure 22. AD8115 Input Impedance vs. Frequency
Figure 19. AD8114 Input Impedance vs. Frequency
0.1
0.1
10
FREQUENCY (MHz)
1
10
FREQUENCY (MHz)
100
1000
1M
1M
100k
100k
OUTPUT IMPEDANCE (Ω)
Figure 23. AD8115 Output Impedance, Enabled vs. Frequency
10k
1k
1k
1
10
FREQUENCY (MHz)
100
10
0.1
1000
01070-029
10
0.1
10k
100
100
01070-026
OUTPUT IMPEDANCE (Ω)
Figure 20. AD8114 Output Impedance, Enabled vs. Frequency
1
10
FREQUENCY (MHz)
100
1000
Figure 24. AD8115 Output Impedance, Disabled vs. Frequency
Figure 21. AD8114 Output Impedance, Disabled vs. Frequency
Rev. C | Page 13 of 25
Data Sheet
–40
–40
–50
–50
–60
–60
–70
–70
OFF ISOLATION (dB)
–80
–90
–100
–110
–120
–80
–90
–100
–110
–140
0.1
1
10
100
01070-033
01070-030
–120
–130
–130
–140
0.1
500
1
FREQUENCY (MHz)
Figure 25. AD8114 Off Isolation, Input-to-Output
–20
–30
–30
–40
–40
–PSRR
–60
+PSRR
–70
–PSRR
–60
–80
–90
–90
01070-031
–80
1
0.1
–100
0.03
10
01070-034
–70
Figure 29. AD8115 PSRR vs. Frequency
170
150
150
130
130
VOLTAGE NOISE (nV/√Hz)
170
110
90
70
01070-032
50
16nV/√Hz
100
1k
10k
100k
10
FREQUENCY (MHz)
Figure 26. AD8114 PSRR vs. Frequency
30
1
0.1
FREQUENCY (MHz)
VOLTAGE NOISE (nV/√Hz)
500
+PSRR
–50
PSRR (dB)
PSRR (dB)
–50
10
10
100
Figure 28. AD8115 Off Isolation, Input-to-Output
–20
–100
0.03
10
FREQUENCY (MHz)
1M
110
90
70
50
30
10
10
10M
FREQUENCY (Hz)
01070-035
OFF ISOLATION (dB)
AD8114/AD8115
18nV/√Hz
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 27. AD8114 Voltage Noise vs. Frequency
Figure 30. AD8115 Voltage Noise vs. Frequency
Rev. C | Page 14 of 25
10M
Data Sheet
AD8114/AD8115
VO = 200mV STEP
RL = 150Ω
0.10V
0.10V
0.05V
0.05V
0V
0V
–0.05V
–0.05V
–0.10V
–0.10V
25ns
–0.15V
Figure 34. AD8115 Pulse Response, Small Signal
VO = 2V STEP
RL = 150Ω
1.5V
1.0V
0.5V
0.5V
0V
0V
–0.5V
–0.5V
–1.0V
–1.0V
01070-037
–1.5V
25ns
VO = 200mV STEP
RL = 150Ω
1.5V
1.0V
500mV
25ns
50mV
Figure 31. AD8114 Pulse Response, Small Signal
–1.5V
500mV
Figure 32. AD8114 Pulse Response, Large Signal
20ns
Figure 35. AD8115 Pulse Response, Large Signal
+5V
UPDATE
01070-039
50mV
01070-036
–0.15V
VO = 200mV STEP
RL = 150Ω
0.15V
01070-040
0.15V
+5V
UPDATE
0V
0V
+2V
VOUT
–0V
–1V
10ns
VOUT
01070-038
INPUT 0
AT –1V
INPUT 0
AT –1V
–2V
10ns
Figure 33. AD8114 Switching Time
Figure 36. AD8115 Switching Time
Rev. C | Page 15 of 25
–0V
01070-041
+1V
INPUT 1
AT +1V
INPUT 1
AT +1V
AD8114/AD8115
Data Sheet
5V
5V
UPDATE
UPDATE
0V
0V
0.05V
0.05V
0V
0V
50ns
50ns
Figure 37. AD8114 Switching Transient (Glitch)
Figure 40. AD8115 Switching Transient (Glitch)
260
240
240
220
220
200
200
180
160
FREQUENCY
160
140
120
100
140
120
100
60
40
40
01070-043
60
20
–10
–8
–6
–4
0
4
–2
2
OFFSET VOLTAGE (mV)
8
6
20
0
–14 –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 14 16 18
OFFSET VOLTAGE (mV)
10
Figure 41. AD8115 Offset Voltage Distribution
44
40
40
36
36
32
32
28
28
FREQUENCY
44
24
20
16
24
20
16
12
12
8
8
01070-044
FREQUENCY
Figure 38. AD8114 Offset Voltage Distribution
4
0
–20 –16
–12
–8
–4
0
4
8
12
OFFSET VOLTAGE DRIFT (µV/°C)
16
01070-046
80
80
01070-047
FREQUENCY
180
0
–12
01070-045
–0.05V
01070-042
–0.05V
4
0
–12
20
Figure 39. AD8114 Offset Voltage Drift Distribution (−40°C to +85°C)
–8
–4
0
4
8
12
OFFSET VOLTAGE DRIFT (µV/°C)
16
20
Figure 42. AD8115 Offset Voltage Drift Distribution (−40°C to +85°C)
Rev. C | Page 16 of 25
Data Sheet
AD8114/AD8115
INPUT/OUTPUT SCHEMATICS
VCC
VCC
ESD
ESD
INPUT
INPUT
ESD
AVEE
01070-009
01070-006
ESD
DGND
Figure 43. Analog Input
Figure 46. Logic Input
VCC
VCC
ESD
2kΩ
ESD
OUTPUT
OUTPUT
AVEE
DGND
Figure 44. Analog Output
Figure 47. Logic Output
VCC
ESD
20kΩ
ESD
DGND
01070-008
RESET
Figure 45. Reset Input
Rev. C | Page 17 of 25
01070-010
ESD
01070-007
ESD
AD8114/AD8115
Data Sheet
THEORY OF OPERATION
The AD8114 (G = 1) and AD8115 (G = 2) are crosspoint arrays
with 16 outputs, each of which can be connected to any one of 16
inputs. Organized by output row, 16 switchable transconductance
stages are connected to each output buffer in the form of a 16-to-1
multiplexer. Each of the 16 rows of transconductance stages are
wired in parallel to the 16 input pins, for a total array of 256
transconductance stages. Decoding logic for each output selects
one (or none) of the transconductance stages to drive the output
stage. The transconductance stages are NPN-input differential
pairs, sourcing current into the folded cascode output stage.
The compensation network and emitter follower output buffer
are in the output stage. Voltage feedback sets the gain, with the
AD8114 configured as a unity gain follower, and the AD8115
configured as a gain-of-2 amplifier with a feedback network.
This architecture provides drive for a reverse-terminated video
load (150 Ω), with low differential gain and phase error for
relatively low power consumption. Power consumption is
further reduced by disabling outputs and transconductance
stages that are not in use. The user notices a small increase in
input bias current as each transconductance stage is enabled.
Features of the AD8114 and AD8115 simplify the construction
of larger switch matrices. The unused outputs of both devices
can be disabled to a high impedance state, allowing the outputs
of multiple ICs to be bused together. In the case of the AD8115,
a feedback isolation scheme is used so that the impedance of the
gain-of-2 feedback network does not load the output. Because
no additional input buffering is necessary, high input resistance
and low input capacitance are easily achieved without additional
signal degradation. To control enable glitches, it is recommended
that the disabled output voltage be maintained within its normal
enabled voltage range (±3.3 V). If necessary, the disabled output
can be kept from drifting out of range by applying an output
load resistor to ground.
A flexible TTL-compatible logic interface simplifies the
programming of the matrix. Both parallel and serial loading
into a first rank of latches programs each output. A global latch
simultaneously updates all outputs. A power-on reset pin is
available to avoid bus conflicts by disabling all outputs.
APPLICATIONS
The AD8114/AD8115 have two options for changing the
programming of the crosspoint matrix. In the first option a
serial word of 80 bits can be provided that updates the entire
matrix each time. The second option allows for changing the
programming of a single output via a parallel interface. The
serial option requires fewer signals, but more time (clock cycles)
for changing the programming, while the parallel programming
technique requires more signals, but can change a single output
at a time and requires fewer clock cycles to complete programming.
Serial Programming
The serial programming mode uses the CE, CLK, DATA IN,
UPDATE, and SER/PAR device pins. The first step is to assert a
low on SER/PAR to enable the serial programming mode. CE
for the chip must be low to allow data to be clocked into the
device. The CE signal can be used to address an individual
device when devices are connected in parallel.
The UPDATE signal should be high during the time that data is
shifted into the serial port of the device. Although the data still
shifts in when UPDATE is low, the transparent, asynchronous
latches allow the shifting data to reach the matrix. This causes
the matrix to try to update to every intermediate state as defined
by the shifting data.
The data at DATA IN is clocked in at every down edge of CLK.
A total of 80 bits must be shifted in to complete the programming.
For each of the 16 outputs, there are four bits (D0 to D3) that
determine the source of its input followed by one bit (D4) that
determines the enabled state of the output. If D4 is low (output
disabled), the four associated bits (D0 to D3) do not matter
because no input is switched to that output.
The most significant output address data is shifted in first, and
then following in sequence until the least significant output
address data is shifted in. At this point UPDATE can be taken
low, which causes the programming of the device according to
the data that was just shifted in. The UPDATE registers are
asynchronous, and when UPDATE is low (and CE is low),
they are transparent.
If more than one AD8114/AD8115 device is to be serially
programmed in a system, the DATA OUT signal from one
device can be connected to the DATA IN of the next device to
form a serial chain. All of the CLK, CE, UPDATE, and SER
/PAR pins should be connected in parallel and operated as
described above. The serial data is input to the DATA IN pin of
the first device of the chain, and it ripples on through to the last.
Therefore, the data for the last device in the chain should come
at the beginning of the programming sequence. The length of
the programming sequence (80 bits) is multiplied by the
number of devices in the chain.
Parallel Programming
While using the parallel programming mode, it is not necessary
to reprogram the entire device when making changes to the matrix.
In fact, parallel programming allows the modification of a single
output at a time. Since this takes only one CLK/UPDATE cycle,
significant time savings can be realized by using parallel
programming.
Rev. C | Page 18 of 25
Data Sheet
AD8114/AD8115
One important consideration in using parallel programming is
that the RESET signal does not reset all registers in the AD8114/
AD8115. When taken low, the RESET signal only sets each output
to the disabled state. This is helpful during power-up to ensure
that two parallel outputs are not active at the same time.
After initial power-up, the internal registers in the device generally
have random data, even though the RESET signal was asserted.
If parallel programming is used to program one output, then
that output is properly programmed, but the rest of the device
has a random program state depending on the internal register
content at power-up. Therefore, when using parallel programming,
it is essential that all outputs be programmed to a desired state
after power-up. This ensures that the programming matrix is
always in a known state. From then on, parallel programming
can be used to modify a single output or more at a time.
In similar fashion, if both CE and UPDATE are taken low after
initial power-up, the random power-up data in the shift register
is programmed into the matrix. Therefore, to prevent the
crosspoint from being programmed into an unknown state, do
not apply low logic levels to both CE and UPDATE after power
is initially applied. Programming the full shift register one time
to a desired state by either serial or parallel programming after
initial power-up eliminates the possibility of programming the
matrix to an unknown state.
To change the programming of an output via parallel
programming, SER/PAR and UPDATE should be taken high
and CE should be taken low. The CLK signal should be in the
high state. The 4-bit address of the output to be programmed
should be put on A0 to A3. The first four data bits (D0 to D3)
should contain the information that identifies the input that
gets programmed to the output that is addressed. The fourth
data bit (D4) determines the enabled state of the output. If D4 is
low (output disabled), then the data on D0 to D3 does not matter.
After the desired address and data signals have been established,
they can be latched into the shift register by a high to low transition
of the CLK signal. The matrix is not programmed, however, until
the UPDATE signal is taken low. It is thus possible to latch in
new data for several or all of the outputs first via successive
negative transitions of CLK while UPDATE is held high, and
then have all the new data take effect when UPDATE goes low.
This technique should be used when programming the device
for the first time after power-up when using parallel programming.
POWER-ON RESET
When powering up the AD8114/AD8115, it is usually desirable
to have the outputs come up in the disabled state. When taken
low, the RESET pin causes all outputs to be in the disabled state.
However, the RESET signal does not reset all registers in the
AD8114/AD8115. This is important when operating in the
parallel programming mode.
Please refer to that section for information about programming
internal registers after power-up. Serial programming programs
the entire matrix each time, so no special considerations apply.
Since the data in the shift register is random after power-up, it
should not be used to program the matrix, or the matrix can
enter unknown states. To prevent this, do not apply logic low
signals to both CE and UPDATE initially after power-up. The
shift register should first be loaded with the desired data, and
then UPDATE can be taken low to program the device.
The RESET pin has a 20 kΩ pull-up resistor to DVDD that can
be used to create a simple power-up reset circuit. A capacitor
from RESET to ground holds RESET low for some time while
the rest of the device stabilizes. The low condition causes all the
outputs to be disabled. The capacitor then charges through the
pull-up resistor to the high state, thus allowing full programming
capability of the device.
GAIN SELECTION
The 16 × 16 crosspoints come in two versions, depending on
the gain of the analog circuit paths that is desired. The AD8114
device is unity gain and can be used for analog logic switching
and other applications where unity gain is desired. The AD8114
can also be used for the input and interior sections of larger
crosspoint arrays where termination of output signals is not
usually used. The AD8114 outputs have very high impedance
when their outputs are disabled.
The AD8115 can be used for devices that are used to drive a
terminated cable with its outputs. This device has a built-in gain
of 2 that eliminates the need for a gain-of-2 buffer to drive a
video line. Its high output disabled impedance minimizes
signal degradation when paralleling additional outputs.
CREATING LARGER CROSSPOINT ARRAYS
The AD8114/AD8115 are high density building blocks for
creating crosspoint arrays of dimensions larger than 16 × 16.
Various features, such as output disable, chip enable, and gainof-1 and gain-of-2 options, are useful for creating larger arrays.
When required for customizing a crosspoint array size, they can
be used with the AD8108 and AD8109, a pair of (unity gain and
gain-of-2) 8 × 8 video crosspoint switches, or with the AD8110
and AD8111, a pair of (unity gain and gain-of-2) 16 × 8 video
crosspoint switches.
The first consideration in constructing a larger crosspoint is to
determine the minimum number of devices required. The 16 ×
16 architecture of the AD8114/AD8115 contains 256 points, which
is a factor of 64 greater than a 4 × 1 crosspoint (or multiplexer).
The printed circuit board area, power consumption, and design
effort savings are readily apparent when compared to using
these smaller devices.
Rev. C | Page 19 of 25
AD8114/AD8115
Data Sheet
For a nonblocking crosspoint, the number of points required is
the product of the number of inputs multiplied by the number
of outputs. Nonblocking requires that the programming of a given
input to one or more outputs does not restrict the availability of
that input to be a source for any other outputs.
AD8114
OR
AD8115
16
IN 00–15
16
16
AD8114
OR
AD8115
RTERM
16
16
Some nonblocking crosspoint architectures require more than
this minimum as calculated above. Also, there are blocking
architectures that can be constructed with fewer devices than
this minimum. These systems have connectivity available on a
statistical basis that is determined when designing the overall
system.
Figure 48. 32 × 32 Crosspoint Array Using Four AD8114 or AD8115 Devices
The basic concept in constructing larger crosspoint arrays is to
connect inputs in parallel in a horizontal direction and to wireOR the outputs together in the vertical direction. The meaning
of horizontal and vertical can best be understood by looking at
a diagram. Figure 48 illustrates this concept for a 32 × 32
crosspoint array that uses four AD8114 or AD8115 devices.
The inputs are each uniquely assigned to each of the 32 inputs
of the two devices and terminated appropriately. The outputs
are wired-OR’ed together in pairs. The output from only one of
a wire-OR’ed pair should be enabled at any given time. The device
programming software must be properly written to cause this to
happen.
16
16
RTERM
16
16
RANK 1
(8 × AD8114)
128:32
8
IN 00–15
AD8114
16
8
RTERM
8
IN 16–31
AD8114
16
8
RTERM
8
IN 32–47
AD8114
16
8
RANK 2
32:16 NONBLOCKING
(32:32 BLOCKING)
RTERM
8
8
IN 48–63
AD8114
16
8
8
1kΩ
RTERM
8
IN 64–79
AD8114
16
8
IN 80–95
AD8114
16
AD8115
8
OUT 00Ð15
NONBLOCKING
8
1kΩ
8
RTERM
8
1kΩ
8
AD8115
8
8
ADDITIONAL
16 OUTPUTS
(SUBJECT
TO BLOCKING)
8
1kΩ
RTERM
8
IN 96–111
AD8114
16
8
RTERM
8
IN 112–127
AD8114
AD8114
OR
AD8115
8
01070-049
16
RTERM
Figure 49. Nonblocking 128 × 16 Array (128 × 32 Blocking)
Rev. C | Page 20 of 25
01070-048
AD8114
OR
AD8115
16
IN 16–31
Data Sheet
AD8114/AD8115
Using additional crosspoint devices in the design can lower the
number of outputs that must be wire-OR’ed together. Figure 49
shows a block diagram of a system using eight AD8114 devices
and two AD8115 devices to create a nonblocking, gain-of-2,
128 × 16 crosspoint that restricts the wire-OR’ing at the
output to only four outputs.
Additionally, by using the lower eight outputs from each of the
two Rank 2 AD8115 devices, a blocking 128 × 32 crosspoint
array can be realized. There are, however, some drawbacks to
this technique. The offset voltages of the various cascaded
devices accumulates, and the bandwidth limitations of the
devices compound. In addition, the extra devices consume
more current and take up more board space. Once again, the
overall system design specifications determine how to make
the various tradeoffs.
MULTICHANNEL VIDEO
The excellent video specifications of the AD8114/AD8115 make
them ideal candidates for creating composite video crosspoint
switches. These can be made quite dense by taking advantage of
the high level of integration of the AD8114/AD8115 and the
fact that composite video requires only one crosspoint channel
per system video channel. There are, however, other video
formats that can be routed with the AD8114/AD8115 requiring
more than one crosspoint channel per video channel.
Some systems use twisted-pair wiring to carry video signals. These
systems utilize differential signals and can lower costs because
they use lower cost cables, connectors and termination methods.
They also have the ability to lower crosstalk and reject commonmode signals, which can be important for equipment that
operates in noisy environments or where common-mode voltages
are present between transmitting and receiving equipment.
In such systems, the video signals are differential; there is a
positive and negative (or inverted) version of the signals. These
complementary signals are transmitted onto each of the two
wires of the twisted pair, yielding a first-order zero commonmode voltage. At the receive end, the signals are differentially
received and converted back into a single-ended signal.
When switching these differential signals, two channels are
required in the switching element to handle the two differential
signals that make up the video channel. Thus, one differential
video channel is assigned to a pair of crosspoint channels, both
input and output. For a single AD8114/AD8115, eight differential
video channels can be assigned to the 16 inputs and 16 outputs.
This effectively forms an 8 × 8 differential crosspoint switch.
Programming such a device requires that inputs and outputs be
programmed in pairs. This information can be deduced by
inspection of the programming format of the AD8114/AD8115
and the requirements of the system.
There are other analog video formats requiring more than one
analog circuit per video channel. One 2-circuit format that is
commonly being used in systems such as satellite TV, digital
cable boxes, and higher quality VCRs is called S-video or Y/C
video. This format carries the brightness (luminance or Y)
portion of the video signal on one channel and the color
(chrominance, chroma, or C) on a second channel.
Since S-video also uses two separate circuits for one video
channel, creating a crosspoint system requires assigning one
video channel to two crosspoint channels, as in the case of a
differential video system. Aside from the nature of the video
format, other aspects of these two systems are the same.
There are yet other video formats using three channels to carry
the video information. Video cameras produce RGB (red, green,
blue) directly from the image sensors. RGB is also the usual
format used by computers internally for graphics. RGB can be
converted to Y, R-Y, B-Y format, sometimes called YUV format.
These 3-circuit video standards are referred to as component
analog video.
The component video standards require three crosspoint channels
per video channel to handle the switching function. In a fashion
similar to the 2-circuit video formats, the inputs and outputs
are assigned in groups of three, and the appropriate logic
programming is performed to route the video signals.
CROSSTALK
Many systems, such as broadcast video, that handle numerous
analog signal channels have strict requirements for keeping the
various signals from influencing any of the others in the system.
Crosstalk is the term used to describe the coupling of the
signals of other nearby channels to a given channel.
When there are many signals in close proximity in a system, as
is undoubtedly the case in a system that uses the AD8114/
AD8115, the crosstalk issues can be quite complex. A good
understanding of the nature of crosstalk and some definition
of terms is required to specify a system that uses one or more
AD8114/AD8115 devices.
Types of Crosstalk
Crosstalk can be propagated by means of any of three methods.
These fall into the categories of electric field, magnetic field,
and sharing of common impedances. This section explains
these effects.
Every conductor can be both a radiator of electric fields and a
receiver of electric fields. The electric field crosstalk mechanism
occurs when the electric field created by the transmitter propagates
across a stray capacitance (for example, free space) and couples
with the receiver and induces a voltage. This voltage is an
unwanted crosstalk signal in any channel that receives it.
Currents flowing in conductors create magnetic fields that circulate
around the currents. These magnetic fields then generate voltages
in any other conductors whose paths they link. The undesired
induced voltages in these other channels are crosstalk signals.
The channels that crosstalk can be said to have a mutual
inductance that couples signals from one channel to another.
Rev. C | Page 21 of 25
AD8114/AD8115
Data Sheet
The power supplies, grounds, and other signal return paths of a
multichannel system are generally shared by the various channels.
When a current from one channel flows in one of these paths, a
voltage that is developed across the impedance becomes an input
crosstalk signal for other channels that share the common
impedance.
All these sources of crosstalk are vector quantities, so the
magnitudes cannot simply be added together to obtain the
total crosstalk. In fact, there are conditions where driving
additional circuits in parallel in a given configuration can
actually reduce the crosstalk.
Areas of Crosstalk
For a practical AD8114/AD8115 circuit, it is required that the
device be mounted to some sort of circuit board to connect it
to the power supplies and the measurement equipment. This
requirement, however, raises the issue that the crosstalk of a
system is a combination of the intrinsic crosstalk of the devices
in addition to the circuit board to which they are mounted. It is
important to try to separate these two areas of crosstalk when
attempting to minimize its effect.
In addition, crosstalk can occur among the inputs to a crosspoint
and among the output. It can also occur from input to output.
Techniques are discussed for diagnosing which part of a system
is contributing to crosstalk.
Measuring Crosstalk
Crosstalk is measured by applying a signal to one or more
channels and measuring the relative strength of that signal on a
desired selected channel. The measurement is usually expressed
as dB down from the magnitude of the test signal. The crosstalk
is expressed by
XT = 20 log 10 ( Asel ( s ) Atest ( s ))
First, we can measure the crosstalk terms associated with driving
a test signal into each of the other 15 inputs one at a time while
applying no signal to IN00. We can then measure the crosstalk
terms associated with driving a parallel test signal into all 15
other inputs taken two at a time in all possible combinations, then
three at a time, and so on, until there is only one way to drive a
test signal into all 15 other inputs in parallel.
Each of these cases is legitimately different from the others and
might yield a unique value depending on the resolution of the
measurement system, but it is hardly practical to measure all
these terms and then to specify them. In addition, this describes
the crosstalk matrix for just one input channel. A similar crosstalk
matrix can be proposed for every other input. In addition, if the
possible combinations and permutations for connecting inputs
to the other (not used for measurement) outputs are taken into
consideration, the numbers rather quickly grow to astronomical
proportions. If a larger crosspoint array of multiple AD8114/
AD8115 devices is constructed, the numbers grow larger still.
Some subset of all these cases must be selected to be used as a
guide for a practical measure of crosstalk. One common method is
to measure all hostile crosstalk. This term means that the crosstalk
to the selected channel is measured while all other system channels
are driven in parallel. In general, this yields the worst crosstalk
number, but this is not always the case due to the vector nature
of the crosstalk signal.
Other useful crosstalk measurements are those created by one
nearest neighbor or by the two nearest neighbors on either side.
These crosstalk measurements are generally higher than those
of more distant channels, so they can serve as a worst-case
measure for any other 1-channel or 2-channel crosstalk
measurements.
Input and Output Crosstalk
where:
s = jω is the Laplace transform variable.
Asel(s) is the amplitude of the crosstalk-induced signal in the
selected channel.
Atest(s) is the amplitude of the test signal.
It can be seen that crosstalk is a function of frequency, but not a
function of the magnitude of the test signal (to first order).
In addition, the crosstalk signal has a phase relative to the
test signal associated with it.
A network analyzer is most commonly used to measure crosstalk
over a frequency range of interest. It can provide both magnitude
and phase information about the crosstalk signal.
As a crosspoint system or device grows larger, the number of
theoretical crosstalk combinations and permutations can become
extremely large. For example, in the case of the 16 × 16 matrix
of the AD8114/AD8115, we can examine the number of crosstalk
terms that can be considered for a single channel, say IN00 input.
IN00 is programmed to connect to one of the AD8114/AD8115
outputs where the measurement can be made.
The flexible programming capability of the AD8114/AD8115
can be used to diagnose whether crosstalk is occurring more on
the input side or the output side. Some examples are illustrative.
A given input channel (IN07 in the middle for this example)
can be programmed to drive OUT07 (also in the middle). The
input to IN07 is just terminated to ground (via 50 Ω or 75 Ω)
and no signal is applied.
All the other inputs are driven in parallel with the same test
signal (practically that is provided by a distribution amplifier),
with all other outputs except OUT07 disabled. Since grounded
IN07 is programmed to drive OUT07, no signal should be present.
Any signal that is present can be attributed to the other 15 hostile
input signals because no other outputs are driven. (They are all
disabled.) Thus, this method measures the all-hostile input
contribution to crosstalk into IN07. Of course, the method can
be used for other input channels and combinations of hostile
inputs.
Rev. C | Page 22 of 25
Data Sheet
AD8114/AD8115
For output crosstalk measurement, a single input channel is
driven (IN00, for example) and all outputs other than a given
output (IN07 in the middle) are programmed to connect to
IN00. OUT07 is programmed to connect to IN15 (far away
from IN00), which is terminated to ground.
Thus OUT07 should not have a signal present since it is
listening to a quiet input. Any signal measured at the OUT07
can be attributed to the output crosstalk of the other 16 hostile
outputs. Again, this method can be modified to measure other
channels and other crosspoint matrix combinations.
Effect of Impedances on Crosstalk
The input side crosstalk can be influenced by the output
impedance of the sources that drive the inputs. The lower the
impedance of the drive source, the lower the magnitude of the
crosstalk. The dominant crosstalk mechanism on the input side
is capacitive coupling. The high impedance inputs do not have
significant current flow to create magnetically induced crosstalk.
However, significant current can flow through the input
termination resistors and the loops that drive them. Thus,
the printed circuit board on the input side can contribute to
magnetically coupled crosstalk.
From a circuit standpoint, the input crosstalk mechanism looks
like a capacitor coupling to a resistive load. For low frequencies,
the magnitude of the crosstalk is given by
XT = 20 log10 ((RS CM ) × s )
where:
RS is the source resistance.
CM is the mutual capacitance between the test signal circuit
and the selected circuit.
s is the Laplace transform variable.
From the equation, it can be observed that this crosstalk
mechanism has a high-pass nature; it can be minimized by
reducing the coupling capacitance of the input circuits and
lowering the output impedance of the drivers. If the input is
driven from a 75 Ω terminated cable, the input crosstalk can be
reduced by buffering this signal with a low output impedance
buffer.
On the output side, the crosstalk can be reduced by driving a
lighter load. Although the AD8114/AD8115 is specified with
excellent differential gain and phase when driving a standard
150 Ω video load, the crosstalk is higher than the minimum
obtainable due to the high output currents. These currents
induce crosstalk via the mutual inductance of the output pins
and bond wires of the AD8114/AD8115.
From a circuit standpoint, this output crosstalk mechanism
looks like a transformer, with a mutual inductance between the
windings, that drives a load resistor. For low frequencies, the
magnitude of the crosstalk is given by
XT = 20 log 10 ( Mxy × s / R L )
where:
Mxy is the mutual inductance of Output X to Output Y.
RL is the load resistance on the measured output.
This crosstalk mechanism can be minimized by keeping
the mutual inductance low and increasing RL. The mutual
inductance can be kept low by increasing the spacing of
the conductors and minimizing their parallel length.
Rev. C | Page 23 of 25
AD8114/AD8115
Data Sheet
OUTLINE DIMENSIONS
16.20
16.00 SQ
15.80
1.60 MAX
0.75
0.60
0.45
100
1
76
75
PIN 1
14.20
14.00 SQ
13.80
TOP VIEW
(PINS DOWN)
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
VIEW A
ROTATED 90° CCW
51
50
25
26
VIEW A
0.50
BSC
LEAD PITCH
0.27
0.22
0.17
COMPLIANT TO JEDEC STANDARDS MS-026-BED
051706-A
1.45
1.40
1.35
Figure 50. 100-Lead Low Profile Quad Flat Package [LQFP]
(ST-100-1)
Dimension shown in millimeters
ORDERING GUIDE
Model 1, 2
AD8114ASTZ
AD8115ASTZ
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
100-Lead Low Profile Quad Flat Package [LQFP]
100-Lead Low Profile Quad Flat Package [LQFP]
Package Option
ST-100-1
ST-100-1
Details of the lead finish composition can be found on the Analog Devices website at www.analog.com by reviewing the Material Description of each relevant package.
Z = RoHS Compliant Part.
Rev. C | Page 24 of 25
Data Sheet
AD8114/AD8115
NOTES
©1998–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01070-0-7/16(C)
Rev. C | Page 25 of 25
