a
200 MHz, 16 ⴛ 16 Buffered
Video Crosspoint Switch
AD8116
PRODUCT DESCRIPTION
The AD8116 is a high speed 16 × 16 video crosspoint switch
matrix. It offers a –3 dB signal bandwidth greater than 200 MHz
and channel switch times of 60 ns with 0.1% settling. With –70dB
of crosstalk and –1 dB of isolation (@ 5 MHz), the AD8116
is useful in many high speed applications. The differential gain
and differential phase errors of better than 0.01% and 0.01°,
respectively, along with 0.1 dB flatness out to 60 MHz make the
AD8116 ideal for video signal switching.
The AD8116 includes output buffers that can be placed into a
high impedance state for paralleling crosspoint outputs so that
off channels do not load the output bus. It operates on voltage
AD8116
CLK
CLK
DATA IN
DATA OUT
80-BIT SHIFT REG.
UPDATE
CE
UPDATE
CE
80
PARALLEL LATCH
80
DECODE
16 ⴛ 5:16 DECODERS
256
SET INDIVIDUAL OR
RESET ALL OUTPUTS
TO "OFF"
RESET
16
OUTPUT
BUFFER
RESET
+1
+1
ENABLE/DISABLE
+1
+1
+1
SWITCH
MATRIX
+1
+1
16 INPUTS
+1
+1
+1
16 OUTPUTS
+1
+1
+1
+1
+1
+1
4
0.5
RL = 50⍀
3
0.4
2
0.3
1
0.2
200mV p-p
0
–1
0.1
FLATNESS
2V p-p
0
–2
0.1dB FLATNESS – dB
APPLICATIONS
Routing of High Speed Signals Including:
Composite Video (NTSC, PAL, S, SECAM, etc.)
Component Video (YUV, RGB, etc.)
3-Level Digital (HDB3)
Video on Demand
Ultrasound
Communication Satellites
FUNCTIONAL BLOCK DIAGRAM
MAGNITUDE – dB
FEATURES
Large 16 ⴛ 16 High Speed Nonblocking Switch Array
Switch Array Controllable via an 80-Bit Serial Word
Serial Data Out Allows “Daisy Chaining” of Multiple
AD8116s to Create Large Switch Arrays Over 256 ⴛ 256
Complete Solution
Buffered Inputs
16 Individual Output Amplifiers
Drives 150 ⍀ Loads
Excellent Video Performance
60 MHz 0.1 dB Gain Flatness
0.01% Differential Gain Error (RL = 150 ⍀)
0.01ⴗ Differential Phase Error (RL = 150 ⍀)
Excellent AC Performance
200 MHz –3 dB Bandwidth
300 V/s Slew Rate
Low Power of 900 mW (3.5 mW per Point)
Low All Hostile Crosstalk of –70 dB @ 5 MHz
Output Disable Allows Direct Connection of Multiple
Device Outputs
Chip Enable Allows Selection of Individual AD8116s in
Large Arrays (or Parallel Programming of AD8116s)
Reset Pin Allows Disabling of All Outputs (Connected
Through a Capacitor to Ground Provides “PowerOn” Reset Capability)
128-Lead LQFP Package (14 mm ⴛ 14 mm)
–0.1
2V p-p
–3
–0.2
200mV p-p
–4
100k
1M
10M
FREQUENCY – Hz
100M
–0.3
1G
Figure 1. Frequency Response
supplies of ± 5 V while consuming only 90 mA of idle current.
The channel switching is performed via a serial digital control
that can accommodate “daisy chaining” of several devices.
The AD8116 is packaged in a 128-lead LQFP package occupying only 0.36 square inches, and is specified over the commercial temperature range of 0°C to 70°C.
Rev. C
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD8116–SPECIFICATIONS (V = ⴞ5 V, T = 25ⴗC, R = 1 k⍀ unless otherwise noted.)
S
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Slew Rate
Settling Time
Gain Flatness
NOISE/DISTORTION PERFORMANCE
Differential Gain Error
Differential Phase Error
Crosstalk, All Hostile
Off Isolation, Input-Output
Input Voltage Noise
DC PERFORMANCE
Gain
Gain Matching
OUTPUT CHARACTERISTICS
Output Offset Voltage
Output Impedance
Output Disable Capacitance
Output Leakage Current
Output Voltage Range
Output Current
Short Circuit Current
INPUT CHARACTERISTICS
Input Voltage Range
Input Capacitance
Input Resistance
Input Bias Current
SWITCHING CHARACTERISTICS
Enable On Time
Switching Time
A
L
Conditions
Min
Supply Voltage Range
PSRR
OPERATING TEMPERATURE RANGE
Temperature Range
θJA
Max
Unit
Reference
Figure
200 mV p-p, RL = 150 Ω
1 V p-p, RL = 150 Ω
2 V p-p, RL = 150 Ω
2 V Step, RL = 150 Ω
0.1%, 2 V Step, RL = 150 Ω
0.05 dB, 200 mV p-p, R L = 150 Ω
0.05 dB, 2 V p-p, RL = 150 Ω
0.1 dB, 200 mV p-p, RL = 150 Ω
0.1 dB, 2 V p-p, RL = 150 Ω
200
120
80
300
60
25
20
60
45
MHz
MHz
MHz
V/μs
ns
MHz
MHz
MHz
MHz
1
5
6
1
1
1
1
NTSC or PAL, R L = 1 kΩ
NTSC or PAL, R L = 150 Ω
NTSC or PAL, R L = 1 kΩ
NTSC or PAL, R L = 150 Ω
ƒ = 5 MHz
ƒ = 10 MHz
ƒ = MHz, RL = 150 Ω, One Channel
0.01 MHz to 50 MHz
0.01
0.01
0.01
0.01
–70
–60
–1
15
%
%
Degrees
Degrees
dB
dB
dB
nV/√Hz
2
2
11
8
No Load
RL = 1 kΩ
No Load, Ch-Ch
RL = 1 kΩ, Ch-Ch
0.995 0.999
0.992 0.999
Worst-Case All Switch Configurations
DC, Enabled
Disabled
1
Disabled
± 2.5
20
± 2.5
Any Switch Configuration
1
15
0.2
10
3
1
±3
40
65
±3
5
10
2
1.000
1.000
0.15
0.5
V/V
V/V
%
%
45
mV
Ω
MΩ
pF
μA
V
mA
mA
5
V
pF
MΩ
μA
1
17
12
9
9
13
13
60
50
ns
ns
16
15
mV p-p
10
ƒ = 100 kHz
ƒ = 1 MHz
75
95
25
70
95
22.5
25
35
10
15
± 4.5 to ± 5.5
60
40
mA
mA
mA
mA
mA
mA
V
dB
dB
7
7
Operating (Still Air)
Operating (Still Air)
0 to 70
37
°C
°C/W
50% UPDATE to 1% Output Settling,
2 V Step
Switching Transient (Glitch)
POWER SUPPLIES
Supply Current
Limit
Typ
AVCC, Outputs Enabled, No Load
AVCC, Outputs Disabled
AVEE, Outputs Enabled, No Load
AVEE, Outputs Disabled
DVCC, Outputs Enabled, No Load
DVEE, Outputs Enabled, No Load
Specifications subject to change without notice.
–2–
REV.
REV.CC
AD8116
TIMING CHARACTERISTICS
Parameter
Symbol
Min
Data Setup Time
CLK Pulsewidth
Data Hold Time
CLK Pulse Separation
CLK to UPDATE Delay
UPDATE Pulsewidth
CLK to DATA OUT Valid
Propagation Delay, UPDATE to Switch On or Off
Data Load Time, CLK = 5 MHz
CLK, UPDATE Rise and Fall Times
RESET Time
t1
t2
t3
t4
t5
t6
t7
–
–
–
–
20
100
20
100
0
50
t2
Limit
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
200
50
16
100
200
t4
1
CLK
0
1
DATA IN
0
t1
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
t3
OUT15 (D4)
OUT15 (D3)
OUT00 (D0)
t5
1 = LATCHED
UPDATE
0 = TRANSPARENT
t6
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
t7
DATA OUT
0 1 2 3 4 5 6 7 8 9 10
15
20
25
75
79
CLOCK
CONNECT TO
INPUT 00
ENABLE OUTPUT 00
CONNECT TO
INPUT 03
ENABLE OUTPUT 11
CONNECT TO
INPUT 15
ENABLE OUTPUT 12
DON’T CARE
DISABLE OUTPUT 13
CONNECT TO
INPUT 01
ENABLE OUTPUT 14
CONNECT TO
NPUT 00
ENABLE OUTPUT 15
DATA IN
UPDATE
T=0
INCREASING TIME
Figure 2. Timing Diagram and Programming Example
Table I. Logic Levels
VIH
VIL
VOH
VOL
IIH
IIL
IOH
IOL
CLK, DATA IN,
CE, UPDATE
CLK, DATA IN,
CE, UPDATE
DATA OUT
DATA OUT
CLK, DATA IN,
CE, UPDATE
CLK, DATA IN,
CE, UPDATE
DATA OUT
DATA OUT
2.0 V min
0.8 V max
2.7 V min
0.5 V max
20 μA max
–400 μA min
–400 μA max
3.0 mA min
REV. C
–3–
AD8116
ABSOLUTE MAXIMUM RATINGS 1
MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.0 V
Internal Power Dissipation2
AD8116 128-Lead Plastic LQFP (ST) . . . . . . . . . . . . 3.5 W
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ⫾VS
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
The maximum power that can be safely dissipated by the
AD8116 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition
temperature of the plastic, approximately 150°C. Temporarily
exceeding this limit may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of 175°C for an extended
period can result in device failure.
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air (T A = 25°C):
128-lead plastic LQFP (ST): θJA = 37°C/W.
While the AD8116 is internally short circuit protected, this may
not be sufficient to guarantee that the maximum junction temperature (150°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maximum
power derating curves shown in Figure 3.
MAXIMUM POWER DISSIPATION – Watts
5.0
TJ = 150 C
4.0
3.0
2.0
1.0
0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70
AMBIENT TEMPERATURE – C
80 90
Figure 3. Maximum Power Dissipation vs. Temperature
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8116 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. C
AD8116
Table II. Operation Truth Table
Control Lines
CE
UPDATE
CLK
DATA IN
DATA OUT
RESET
Operation/Comment
1
0
X
1
X
f
X
Data i
X
Data i-80
1
1
0
0
X
X
X
1
X
X
X
X
X
0
No change in logic.
The data on the DATA IN line is loaded into the
serial register. The first bit clocked into the serial
register appears at DATA OUT 80 clocks later.
Data in the serial shift register transfers into the
parallel latches that control the switch array.
Latches are transparent.
Asynchronous operation. All outputs are disabled.
Remainder of logic is unchanged.
DATA IN
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
DATA OUT
CLK
CE
UPDATE
LE
OUTPUT CH
CH BIT #
SERIAL BIT #
D LE
OUT0
0
LSB
79
Q
D LE
D LE
OUT0 OUT0
1
2
78
3
77
Q
D LE
76
Q
D LE
OUT0 OUT0
EN
MSB
75
Q CLR Q
D
LE
OUT1
D LE
D LE
D LE
D LE
D LE
D
OUT14 OUT15 OUT15 OUT15 OUT15 OUT15
0
EN
74
5
Q
CLR Q
0
LSB
4
Q
1
2
3
3
2
Q
1
Q
EN
MSB
0
Q CLR Q
RESET
DECODE
256
16
SWITCH MATRIX
OUTPUT
ENABLE
Figure 4. Logic Diagram
REV. C
–5–
AD8116
PIN FUNCTION DESCRIPTIONS
Pin Name
Pin Numbers
Pin Description
INxx
2, 4, 6, 8, 10, 12, 14, 16, 18,
20, 22, 24, 26, 28, 30, 32
37, 126
36, 125
35, 124
38, 123
Analog Inputs; xx = Channel No. 00 thru 15.
DATA IN
CLK
DATA OUT
UPDATE
RESET
CE
OUTyy
AGND
DVCC
DGND
DVEE
AVEE
AVCC
AGNDxx
AVCC00
AVCC15
AVCCxx/yy
AVEExx/yy
39, 122
40, 121
65, 67, 69, 71, 73, 75, 77, 79,
81, 83, 85, 87, 89, 91, 93, 95
1, 3, 5, 7, 9, 11, 13, 15, 17, 19,
21, 23, 25, 27, 29, 31, 33, 128
34, 127
41, 120
42, 119
43, 44, 45, 116, 117, 118
46, 47, 48, 113, 114, 115
56–63, 97–104
96
64
68, 72, 76, 80, 84, 88, 92
66, 70, 74, 78, 82, 86, 90, 94
Serial Data Input, TTL Compatible.
Serial Clock, TTL Compatible. Falling edge triggered.
Serial Data Out, TTL Compatible.
Enable (Transparent) “Low.” Allows serial register to connect directly to switch
matrix. Data latched when “high.”
Disable Outputs, Enable “Low.”
Chip Enable, Enable “Low.” Must be “low” to clock in & latch data.
Analog Outputs yy = Channel Nos. 00 thru 15.
Analog Ground for inputs and switch matrix.
+5 V for Digital Circuitry.
Ground for Digital Circuitry.
–5 V for Digital Circuitry.
–5 V for Inputs and Switch Matrix.
+5 V for Inputs and Switch Matrix.
Ground for Output Amp, xx = Output Channel Nos. 00 thru 15. Must be connected.
+5 V for Output Channel 00. Must be connected.
+5 V for Output Channel 15. Must be connected.
+5 V for Output Amplifier that is shared by Channel Nos. xx and yy. Must be connected.
–5 V for Output Amplifier that is shared by Channel Nos. xx and yy. Must be connected.
VCC
VCC
ESD
VCC
ESD
INPUT
ESD
OUTPUT
ESD
20k⍀
RESET
ESD
ESD
VEE
VEE
c. Reset Input
b. Analog Output
a. Analog Input
VCC
VCC
ESD
2k⍀
ESD
OUTPUT
INPUT
ESD
ESD
VEE
VEE
d. Logic Input
e. Logic Output
Figure 5. I/O Pin Schematics
–6–
REV. C
AD8116
DVCC
DATA IN
CLK
DATA OUT
UPDATE
RESET
CE
DGND
DVEE
AVEE
AVEE
AVEE
AVCC
AVCC
AVCC
NC
NC
NC
NC
NC
NC
NC
NC
AGND00
AGND01
AGND02
AGND03
AGND04
AGND05
AGND06
AGND07
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
AGND
128
127
PIN CONFIGURATION
AGND
1
IN00
2
AGND
96
AVCC00
95
OUT00
3
94
AVEE00/01
IN01
4
93
OUT01
AGND
5
92
AVCC01/02
IN02
6
91
OUT02
AGND
7
90
AVEE02/03
IN03
8
89
OUT03
AGND
9
88
AVCC03/04
IN04
10
87
OUT04
AGND
11
86
AVEE04/05
IN05
12
85
OUT05
AGND
13
84
AVCC05/06
IN06
14
83
OUT06
AGND
15
82
AVEE06/07
IN07
16
AD8116
81
OUT07
AGND
17
80
AVCC07/08
IN08
18
79
OUT08
AGND
19
128L LQFP
(14mm × 14mm)
TOP VIEW
(Not to Scale)
78
AVEE08/09
IN09
20
77
OUT09
AGND
21
76
AVCC09/10
IN10
22
75
OUT10
AGND
23
74
AVEE10/11
IN11
24
73
OUT11
AGND
25
72
AVCC11/12
IN12
26
71
OUT12
AGND
27
70
AVEE12/13
IN13
28
69
OUT13
AGND
29
68
AVCC13/14
IN14
30
67
OUT14
AGND
31
66
AVEE14/15
IN15
32
65
OUT15
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
AGND
DVCC
DATA OUT
CLK
DATA IN
UPDATE
RESET
CE
DGND
DVEE
AVEE
AVEE
AVEE
AVCC
AVCC
AVCC
NC
NC
NC
NC
NC
NC
NC
AGND15
AGND14
AGND13
AGND12
AGND11
AGND10
AGND09
AGND08
AVCC15
PIN 1
IDENTIFIER
NC = NO CONNECT
REV. C
–7–
AD8116 –Typical Performance Characteristics
0.5
4
RL = 150⍀
CL = 0pF
3
0.2
1
200mV p-p
0
0.1
FLATNESS
–1
2V p-p
0
FLATNESS – dB
0.3
2
MAGNITUDE – dB
100mV p-p
0.4
25mV/DIV
–0.1
–2
2V p-p
–0.2
–3
200mV p-p
–0.3
–4
100k
1M
10M
FREQUENCY – Hz
100M
100ns/DIV
1G
TPC 4. Step Response, 100 mV Step
TPC 1. Frequency Response
–10
–20
RL = 1k⍀
RS = 37.5⍀
ALL HOSTILE CROSSTALK
VIN = 632mV p-p
CROSSTALK – dB
–30
–40
2V p-p
–50
500mV/DIV
–60
–70
ADJACENT CHANNEL
CROSSTALK
VIN = 632mV p-p
–80
–90
–100
300k
1M
10M
FREQUENCY – Hz
100ns/DIV
100M 200M
TPC 5. Step Response, 2 V Step
TPC 2. Crosstalk vs. Frequency
0
VIN = 2V p-p, RL = 150⍀
HARMONIC DISTORTION – dB
–10
2V STEP
RL = 150⍀
–20
–30
–40
2mV/DIV
= 0.1%/DIV
–50
–60
2ND HARMONIC
–70
3RD HARMONIC
–80
–90
–100
100k
1M
10M
FREQUENCY – Hz
0
100M
20
40 60
80 100 120 140 160 180
20ns/DIV
TPC 6. Settling Time
TPC 3. Total Harmonic Distortion
–8–
REV. C
Typical Performance Characteristics–AD8116
POWER SUPPLY REJECTION – dB
–20
5
4
3
1V/DIV 2
1
0
–30
–40
20
10
–50
10mV/DIV 0
–10
–60
–20
–70
10k
100k
1M
FREQUENCY – Hz
50ns/DIV
10M
TPC 7. PSRR vs. Frequency
TPC 10. Switching Transient (Glitch)
316
–50
–60
VIN = 2V p-p
–70
OFF ISOLATION – dB
nV/ Hz
100
31.6
10
–80
–90
–100
–110
–120
–130
–140
3.16
10
100
1k
10k
100k
1M
FREQUENCY – Hz
10M
–150
100k
100M
10M
10,000
1M
1000
100k
10k
1k
100M
500M
100
10
1
0.1
100
100k
1M
10M
FREQUENCY – Hz
100M
100k
500M
TPC 9. Output Impedance, Disabled
REV. C
10M
FREQUENCY – Hz
TPC 11. Off Isolation, Input-Output
OUTPUT IMPEDANCE – ⍀
OUTPUT IMPEDANCE – ⍀
TPC 8. Voltage Noise vs. Frequency
1M
1M
10M
FREQUENCY – Hz
100M
TPC 12. Output Impedance, Enabled
–9–
500M
AD8116
10M
INPUT IMPEDANCE – ⍀
1M
VOUT
100k
10k
UPDATE
1k
100mV, 50ns
100
30k
100k
1M
10M
FREQUENCY – Hz
100M
500M
TPC 13. Input Impedance vs. Frequency
TPC 16. Switching Time
170
15
VIN = 200mV
RL = 150⍀
12
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
–0.035
9
30pF
FREQUENCY
GAIN – dB
6
18pF
3
0
12pF
–3
–6
–9
–12
–15
30k
100k
1M
10M
FREQUENCY – Hz
100M
500M
TPC 14. Frequency Response vs. Capacitive Load
–0.015
–0.005
0.005
OFFSET VOLTAGE – Volts
0.015
0.025
TPC 17. Offset Voltage Distribution
0.5
2.0
VIN = 200mV
RL = 150⍀
0.4
0.3
1.5
CL = 30pF
1.0
0.2
CL = 18pF
0.5
0.1
VOS – mV
FLATNESS – dB
–0.025
0
–0.1
–0.5
CL = 12pF
–0.2
0.0
–1.0
–0.3
–1.5
–0.4
–0.5
30k
100k
1M
10M
FREQUENCY – Hz
–2.0
–60
100M
TPC 15. Flatness vs. Capacitive Load
–40
–20
0
20
40
TEMPERATURE – ⴗC
60
80
100
TPC 18. Offset Voltage Drift vs. Temperature
–10–
REV. C
AD8116
THEORY OF OPERATION
APPLICATIONS
Multichannel Video
Loading Data
Data to control the switches is clocked serially into an 80-bit
shift register and then transferred in parallel to an 80-bit latch.
The falling edge of CLK (the serial clock input) loads data into
the shift register. The first five bits of the 80 bits are loaded via
DATA IN (the serial data input) program OUT15. The first of
the five bits (D4) enables or disables the output. The next four
bits (D3–D0, D3 = MSB, D0 = LSB) determine which one of
the 16 inputs will be connected to OUT15 (only one of the 16
inputs can be connected to a given output). The remaining bits
program OUT14 through OUT00.
The excellent video specifications of the AD8116 make it an
ideal candidate for creating composite video crosspoint switches.
These can be made quite dense by taking advantage of the
AD8116’s high level of integration and the fact that composite
video requires only one crosspoint channel per system video
channel. There are, however, other video formats that can be
routed with the AD8116 requiring more than one crosspoint
channel per video channel.
Some systems use twisted pair wiring to carry video signals.
These systems utilize differential signals and can lower costs
because they use lower cost cables, connectors and termination
methods. They also have the ability to lower crosstalk and reject
common-mode signals, which can be important for equipment that operates in noisy environments or where commonmode voltages are present between transmitting and receiving
equipment.
After the shift register is filled with the new 80 bits of control
data, UPDATE is activated (low) to transfer the data to the
parallel latches. The switch control latches are static and will
hold their data as long as power is applied.
To extend the number of switches in an array, the DATA
OUT and DATA IN pins of multiple AD8116s can be daisychained together. The DATA OUT pin is the end of the shift
register and may be directly connected to the DATA IN pin of
the follow-on AD8116. CE can be used to control the clocking
of data into selected devices.
Serial Logic
The AD8116 employs a serial interface for programming the
state of the crosspoint array. The 80-bit shift register (Figure
consists of static D flip-flops while the parallel latch uses
transparent latches that are latched by a logic high state of
UPDATE, and transparent on logic low of the same signal.
The 4-to-16 decoder is a small current-mode multilevel gate
array that steers a small select current to the selected point in the
crosspoint array.
The RESET signal is connected to only the enable/disable bit on
each output buffer. This means that the AD8116 will have a random configuration on power-up. In normal operation though,
RESET and UPDATE can be used together to alternately
enable and disable an entire array at once, if desired.
Separate chip enable (CE), update (UPDATE) and serial data
out (DATA OUT) signals allow several options for programming larger arrays of AD8116s. The function of each bit in the
80-bit word that programs the state of the AD8116 is shown in
Figure 4. In normal operation, the DATA OUT pin of one
AD8116 is connected to the DATA IN of the next. In this way, for
example, an array of eight AD8116s would be programmed with
one 640-bit sequence. In this mode CE is logic low and the
CLK and UPDATE pins are connected in parallel.
In one alternate mode of programming, the CE pin can be used
to select one AD8116 at a time. This might be desirable when
the ability to program just one device at a time is required. In
this mode CLK, UPDATE and DATA IN are all connected in
parallel. The user then selects each AD8116 in turn (with the
CE signal) and programs it with the desired data. Larger arrays
can also be programmed by connecting each DATA IN signal to
a larger parallel bus. In this way only 80 clock cycles would be
needed to program the entire array. The logic signals are configured so that all programming can be accomplished with
synchronous logic and a continuous clock, so that no missing
cycles or delays need be generated.
REV. C
In such systems, the video signals are differential; there is a
positive and negative (or inverted) version of the signals. These
complementary signals are transmitted onto each of the two
wires of the twisted pair, yielding a first order zero commonmode voltage. At the receive end, the signals are differentially
received and converted back into a single-ended signal.
When switching these differential signals, two channels are
required in the switching element to handle the two differential
signals that make up the video channel. Thus, one differential
video channel is assigned to a pair of crosspoint channels, both
input and output. For a single AD8116, eight differential video
channels can be assigned to the 16 inputs and 16 outputs. This
will effectively form an 8 × 8 differential crosspoint switch.
Programming such a device will require that inputs and outputs
be programmed in pairs. This information can be deduced by
inspection of the programming format of the AD8116 and the
requirements of the system.
There are other analog video formats requiring more than one
analog circuit per video channel. One two-circuit format that is
more commonly being used in systems such as satellite TV,
digital cable boxes and higher quality VCRs, is called S-video or
Y/C video. This format carries the brightness (luminance or Y)
portion of the video signal on one channel and the color (chrominance or C) on a second channel.
Since S-video also uses two separate circuits for one video channel, creating a crosspoint system requires assigning one video
channel to two crosspoint channels as in the case of a differential video system. Aside from the nature of the video format,
other aspects of these two systems will be the same.
There are yet other video formats using three channels to carry
the video information. Video cameras produce RGB (red, green,
blue) directly from the image sensors. RGB is also the usual
format used by computers internally for graphics. RGB can also
be converted to Y, R-Y, B-Y format, sometimes called YUV
format. These three-circuit video standards are referred to as
component analog video.
The three-circuit video standards require three crosspoint channels per video channel to handle the switching function. In a
fashion similar to the two-circuit video formats, the inputs and
outputs are assigned in groups of three and the appropriate logic
programming is performed to route the video signals.
–11–
AD8116
Creating Larger Crosspoint Arrays
The AD8116 is a high density building block for crosspoint
arrays over 256 × 256. Various features such as output disable,
chip enable, serial data out and multiple pinouts for logic signals
are very useful for the creation of these larger arrays.
The first consideration in constructing a larger crosspoint is to
determine the minimum number of devices that are required.
The 16 × 16 architecture of the AD8116 contains 256 “points,”
which is a factor of four greater than an 8 × 8 crosspoint and a
factor of 64 greater than a 4 × 1 crosspoint. The PC board area
and power consumption savings are readily apparent when
compared to using these smaller devices.
For a nonblocking crosspoint, the number of points required is
the product of the number of inputs multiplied by the number
of outputs. Nonblocking requires that the programming of a
given input to one or more outputs does not restrict the availability of that input to be a source for any other outputs.
Using additional crosspoint devices in the design can lower the
number of outputs that have to be wire-ORed together. Figure
shows a block diagram of a system using ten AD8116s tocreate a
nonblocking 128 × 16 crosspoint that restricts the wire-ORing at
the output to only four outputs. This will prevent anenabled
output from having to drive a large number of disableddevices.
Additionally, by using the lower eight outputs fromeach of the
two Rank 2 AD8116s, a blocking 128 × 32 crosspointarray can be
realized.
There are, however, some drawbacks to this technique. The
offset voltages of the various cascaded devices will accumulate
and the bandwidth limitations of the devices will compound. In
addition, the extra devices will consume more current and take
up more board space. Once again, the overall system design
specifications will determine how to make the various trade-offs.
Thus a 32 × 32 crosspoint will require 1024 points. This number is
then divided by 256, or the number of points in one AD8116
device, to yield four in this case. This says that the minimum
number of 16 × 16 devices required for a fully programmable
32 × 32 crosspoint is four.
The 32 × 32 crosspoint requires each input driver drive two inputs
in parallel and each output be wire-ORed with one other output.
The 48 × 48 crosspoint requires driving three inputs in parallel and
having the outputs wire-ORed in groups of three. It is required of
the system programming that only one output of a wired-OR node
be active at a time.
It is not essential that crosspoint architectures be square. For
example, a 64 × 16 crosspoint array can be constructed with
four AD8116s by driving each input with a separate signal
and wire-ORing together the corresponding outputs of each
device. It can be seen, however, that by going to larger arrays
the number of disabled outputs an active output has to drive
starts to increase.
IN
0–15
OUT
AD8116
IN
OUT
16
Some nonblocking crosspoint architectures will require more
than this minimum as calculated above. Also, there are blocking
architectures that can be constructed with fewer devices than this
minimum. These systems have connectivity available on a statistical basis that is determined when designing the overall system.
The basic concept in constructing larger crosspoint arrays is to
connect inputs in parallel in a horizontal direction and to “wireOR” the outputs together in the vertical direction. The meaning
of horizontal and vertical can best be understood by looking at a
diagram. Figure 6 illustrates this concept for a 32 × 32 crosspoint
array. A 48 × 48 crosspoint is illustrated in Figure 7.
AD8116
IN 0–15
AD8116
IN 16–31
IN
16–31
OUT
AD8116
IN
OUT
16
16
16
OUT 0–15
OUT 16–31
Figure 6. 32 × 32 Crosspoint Array Using Four AD8116s
IN
AD8116
AD8116
AD8116
IN 0–15
OUT
IN
IN
OUT
OUT
16
AD8116
IN16–31
IN
AD8116
IN
OUT
AD8116
IN
OUT
OUT
16
At some point, the number of outputs that are wire-ORed becomes
too great to maintain system performance. This will vary according
to which system specifications are most important. For example, a
128 × 16 crosspoint can be created with eight AD8116s. This
design will have 128 separate inputs and have the corresponding
outputs of each device wire-ORed together in groups of eight.
–12–
AD8116
AD8116
IN 32–47
IN
IN
OUT
AD8116
IN
OUT
OUT
16
16
OUT 0–15
16
OUT 16–31
16
OUT 32–47
Figure 7. 48 × 48 Crosspoint Array Using Nine AD8116s
REV. C
AD8116
capacitor to the logical high state. If several AD8116s are used,
the pull-up resistors will be in parallel, so a larger value capacitance should be used.
RANK 1
(128:32)
8
IN 0–15
16
8
If the system requires the ability to be reset while power is still
applied, the RESET driver will have to be able to charge and
discharge this capacitance in the required time. With too many
devices in parallel, this might become more difficult; if this
occurs, the reset circuits should be broken up into smaller subsets with each controlled by a separate driver.
8
IN 16–31
16
8
8
IN 32–47
16
8
8
IN 48–63
16
RANK 2
32:16 NONBLOCKING
(32:32 BLOCKING)
8
8
NONBLOCKING
OUTPUTS
OUT 0–16
8
8
IN 64–79
8
16
8
8
ADDITIONAL
16 OUTPUTS
8
IN 80–95
16
8
IN 112–127
16
16
8
8
Types of Crosstalk
8
FOUR AD8116 OUTPUTS
WIRE-ORED TOGETHER
Figure 8. Nonblocking 128 × 16 Array (128 × 32 Blocking)
Logic Operation
There are two basic options for controlling the logic in multicrosspoint arrays. One is to serially connect the data paths
(DATA OUT to DATA IN) of all the devices and tie all the
CLK and UPDATE signals in parallel. CE can be tied low for all
the devices. A long serial sequence with the desired programming
data consisting of 80 bits times the number of AD8116 devices can
then be shifted through all the parallel devices by using the DATA
IN of the first device and the CLK. When finished clocking
in the data, UPDATE can be pulled low to program all the
device crosspoint matrices.
This technique has an advantage in that a separate CE signal is not
required for each chip, but has a disadvantage in that several chips’
data cannot be shifted in parallel. In addition, if another device is
added into the system between already existing devices, the programming sequence will have to be lengthened at some midpoint
to allow for programming of the added device.
The second programming method is to connect all the CLK and
the DATA IN pins in parallel and use the CE pins in sequence to
program each device. If a byte or 16-bit word of data is available
for providing the programming data, then multiple AD8116s can
be programmed in parallel with just 80 clock cycles. This method
can be used to speed up the programming of large arrays. Of
course, in a practical system, various combinations of these
basic methods can be used.
Power-On Reset
Most systems will want all the AD8116s to be in the reset state
(all outputs disabled) when power is applied to the system. This
ensures that two outputs that are wire-ORed together will not
fight each other at power up.
The power-on reset function can be implemented by adding a
0.1 μF capacitor from the RESET pin to ground. This will hold
this signal low after the power is applied to reset the device. An
on-chip 20 kΩ resistor from RESET to DVCC will charge the
REV. C
Many systems, such as broadcast video, that handle numerous
analog signal channels have strict requirements for keeping the
various signals from influencing any of the others in the system.
Crosstalk is the term used to describe the coupling of the signals
of other nearby channels to a given channel.
When there are many signals in close proximity in a system, as
will undoubtedly be the case in a system that uses the AD8116,
the crosstalk issues can be quite complex. A good understanding
of the nature of crosstalk and some definition of terms is required
in order to specify a system that uses one or more AD8116s.
8
IN 96–111
CROSSTALK
Crosstalk can be propagated by means of any of three methods.
These fall into the categories of electric field, magnetic field
and sharing of common impedances. This section will explain
these effects.
Every conductor can be both a radiator of electric fields and a
receiver of electric fields. The electric field crosstalk mechanism occurs when the electric field created by the transmitter
propagates across a stray capacitance and couples with the
receiver and induces a voltage. This voltage is an unwanted
crosstalk signal in any channel that receives it.
Currents flowing in conductors create magnetic fields that
circulate around the currents. These magnetic fields will then
generate voltages in any other conductors whose paths they
link. The undesired induced voltages in these other channels
are crosstalk signals. The channels that crosstalk can be said
to have a mutual inductance that couples signals from one
channel to another.
The power supplies, grounds and other signal return paths of a
multichannel system are generally shared by the various channels.
When a current from one channel flows in one of these paths, a
voltage that is developed across the impedance becomes an
input crosstalk signal for other channels that share the common
impedance.
All these sources of crosstalk are vector quantities, so the
magnitudes cannot be simply added together to obtain the total
crosstalk. In fact, there are conditions where driving additional
circuits in parallel in a given configuration can actually reduce
the crosstalk.
Areas of Crosstalk
For a practical AD8116 circuit, it is required that it be mounted
to some sort of circuit board in order to connect it to power
supplies and measurement equipment. Great care has been
taken to create a characterization board that adds minimum
crosstalk to the intrinsicdevice. This, however, raises the issue
that a system’s crosstalkis a combination of the intrinsic
crosstalk of the devices and theDJSDVJUCPBSEUPXIJDIUIFZBSF
–13–
AD8116
mounted. It is important to tryto separate these two areas of
crosstalk when attempting tominimize its effect.
Input and Output Crosstalk
The flexible programming capability of the AD8116 can be
used to diagnose whether crosstalk is occurring more on the
input side or the output side. Some examples are illustrative.
A given input channel (IN07 in the middle for this example)
can be programmed to drive OUT07. The input to IN07 is
just terminated to ground and no signal is applied.
In addition, crosstalk can occur among the input circuits to a
crosspoint and among the output circuits. Techniques will be
discussed for diagnosing which part of a system is contributing
to crosstalk.
Measuring Crosstalk
Crosstalk is measured by applying a signal to one or more channels
and measuring the relative strength of that signal on a desired
selected channel. The measurement is usually expressed as dB
down from the magnitude of the test signal. The crosstalk is
expressed by:
|XT| = 20 log10 (Asel(s)/Atest(s))
where s = jω is the Laplace transform variable, Asel(s) is the
amplitude of the crosstalk-induced signal in the selected channel and Atest(s) is the amplitude of the test signal. It can be
seen that crosstalk is a function of frequency, but not a function
of the magnitude of the test signal. In addition, the crosstalk
signal will have a phase relative to the test signal associated
with it.
A network analyzer is most commonly used to measure crosstalk
over a frequency range of interest. It can provide both magnitude
and phase information about the crosstalk signal.
All the other inputs are driven in parallel with the same test
signal (practically provided by a distribution amplifier), but
all other outputs except OUT07 are disabled. Since grounded
IN07 is programmed to drive OUT07, there should be no
signal present. Any signal that is present can be attributed to
the other 15 hostile input signals, because no other outputs
are driven. Thus, this method measures the all-hostile input
contribution to crosstalk into IN07. Of course, the method
can be used for other input channels and combinations of
hostile inputs.
For output crosstalk measurement, a single input channel is
driven (IN00 for example) and all outputs other than a given
output (IN07 in the middle) are programmed to connect to
IN00. OUT07 is programmed to connect to IN15 which is
terminated to ground. Thus OUT07 should not have a signal
present since it is listening to a quiet input. Any signal measured at the OUT07 can be attributed to the output crosstalk
of the other 15 hostile outputs. Again, this method can be
modified to measure other channels and other crosspoint
matrix combinations.
As a crosspoint system or device grows larger, the number
of theoretical crosstalk combinations and permutations can
become extremely large. For example, in the case of the 16 × 16
matrix of the AD8116, we can examine the number of crosstalk
terms that can be considered for a single channel, say IN00 input.
IN00 is programmed to connect to one of the AD8116 outputs
where the measurement can be made.
Effect of Impedances on Crosstalk
The input side crosstalk can be influenced by the output impedance of the sources that drive the inputs. The lower the impedance
of the drive source, the lower the magnitude of the crosstalk. The
dominant crosstalk mechanism on the input side is capacitive
coupling. The high impedance inputs do not have significant current flow to create magnetically induced crosstalk.
First, we can measure the crosstalk terms associated with driving a test signal into each of the other 15 inputs one at a time.
We can then measure the crosstalk terms associated with driving a
parallel test signal into all 15 other inputs taken two at a time in all
possible combinations; and then three at a time, etc., until, finally,
there is only one way to drive a test signal into all 15 other inputs.
From a circuit standpoint, the input crosstalk mechanism looks
like a capacitor coupling to a resistive load. For low frequencies
the magnitude of the crosstalk will be given by:
Each of these cases is legitimately different from the others and
might yield a unique value depending on the resolution of the
measurement system, but it is hardly practical to measure all these
terms and then to specify them. In addition, this describes the
crosstalk matrix for just one input channel. A similar crosstalk
matrix can be proposed for every other input. In addition, if the
possible combinations and permutations for connecting inputs to
the other (not used for measurement) outputs are taken into
consideration, the numbers rather quickly grow to astronomical
proportions. If a larger crosspoint array of multiple AD8116s is
constructed, the numbers grow larger still.
Obviously, some subset of all these cases must be selected to be
used as a guide for a practical measure of crosstalk. One common
term is “all hostile” crosstalk. This term means that all other system channels are driven in parallel, and the crosstalk to the selected
channel is measured. In general, this will yield the worst crosstalk
number, but this is not always the case.
|XT| = 20 log10 [(RS CM) × s]
where RS is the source resistance, CM is the mutual capacitance
between the test signal circuit and the selected circuit, and s is
the Laplace transform variable.
From the equation it can be observed that this crosstalk mechanism has a high pass nature; it can be also minimized by reducing
the coupling capacitance of the input circuits and lowering
the output impedance of the drivers. If the input is driven from
a 75 Ω terminated cable, the input crosstalk can be reduced by
buffering this signal with a low output impedance buffer.
On the output side, the crosstalk can be reduced by driving a
lighter load. Although the AD8116 is specified with excellent
differential gain and phase when driving a standard 150 Ω video
load, the crosstalk will be higher than the minimum due to the
high output currents. These currents will induce crosstalk via
the mutual inductance of the output pins and bond wires of the
AD8116.
Other useful crosstalk measurements are those created by one
nearest neighbor or by the two nearest neighbors on either side. These
crosstalk measurements will generally be higher than those of more
distant channels, so they can serve as a worst case measure for any
other one-channel or two-channel crosstalk measurements.
–14–
REV. C
AD8116
From a circuit standpoint, this output crosstalk mechanism
looks like a transformer with a mutual inductance between
the windings that drives a load resistor. For low frequencies,
the magnitude of the crosstalk is given by:
Each output also has an on-chip compensation capacitor that is
individually tied to a package pin via the signals called AGND00
through AGND15. This technique reduces crosstalk by preventing
the currents that flow in these paths from sharing a common
impedance on the IC and in the package pins. These AGNDxx
signals should all be connected directly to the ground plane.
|XT| = 20 log10 (Mxy × s/RL)
where Mxy is the mutual inductance of output x to output y and
RL is the load resistance on the measured output. This crosstalk
mechanism can be minimized by keeping the mutual inductance
low and increasing RL. The mutual inductance can be kept low
by increasing the spacing of the conductors and minimizing
their parallel length.
One way to increase the load resistance is to buffer the outputs
with a high input impedance buffer as shown in Figure . The
AD8079AR is a dual buffer that can be strapped for a gain of +2
(B grade = +2.2). This offsets the halving of the signal when
driving a standard back-terminated video cable.
The input and output signals minimize crosstalk if they are
located between ground planes on layers above and below, and
separated by ground in between. Vias should be located as close
to the IC as possible to carry the inputs and outputs to the inner
layer. The only place the input and output signals surface is at
the input termination resistors and the output series back termination resistors. These signals should also be separated, to the
extent possible, as soon as they emerge from the IC package.
The input of the buffer requires a path for bias current. This can
be provided by a 500 Ω to 5 kΩ resistor to ground. This resistor
also serves the purpose of biasing the outputs of the crosspoints
at zero volts when all the outputs are disabled.
In addition, the load resistor actually lowers the crosstalk compared to the conditions of the AD8116 outputs driving a high
impedance (greater than 10 kΩ) or driving a video load (150 Ω).
This is because the electric field crosstalk that dominates in the
high impedance case has a phase of –90 degrees, while the magnetic field crosstalk that dominates in the video load case has a
phase of +90 degrees. With a 500 Ω to 5 kΩ load, the contributions from each of these is roughly equal, and there is some
cancellation of crosstalk due to the phase differences.
10F
0.1F
+
+VS
G = +2
OUTXX
75⍀
1k⍀
75⍀
AD8079AR
AD8116
75⍀
OUTYY
75⍀
G = +2
1k⍀
–VS
OUTZZ
PCB Layout
0.1F
10F
+
AD8116
Extreme care must be exercised to minimize additional crosstalk
generated by the system circuit board(s). The areas that must be
carefully detailed are grounding, shielding, signal routing and
supply bypassing.
OUTWW
–5V
TO OTHER
AD8116 OUTPUTS
The packaging of the AD8116 is designed to help keep the
crosstalk to a minimum. Each input is separated from each
other’s input by an analog ground pin. All of these AGNDs
should be directly connected to the ground plane of the circuit
board. These ground pins provide shielding, low impedance
return paths and physical separation for the inputs. All of these
help to reduce crosstalk.
Figure 9. Buffering Wired OR Outputs with the AD8079
Each output is separated from its two neighboring outputs by
analog supply pins of either polarity. Each of these analog supply pins provides power to the output stages of only the two
adjacent outputs. These supply pins provide shielding, physical
separation and low impedance supply for the channel outputs.
Individual bypassing of each of these supply pins with a
0.01 μF chip capacitor directly to the ground plane minimizes
high frequency output crosstalk via the mechanism of sharing
common impedances.
REV. C
+5V
–15–
AD8116
OUTLINE DIMENSIONS
0.75
0.60
0.45
16.20
16.00 SQ
15.80
1.60
MAX
128
1
97
96
PIN 1
14.20
14.00 SQ
13.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.15
0.05
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
SEATING
PLANE
32
VIEW A
VIEW A
ROTATED 90° CCW
65
64
33
0.40
BSC
LEAD PITCH
0.23
0.13
Figure 10. 128-Lead Low Profile Quad Flat Package [LQFP]
(ST-128-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD8116JSTZ
1
Temperature Range
0°C to 70°C
Package Description
128-Lead Low Profile Quad Flat Package [LQFP]
Package Option
ST-128-1
Z = RoHS-Compliant Part.
REVISION HISTORY
5/16—Rev. B to Rev. C
Changes to General Description ..................................................... 1
Changes to Off Isolation, Input-Output Parameter...................... 2
Changes to Areas of Crosstalk Section .........................................13
Deleted Evaluation Board Section ................................................15
Deleted Figure 10; Renumbered Sequentially .............................16
Moved Outline Dimensions, Ordering Guide, and Revision
History ..............................................................................................16
Updated Outline Dimensions ........................................................16
Changes to Ordering Guide ...........................................................16
Deleted Figure 11 ............................................................................17
Deleted Figure 12 ............................................................................18
Deleted Figure 13 ............................................................................19
Deleted Figure 14 ............................................................................ 20
Deleted Figure 15 ............................................................................ 21
Deleted Figure 16 ............................................................................ 22
Deleted Figure 17 ............................................................................ 23
Deleted Controlling the Evaluation Board from a PC Section,
Figure 18, and Overshoot on PC Printer Ports’ Data Lines
Section .............................................................................................. 24
Deleted Figure 19 ............................................................................ 25
6/01—Rev. A to Rev. B
Correction to Pin Number in Pin Function Description ............ 6
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01071a-0-5/16(C)
±±
REV. C
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