AD8132

a FEATURES High Speed 350 MHz –3 dB Bandwidth 1200 V/ s Slew rate Resistor-Settable Gain Internal Common-Mode Feedback to Improve Gain and Phase Balance –68 dB @ 10 MHz Separate Input to Set the Common-Mode Output Voltage Low Distortion –99 dBc SFDR @ 5 MHz 800 Load Low Power 10.7 mA @ 5 V Power Supply Range +2.7 V to 5.5 V APPLICATIONS Low Power Differential ADC Driver Differential Gain and Differential Filtering Video Line Driver Differential In/Out Level-Shifting Single-Ended Input to Differential Output Driver Active Transformer Low-Cost, High-Speed Differential Amplifier AD8132 FUNCTIONAL BLOCK DIAGRAM AD8132 –IN 1 VOCM 2 V+ 3 +OUT 4 + 6 V– 5 –OUT 8 +IN 7 NC NC = NO CONNECT GENERAL DESCRIPTION The AD8132 is a low-cost differential or single-ended input to differential output amplifier with resistor-settable gain. The AD8132 is a major advancement over op amps for driving differential input ADCs or for driving signals over long lines. The AD8132 has a unique internal feedback feature that provides output gain and phase matching balanced to –68 dB at 10 MHz, suppressing harmonics, and reducing radiated EMI. Manufactured on ADI’s next generation of XFCB bipolar process, the AD8132 has a –3 dB bandwidth of 350 MHz and delivers a differential signal with –99 dBc SFDR at 5 MHz, despite its low cost. The AD8132 eliminates the need for a transformer with high-performance ADCs, preserving the low frequency and dc information. The common-mode level of the differential output is adjustable by applying a voltage on the VOCM pin, easily level-shifting the input signals for driving single supply ADCs. Fast overload recovery preserves sampling accuracy. The AD8132 can also be used as a differential driver for the transmission of high-speed signals over low-cost twisted pair or coaxial cables. The feedback network can be adjusted to boost the high-frequency components of the signal. The AD8132 can be used for either analog or digital video signals or for other highspeed data transmission. The AD8132 is capable of driving either cat3 or cat5 twisted pair or coaxial with minimal line attenuation. The AD8132 has considerable cost and performance improvements over discrete line driver solutions. Differential signal processing reduces the effects of ground noise which plagues ground referenced systems. The AD8132 can be used for differential signal processing (gain and filtering) throughout a signal chain, easily simplifying the conversion between differential and single-ended components. The AD8132 is available in both SOIC and µSOIC packages for operation over –40°C to +85°C temperatures. 6 VS = 5V G=1 VO,dm = 2V p-p RL,dm = 499 3 0 GAIN – dB –3 –6 –9 –12 1 10 100 FREQUENCY – MHz 1k Figure 1. Large Signal Frequency Response R EV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 , 5 V, = = R = 48 unless AD8132–SPECIFICATIONS ,(@ 254C99V =. ReferV,toV TPC=10andGTPC1,10R for = 499setup, Rand label 3descriptions. All otherwise noted. For G = 2, R = 200 , R = 1000 R= test S OCM L,dm F G L,dm F G specifications refer to single-ended input and differential outputs unless otherwise noted.) Parameter DIN to OUT Specifications VOUT = 2 V p-p VOUT = 2 V p-p, G = 2 VOUT = 0.2 V p-p VOUT = 0.2 V p-p, G = 2 VOUT = 0.2 V p-p VOUT = 0.2 V p-p, G = 2 VOUT = 2 V p-p 0.1%, VOUT = 2 V p-p VIN = 5 V to 0 V Step, G = 2 VOUT = 2 V p-p, 1 MHz, RL,dm = 800 Ω VOUT = 2 V p-p, 5 MHz, RL,dm = 800 Ω VOUT = 2 V p-p, 20 MHz, RL,dm = 800 Ω VOUT = 2 V p-p, 1 MHz, RL,dm = 800 Ω VOUT = 2 V p-p, 5 MHz, RL,dm = 800 Ω VOUT = 2 V p-p, 20 MHz, RL,dm = 800 Ω 20 MHz, RL,dm = 800 Ω 20 MHz, RL,dm = 800 Ω f = 0.1 MHz to 100 MHz f = 0.1 MHz to 100 MHz NTSC, G = 2, RL,dm = 150 Ω NTSC, G = 2, RL,dm = 150 Ω VOS,dm = VOUT,dm/2; VDIN+ = VDIN– = VOCM = 0 V TMIN to TMAX Variation Differential Common-Mode ∆VOUT,dm/∆VIN,cm; ∆VIN,cm = ± 1 V; Resistors Matched to 0.01% Maximum ∆VOUT; Single-Ended Output ∆VOUT,cm/∆VOUT,dm; ∆VOUT,dm = 1 V 300 350 190 360 160 90 50 1200 15 5 –96 –83 –73 –102 –98 –67 –76 40 8 1.8 0.01 0.10 ± 1.0 10 3 12 3.5 1 –7 to +6 –70 ± 3.5 7 MHz MHz MHz MHz MHz MHz V/µs ns ns dBc dBc dBc dBc dBc dBc dBc dBm nV/√Hz pA/√Hz % Degrees mV µV/°C µA MΩ MΩ pF V dB Conditions Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Large Signal Bandwidth –3 dB Small Signal Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE Second Harmonic 1000 Third Harmonic IMD IP3 Input Voltage Noise (RTI) Input Current Noise Differential Gain Error Differential Phase Error INPUT CHARACTERISTICS Offset Voltage (RTI) Input Bias Current Input Resistance Input Capacitance Input Common-Mode Voltage CMRR OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Output Balance Error VOCM to OUT Specifications DYNAMIC PERFORMANCE –3 dB Bandwidth Slew Rate DC PERFORMANCE Input Voltage Range Input Resistance Input Offset Voltage Input Bias Current VOCM CMRR Gain POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE Specifications subject to change without notice. –60 –3.6 to +3.6 70 –70 V mA dB ∆VOCM = 600 mV p-p ∆VOCM = –1 V to +1 V 210 400 ± 3.6 150 ± 1.5 0.5 –68 0.985 ± 1.35 11 1 MHz V/µs V kΩ mV µA dB V/V V mA µA/°C dB VOS,cm = VOUT,cm; VDIN+ = VDIN– = VOCM = 0 V [∆VOUT,dm/∆VOCM]; ∆VOCM = ± 1 V; Resistors Matched to 0.01% ∆VOUT,cm/∆VOCM; ∆VOCM = ± 1 V ±7 1.015 ± 5.5 13 –60 VDIN+ = VDIN– = VOCM = 0 V TMIN to TMAX Variation ∆VOUT,dm/∆VS; ∆VS = ± 1 V 12 16 –70 –40 +85 °C –2– REV. 0 AD8132–SPECIFICATIONS Parameter DIN to OUT Specifications AD8132 (@ 25 C, VS = 5 V, VOCM = 2.5 V, G = 1, RL,dm = 499 , RF = RG = 348 unless otherwise noted. For G = 2, RL,dm = 200 , RF = 1000 , RG = 499 . Refer to TPC 1 and TPC 10 for test setup and label descriptions. All specifications refer to single-ended input and differential outputs unless otherwise noted.) Conditions Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Large Signal Bandwidth –3 dB Small Signal Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE Second Harmonic VOUT = 2 V p-p VOUT = 2 V p-p, G = 2 VOUT = 0.2 V p-p VOUT = 0.2 V p-p, G = 2 VOUT = 0.2 V p-p VOUT = 0.2 V p-p, G = 2 VOUT = 2 V p-p 0.1%, VOUT = 2 V p-p VIN = 2.5 V to 0 V Step, G = 2 VOUT = 2 V p-p, 1 MHz, RL,dm = 800 Ω VOUT = 2 V p-p, 5 MHz, RL,dm = 800 Ω VOUT = 2 V p-p, 20 MHz, RL,dm = 800 Ω VOUT = 2 V p-p, 1 MHz, RL,dm = 800 Ω VOUT = 2 V p-p, 5 MHz, RL,dm = 800 Ω VOUT = 2 V p-p, 20 MHz, RL,dm = 800 Ω 20 MHz, RL,dm = 800 Ω 20 MHz, RL,dm = 800 Ω f = 0.1 MHz to 100 MHz f = 0.1 MHz to 100 MHz NTSC, G = 2, RL,dm = 150 Ω NTSC, G = 2, RL,dm = 150 Ω VOS,dm = VOUT,dm/2; VDIN+ = VDIN– = VOCM = 2.5 V TMIN to TMAX Variation Differential Common-Mode ∆VOUT,dm/∆VIN,cm; ∆VIN,cm = ± 1 V; Resistors Matched to 0.01% Maximum ∆VOUT; Single-Ended Output ∆VOUT,cm/∆VOUT,dm; ∆VOUT,dm = 1 V 250 800 300 180 360 155 65 50 1000 20 5 –97 –100 –74 –100 –99 –67 –76 40 8 1.8 0.025 0.15 ± 1.0 6 3 10 3 1 –1 to +4 –70 ± 3.5 7 MHz MHz MHz MHz MHz MHz V/µs ns ns dBc dBc dBc dBc dBc dBc dBc dBm nV/√Hz pA/√Hz % Degree mV µV/°C µA MΩ MΩ pF V dB Third Harmonic IMD IP3 Input Voltage Noise (RTI) Input Current Noise Differential Gain Error Differential Phase Error INPUT CHARACTERISTICS Offset Voltage (RTI) Input Bias Current Input Resistance Input Capacitance Input Common-Mode Voltage CMRR OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Output Balance Error VOCM to OUT Specifications DYNAMIC PERFORMANCE –3 dB Bandwidth Slew Rate DC PERFORMANCE Input Voltage Range Input Resistance Input Offset Voltage Input Bias Current VOCM CMRR Gain POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE Specifications subject to change without notice. –60 1 to 3.7 50 –68 V mA dB ∆VOCM = 600 mV p-p ∆VOCM = 1.5 V to 3.5 V 210 340 1 to 3.7 130 ±5 0.5 –66 0.985 2.7 9.4 1 MHz V/µs V kΩ mV µA dB V/V V mA µA/°C dB VOS,cm = VOUT,cm; VDIN+ = VDIN– = VOCM = 2.5 V [∆VOUT,dm/∆VOCM]; ∆VOCM = 2.5 ± 1 V; Resistors Matched to 0.01% ∆VOUT,cm/∆VOCM; ∆VOCM = 2.5 ± 1 V ± 11 1.015 11 12 –60 VDIN+ = VDIN– = VOCM = 2.5 V TMIN to TMAX Variation ∆VOUT,dm/∆VS; ∆VS = ± 1 V 10.7 10 –70 –40 +85 °C REV. 0 –3– (@ 25 C, VS = 3 V, VOCM = 1.5 V, G = 1, RL,dm = 499 , RF = RG = 348 unless otherwise noted. For G = 2, RL,dm = 200 , RF = 1000 , RG = 499 . Refer to TPC 1 and TPC 10 for test setup and label descriptions. All specifications refer to single-ended input and differential outputs unless otherwise noted.) Parameter DIN to OUT Specifications VOUT = 1 V p-p VOUT = 1 V p-p, G = 2 VOUT = 0.2 V p-p VOUT = 0.2 V p-p, G = 2 VOUT = 0.2 V p-p VOUT = 0.2 V p-p, G = 2 VOUT = 1 V p-p, 1 MHz, RL,dm = 800 Ω VOUT = 1 V p-p, 5 MHz, RL,dm = 800 Ω VOUT = 1 V p-p, 20 MHz, RL,dm = 800 Ω VOUT = 1 V p-p, 1 MHz, RL,dm = 800 Ω VOUT = 1 V p-p, 5 MHz, RL,dm = 800 Ω VOUT = 1 V p-p, 20 MHz, RL,dm = 800 Ω VOS,dm = VOUT,dm/2; VDIN+ = VDIN– = VOCM = 1.5 V ∆VOUT,dm/∆VIN,cm; ∆VIN,cm = ± 0.5 V; Resistors Matched to 0.01% 350 165 350 150 45 50 –100 –94 –77 –90 –85 –66 ± 10 3 –60 MHz MHz MHz MHz MHz MHz dBc dBc dBc dBc dBc dBc mV µA dB Conditions Min Typ Max Unit AD8132–SPECIFICATIONS DYNAMIC PERFORMANCE –3 dB Large Signal Bandwidth –3 dB Small Signal Bandwidth Bandwidth for 0.1 dB Flatness NOISE/HARMONIC PERFORMANCE Second Harmonic Third Harmonic INPUT CHARACTERISTICS Offset Voltage (RTI) Input Bias Current CMRR VOCM to OUT Specifications DC PERFORMANCE Input Offset Voltage Gain POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE Specifications subject to change without notice. VOS,cm = VOUT,cm; VDIN+ = VDIN– = VOCM = 1.5 V ∆VOUT,cm/∆VOCM; ∆VOCM = ± 0.5 V 2.7 VDIN+ = VDIN– = VOCM = 0 V ∆VOUT,dm/∆VS; ∆VS = ± 0.5 V –40 ±7 1 11 7.25 –70 mV V/V V mA dB +85 °C –4– REV. 0 AD8132 ABSOLUTE MAXIMUM RATINGS 1, 2 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5.5 V VOCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 250 mW Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . 300°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above listed in the operational section of this specification is not implied. Exposure to Absolute Maximum Ratings for any extended periods may affect device reliability. 2 Thermal resistance measured on SEMI standard 4-layer board. 8-Lead SOIC: θJA = 121°C/W 8-Lead µSOIC: θJA = 142°C/W PIN FUNCTION DESCRIPTIONS Pin No. Name 1 2 –IN VOCM Function 3 4 5 6 7 8 Negative Input. Voltage applied to this pin sets the commonmode output voltage with a ratio of 1:1. For example, 1 V dc on VOCM will set the dc bias level on +OUT and –OUT to 1 V. V+ Positive Supply Voltage. +OUT Positive Output. Note: the voltage at –DIN is inverted at +OUT. –OUT Negative Output. Note: the voltage at +DIN is inverted at –OUT. V– Negative Supply Voltage. NC No Connect. +IN Positive Input. PIN CONFIGURATION AD8132 –IN 1 8 +IN 7 NC + 6 V– 5 –OUT VOCM 2 V+ 3 2.0 MAXIMUM POWER DISSIPATION – Watts 1.5 8-LEAD SOIC PACKAGE TJ = 150 C 1.0 8-LEAD microSOIC 0.5 +OUT 4 NC = NO CONNECT 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE – C 80 90 Figure 2. Plot of Maximum Power Dissipation vs. Temperature ORDERING GUIDE Model AD8132AR AD8132AR-REEL1 AD8132AR-REEL72 AD8132ARM AD8132ARM-REEL3 AD8132ARM-REEL72 AD8132-EVAL NOTES 1 13" Reels of 2500 each. 2 7" Reels of 1000 each. 3 13" Reels of 3000 each. Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 8-Lead SOIC 13" Tape and Reel 7" Tape and Reel 8-Lead µSOIC 13" Tape and Reel 7" Tape and Reel Evaluation Board Package Option SO-8 SM-8 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8132 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 –5– AD8132–Typical Performance Characteristics 2 CF 348 0.5 1 0 GAIN – dB VS = 3V 0.4 VS = 5V 0.3 0.2 GAIN – dB VS AS SHOWN G=1 VO,dm = 0.2V p-p RL,dm = 499 VS = 3V VS = 5V 348 49.9 0.1 F 499 –1 –2 –3 VS AS SHOWN G=1 VO,dm = 0.2V p-p RL,dm = 499 1 10 VS = 5V 0.1 0.0 –0.1 –0.2 –0.3 –0.4 –0.5 VS = 5V 24.9 348 348 CF –4 –5 100 1k 1 10 100 1k FREQUENCY – MHz FREQUENCY – MHz TPC 1. Basic Test Circuit, G = 1 TPC 2. Small Signal Frequency Response TPC 3. 0.1 dB Flatness vs. Frequency; CF = 0 pF 0.2 0.1 0.0 GAIN – dB GAIN – dB 3 VS = 3V VS = 5V 2 1 VS = 3V VS = 5V 2 VS = 5V 1 0 VS = 3V VS = 5V VS = 5V GAIN – dB –0.1 –0.2 –0.3 –0.4 –0.5 VS = 5V 0 –1 –2 –3 –4 VS AS SHOWN G=1 VO,dm = 2V p-p FOR VS = 5V, 5V VO,dm = 1V p-p FOR VS = 3V RL,dm = 499 1 10 100 1k VS = 3V –1 –2 –3 –4 –5 VS = 3V VS AS SHOWN G=1 VO,dm = 0.2V p-p RL,dm = 499 1 10 100 1k VS AS SHOWN G=1 VO,dm = 2V p-p FOR VS = 5V, 5V VO,dm = 1V p-p FOR VS = 3V RL,dm = 499 –5 1 10 100 1k FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz TPC 4. 0.1 dB Flatness vs. Frequency; CF = 0.5 pF TPC 5. Large Signal Frequency Response; CF = 0 pF TPC 6. Large Signal Frequency Response; CF = 0.5 pF 3 2 1 +85 C +25 C 3 2 1 GAIN – dB 100 RF = 499 RF = 348 10 GAIN – dB 0 –1 –2 –3 –4 VS = 5V G=1 VO,dm = 2V p-p RL,dm = 499 RF AS SHOWN 1 10 100 1k RF = 249 –40 C –1 –2 –3 –4 –5 1 VS = 5V G=1 VO,dm = 2V p-p RL,dm = 499 TEMPERATURE AS SHOWN 10 100 1k IMPEDANCE – 0 1 VS = 5V VS = 0.1 1 10 FREQUENCY – MHz 100 5V –5 FREQUENCY – MHz FREQUENCY – MHz TPC 7. Large Signal Response vs. Temperature TPC 8. Large Signal Frequency Response vs. RF TPC 9. Closed-Loop Single-Ended ZOUT vs. Frequency; G = 1 –6– REV. 0 AD8132 7 6.1 6.0 6 1000 499 49.9 0.1 F 200 5 GAIN – dB VS = GAIN – dB 5V, +5V 5.9 4 VS = 3V 3 VS AS SHOWN G=2 VO,dm = 0.2V p-p RL,dm = 200 1 10 100 1k 5.8 24.9 499 1000 5.7 VS = 3V, 5V, 5V G=2 VO,dm = 0.2V p-p RL,dm = 200 1 10 100 1k 2 5.6 1 5.5 FREQUENCY – MHz FREQUENCY – MHz TPC 10. Basic Test Circuit, G = 2 TPC 11. Small Signal Frequency Response TPC 12. 0.1 dB Flatness vs. Frequency 7 6 VS = 3V 5 VS = 5V, 5V 7 RF = 1.5k 6 RF 5 GAIN – dB RF = 1.0k 499 RF = 499 4 VS = 5V G=2 VO,dm = 0.2V p-p RL,dm = 200 RF AS SHOWN 1 10 100 1k 49.9 0.1 F 200 GAIN – dB 4 3 2 VS AS SHOWN G=2 VO,dm = 2V p-p FOR VS = 5V, 5V VO,dm = 1V p-p FOR VS = 3V RL,dm = 200 1 10 100 1k 3 24.9 499 RF 2 1 1 FREQUENCY – MHz FREQUENCY – MHz TPC 13. Large Signal Frequency Response TPC 14. Small Signal Frequency Response vs. RF TPC 15. Test Circuit for Various Gains 25 20 G = 10, RF = 4.99k RG 49.9 0.1 F RL 24.9 RG RF RF RL –25 –30 RTI BALANCE ERROR – dB 15 G = 5, RF = 2.49k GAIN – dB –35 –40 –45 –50 –55 –60 VS = 5V GAIN AS SHOWN VOUT,dm = 2V p-p VOUT,cm/ VOUT,dm 10 G = 2, RF = 1k 5 0 –5 –10 –15 1 G = 1, RF = 499 VS = 5V VO, dm = 2V p-p RL, dm = 200 RG = 499 10 100 1k G=1 G=2 –65 –70 –75 1 10 100 1k G = 1: RF = RG = 348 , RL = 249 (RL,dm = 498 ) G = 2: RF = 1000 , RG = 499 , RL = 100 (RL,dm = 200 ) FREQUENCY – MHz FREQUENCY – MHz TPC 16. Large Signal Response for Various Gains TPC 17. Test Circuit for Output Balance TPC 18. RTI Output Balance Error vs. Frequency REV. 0 –7– AD8132 348 2:1 TRANSFORMER 348 LPF 49.9 0.1 F 300 HPF ZIN = 50 24.9 348 348 300 TPC 19. Harmonic Distortion Test Circuit, G = 1, RL,dm = 800 Ω –40 –50 DISTORTION – dBc –30 –40 HD3 (VS = 5V) –50 DISTORTION – dBc RL,dm = 800 VOUT,dm = 1V p-p HD3 (VS = 3V) DISTORTION – dBc RL,dm = 800 –40 VOUT,dm = 2V p-p –50 –60 –70 –80 –90 HD2 (VS = 5V) VS = 3V RL,dm = 800 HD3 (F = 20MHz) –60 –70 –80 –60 –70 –80 –90 –100 HD2 (F = 20MHz) HD2 (VS = 3V) HD3 (VS = HD2 (VS = 5V) 5V) HD2 (VS = 5V) –90 –100 HD3 (VS = 5V) –110 0 10 20 30 40 50 60 70 –100 –110 0 10 20 30 40 50 60 70 HD3 (F = 5MHz) HD2 (F = 5MHz) FREQUENCY – MHz FREQUENCY – MHz –110 0.25 0.50 0.75 1.00 1.25 1.50 1.75 DIFFERENTIAL OUTPUT VOLTAGE – V p-p TPC 20. Harmonic Distortion vs. Frequency, G = 1 TPC 21. Harmonic Distortion vs. Frequency, G = 1 TPC 22. Harmonic Distortion vs. Differential Output Voltage, G = 1 –40 –50 VS = 5V RL,dm = 800 HD3 (F = 20MHz) –40 –50 VS = 5V RL,dm = 800 HD2 (F = 20MHz) HD3 (F = 20MHz) –50 –60 DISTORTION – dBc VS = 3V VO,dm = 1V p-p HD3 (F = 20MHz) DISTORTION – dBc DISTORTION – dBc –60 –70 –80 –90 –100 –110 –60 –70 –80 –90 –100 –70 HD2 (F = 20MHz) –80 HD2 (F = 20MHz) HD2 (F = 5MHz) HD3 (F = 5MHz) HD2 (F = 5MHz) –90 HD3 (F = 5MHz) –100 HD2 (F = 5MHz) HD3 (F = 5MHz) 0 1 2 3 4 5 6 DIFFERENTIAL OUTPUT VOLTAGE – V p-p 0 1 2 3 4 DIFFERENTIAL OUTPUT VOLTAGE – V p-p –110 –110 200 300 400 500 600 700 RLOAD – 800 900 1000 TPC 23. Harmonic Distortion vs. Differential Output Voltage, G = 1 TPC 24. Harmonic Distortion vs. Differential Output Voltage, G = 1 TPC 25. Harmonic Distortion vs. RLOAD, G = 1 –8– REV. 0 AD8132 –50 –60 DISTORTION – dBc –50 VS = 5V VOUT,dm = 2V p-p HD3 (F = 20MHz) DISTORTION – dBc –60 VS = 5V VOUT,dm = 2V p-p HD3 (F = 20MHz) –70 –70 HD2 (F = 20MHz) HD2 (F = 5MHz) –90 –80 HD2 (F = 20MHz) HD2 (F = 5MHz) –80 –90 HD3 (F = 5MHz) –100 –100 HD3 (F = 5MHz) –110 200 300 400 500 600 700 800 900 1000 RLOAD – –110 200 300 400 500 600 700 RLOAD – 800 900 1000 TPC 26. Harmonic Distortion vs. RLOAD, G = 1 TPC 27. Harmonic Distortion vs. RLOAD, G = 1 1000 2:1 TRANSFORMER 499 LPF 49.9 0.1 F 300 HPF ZIN = 50 24.9 499 1000 300 TPC 28. Harmonic Distortion Test Circuit, G = 2, RL,dm = 800 Ω –40 –50 RL,dm = 800 VOUT,dm = 1V p-p HD3 (VS = 3V) –20 –30 –40 RL,dm = 800 VOUT,dm = 4V p-p HD2 (VS = 5V) –40 HD3 (VS = 5V) –50 –60 VS = 5V RL,dm = 800 HD3 (F = 20MHz) DISTORTION – dBc DISTORTION – dBc DISTORTION – dBc –60 –70 –80 –90 –100 –50 –60 –70 –80 –90 –100 HD3 (VS = 5V) –70 HD2 (F = 20MHz) –80 –90 HD2 (F = 5MHz) –100 HD2 (VS = 5V) HD2 (VS = 3V) HD3 (VS = 5V) HD2 (VS = 5V) –110 HD3 (F = 5MHz) –120 –110 0 10 20 30 40 50 FREQUENCY – MHz 60 70 0 10 20 30 40 50 60 FREQUENCY – MHz 70 80 0 2 1 3 4 DIFFERENTIAL OUTPUT VOLTAGE – V p-p TPC 29. Harmonic Distortion vs. Frequency, G = 2 TPC 30. Harmonic Distortion vs. Frequency, G = 2 TPC 31. Harmonic Distortion vs. Differential Output Voltage, G = 2 REV. 0 –9– AD8132 –40 –50 DISTORTION – dBc –50 VS = 5V RL,dm = 800 HD3 (F = 20MHz) –60 DISTORTION – dBc –50 VS = 5V VOUT,dm = 2V p-p HD3 (F = 20MHz) –60 VS = 5V VOUT,dm = 2V p-p HD3 (F = 20MHz) DISTORTION – dBc –60 –70 –80 –90 HD2 (F = 20MHz) HD2 (F = 20MHz) –70 HD2 (F = 20MHz) –80 HD2 (F = 5MHz) –70 –80 HD2 (F = 5MHz) –90 –90 HD3 (F = 5MHz) –100 –110 HD2 (F = 5MHz) –100 HD3 (F = 5MHz) –110 200 300 400 500 600 700 800 900 1000 RLOAD – –100 HD3 (F = 5MHz) –110 200 300 400 500 600 700 800 900 1000 RLOAD – 0 4 1 2 3 5 6 DIFFERENTIAL OUTPUT VOLTAGE – V p-p TPC 32. Harmonic Distortion vs. Differential Output Voltage, G = 2 TPC 33. Harmonic Distortion vs. RLOAD, G = 2 TPC 34. Harmonic Distortion vs. RLOAD, G = 2 10 0 –10 POUT – dBm (Re:50 ) 45 fC = 20MHz VS = 5V RL,dm = 800 VS = 5V, 5V RL,dm = 800 VS = 5V, 5V, 3V –20 –30 –40 –50 –60 –70 –80 –90 19.5 INTERCEPT – dBm (Re:50 ) 40 35 30 25 20 40mV 15 20 FREQUENCY – MHz 20.5 5ns 0 10 20 30 40 50 FREQUENCY – MHz 60 70 TPC 35. Intermodulation Distortion, G = 1 TPC 36. Third Order Intercept vs. Frequency, G = 1 TPC 37. Small Signal Transient Response, G = 1 CF = 0pF VS = 3V VOUT,dm = 1.5V p-p CF = 0pF VS = 5V VOUT,dm = 2V p-p VS = 5V VOUT,dm = 2V p-p CF = 0pF CF = 0.5pF CF = 0.5pF CF = 0.5pF 300mV 5ns 400mV 5ns 400mV 5ns TPC 38. Large Signal Transient Response, G = 1 TPC 39. Large Signal Transient Response, G = 1 TPC 40. Large Signal Transient Response, G = 1 –10– REV. 0 AD8132 VS = 5, 5, 3V VS = 3V VOUT,dm VOUT– VOUT+ V+DIN 1V 5ns 40mV 5ns 300mV 5ns TPC 41. Large Signal Transient Response, G = 1 TPC 42. Small Signal Transient Response, G = 2 TPC 43. Large Signal Transient Response, G = 2 VS = 5, 5V VS = 5V VOUT,dm VOUT– VS = 5V G=1 VO,dm = 2V p-p RL,dm = 499 VOUT+ V+DIN 400mV 5ns 1V 5ns 0.1%/DIV 2mV 0 5 10 15 20 25 5ns/DIV 5ns 30 35 40 TPC 44. Large Signal Transient Response, G = 2 TPC 45. Large Signal Transient Response, G = 2 TPC 46. 0.1% Settling Time CL = 0pF CL = 5pF 0 –10 –20 VOUT,dm VS –PSRR 348 348 49.9 0.1 F 348 24.9 348 400mV 5ns PSRR – dB 24.9 CL 24.9 453 CL = 20pF +PSRR (VS = –30 –PSRR (V = S –40 –50 –60 –70 –80 –90 0.1 1 5V, 5V) 5V) +PSRR 10 100 FREQUENCY – MHz 1000 TPC 47. Test Circuit for Cap Load Drive TPC 48. Large Signal Transient Response for Various Capacitor Loads TPC 49. PSRR vs. Frequency REV. 0 –11– AD8132 –20 –30 348 –40 348 249 VOUT,dm 49.9 348 348 NOTE: RESISTORS MATCHED TO 0.01%. –80 1 10 100 FREQUENCY – MHz 1000 –15 1 10 100 FREQUENCY – MHz 1000 249 CMRR – dB VS = 5V VIN,cm = 2V p-p 6 3 0 VOUT,cm VOCM VS = 5V VOCM = 600mV p-p VOUT,cm VIN,cm dB –3 –6 VOCM = 2V p-p –50 –60 VOUT, cm –9 –70 VOUT,dm VIN,cm –12 TPC 50. CMRR Test Circuit TPC 51. CMRR vs. Frequency TPC 52. VOCM Gain Response –10 VS = 5V VOCM = –1V TO +1V 1000 INPUT VOLTAGE NOISE – nV/ Hz –20 –30 VOUT,dm VOCM VOCM = 600mV p-p VOCM CMRR – dB VOUT,cm VOCM = 2V p-p –40 –50 –60 –70 100 8nV/ Hz 10 400mV 5ns –80 1 10 100 FREQUENCY – MHz 1000 1 10 100 1k 10k 100k 1M FREQUENCY – Hz 10M 100M TPC 53. VOCM Transient Response TPC 54. VOCM CMRR vs. Frequency TPC 55. Input Voltage Noise vs. Frequency 1000 INPUT CURRENT NOISE – pA/ Hz 15 VOUT,dm (0.5V/DIV) VIN,sm (1V/DIV) 100 SUPPLY CURRENT – mA 13 VS = 11 VS = 5V 9 5V 10 1.8pA/ Hz VS = 5V VIN = 2.5V STEP G=2 RF = 1k RL,dm = 200 V/DIV AS SHOWN 7 5ns 1 10 100 1k 10k 100k 1M FREQUENCY – Hz 10M 100M 5 –50 –30 –10 10 30 50 TEMPERATURE – C 70 90 TPC 56. Input Current Noise vs. Frequency TPC 57. Overdrive Recovery TPC 58. Quiescent Current vs. Temperature –12– REV. 0 AD8132 0 DIFFERENTIAL OUTPUT OFFSET – mV –0.5 VS = 5V –1.0 VS = –1.5 5V –2.0 –2.5 –40 –20 0 20 40 60 TEMPERATURE – C 80 100 TPC 59. Differential Offset Voltage vs. Temperature OPERATIONAL DESCRIPTION Definition of Terms CF RF RG +IN –OUT Table I indicates the gain from any type of input to either type of output. Table I. Differential and Common-Mode Gains Input RL, dm +OUT VOUT, dm VOUT,dm RF/RG 0 0 VOUT,cm 0 (By Design) 0 (By Design) 1 (By Design) +DIN VOCM –DIN AD8132 RG –IN RF CF VIN,dm VIN,cm VOCM Figure 3. Circuit Definitions Differential voltage refers to the difference between two node voltages. For example, the output differential voltage (or equivalently output differential-mode voltage) is defined as: VOUT,dm = (V+OUT – V–OUT) V+OUT and V–OUT refer to the voltages at the +OUT and –OUT terminals with respect to a common reference. Common-mode voltage refers to the average of two node voltages. The output common-mode voltage is defined as: VOUT,cm = (V+OUT + V–OUT)/2 Basic Circuit Operation The differential output (VOUT,dm) is equal to the differential input voltage (VIN,dm) times RF/RG. In this case, it does not matter if both differential inputs are driven, or only one output is driven and the other is tied to a reference voltage, like ground. As can be seen from the two zero entries in the first column, neither of the common-mode inputs has any effect on this gain. The gain from VIN,dm to VOUT,cm is 0 and to first order does not depend on the ratio matching of the feedback networks. The common-mode feedback loop within the AD8132 provides a corrective action to keep this gain term minimized. The term “balance error” describes the degree to which this gain term differs from zero. The gain from VIN,cm to VOUT,dm does directly depend on the matching of the feedback networks. The analogous term for this transfer function, which is used in conventional op amps, is “common-mode rejection ratio” or CMRR. Thus, if it is desirable to have a high CMRR, the feedback ratios must be well matched. The gain from VIN,cm to VOUT,cm is also ideally 0, and is firstorder independent of the feedback ratio matching. As in the case of VIN,dm to VOUT,cm, the common-mode feedback loop keeps this term minimized. The gain from VOCM to VOUT,dm is ideally 0 only when the feedback ratios are matched. The amount of differential output signal that will be created by varying VOCM is related to the degree of mismatch in the feedback networks. VOCM controls the output common-mode voltage VOUT,cm with a unity-gain transfer function. With equal-ratio feedback networks (as assumed above), its effect on each output will be the same, which is another way to say that the gain from VOCM to VOUT,dm is zero. If not driven, the output common-mode will be at midsupplies. It is recommended that a 0.1 µF bypass capacitor be connected to VOCM. –13– One of the more useful and easy to understand ways to use the AD8132 is to provide two equal-ratio feedback networks. To match the effect of parasitics, these networks should actually be comprised of two equal-value feedback resistors, RF and two equal-value gain resistors, RG. This circuit is diagrammed in Figure 3. Like a conventional op amp, the AD8132 has two differential inputs that can be driven with both a differential-mode input voltage, VIN,dm, and a common-mode input voltage, VIN,cm. There is another input, VOCM, which is not present on conventional op amps, but provides another input to consider on the AD8132. It is totally separate from the above inputs. There are two complementary outputs whose response can be defined by a differential-mode output, VOUT,dm and a commonmode output, VOUT,cm. REV. 0 AD8132 When unequal feedback ratios are used, the two gains associated with VOUT,dm become nonzero. This significantly complicates the mathematical analysis along with any intuitive understanding of how the part operates. Some of these configurations will be in another section. THEORY OF OPERATION The feedback factor β1 is for the side that is driven, while the feedback factor β2 is for the side that is tied to a reference voltage, (ground for now). Note also that each feedback factor can vary anywhere between 0 and 1. A single-ended-to-differential gain equation can be derived which is true for all values of β1 and β2: G = 2 × (1–β1)/(β1 + β2) This expression is not very intuitive, but some further examples can provide better understanding of its implications. One observation that can be made right away is that a tolerance error in β1 does not have the same effect on gain as the same tolerance error in β2. Resistorless Differential Amplifier (High Input Impedance Inverting Amplifier) The AD8132 differs from conventional op amps by the external presence of an additional input and output. The additional input, VOCM, controls the output common-mode voltage. The additional output is the analog complement of the single output of a conventional op amp. For its operation, the AD8132 makes use of two feedback loops as compared to the single loop of conventional op amps. While this provides significant freedom to create various novel circuits, basic op amp theory can still be used to analyze the operation. One of the feedback loops controls the output common-mode voltage, VOUT,cm. Its input is VOCM (Pin 2) and the output is the common-mode, or average voltage, of the two differential outputs (+OUT and –OUT). The gain of this circuit is internally set to unity. When the AD8132 is operating in its linear region, this establishes one of the operational constraints: VOUT,cm = VOCM. The second feedback loop controls the differential operation. Similar to an op amp, the gain and gain-shaping of the transfer function is controllable by adding passive feedback networks. However, only one feedback network is required to “close the loop” and fully constrain the operation. But depending on the function desired, two feedback networks can be used. This is possible as a result of having two outputs that are each inverted with respect to the differential inputs. General Usage of the AD8132 The simplest closed-loop circuit that can be made does not require any resistors and is shown in Figure 7. In this circuit, β1 is equal to zero, and β2 is equal to one. The gain is equal to two. A more intuitive means to figure the gain is by simple inspection. +OUT is connected to –IN, whose voltage is equal to the voltage at +IN under equilibrium conditions. Thus, +VOUT is equal to VIN, and there is unity gain in this path. Since –OUT has to swing in the opposite direction from +OUT due to the common-mode constraint, its effect will double the output signal and produce a gain of two. One useful function that this circuit provides is a high inputimpedance inverter. If +OUT is ignored, there is a unity-gain, high-input-impedance amplifier formed from +IN to –OUT. Most traditional op amp inverters have relatively low input impedances, unless they are buffered with another amplifier. VOCM has been assumed to be at midsupply. Since there is still the constraint from the above discussion that +VOUT must equal VIN, changing the VOCM voltage will not change +VOUT (= VIN). Therefore, all of the effect of changing VOCM must show up at –OUT. For example, if VOCM is raised by 1 V, then –VOUT must go up by 2 V. This makes VOUT,cm also go up by 1 V, since it is defined as the average of the two differential output voltages. This means that the gain from VOCM to the differential output is two. Other 2 = 1 Circuits Several assumptions are made here for a first-order analysis, which are the typical assumptions used for the analysis of op amps: • The input impedances are arbitrarily large and their loading effect can be ignored. • The input bias currents are sufficiently small so they can be neglected. • The output impedances are arbitrarily low. • The open-loop gain is arbitrarily large, which drives the amplifier to a state where the input differential voltage is effectively zero. • Offset voltages are assumed to be zero. While it is possible to operate the AD8132 with a purely differential input, many of its applications call for a circuit that has a single-ended input with a differential output. For a single-ended-to-differential circuit, the RG of the undriven input will be tied to a reference voltage. For now this is ground, and other conditions will be discussed later. Also, the voltage at VOCM, and hence VOUT,cm will be assumed to be ground for now. Figure 4 shows a generalized schematic of such a circuit using an AD8132 with two feedback paths. For each feedback network, a feedback factor can be defined, which is the fraction of the output signal that is fed back to the opposite-sign input. These terms are: β1 = RG1/(RG1+ RF1) β2 = RG2/(RG2 + RF2) The above simple configuration with β2 = 1 and its gain-of-two is the highest gain circuit that can be made under this condition. Since β1 was equal to zero, only higher β1 values are possible. All of these circuits with higher values of β1 will have gains lower than two. However, circuits with β1 equal to one are not practical, because they have no effective input, and result in a gain of 0. To increase β1 from zero, it is necessary to add two resistors in a feedback network. A generalized circuit that has β1 with a value higher than zero is shown in Figure 6. A couple of different convenient gains that can be created are a gain of 1, when β1 is equal to 1/3, and a gain of 0.5 when β1 equals 0.6. In all of these circuits with β2 equal to 1, VOCM serves as the reference voltage from which to measure the input voltage and the individual output voltages. In general, when VOCM is varied in these circuits, a differential output signal will be generated in addition to VOUT,cm changing the same amount as the voltage change of VOCM. –14– REV. 0 AD8132 Varying 2 While the circuit above sets β2 to 1, another class of simple circuits can be made that set β2 equal to zero. This means that there is no feedback from +OUT to –IN. This class of circuits is very similar to a conventional inverting op amp. However, the AD8132 circuits have an additional output and common-mode input which can be analyzed separately (see Figure 8). With –IN connected to ground, +IN becomes a “virtual ground” in the same sense that the term is used in conventional op amps. Both inputs must maintain the same voltage for equilibrium operation, so if one is set to ground, the other will be driven to ground. The input impedance can also be seen to be equal to RG, just as in a conventional op amp. In this case, however, the positive input and negative output are used for the feedback network. Since a conventional op amp does not have a negative output, only its inverting input can be used for the feedback network. The AD8132 is symmetrical, so the feedback network on either side can be used to produce the same results. Since +IN is a summing junction, by analogy to conventional op amps, the gain from VIN to –OUT will be –RF/RG. This will hold true regardless of the voltage on VOCM. And since +OUT will move the same amount in the opposite direction from –OUT, the overall gain will be –2 (RF/RG). VOCM still governs VOUT,cm, so +OUT must be the only output that moves when VOCM is varied. Since VOUT,cm is the average of the two outputs, +OUT must move twice as fast and in the same direction as VOCM to create the proper VOUT,cm. Therefore, the gain from VOCM to +OUT must be two. In these circuits with β2 equal to zero, the gain can theoretically be set to any value from close to zero to infinity, just as it can with a conventional op amp in the inverting mode. However, practical real-world limitations and parasitics will limit the range of acceptable gains to more modest values. 1=0 To compute the total output referred noise for the circuit of Figure 3, consideration must also be given to the contribution of the resistors RF and RG. Refer to Table II for estimated output noise voltage densities at various closed-loop gains. Table II. Recommended Resistor Values and Noise Performance for Specific Gains Gain 1 2 5 10 RG RF ()() 499 499 499 499 499 1.0 k 2.49 k 4.99 k Bandwidth Output Noise Output Noise –3 dB AD8132 Only AD8132 + RG, RF 360 MHz 160 MHz 65 MHz 20 MHz 16 nV/√Hz 24.1 nV/√Hz 48.4 nV/√Hz 88.9 nV/√Hz 17 nV/√Hz 26.1 nV/√Hz 53.3 nV/√Hz 98.6 nV/√Hz Calculating an Application Circuit’s Input Impedance The effective input impedance of a circuit such as that in Figure 3, at +DIN and –DIN, will depend on whether the amplifier is being driven by a single-ended or differential signal source. For balanced differential input signals, the input impedance (RIN,dm) between the inputs (+DIN and –DIN) is simply: RIN,dm = 2 × RG In the case of a single-ended input signal (for example if –DIN is grounded and the input signal is applied to +DIN), the input impedance becomes: RIN , dm   RG =  RF 1 −  2 × RG + RF  ( )        There is yet another class of circuits where there is no feedback from –OUT to +IN. This is the case where β1 = 0. The resistorless differential amplifier described above meets this condition, but it was presented only with the condition that β2 = 1. Recall that this circuit had a gain equal to two. If β2 is decreased in this circuit from unity, a smaller part of +VOUT will be fed back to –IN and the gain will increase. See Figure 5. This circuit is very similar to a noninverting op amp configuration, except for the presence of the additional complementary output. Therefore, the overall gain is twice that of a noninverting op amp or 2 × (1 + RF2/RG2) or 2 × (1/ β2). Once again, varying VOCM will not affect both outputs in the same way, so in addition to varying VOUT,cm with unity gain, there will also be an affect on VOUT,dm by changing VOCM. Estimating the Output Noise Voltage The circuit’s input impedance is effectively higher than it would be for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the input resistor RG. Input Common-Mode Voltage Range in Single Supply Applications The AD8132 is optimized for level-shifting “ground” referenced input signals. For a single-ended input this would imply, for example, that the voltage at –DIN in Figure 3 would be zero volts when the amplifier’s negative power supply voltage (at V–) was also set to zero volts. Setting the Output Common-Mode Voltage The AD8132’s VOCM pin is internally biased at a voltage approximately equal to the midsupply point (average value of the voltages on V+ and V–). Relying on this internal bias will result in an output common-mode voltage that is within about 100 mV of the expected value. In cases where more accurate control of the output common-mode level is required, it is recommended that an external source, or resistor divider (with RSOURCE < 10K), be used. The output common-mode offset specified on pages 2 and 3 assume the VOCM input is driven by a low impedance voltage source. Similar to the case of a conventional op amp, the differential output errors (noise and offset voltages) can be estimated by multiplying the input referred terms, at +IN and –IN, by the circuit noise gain. The noise gain is defined as: R  GN = 1 +  F   RG  REV. 0 –15– AD8132 Driving a Capacitive Load CIRCUITS RF1 RG1 + A purely capacitive load can react with the pin and bondwire inductance of the AD8132 resulting in high frequency ringing in the pulse response. One way to minimize this effect is to place a small capacitor across each of the feedback resistors. The added capacitance should be small to avoid destabilizing the amplifier. An alternative technique is to place a small resistor in series with the amplifier’s outputs as shown in TPC 47. LAYOUT, GROUNDING AND BYPASSING RG2 RF2 Figure 4. Typical Four-Resistor Feedback Circuit As a high-speed part, the AD8132 is sensitive to the PCB environment in which it has to operate. Realizing its superior specifications requires attention to various details of good highspeed PCB design. The first requirement is a good solid ground plane that covers as much of the board area around the AD8132 as possible. The only exception to this is that the two input pins (Pins 1 and 8) should be kept a few mm from the ground plane, and ground should be removed from inner layers and the opposite side of the board under the input pins. This will minimize the stray capacitance on these nodes and help preserve the gain flatness vs. frequency. The power supply pins should be bypassed as close as possible to the device to the nearby ground plane. Good high-frequency ceramic chip capacitors should be used. This bypassing should be done with a capacitance value of 0.01 µF to 0.1 µF for each supply. Further away, low frequency bypassing should be provided with 10 µF tantalum capacitors from each supply to ground. The signal routing should be short and direct in order to avoid parasitic effects. Wherever there are complementary signals, a symmetrical layout should be provided to the extent possible to maximize the balance performance. When running differential signals over a long distance, the traces on PCB should be close together or any differential wiring should be twisted together to minimize the area of the loop that is formed. This will reduce the radiated energy and make the circuit less susceptible to interference. VIN + RG2 RF2 Figure 5. Typical Circuit with β1 = 0 RF1 RG1 + Figure 6. Typical Circuit with β2 = 1 VIN + Figure 7. Resistorless G = 2 Circuit with β1 = 0 RF1 VIN RG1 + Figure 8. Typical Circuit with β2 = 0 –16– REV. 0 AD8132 3V 10k 0.1 F 1V p-p 10k 348 49.9 0.1 F 348 24.9 348 348 60.4 20pF AINN 3V + 10 F 0.1 F 0.1 F 3V AVDD DRVDD DIGITAL OUTPUTS AD8132 20pF 60.4 AINP AD9203 AVSS DRVSS Figure 9. AD8132 Driving AD9203, a 10-Bit 40 MSPS A/D Converter APPLICATIONS A/D Driver 10 FUND 0 –10 –20 –30 OUTPUT – dBc Many of the newer high-speed A/D converters are single-supply and have differential inputs. Thus, the driver for these devices should be able to convert from a single-ended to a differential signal and provide output common-mode level-shifting in addition to having low distortion and noise. The AD8132 conveniently performs these functions when driving the AD9203, a 10-bit, 40 MSPS A/D converter. In Figure 9 a 1 V p-p signal drives the input of an AD8132 configured for unity gain. Both the AD8132 and the AD9203 are powered from a single 3 V supply. A voltage divider biases VOCM at midsupply, which in turn drives VOUT,cm to be half the supply voltage. This is within the common-mode range of the AD9203. Between the A/D and the driver is a one-pole, differential filter that helps to filter some of the noise and assists the switchedcapacitor inputs of the A/D. Each of the A/D inputs will be driven by a 0.5 V p-p signal that goes from 1.25 V dc to 1.75 V dc. Figure 10 is an FFT plot of the performance of the circuit when running at a clock rate of 40 MSPS and an input frequency of 2.5 MHz. fS = 40MHz fIN = 2.5MHz –40 –50 –60 –70 –80 –90 2ND 3RD 4TH 5TH 6TH 9TH 8TH 7TH –100 –110 –120 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 INPUT FREQUENCY – MHz Figure 10. FFT Response for AD8132 Driving AD9203 Balanced Cable Driver When driving a twisted pair cable, it is desirable to drive only a pure differential signal onto the line. If the signal is purely differential (i.e., fully balanced), and the transmission line is twisted and balanced, there will be a minimum radiation of any signal. +5V + 10 F +5V + 10 F 0.1 F 1k 499 49.9 50 SOURCE 0.1 F 523 1k 10 F + 0.1 F –5V 49.9 0.1 F 1 100 49.9 TWISTED PAIR 2 3 4 5 AD8132 AD830 7 VOUT 10 F + 0.1 F –5V Figure 11. Balanced Line Driver and Receiver Using AD8132 and AD830 REV. 0 –17– AD8132 The complementary electrical fields will mostly be confined to the space between the two twisted conductors and will not significantly radiate out from the cable. The current in the cable will create magnetic fields that will radiate to some degree. However, the amount of radiation is mitigated by the twists, because for each twist, the two adjacent twists will have an opposite polarity magnetic field. If the twist pitch is tight enough, these small magnetic field loops will contain most of the magnetic flux, and the magnetic far-field strength will be negligible. Any imbalance in the differential drive signal will appear as a common-mode signal on the cable. This is the equivalent of a single wire that is driven with the common-mode signal. In this case, the wire will act as an antenna and radiate. Thus, in order to minimize radiation when driving differential twisted pair cables, the differential drive signal should be very well balanced. The common-mode feedback loop in the AD8132 helps to minimize the amount of common-mode voltage at the output, and can therefore be used to create a well-balanced differential line driver. Figure 11 shows an application that uses an AD8132 as a balanced line driver and AD830 as a differential receiver configured for unity gain. This circuit was operated with 10 m of Category 5 cable. Transmit Equalizer Low-Pass Differential Filter Similar to an op amp, various types of active filters can be created with the AD8132. These can have single-ended inputs and differential outputs, which can provide an antialias function when driving a differential A/D converter. Figure 14 is a schematic of a low-pass, multiple-feedback filter. The active section contains two poles, and an additional pole is added at the output. The filter was designed to have a –3 dB frequency of 1 MHz. The actual –3 dB frequency was measured to be 1.12 MHz as shown in Figure 15. 2.15k 33pF 549 2k VIN 953 100pF 100pF 200pF 953 33pF VOUT 49.9 2k 24.9 200pF 549 2.15k Figure 14. 1 MHz, 3-Pole Differential Output Low-Pass Multiple Feedback Filter 10 0 –10 –20 Any length of transmission line will attenuate the signals it carries. This effect is worse at higher frequencies than at low frequencies. One way to compensate for this is to provide an equalizer circuit that boosts the higher frequencies in the transmitter circuit, so that at the receive end of the cable, the attenuation effects are diminished. By lowering the impedance of the RG component of the feedback network at higher frequency, the gain can be increased at high frequency. Figure 12 shows a gain-of-two line driver that has its RGs shunted by 10 pF resistors. The effect of this is shown in the frequency response plot of Figure 13. 10pF VIN VOUT/VIN – dB –30 –40 –50 –60 –70 –80 –90 10k 100k 1M FREQUENCY – Hz 10M 100M 499 49.9 Figure 15. Frequency Response of 1 MHz Low-Pass Filter High Common-Mode-Output-Impedance Amplifier VOUT 49.9 24.9 249 249 100 49.9 10pF 499 Figure 12. Frequency Boost Circuit 20 10 0 –10 VOUT/VIN – dB Changing the connection to VOCM (Pin 2) can change the common-mode from low impedance to high impedance. If VOCM is actively set to a particular voltage, the AD8132 will try to force VOUT,cm to the same voltage with a relatively low output impedance. All the previous analysis assumed that this output impedance is arbitrarily low enough to drive the load condition in the circuit. However, the are some applications that benefit from a high common-mode output impedance. This can be accomplished with the circuit shown in Figure 16. RF 348 RG 348 10 1k 1k RG 348 RF 348 10 49.9 49.9 –20 –30 –40 –50 –60 –70 –80 1 10 100 FREQUENCY – MHz 1000 Figure 13. Frequency Response for Transmit Boost Circuit Figure 16. High Common-Mode Output Impedance Differential Amplifier –18– REV. 0 AD8132 VOCM is driven by a resistor divider that “measures” the output common- mode voltage. Thus, the common-mode output voltage takes on the value that is set by the driven circuit. In this case it comes from the center point of the termination at the receive end of a 10 m length of Category 5 twisted pair cable. If the receive end common-mode voltage is set to “ground,” it will be well-defined at the receive end. Any common-mode signal that is picked up over the cable length due to noise, will appear at the transmit end, and must be “absorbed” by the transmitter. Thus, it is important that the transmitter have adequate common-mode output range to absorb the full amplitude of the common-mode signal coupled onto the cable and thus prevent clipping. Another way to look at this is that the circuit performs what is sometimes called “transformer action.” One main difference is that the AD8132 passes dc while transformers do not. A transformer can also be easily configured to have either a high or low common-mode output impedance. If the transformer’s center tap is connected to a solid voltage reference, it will set the common-mode voltage on the secondary side of the transformer. In this case, if one of the differential outputs is grounded, the other output will have only half of the differential output signal. This keeps the common-mode voltage at ground, where it is required to be due to the center tap connection. This is analogous to the AD8132 operating with a low output impedance common-mode. See Figure 17. VOCM VDIFF VOCM VDIFF Figure 18. Transformer with High Output Impedance Secondary Full-Wave Rectifier The balanced outputs of the AD8132, along with a couple of Schottky diodes, can create a very high-speed full-wave rectifier. Such circuits are useful for measuring ac voltages and other computational tasks. Figure 19 shows the configuration of such a circuit. Each of the AD8132 outputs drives the anode of an HP 2835 Schottky diode. These Schottky diodes were chosen for their high-speed operation. At lower frequencies (approximately lower than 10 MHz), a silicon signal diode, like a 1N4148 can be used. The cathodes of the two diodes are connected together and this output node is connected to ground by a 50 Ω resistor. +5V RF1 348 VIN RG1 348 RT1 49.9 RT2 24.9 RG2 348 5V 10k CR1 HP2835 RF2 348 –5V RL 100 VOUT Figure 19. Full-Wave Rectifier Figure 17. Transformer Whose Low Output Impedance Secondary Is Set at VOCM If the center tap of the secondary of a transformer is allowed to float (or there is no center tap), the transformer will have a high common-mode output impedance. This means that the commonmode of the secondary will be determined by what it is connected to, and not by anything to do with the transformer itself. If one of the differential ends of the transformer is grounded, the other end will swing with the full output voltage. This means that the common-mode of the output voltage is one-half of the differential output voltage. But this shows that the common-mode is not forced via a low impedance to a given voltage. The commonmode output voltage can easily be changed to any voltage through its other output terminals. The AD8132 can exhibit the same performance when one of the outputs in Figure 16 is grounded. The other output will swing at the full differential output voltage. The common-mode signal is “measured” by the voltage divider across the outputs and input to VOCM. This then drives VOUT,cm to the same level. At higher frequencies, it is important to minimize the capacitance on the VOCM node or else phase shifts can compromise the performance. The voltage divider resistances can also be lowered for better frequency response. The diodes should be operated such that they are slightly forwardbiased when the differential output voltage is zero. For the Schottky diodes, this is about 400 mV. The forward biasing can be conveniently adjusted by CR1, which, in this circuit, raises and lowers VOUT,CM without creating a differential output voltage. One advantage of this circuit is that the feedback loop is never momentarily opened while the diodes reverse their polarity within the loop. This is the scheme that is sometimes used for full-wave rectifiers that use conventional op amps. These conventional circuits do not work well at frequencies above about 1 MHz. If there is not enough forward bias (VOUT,cm too low), the lower sharp cusps of the full-wave rectified output waveform will be rounded off. Also, as the frequency increases, there tends to be some rounding of the lower cusps. The forward bias can be increased to yield sharper cusps at higher frequencies. There is not a reliable, entirely quantifiable, means to measure the performance of a full-wave rectifier. Since the ideal waveform has periodic sharp discontinuities, it should have (mostly even) harmonics that have no upper bound on the frequency. However, for a practical circuit, as the frequency increases, the higher harmonics become attenuated and the sharp cusps that are present at low frequencies become significantly rounded. REV. 0 –19– AD8132 The circuit was run at a frequency up to 300 MHz and, while it was still functional, the major harmonic that remained in the output was the second. This made it look like a sine wave at 600 MHz. Figure 20 is an oscilloscope plot of the output when driven by a 100 MHz, 2.5 V p-p input. Sometimes a second harmonic generator is actually useful, as for creating a clock to oversample a DAC by a factor of two. If the output of this circuit is run through a low-pass filter, it can be used as a second harmonic generator. 100mV 2ns 1V Figure 20. Full-Wave Rectifier Response with 100 MHz Input OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead SOIC (SO-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 4 0.1574 (4.00) 0.1497 (3.80) PIN 1 1 0.2440 (6.20) 0.2284 (5.80) 0.0500 (1.27) BSC 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE 0.0688 (1.75) 0.0532 (1.35) 0.0192 (0.49) 0.0138 (0.35) 8 0.0098 (0.25) 0 0.0075 (0.19) 0.0196 (0.50) 0.0099 (0.25) 45 0.0500 (1.27) 0.0160 (0.41) 8-Lead microSOIC (SM-8) 0.122 (3.10) 0.114 (2.90) 8 5 0.122 (3.10) 0.114 (2.90) 1 4 0.199 (5.05) 0.187 (4.75) PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) SEATING 0.008 (0.20) PLANE 0.043 (1.09) 0.037 (0.94) 0.011 (0.28) 0.003 (0.08) 0.120 (3.05) 0.112 (2.84) 33 27 0.028 (0.71) 0.016 (0.41) –20– REV. 0 PRINTED IN U.S.A. C3846–8–4/00 (rev. 0) 01035