AD8139ACP-R2

Low Noise, Rail-to-Rail, Differential ADC Driver AD8139 FEATURES Fully differential Low noise 2.25 nV/√Hz 2.1 pA/√Hz Low harmonic distortion 98 dBc SFDR @ 1 MHz 85 dBc SFDR @ 5 MHz 72 dBc SFDR @ 20 MHz High speed 410 MHz, 3 dB BW (G = 1) 800 V/μs slew rate 45 ns settling time to 0.01% 69 dB output balance @ 1 MHz 80 dB dc CMRR Low offset: ±0.5 mV maximum Low input offset current: 0.5 μA maximum Differential input and output Differential-to-differential or single-ended-to-differential operation Rail-to-rail output Adjustable output common-mode voltage Wide supply voltage range: 5 V to 12 V Available in a small SOIC package and an 8-lead LFCSP APPLICATIONS ADC drivers to 18 bits Single-ended-to-differential converters Differential filters Level shifters Differential PCB drivers Differential cable drivers FUNCTIONAL BLOCK DIAGRAMS –IN 1 VOCM 2 V+ 3 +OUT 4 AD8139 8 7 6 5 +IN NC V– 04679-001 –OUT NC = NO CONNECT Figure 1. 8-Lead SOIC AD8139 TOP VIEW (Not to Scale) –IN 1 VOCM 2 V+ 3 +OUT 4 NC = NO CONNECT 8 +IN 7 NC 6 V– 5 –OUT 04679-102 Figure 2. 8-Lead LFCSP GENERAL DESCRIPTION The AD8139 is an ultralow noise, high performance differential amplifier with rail-to-rail output. With its low noise, high SFDR, and wide bandwidth, it is an ideal choice for driving ADCs with resolutions to 18 bits. The AD8139 is easy to apply, and its internal common-mode feedback architecture allows its output common-mode voltage to be controlled by the voltage applied to one pin. The internal feedback loop also provides outstanding output balance as well as suppression of even-order harmonic distortion products. Fully differential and singleended-to-differential gain configurations are easily realized by the AD8139. Simple external feedback networks consisting of four resistors determine the closed-loop gain of the amplifier. The AD8139 is manufactured on the Analog Devices, Inc. proprietary, second-generation XFCB process, enabling it to achieve low levels of distortion with input voltage noise of only 2.25 nV/√Hz. The AD8139 is available in an 8-lead SOIC package with an exposed paddle (EP) on the underside of its body and a 3 mm × 3 mm LFCSP. It is rated to operate over the temperature range of −40°C to +125°C. 100 INPUT VOLTAGE NOISE (nV/ Hz) 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 1G Figure 3. Input Voltage Noise vs. Frequency Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. 04679-078 1 10 AD8139 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagrams............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 VS = ±5 V, VOCM = 0 V .................................................................. 3 VS = 5 V, VOCM = 2.5 V ................................................................. 5 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution.................................................................................. 7 Pin Configurations and Function Descriptions ............................8 Typical Performance Characteristics ..............................................9 Test Circuits ................................................................................ 17 Theory of Operation ...................................................................... 18 Typical Connection and Definition of Terms ........................ 18 Applications..................................................................................... 19 Estimating Noise, Gain, and Bandwidth with Matched Feedback Networks .................................................................... 19 Outline Dimensions ....................................................................... 24 Ordering Guide .......................................................................... 24 REVISION HISTORY 10/07—Rev. A to Rev. B. Changes to General Description .................................................... 1 Inserted Figure 2; Renumbered Sequentially................................ 1 Changes to Table 1............................................................................ 3 Changes to Table 2............................................................................ 5 Changes to Table 6 and Layout ....................................................... 8 Inserted Figure 6; Renumbered Sequentially................................ 8 Changes to Figure 30...................................................................... 12 Changes to Layout .......................................................................... 17 Changes to Figure 63...................................................................... 22 Changes to Exposed Paddle (EP) Section ................................... 23 Updated Outline Dimensions ....................................................... 24 8/04—Rev. 0 to Rev. A. Added 8-Lead LFCSP.........................................................Universal Changes to General Description .....................................................1 Changes to Figure 2...........................................................................1 Changes to VS = ±5 V, VOCM = 0 V Specifications .........................3 Changes to VS = 5 V, VOCM = 2.5 V Specifications.........................5 Changes to Table 4.............................................................................7 Changes to Maximum Power Dissipation Section........................7 Changes to Figure 26 and Figure 29............................................. 12 Inserted Figure 39 and Figure 42.................................................. 14 Changes to Figure 45 to Figure 47................................................ 15 Inserted Figure 48........................................................................... 15 Changes to Figure 52 and Figure 53............................................. 16 Changes to Figure 55 and Figure 56............................................. 17 Changes to Table 6.......................................................................... 19 Changes to Voltage Gain Section ................................................. 19 Changes to Driving a Capacitive Load Section .......................... 22 Changes to Ordering Guide .......................................................... 24 Updated Outline Dimensions....................................................... 24 5/04—Revision 0: Initial Version Rev. B | Page 2 of 24 AD8139 SPECIFICATIONS VS = ±5 V, VOCM = 0 V TA = 25°C, differential gain = 1, RL, dm = 1 kΩ, RF = RG = 200 Ω, unless otherwise noted. TMIN to TMAX = −40°C to +125°C. Table 1. Parameter DIFFERENTIAL INPUT PERFORMANCE Dynamic Performance −3 dB Small Signal Bandwidth −3 dB Large Signal Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.01% Overdrive Recovery Time Noise/Harmonic Performance SFDR Conditions Min Typ Max Unit VO, dm = 0.1 V p-p VO, dm = 2 V p-p VO, dm = 0.1 V p-p VO, dm = 2 V step VO, dm = 2 V step, CF = 2 pF G = 2, VIN, dm = 12 V p-p triangle wave VO, dm = 2 V p-p, fC = 1 MHz VO, dm = 2 V p-p, fC = 5 MHz VO, dm = 2 V p-p, fC = 20 MHz VO, dm = 2 V p-p, fC = 10.05 MHz ± 0.05 MHz f = 100 kHz f = 100 kHz VIP = VIN = VOCM = 0 V TMIN to TMAX TMIN to TMAX 340 210 410 240 45 800 45 30 98 85 72 −90 2.25 2.1 MHz MHz MHz V/μs ns ns dBc dBc dBc dBc nV/√Hz pA/√Hz +500 8.0 0.5 μV μV/°C μA μA dB V kΩ MΩ pF dB V V mA dB Third-Order IMD Input Voltage Noise Input Current Noise DC Performance Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Open-Loop Gain Input Characteristics Input Common-Mode Voltage Range Input Resistance Input Capacitance CMRR Output Characteristics Output Voltage Swing −500 ±150 1.25 2.25 0.12 114 −4 Differential Common mode Common mode ∆VICM = ±1 V dc, RF = RG = 10 kΩ Each single-ended output, RF = RG = 10 kΩ Each single-ended output, RL, dm = open circuit, RF = RG = 10 kΩ Each single-ended output f = 1 MHz 600 1.5 1.2 84 +4 80 −VS + 0.20 −VS + 0.15 +VS – 0.20 +VS − 0.15 100 −69 Output Current Output Balance Error VOCM TO VO, cm PERFORMANCE VOCM Dynamic Performance −3 dB Bandwidth Slew Rate Gain VOCM Input Characteristics Input Voltage Range Input Resistance Input Offset Voltage Input Voltage Noise Input Bias Current CMRR VO, cm = 0.1 V p-p VO, cm = 2 V p-p 0.999 −3.8 VOS, cm = VO, cm − VOCM; VIP = VIN = VOCM = 0 V f = 100 kHz ∆VOCM/∆VO, dm, ∆VOCM = ±1 V −900 515 250 1.000 1.001 +3.8 MHz V/μs V/V V MΩ μV nV/√Hz μA dB 74 3.5 ±300 3.5 1.3 88 +900 4.5 Rev. B | Page 3 of 24 AD8139 Parameter POWER SUPPLY Operating Range Quiescent Current +PSRR −PSRR OPERATING TEMPERATURE RANGE Conditions Min +4.5 Change in +VS = ±1 V Change in −VS = ±1 V 95 95 −40 24.5 112 109 Typ Max ±6 25.5 Unit V mA dB dB °C +125 Rev. B | Page 4 of 24 AD8139 VS = 5 V, VOCM = 2.5 V TA = 25°C, differential gain = 1, RL, dm = 1 kΩ, RF = RG = 200 Ω, unless otherwise noted. TMIN to TMAX = −40°C to +125°C. Table 2. Parameter DIFFERENTIAL INPUT PERFORMANCE Dynamic Performance −3 dB Small Signal Bandwidth −3 dB Large Signal Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.01% Overdrive Recovery Time Noise/Harmonic Performance SFDR Conditions Min Typ Max Unit VO, dm = 0.1 V p-p VO, dm = 2 V p-p VO, dm = 0.1 V p-p VO, dm = 2 V step VO, dm = 2 V step G = 2, VIN, dm = 7 V p-p triangle wave VO, dm = 2 V p-p, fC = 1 MHz VO, dm = 2 V p-p, fC = 5 MHz, RL = 800 Ω VO, dm = 2 V p-p, fC = 20 MHz, RL = 800 Ω VO, dm = 2 V p-p, fC = 10.05 MHz ± 0.05 MHz f = 100 kHz f = 100 kHz VIP = VIN = VOCM = 2.5 V TMIN to TMAX TMIN to TMAX 330 135 385 165 34 540 55 35 99 87 75 −87 2.25 2.1 MHz MHz MHz V/μs ns ns dBc dBc dBc dBc nV/√Hz pA/√Hz +500 7.5 0.5 μV μV/°C μA μA dB V kΩ MΩ pF dB V V mA dB Third-Order IMD Input Voltage Noise Input Current Noise DC Performance Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Open-Loop Gain Input Characteristics Input Common-Mode Voltage Range Input Resistance Input Capacitance CMRR Output Characteristics Output Voltage Swing −500 ±150 1.25 2.2 0.13 112 1 Differential Common mode Common mode ΔVICM = ±1 V dc, RF = RG = 10 kΩ Each single-ended output, RF = RG = 10 kΩ Each single-ended output, RL, dm = open circuit, RF = RG = 10 kΩ Each single-ended output f = 1 MHz 600 1.5 1.2 79 4 75 −VS + 0.15 −VS + 0.10 +VS − 0.15 +VS − 0.10 80 −70 Output Current Output Balance Error VOCM TO VO, cm PERFORMANCE VOCM Dynamic Performance −3 dB Bandwidth Slew Rate Gain VOCM Input Characteristics Input Voltage Range Input Resistance Input Offset Voltage Input Voltage Noise Input Bias Current CMRR VO, cm = 0.1 V p-p VO, cm = 2 V p-p 0.999 1.0 VOS, cm = VO, cm − VOCM; VIP = VIN = VOCM = 2.5 V f = 100 kHz ΔVOCM/ΔVO, dm, ΔVOCM = ±1 V −1.0 440 150 1.000 1.001 3.8 MHz V/μs V/V V MΩ mV nV/√Hz μA dB 67 3.5 ±0.45 3.5 1.3 79 +1.0 4.2 Rev. B | Page 5 of 24 AD8139 Parameter POWER SUPPLY Operating Range Quiescent Current +PSRR −PSRR OPERATING TEMPERATURE RANGE Conditions Min +4.5 Change in +VS = ±1 V Change in −VS = ±1 V 86 92 −40 21.5 97 105 Typ Max ±6 22.5 Unit V mA dB dB °C +125 Rev. B | Page 6 of 24 AD8139 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage VOCM Power Dissipation Input Common-Mode Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature Rating 12 V ±VS See Figure 4 ±VS −65°C to +125°C −40°C to +125°C 300°C 150°C The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The load current consists of differential and common-mode currents flowing to the load, as well as currents flowing through the external feedback networks and the internal common-mode feedback loop. The internal resistor tap used in the common-mode feedback loop places a 1 kΩ differential load on the output. RMS output voltages should be considered when dealing with ac signals. Airflow reduces θJA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduce the θJA. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the exposed paddle (EP) 8-lead SOIC (θJA = 70°C/W) and the 8-lead LFCSP (θJA = 70°C/W) on a JEDEC standard 4-layer board. θJA values are approximations. 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 04679-055 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, θJA is specified for device soldered in circuit board for surface-mount packages. Table 4. Package Type 8-Lead SOIC with EP/4-Layer 8-Lead LFCSP/4-Layer θJA 70 70 Unit °C/W °C/W MAXIMUM POWER DISSIPATION (W) Maximum Power Dissipation The maximum safe power dissipation in the AD8139 package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the glass transition temperature, the plastic will change its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8139. Exceeding a junction temperature of 175°C for an extended period can result in changes in the silicon devices potentially causing failure. SOIC AND LFCSP 0 –40 –20 0 20 40 60 80 100 120 AMBIENT TEMPERATURE (°C) Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board ESD CAUTION Rev. B | Page 7 of 24 AD8139 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AD8139 –IN 1 VOCM 2 V+ 3 +OUT 4 AD8139 8 7 6 5 TOP VIEW (Not to Scale) +IN NC V– 04679-003 –IN 1 VOCM 2 V+ 3 +OUT 4 NC = NO CONNECT 8 +IN 7 NC 6 V– 5 –OUT 04679-103 –OUT NC = NO CONNECT Figure 5. 8-Lead SOIC Pin Configuration Figure 6. 8-Lead LFCSP Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 Mnemonic −IN VOCM V+ +OUT −OUT V− NC +IN Exposed Paddle Description Inverting Input. An internal feedback loop drives the output common-mode voltage to be equal to the voltage applied to the VOCM pin, provided the operation of the amplifier remains linear. Positive Power Supply Voltage. Positive Side of the Differential Output. Negative Side of the Differential Output. Negative Power Supply Voltage. No Internal Connection. Noninverting Input. Solder exposed paddle on back of package to ground plane or to a power plane. Rev. B | Page 8 of 24 AD8139 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, differential gain = +1, RG = RF = 200 Ω, RL, dm = 1 kΩ, VS = ±5 V, TA = 25°C, VOCM = 0 V. Refer to the basic test circuit in Figure 57 for the definition of terms. 2 1 2 G=1 G=2 1 G=1 NORMALIZED CLOSED-LOOP GAIN (dB) 0 –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 –11 –12 –13 1 RG = 200Ω VO, dm = 0.1V p-p G = 10 NORMALIZED CLOSED-LOOP GAIN (dB) 0 –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 –11 –12 –13 1 RG = 200Ω VO, dm = 2.0V p-p 10 100 1000 04679-007 04679-009 04679-008 G=5 G=2 G=5 G = 10 10 100 1000 FREQUENCY (MHz) 04679-004 FREQUENCY (MHz) Figure 7. Small Signal Frequency Response for Various Gains 5 4 3 2 VS = +5V Figure 10. Large Signal Frequency Response for Various Gains 3 2 1 0 CLOSED-LOOP GAIN (dB) 0 –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 10 VO, dm = 0.1V p-p 100 CLOSED-LOOP GAIN (dB) 1 VS = ±5V –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 –11 VO, dm = 2.0V p-p 100 FREQUENCY (MHz) 1000 –12 10 VS = +5V VS = ±5V 1000 FREQUENCY (MHz) Figure 8. Small Signal Frequency Response for Various Power Supplies 3 2 1 0 04679-005 Figure 11. Large Signal Frequency Response for Various Power Supplies 3 2 1 0 +125°C +85°C +125°C +85°C CLOSED-LOOP GAIN (dB) –2 –3 –4 –5 –6 –7 –8 –9 –10 –11 –12 10 VO, dm = 0.1V p-p 100 FREQUENCY (MHz) +25°C 1000 04679-006 CLOSED-LOOP GAIN (dB) –1 –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 –11 –12 10 VO, dm = 2.0V p-p 100 FREQUENCY (MHz) 1000 –40°C +25°C –40°C Figure 9. Small Signal Frequency Response at Various Temperatures Figure 12. Large Signal Frequency Response at Various Temperatures Rev. B | Page 9 of 24 AD8139 3 2 1 0 RL = 200Ω RL = 100Ω 2 1 0 –1 CLOSED-LOOP GAIN (dB) RL = 100Ω RL = 500Ω CLOSED-LOOP GAIN (dB) –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 –11 –12 10 VO, dm = 0.1V p-p 100 FREQUENCY (MHz) RL = 1kΩ 04679-040 –2 –3 –4 –5 –6 –7 –8 –9 –10 –11 –12 VO, dm = 2.0V p-p –13 10 RL = 200Ω 100 FREQUENCY (MHz) 1000 04679-041 04679-0-042 RL = 500Ω RL = 1kΩ 1000 Figure 13. Small Signal Frequency Response for Various Loads 3 2 1 0 Figure 16. Large Signal Frequency Response for Various Loads 2 1 0 –1 CF = 0pF CF = 1pF CF = 0pF CF = 1pF CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 –11 –12 10 VO, dm = 0.1V p-p 04679-011 –2 –3 –4 –5 –6 –7 –8 –9 –10 –11 –12 VO, dm = 2.0V p-p –13 10 CF = 2pF CF = 2pF 100 FREQUENCY (MHz) 1000 100 FREQUENCY (MHz) 1000 Figure 14. Small Signal Frequency Response for Various CF 6 5 4 3 VOCM = +4.3V VOCM = –4.3V VOCM = –4V VOCM = +4V NORMALIZED CLOSED-LOOP GAIN (dB) Figure 17. Large Signal Frequency Response for Various CF 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 1 10 FREQUENCY (Hz) RL = 1kΩ (VO, dm = 0.1V p-p) RL = 100Ω (VO, dm = 0.1V p-p) RL = 100Ω (VO, dm = 2.0V p-p) RL = 1kΩ (VO, dm = 2.0V p-p) CLOSED-LOOP GAIN (dB) 2 1 0 –1 –2 –3 –4 –5 –6 –7 –8 –9 10 VO, dm = 0.1V p-p VOCM = 0V 04679-012 100 FREQUENCY (MHz) 1000 100 Figure 15. Small Signal Frequency Response at Various VOCM Figure 18. 0.1 dB Flatness for Various Loads and Output Amplitudes Rev. B | Page 10 of 24 04679-014 AD8139 –30 –40 –50 VO, dm = 2.0V p-p –30 –40 –50 DISTORTION (dBc) VO, dm = 2.0V p-p VS = +5V DISTORTION (dBc) –60 –70 –80 –90 –100 –110 –120 VS = ±5V –60 –70 –80 –90 –100 –110 –120 VS = ±5V VS = +5V 04679-015 1 10 FREQUENCY (MHz) 100 1 10 FREQUENCY (MHz) 100 Figure 19. Second Harmonic Distortion vs. Frequency and Supply Voltage –30 –40 –50 –60 DISTORTION (dB) Figure 22. Third Harmonic Distortion vs. Frequency and Supply Voltage –30 VO, dm = 2.0V p-p –40 –50 G=1 –60 DISTORTION (dB) VO, dm = 2.0V p-p –70 –80 –90 –100 –110 –120 –130 04679-016 –70 –80 –90 –100 –110 –120 –130 G=5 1 10 FREQUENCY (MHz) 100 04679-019 04679-020 G=5 G=2 G=1 G=2 –140 0.1 1 10 FREQUENCY (MHz) 100 –140 0.1 Figure 20. Second Harmonic Distortion vs. Frequency and Gain –30 –40 –50 DISTORTION (dBc) DISTORTION (dBc) Figure 23. Third Harmonic Distortion vs. Frequency and Gain –30 –40 –50 RL = 100Ω RL = 200Ω VO, dm = 2.0V p-p VO, dm = 2.0V p-p –60 –70 –80 –90 –100 –110 –120 1 RL = 100Ω RL = 200Ω –60 –70 –80 –90 –100 –110 –120 RL = 500Ω RL = 1kΩ RL = 500Ω RL = 1kΩ 1 10 FREQUENCY (MHz) 100 10 FREQUENCY (MHz) 100 Figure 21. Second Harmonic Distortion vs. Frequency and Load 04679-017 –130 0.1 –130 0.1 Figure 24. Third Harmonic Distortion vs. Frequency and Load Rev. B | Page 11 of 24 04679-018 –130 0.1 –130 0.1 AD8139 –30 –40 –50 DISTORTION (dBc) DISTORTION (dBc) –30 VO, dm = 2.0V p-p –40 –50 –60 –70 –80 –90 –100 –110 VO, dm = 2.0V p-p –60 –70 –80 –90 –100 –110 –120 –130 0.1 1 RF = 1kΩ RF = 200Ω RF = 500Ω RF = 200Ω RF = 1kΩ RF = 500Ω 1 10 FREQUENCY (MHz) 100 04679-024 04679-026 –120 10 FREQUENCY (MHz) 100 Figure 25. Second Harmonic Distortion vs. Frequency and RF –80 FC = 2MHz –90 VS = +5V –100 VS = ±5V 04679-021 –130 0.1 Figure 28. Third Harmonic Distortion vs. Frequency and RF –80 –90 VS = +5V –100 FC = 2MHz DISTORTION (dBc) DISTORTION (dBc) VS = ±5V –110 –120 –130 –140 –150 –110 –120 –130 –140 –150 04679-022 0 1 2 3 4 VO, dm (V p-p) 5 6 7 8 0 1 2 3 4 VO, dm (V p-p) 5 6 7 8 Figure 26. Second Harmonic Distortion vs. Output Amplitude –60 –70 –80 Figure 29. Third Harmonic Distortion vs. Output Amplitude –60 –70 –80 DISTORTION (dBc) VO, dm = 2V p-p FC = 2MHz VO, dm = 2V p-p FC = 2MHz DISTORTION (dBc) –90 –100 –110 –120 SECOND HARMONIC –90 –100 –110 –120 SECOND HARMONIC THIRD HARMONIC 0 0.5 1.0 1.5 2.0 2.5 VOCM (V) 3.0 3.5 4.0 4.5 5.0 04679-023 THIRD HARMONIC –130 –5 –4 –3 –2 –1 0 VOCM (V) 1 2 3 4 5 –130 Figure 27. Harmonic Distortion vs. VOCM, VS = +5 V Figure 30. Harmonic Distortion vs. VOCM, VS = ±5 V Rev. B | Page 12 of 24 04679-025 AD8139 100 75 50 25 VO, dm = 100mV p-p 2.5 2.0 1.5 CF = 0pF (CF = 0pF, VS = ±5V) VO, dm (CF = 2pF, VS = ±5V) 1.0 CF = 2pF CF = 0pF CF = 2pF 2V p-p CF = 0pF 4V p-p VO, dm (V) 0 –25 –50 VO, dm (V) 5ns/DIV 04679-043 0.5 0 –0.5 –1.0 –1.5 –75 –100 TIME (ns) –2.0 –2.5 TIME (ns) 04679-044 5ns/DIV Figure 31. Small Signal Transient Response for Various CF 0.100 0.075 0.050 0.025 RS = 31.6Ω CL, dm = 30pF Figure 34. Large Signal Transient Response for Various CF 1.5 RS = 63.4Ω CL, dm = 15pF 1.0 0.5 VO, dm (V) VO, dm (V) RS = 63.4Ω CL, dm = 15pF RS = 31.6Ω CL, dm = 30pF 0 –0.025 –0.050 –0.075 5ns/DIV 04679-064 0 –0.5 –1.0 5ns/DIV –1.5 TIME (ns) 04679-065 –0.100 TIME (ns) Figure 32. Small Signal Transient Response for Capacitive Loads 5 0 VO, dm = 2V p-p –5 FC1 = 10MHz –10 FC2 = 10.1MHz –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 –65 –70 –75 –80 –85 –90 –95 –100 9.55 9.65 9.75 9.85 Figure 35. Large Signal Transient Response for Capacitive Loads 1.5 600 CF = 2pF VO, dm = 2.0V p-p 1.0 400 ERROR (µV) 1DIV = 0.01% 04679-034 NORMALIZED OUTPUT (dBc) AMPLITUDE (V) 0.5 200 0 ERROR –0.5 VO, dm 0 –200 –1.0 VIN TIME (ns) 35ns/DIV –400 9.95 10.05 10.15 10.25 10.35 10.45 10.55 FREQUENCY (MHz) 04679-027 –1.5 –600 Figure 33. Intermodulation Distortion Figure 36. Settling Time (0.01%) Rev. B | Page 13 of 24 AD8139 1.5 ±5V 6 5 4 3 +5V 1.0 VS = +5V 0.5 CLOSED-LOOP GAIN (dB) 2 1 0 –1 –2 –3 –4 –5 –6 –7 VO, cm = 2.0V p-p VO, cm = 0.1V p-p VS = ±5V VS = ±5V VOCM (V) 0 –0.5 VO, cm = 2V p-p VIN, dm = 0V 10ns/DIV –1.5 TIME (ns) 04679-069 –1.0 –8 –9 10 VS = +5V 100 FREQUENCY (MHz) 1000 04679-038 04679-080 04679-045 Figure 37. VOCM Large Signal Transient Response 0 –10 –20 0 –10 –20 Figure 40. VOCM Frequency Response for Various Supplies VIN, cm = 0.2V p-p INPUT CMRR = ΔVO, cm/ΔVIN, cm VO, cm = 0.2V p-p VOCM CMRR = ΔVO, dm/ΔVO, cm VOCM CMRR (dB) 04679-066 –30 –30 –40 –50 –60 –70 –80 –90 CMRR (dB) –40 –50 –60 –70 –80 –90 RF = RG = 10kΩ RF = RG = 200Ω 1 10 FREQUENCY (MHz) 100 500 1 10 FREQUENCY (MHz) 100 500 Figure 38. CMRR vs. Frequency 100 100 Figure 41. VOCM CMRR vs. Frequency INPUT VOLTAGE NOISE (nV/ Hz) VOCM VOLTAGE NOISE (nV/ Hz) 04679-079 10 10 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 1G 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 1G Figure 39. Input Voltage Noise vs. Frequency Figure 42. VOCM Voltage Noise vs. Frequency Rev. B | Page 14 of 24 AD8139 RL, dm = 1kΩ –10 PSRR = ΔVO, dm/ΔVS –20 –30 0 14 12 10 8 6 4 2 0 –2 –4 –6 –8 –10 –12 G=2 2 × VIN, dm VO, dm PSRR (dB) –40 –PSRR –50 +PSRR –60 –70 –80 –90 1 10 FREQUENCY (MHz) 100 500 04679-047 VOLTAGE (V) –100 –14 TIME (ns) Figure 43. PSRR vs. Frequency 100 VS = +5V 0 –10 –20 –30 –40 –50 –60 –70 0.01 0.1 –80 Figure 46. Overdrive Recovery VO, dm = 1V p-p OUTPUT BALANCE = ΔVO, cm/ΔVO, dm OUTPUT IMPEDANCE (Ω) VS = ±5V 1 0.1 OUTPUT BALANCE (dB) 10 04679-028 1 10 FREQUENCY (MHz) 100 1000 1 10 FREQUENCY (MHz) 100 500 Figure 44. Single-Ended Output Impedance vs. Frequency 700 600 500 300 200 100 0 –100 –200 –300 –400 –500 –600 04679-068 Figure 47. Output Balance vs. Frequency 300 VS = ±5V G = 1 (RF = RG = 200Ω) RL, dm = 1kΩ VS+ – VOP –50 SINGLE-ENDED OUTPUT SWING FROM RAIL (mV) VS+ – VOP 200 –150 VS = ±5V VS = +5V 150 –200 VON – VS– 100 VON – VS– –250 1k RESISTIVE LOAD (Ω) 10k –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 45. Output Saturation Voltage vs. Output Load Figure 48. Output Saturation Voltage vs. Temperature Rev. B | Page 15 of 24 04679-077 –700 100 50 –40 –300 VON SWING FROM RAIL (mV) VOP SWING FROM RAIL (mV) 400 250 –100 04679-067 04679-046 50ns/DIV AD8139 3.0 IOS INPUT BIAS CURRENT (µA) SUPPLY CURRENT (mA) 170 26 VS = ±5V 25 OFFSET CURRENT (nA) 2.5 IBIAS 2.0 145 24 120 23 VS = +5V 22 1.5 95 21 –20 0 20 40 60 80 100 120 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 49. Input Bias and Offset Current vs. Temperature 10 8 6 INPUT BIAS CURRENT (µA) Figure 52. Supply Current vs. Temperature 300 VOS, cm 250 400 600 4 2 0 –2 –4 –6 –8 –4 VS = ±5V VS = +5V VOS, dm (µV) 200 200 VOS, cm (µV) 04679-071 04679-061 150 VOS, dm 100 0 –200 50 –400 –3 –2 –1 0 VACM (V) 1 2 3 4 5 04679-073 –10 –5 0 –40 –20 0 20 40 60 80 100 120 –600 TEMPERATURE (°C) Figure 50. Input Bias Current vs. Input Common-Mode Voltage 5 4 3 2 VS = ±2.5V Figure 53. Offset Voltage vs. Temperature 50 45 40 35 FREQUENCY VS = ±5V COUNT = 350 MEAN = –50µV STD DEV = 100µV VOUT, cm (V) 1 0 –1 –2 –3 –4 –4 –3 –2 –1 0 VOCM (V) 1 2 30 25 20 15 10 5 3 4 5 04679-048 Figure 51. VOUT, cm vs. VOCM Input Voltage Rev. B | Page 16 of 24 –500 –450 –400 –350 –300 –250 –200 –150 –100 –50 0 50 100 150 200 250 300 350 400 450 500 VOS, dm (µV) –5 –5 0 Figure 54. VOS, dm Distribution 04679-060 04679-062 1.0 –40 70 20 –40 AD8139 1.7 1.6 1.5 VOCM BIAS CURRENT (µA) VOCM BIAS CURRENT (µA) 6 4 VS = ±5V 2 1.4 1.3 1.2 1.1 1.0 0.9 0.8 04679-063 VS = +5V 0 –2 –4 –20 0 20 40 60 80 100 120 –4 –3 –2 –1 0 VOCM (V) 1 2 3 4 5 TEMPERATURE (°C) Figure 55. VOCM Bias Current vs. Temperature Figure 56. VOCM Bias Current vs. VOCM Input Voltage TEST CIRCUITS RF 50Ω VTEST TEST SIGNAL SOURCE 60.4Ω 60.4Ω 50Ω VOCM RG = 200Ω RG = 200Ω CF AD8139 CF 04679-072 RL, dm = 1kΩ – VO, dm + RF Figure 57. Basic Test Circuit 50Ω VTEST TEST SIGNAL SOURCE 60.4Ω 60.4Ω 50Ω VOCM RG = 200Ω RG = 200Ω RF = 200Ω RS AD8139 RS RF = 200Ω CL, dm – RL, dm VO, dm + 04679-075 Figure 58. Capacitive Load Test Circuit, G = +1 Rev. B | Page 17 of 24 04679-074 0.7 –40 –6 –5 AD8139 THEORY OF OPERATION The AD8139 is a high speed, low noise differential amplifier fabricated on the Analog Devices second-generation eXtra Fast Complementary Bipolar (XFCB) process. It is designed to provide two closely balanced differential outputs in response to either differential or single-ended input signals. Differential gain is set by external resistors, similar to traditional voltagefeedback operational amplifiers. The common-mode level of the output voltage is set by a voltage at the VOCM pin and is independent of the input common-mode voltage. The AD8139 has an H-bridge input stage for high slew rate, low noise, and low distortion operation and rail-to-rail output stages that provide maximum dynamic output range. This set of features allows for convenient single-ended-to-differential conversion, a common need to take advantage of modern high resolution ADCs with differential inputs. outputs of identical amplitude and exactly 180° out of phase. The output balance performance does not require tightly matched external components, nor does it require that the feedback factors of each loop be equal to each other. Low frequency output balance is limited ultimately by the mismatch of an on-chip voltage divider, which is trimmed for optimum performance. Output balance is measured by placing a well-matched resistor divider across the differential voltage outputs and comparing the signal at the midpoint of the divider with the magnitude of the differential output. By this definition, output balance is equal to the magnitude of the change in output common-mode voltage divided by the magnitude of the change in output differential-mode voltage: Output Balance = ΔVO, cm ΔVO, dm (3) TYPICAL CONNECTION AND DEFINITION OF TERMS Figure 59 shows a typical connection for the AD8139, using matched external RF/RG networks. The differential input terminals of the AD8139, VAP and VAN, are used as summing junctions. An external reference voltage applied to the VOCM terminal sets the output common-mode voltage. The two output terminals, VOP and VON, move in opposite directions in a balanced fashion in response to an input signal. CF The block diagram of the AD8139 in Figure 60 shows the external differential feedback loop (RF/RG networks and the differential input transconductance amplifier, GDIFF) and the internal common-mode feedback loop (voltage divider across VOP and VON and the common-mode input transconductance amplifier, GCM). The differential negative feedback drives the voltages at the summing junctions VAN and VAP to be essentially equal to each other. VAN = VAP (4) The common-mode feedback loop drives the output commonmode voltage, sampled at the midpoint of the two 500 Ω resistors, to equal the voltage set at the VOCM terminal. This ensures that VOP = VOCM + and VO, dm 2 VO, dm 2 RF 10pF RF VIP VOCM VIN RG VAN RG VAP + VON – RL, dm VO, dm VOP RF 04679-050 AD8139 – + (5) CF VON = VOCM − VIN RG (6) Figure 59. Typical Connection The differential output voltage is defined as VO, dm = VOP − VON Common-mode voltage is the average of two voltages. The output common-mode voltage is defined as (1) + GO 500Ω MIDSUPPLY VOP VO, cm = VOP + VON 2 VAN (2) VAP GDIFF GCM 500Ω VOCM VON Output Balance Output balance is a measure of how well VOP and VON are matched in amplitude and how precisely they are 180° out of phase with each other. It is the internal common-mode feedback loop that forces the signal component of the output common-mode towards zero, resulting in the near perfectly balanced differential VIP + GO RG RF Figure 60. Block Diagram Rev. B | Page 18 of 24 04679-051 10pF AD8139 APPLICATIONS ESTIMATING NOISE, GAIN, AND BANDWIDTH WITH MATCHED FEEDBACK NETWORKS Estimating Output Noise Voltage The total output noise is calculated as the root-sum-squared total of several statistically independent sources. Because the sources are statistically independent, the contributions of each must be individually included in the root-sum-square calculation. Table 6 lists recommended resistor values and estimates of bandwidth and output differential voltage noise for various closed-loop gains. For most applications, 1% resistors are sufficient. Table 6. Recommended Values of Gain-Setting Resistors and Voltage Noise for Various Closed-Loop Gains Gain 1 2 5 10 RG (Ω) 200 200 200 200 RF (Ω) 200 400 1k 2k 3 dB Bandwidth (MHz) 400 160 53 26 Total Output Noise (nV/√Hz) 5.8 9.3 19.7 37 Voltage Gain The behavior of the node voltages of the single-ended-todifferential output topology can be deduced from the previous definitions. Referring to Figure 59, (CF = 0) and setting VIN = 0, one can write VIP − VAP VAP − VON = RG RF (11) (12) ⎡ RG ⎤ VAN = VAP = VOP ⎢ ⎥ ⎣ RF + RG ⎦ Solving the above two equations and setting VIP to Vi gives the gain relationship for VO, dm/Vi. VOP − VON = VO, dm = RF V RG i (13) An inverting configuration with the same gain magnitude can be implemented by simply applying the input signal to VIN and setting VIP = 0. For a balanced differential input, the gain from VIN, dm to VO, dm is also equal to RF/RG, where VIN, dm = VIP − VIN. Feedback Factor Notation When working with differential amplifiers, it is convenient to introduce the feedback factor β, which is defined as The differential output voltage noise contains contributions from the input voltage noise and input current noise of the AD8139 as well as those from the external feedback networks. The contribution from the input voltage noise spectral density is computed as β= RG RF + RG (14) ⎛ R⎞ Vo_n1 = vn ⎜1 + F ⎟ , or equivalently, vn/β ⎜ R⎟ G⎠ ⎝ (7) This notation is consistent with conventional feedback analysis and is very useful, particularly when the two feedback loops are not matched. Input Common-Mode Voltage The linear range of the VAN and VAP terminals extends to within approximately 1 V of either supply rail. Because VAN and VAP are essentially equal to each other, they are both equal to the input common-mode voltage of the amplifier. Their range is indicated in the Specifications tables as input common-mode range. The voltage at VAN and VAP for the connection diagram in Figure 59 can be expressed as VAN = VAP = VACM = (V + VIN ) ⎞ ⎛ RG ⎞ ⎛ RF × VOCM ⎟ × IP ⎜ ⎟+⎜ RF + RG 2 RF + RG ⎠ ⎝ ⎠⎝ (15) where vn is defined as the input-referred differential voltage noise. This equation is the same as that of traditional op amps. The contribution from the input current noise of each input is computed as Vo_n2 = in (RF) where in is defined as the input noise current of one input. Each input needs to be treated separately because the two input currents are statistically independent processes. The contribution from each RG is computed as (8) ⎛R Vo_n3 = 4kTRG ⎜ F ⎜R ⎝G ⎞ ⎟ ⎟ ⎠ (9) where VACM is the common-mode voltage present at the amplifier input terminals. Using the β notation, Equation 15 can be written as follows: VACM = βVOCM + (1 − β)VICM (16) (17) or equivalently, VACM = VICM + β(VOCM − VICM) where VICM is the common-mode voltage of the input signal, that is, VICM = VIP + VIN/2. This result can be intuitively viewed as the thermal noise of each RG multiplied by the magnitude of the differential gain. The contribution from each RF is computed as Vo_n4 = √4kTRF (10) Rev. B | Page 19 of 24 AD8139 For proper operation, the voltages at VAN and VAP must stay within their respective linear ranges. Calculating Input Impedance The input impedance of the circuit in Figure 59 depends on whether the amplifier is being driven by a single-ended or a differential signal source. For balanced differential input signals, the differential input impedance (RIN, dm) is simply RIN, dm = 2RG (18) For a single-ended signal (for example, when VIN is grounded and the input signal drives VIP), the input impedance becomes The input impedance of a conventional inverting op amp configuration is simply RG, but it is higher in Equation 19 because a fraction of the differential output voltage appears at the summing junctions, VAN and VAP. This voltage partially bootstraps the voltage across the input resistor RG, leading to the increased input resistance. Input Common-Mode Swing Considerations In some single-ended-to-differential applications, when using a single-supply voltage, attention must be paid to the swing of the input common-mode voltage, VACM. Consider the case in Figure 61, where VIN is 5 V p-p swinging about a baseline at ground, and VREF is connected to ground. The circuit has a differential gain of 1.6 and β = 0.38. VICM has an amplitude of 2.5 V p-p and is swinging about ground. Using the results in Equation 16, the common-mode voltage at the inputs of the AD8139, VACM, is a 1.5 V p-p signal swinging about a baseline of 0.95 V. The maximum negative excursion of VACM in this case is 0.2 V, which exceeds the lower input common-mode voltage limit. 5V RIN = RG RF 1− 2(RG + RF ) (19) 0.1µF 324Ω 200Ω 2.5V VIN VREF VOCM 3 8 2 1 + 5 15Ω 2.7nF 0.1µF 20Ω 0.1µF AVDD IN– DVDD +2.5V GND –2.5V AD8139 – 6 4 324Ω +1.7V +0.95V +0.2V 15Ω AD7674 IN+ DGND AGND REFGND REF REFBUFIN PDBUF 47µF 200Ω 2.7nF VACM WITH VREF = 0 0.1µF Figure 61. AD8139 Driving AD7674, 18-Bit, 800 kSPS ADC Rev. B | Page 20 of 24 04679-052 ADR431 2.5V REFERENCE AD8139 One way to avoid the input common-mode swing limitation is to bias VIN and VREF at midsupply. In this case, VIN is 5 V p-p swinging about a baseline at 2.5 V, and VREF is connected to a low-Z 2.5 V source. VICM now has an amplitude of 2.5 V p-p and is swinging about 2.5 V. Using the results in Equation 17, VACM is calculated to be equal to VICM because VOCM = VICM. Therefore, VACM swings from 1.25 V to 3.75 V, which is well within the input common-mode voltage limits of the AD8139. Another benefit seen in this example is that because VOCM = VACM = VICM no wasted common-mode current flows. Figure 62 illustrates how to provide the low-Z bias voltage. For situations that do not require a precise reference, a simple voltage divider suffices to develop the input voltage to the buffer. 5V 0.1µF 200Ω VIN 0V TO 5V VOCM 3 8 2 1 + 5 Estimating DC Errors Primary differential output offset errors in the AD8139 are due to three major components: the input offset voltage, the offset between the VAN and VAP input currents interacting with the feedback network resistances, and the offset produced by the dc voltage difference between the input and output common-mode voltages in conjunction with matching errors in the feedback network. The first output error component is calculated as ⎛ R + RG Vo _ e1 = VIO ⎜ F ⎜R G ⎝ ⎞ ⎟ , or equivalently as VIO/β ⎟ ⎠ (21) where VIO is the input offset voltage. The input offset voltage of the AD8139 is laser trimmed and guaranteed to be less than 500 μV. 324Ω The second error is calculated as ⎛ R + RG Vo _ e2 = I IO ⎜ F ⎜R G ⎝ ⎞⎛ RG RF ⎟⎜ ⎟⎜ R + R G ⎠⎝ F ⎞ ⎟ = I IO (RF ) ⎟ ⎠ (22) AD8139 – 6 4 324Ω 5V TO AD7674 REFBUFIN 200Ω 0.1µF 0.1µF where IIO is defined as the offset between the two input bias currents. The third error voltage is calculated as Vo_e3 = Δenr × (VICM − VOCM) (23) where Δenr is the fractional mismatch between the two feedback resistors. The total differential offset error is the sum of these three error sources. 04679-053 10µF + + AD8031 – ADR431 2.5V REFERENCE Figure 62. Low-Z 2.5 V Buffer Other Impact of Mismatches in the Feedback Networks The internal common-mode feedback network still forces the output voltages to remain balanced, even when the RF/RG feedback networks are mismatched. However, the mismatch will cause a gain error proportional to the feedback network mismatch. Ratio-matching errors in the external resistors degrade the ability to reject common-mode signals at the VAN and VIN input terminals, much the same as with a four-resistor difference amplifier made from a conventional op amp. Ratio-matching errors also produce a differential output component that is equal to the VOCM input voltage times the difference between the feedback factors (βs). In most applications using 1% resistors, this component amounts to a differential dc offset at the output that is small enough to be ignored. Another way to avoid the input common-mode swing limitation is to use dual power supplies on the AD8139. In this case, the biasing circuitry is not required. Bandwidth vs. Closed-Loop Gain The 3 dB bandwidth of the AD8139 decreases proportionally to increasing closed-loop gain in the same way as a traditional voltage feedback operational amplifier. For closed-loop gains greater than 4, the bandwidth obtained for a specific gain can be estimated as f − 3 dB,VOUT , dm = RG × (300 MHz) RG + RF (20) or equivalently, β(300 MHz). This estimate assumes a minimum 90° phase margin for the amplifier loop, which is a condition approached for gains greater than 4. Lower gains show more bandwidth than predicted by the equation due to the peaking produced by the lower phase margin. Rev. B | Page 21 of 24 AD8139 Driving a Capacitive Load A purely capacitive load reacts with the bondwire and pin inductance of the AD8139, resulting in high frequency ringing in the transient response and loss of phase margin. One way to minimize this effect is to place a small resistor in series with each output to buffer the load capacitance (see Figure 58 and Figure 63). The resistor and load capacitance form a first-order, low-pass filter; therefore, the resistor value should be as small as possible. In some cases, the ADCs require small series resistors to be added on their inputs. 5 RS = 30.1Ω 4 CL = 15pF 3 2 1 0 –1 –2 RS = 60.4Ω –3 CL = 15pF –4 –5 –6 –7 RS = 60.4Ω –8 CL = 5pF –9 VS = ±5V –10 V = 0.1V p-p –11 GO, dm = 1 (RF = RG = 200Ω) –12 R L, dm = 1kΩ –13 10M 100M FREQUENCY (Hz) RS = 30.1Ω CL = 5pF The input resistance presented by the AD8139 input circuitry is seen in parallel with the termination resistor, and its loading effect must be taken into account. The Thevenin equivalent circuit of the driver, its source resistance, and the termination resistance must all be included in the calculation as well. An exact solution to the problem requires the solution of several simultaneous algebraic equations and is beyond the scope of this data sheet. An iterative solution is also possible and simpler, especially considering the fact that standard 1% resistor values are generally used. Figure 64 shows the AD8139 in a unity-gain configuration driving the AD6645, which is a 14-bit, high speed ADC, and with the following discussion, provides a good example of how to provide a proper termination in a 50 Ω environment. The termination resistor, RT, in parallel with the 268 Ω input resistance of the AD8139 circuit (calculated using Equation 19), yields an overall input resistance of 50 Ω that is seen by the signal source. To have matched feedback loops, each loop must have the same RG if they have the same RF. In the input (upper) loop, RG is equal to the 200 Ω resistor in series with the (+) input plus the parallel combination of RT and the source resistance of 50 Ω. In the upper loop, RG is therefore equal to 228 Ω. The closest standard 1% value to 228 Ω is 226 Ω and is used for RG in the lower loop. Greater accuracy could be achieved by using two resistors in series to obtain a resistance closer to 228 Ω. Things get more complicated when it comes to determining the feedback resistor values. The amplitude of the signal source generator VS is two times the amplitude of its output signal when terminated in 50 Ω. Therefore, a 2 V p-p terminated amplitude is produced by a 4 V p-p amplitude from VS. The Thevenin equivalent circuit of the signal source and RT must be used when calculating the closed-loop gain, because in the upper loop, RG is split between the 200 Ω resistor and the Thevenin resistance looking back toward the source. The Thevenin voltage of the signal source is greater than the signal source output voltage when terminated in 50 Ω because RT must always be greater than 50 Ω. In this case, RT is 61.9 Ω and the Thevenin voltage and resistance are 2.2 V p-p and 28 Ω, respectively. Now the upper input branch can be viewed as a 2.2 V p-p source in series with 228 Ω. Because this is a unitygain application, a 2 V p-p differential output is required, and RF must therefore be 228 × (2/2.2) = 206 Ω. The closest standard value to this is 205 Ω. When generating the Typical Performance Characteristics data, the measurements were calibrated to take the effects of the terminations on the closed-loop gain into account. CLOSED LOOP GAIN (dB) RS = 0Ω CL, dm = 0pF 1G Figure 63. Frequency Response for Various Capacitive Load and Series Resistance The Typical Performance Characteristics that illustrate transient response vs. the capacitive load were generated using series resistors in each output and a differential capacitive load. Layout Considerations Standard high speed PCB layout practices should be adhered to when designing with the AD8139. A solid ground plane is recommended, and good wideband power supply decoupling networks should be placed as close as possible to the supply pins. To minimize stray capacitance at the summing nodes, the copper in all layers under all traces and pads that connect to the summing nodes should be removed. Small amounts of stray summing-node capacitance cause peaking in the frequency response, and large amounts can cause instability. If some stray summing-node capacitance is unavoidable, its effects can be compensated for by placing small capacitors across the feedback resistors. Terminating a Single-Ended Input Controlled impedance interconnections are used in most high speed signal applications, and they require at least one line termination. In analog applications, a matched resistive termination is generally placed at the load end of the line. This section deals with how to properly terminate a single-ended input to the AD8139. 04679-076 Rev. B | Page 22 of 24 AD8139 Because this is a single-ended-to-differential application on a single supply, the input common-mode voltage swing must be checked. From Figure 64, β = 0.52, VOCM = 2.4 V, and VICM is 1.1 V p-p swinging about ground. Using Equation 16, VACM is calculated to be 0.53 V p-p swinging about a baseline of 1.25 V, and the minimum negative excursion is approximately 1 V. Exposed Paddle (EP) The 8-lead SOIC and the 8-lead LFCSP have an exposed paddle on the bottom of the package. To achieve the specified thermal resistance, the exposed paddle must be soldered to one of the PCB planes. The exposed paddle mounting pad should contain several thermal vias within it to ensure a low thermal path to the plane. 5V 3.3V 0.01µF 0.01µF 205Ω 50Ω VS 2V p-p RT 61.9Ω 200Ω VOCM 3 8 2 1 226Ω + 5 25Ω AIN AVCC DVCC 0.01µF SIGNAL SOURCE AD8139 – 6 4 AIN 205Ω 25Ω GND C1 AD6645 C2 0.1µF 0.1µF VREF 04679-054 2.4V Figure 64. AD8139 Driving AD6645, 14-Bit, 80 MSPS/105 MSPS ADC Rev. B | Page 23 of 24 AD8139 OUTLINE DIMENSIONS 4.00 (0.157) 3.90 (0.154) 3.80 (0.150) 5.00 (0.197) 4.90 (0.193) 4.80 (0.189) 8 1 5 4 2.29 (0.090) TOP VIEW 6.20 (0.244) 6.00 (0.236) 5.80 (0.228) BOTTOM VIEW (PINS UP) 2.29 (0.090) 1.27 (0.05) BSC 1.75 (0.069) 1.35 (0.053) 0.10 (0.004) MAX COPLANARITY 0.10 1.65 (0.065) 1.25 (0.049) SEATING PLANE 0.50 (0.020) 0.25 (0.010) 45° 0.51 (0.020) 0.31 (0.012) 0.25 (0.0098) 0.17 (0.0067) 8° 0° 1.27 (0.050) 0.40 (0.016) COMPLIANT TO JEDEC STANDARDS MS-012-A A 060506A CONTROLLING DIMENSIONS ARE IN MILLIMETER; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 65. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] Narrow Body (RD-8-1)—Dimensions shown in millimeters and (inches) 3.25 3.00 SQ 2.75 0.60 MAX 0.60 MAX 5 8 0.50 BSC PIN 1 INDICATOR TOP VIEW 2.95 2.75 SQ 2.55 EXPOSED PAD (BOTTOM VIEW) 1.60 1.45 1.30 PIN 1 INDICATOR 4 1 12° MAX 0.90 MAX 0.85 NOM SEATING PLANE 0.70 MAX 0.65 TYP 0.50 0.40 0.30 0.05 MAX 0.01 NOM 1.89 1.74 1.59 Figure 66. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm × 3 mm Body, Very Thin, Dual Lead (CP-8-2)—Dimensions shown in millimeters ORDERING GUIDE Model AD8139ARD AD8139ARD-REEL AD8139ARD-REEL7 AD8139ARDZ 1 AD8139ARDZ-REEL1 AD8139ARDZ-REEL71 AD8139ACP-R2 AD8139ACP-REEL AD8139ACP-REEL7 AD8139ACPZ-R21 AD8139ACPZ-REEL1 AD8139ACPZ-REEL71 1 061507-B 0.30 0.23 0.18 0.20 REF Temperature Range –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C Package Description 8-Lead Small Outline Package with Exposed Pad (SOIC_N_EP) 8-Lead Small Outline Package with Exposed Pad (SOIC_N_EP) 8-Lead Small Outline Package with Exposed Pad (SOIC_N_EP) 8-Lead Small Outline Package with Exposed Pad (SOIC_N_EP) 8-Lead Small Outline Package with Exposed Pad (SOIC_N_EP) 8-Lead Small Outline Package with Exposed Pad (SOIC_N_EP) 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) Package Option RD-8-1 RD-8-1 RD-8-1 RD-8-1 RD-8-1 RD-8-1 CP-8-2 CP-8-2 CP-8-2 CP-8-2 CP-8-2 CP-8-2 Branding HEB HEB HEB HEB# HEB# HEB# Z = RoHS Compliant Part, # denotes RoHS product may be top or bottom marked. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04679-0-10/07(B) Rev. B | Page 24 of 24