Low Cost, Triple Differential Drivers
for Wideband Video
AD8141/AD8142
Data Sheet
VOCMA
VOCMB
VS–/GND
VS+
–IN B
+IN B
FUNCTIONAL BLOCK DIAGRAMS
24 23 22 21 20 19
AD8141
DIS 1
–
–IN A 3
+
16 –IN C
15 +IN C
+IN A 4
–
+
VS–/GND 5
–
+
14 VS–/GND
13 –OUT C
09461-001
+OUT C
10 11 12
VS+
VS+
9
–OUT B
8
+OUT B
7
+OUT A
–OUT A 6
HSYNC
VSYNC
+IN G
VS–/GND
Figure 1.
APPLICATIONS
24 23 22 21 20 19
Keyboard-video-mouse (KVM) networking
Video distribution
Digital signage
Security cameras
AD8142
DIS 1
18 SYNC LEVEL
17 VS+
VS–/GND 2
×2
–IN R 3
+IN R 4
+
16 –IN B
–
–
+
15 +IN B
–
+
14 VS–/GND
13 –OUT B
9
10 11 12
VS+
+OUT G
–OUT G
+OUT B
8
VS+
7
+OUT R
–OUT R 6
09461-002
VS–/GND 5
Figure 2.
GENERAL DESCRIPTION
The AD8141 and AD8142 are triple, low cost, differential or
single-ended-input-to-differential-output drivers. Each amplifier
has a fixed gain of 2 to compensate for the attenuation of the
line termination resistors. The AD8141 and AD8142 are
specifically designed for RGB signals but can be used for any
type of signals. The amplifiers have very fast slew rate and
settling time while being manufactured on a cost effective
CMOS process. They are optimized for high resolution video
performance with a 0.1 dB flatness of 65 MHz, which allows
driving high resolution video over any type of UTP cable.
The drivers have an internal common-mode feedback loop
that provides output amplitude and phase matching, achieving
−50 dB balance error at 50 MHz and thereby suppressing evenorder harmonics and minimizing radiated electromagnetic
interference (EMI).
Rev. B
18 VOCMC
17 VS+
VS–/GND 2
VS+
Triple, high speed differential drivers
255 MHz, −3 dB large signal bandwidth
65 MHz, 0.1 dB flatness
1150 V/μs slew rate
12 ns settling time
Single 5 V or split supply operation
Fixed gain of 2
Internal common-mode feedback network
Output balance error −50 dB at 50 MHz
AD8142 has integrated sync-on-common-mode circuitry
High-Z output when disabled
Differential-to-differential or single-ended-to-differential
operation
High isolation between amplifiers: −100 dB at 10 MHz
Low power: 44 mA at 5 V
Available in space-saving packaging: 4 mm × 4 mm LFCSP
–IN G
FEATURES
The AD8142 includes a unique sync-on-common-mode feature
that allows the user to transmit balanced horizontal and vertical
video sync signals over the three common-mode channels.
Additionally, the AD8141 and AD8142 both have a disable
feature that, when asserted, produces high-Z outputs, allowing
line isolation and easy multiplexing.
The AD8141 and AD8142 are available in a 24-lead 4 mm × 4 mm
LFCSP and operate over a temperature range of −40°C to +85°C.
They can be used with the AD8145 triple differential-to-singleended receiver, AD8123 triple equalizer, AD8120 triple delay
line, and the AD8117 or AD8175 crosspoint switches to produce
a high resolution video distribution system.
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD8141/AD8142
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
Maximum Power Dissipation ..................................................... 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 8
Basic Test Circuit ........................................................................ 13
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
Analyzing an Application Circuit............................................. 15
Closed-Loop Gain ...................................................................... 15
Calculating an Application Circuit’s Input Impedance ......... 15
Input Common-Mode Voltage Range in Single-Supply
Applications ................................................................................ 16
Terminating a Single-Ended Input........................................... 16
Driving a Capacitive Load......................................................... 17
Disable ......................................................................................... 17
AD8142 Sync-On-Common-Mode ......................................... 17
Applications Information .............................................................. 18
Driving RGB Video Over Cat-5 Cable .................................... 18
Single 5 V Supply Application Information ............................ 19
AD8142 Signal Levels on Various Supplies ............................ 20
Disable Feature ........................................................................... 20
Driving Multiple Outputs.......................................................... 21
Video Sync-On-Common-Mode (AD8142) ........................... 21
Layout and Power Supply Decoupling Considerations ......... 22
Amplifier-to-Amplifier Isolation ............................................. 22
Exposed Paddle (EPAD) ............................................................ 22
Typical AD8142 5 V Application Circuit ................................ 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
3/2017—Rev. A to Rev. B
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
4/2013—Rev. 0 to Rev. A
Changed Gain to Green Common-Mode Output Maximum
Parameter from 1.2 V/V to 2.20 V/V; Table 1............................... 3
7/2011—Revision 0: Initial Version
Rev. B | Page 2 of 24
Data Sheet
AD8141/AD8142
SPECIFICATIONS
VS+ = 5 V, VS− = 0 V, RL, dm = 200 Ω, TA = 25°C, VOCM = 1.5 V (AD8141), HSYNC, VSYNC, and SYNC LEVEL = 0 V (AD8142), unless otherwise noted.
Table 1.
Parameter
DIFFERENTIAL INPUT PERFORMANCE
Dynamic Performance
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
Isolation Between Amplifiers
Differential Input Characteristics
Input Common-Mode Voltage Range
Input Resistance
Input Capacitance
DC CMRR
Differential Output Characteristics
Differential Signal Gain
Output Voltage Swing
Output Offset Voltage
Output Offset Drift
Output Balance Error
Output Voltage Noise (RTO)
Maximum Number of Parallel Loads
COMMON-MODE INPUT PERFORMANCE (AD8141)
VOCM Dynamic Performance
−3 dB Bandwidth
Slew Rate
DC Gain
VOCM Input Characteristics
Input Voltage Range
Input Resistance
Input Offset Voltage
DC CMRR
COMMON-MODE SYNC PERFORMANCE (AD8142)
Slew Rate
Nominal Output Common-Mode Level
HSYNC AND VSYNC INPUTS (AD8142)
Input Low Voltage
Input High Voltage
SYNC LEVEL INPUT (AD8142)
Input Voltage Range
Setting to Achieve 0.5 V Pulse Levels
Gain to Red Common-Mode Output
Gain to Green Common-Mode Output
Gain to Blue Common-Mode Output
Test Conditions/Comments
Min
VO = 0.2 V p-p, AD8141/AD8142
VO = 2 V p-p, AD8141/AD8142
VO = 2 V p-p
VO = 2 V p-p, 25% to 75% (rise/fall)
VO = 2 V step
f = 10 MHz, between Amplifier R and
Amplifier G
Typ
275/285
255/265
65
1150/1250
12
−100
VOCM = Vs+/2
Differential
Single-ended input
Differential
ΔVOUT, dm/ΔVIN, cm, ΔVIN, cm = ±1 V
VS− + 0.2
ΔVOUT, dm/ΔVIN, dm, ΔVIN, dm = ±1 V
Each single-ended output
1.95
VS− + 0.18
−70
2
1.5
±30
−50
−66
41
4
ΔVOCM = 100 mV p-p
VOCM = 0.5 V to 2.5 V, 25% to 75% (rise/fall)
ΔVOCM = ±1 V
114
130/155
1.00
0.98
VS− + 0.2
Thevenin to midsupply
−87
ΔVOUT, dm/ΔVOCM; ΔVOCM = ±1 V
VOUT, cm = 0.5 V to +2.5 V; 25% to 75%
(rise/fall)
Referenced to GND
Referenced to GND
Rev. B | Page 3 of 24
VS+ − 1
V
kΩ
kΩ
pF
dB
2.04
VS+ − 0.4
+70
V/V
V
mV
µV/°C
dB
dB
nV/√Hz
Loads
1.02
+26
MHz
V/µs
V/V
V
kΩ
mV
dB
130/155
V/µs
VS− + 1.5
V
0 to 1.6
1.9 to 5
V
V
VS−
0.85
1.80
−1.15
−43
VS+ − 0.2
2.8
−30
−60
Unit
MHz
MHz
MHz
V/µs
ns
dB
2
1.5
2
−60
TMIN to TMAX
f = 50 MHz
DC
f = 20 MHz
1.4 V p-p into 200 Ω per load
Referenced to VS−
Referenced to VS−
ΔVOUT, cm/ΔVSYNC LEVEL
ΔVOUT, cm/ΔVSYNC LEVEL
ΔVOUT, cm/ΔVSYNC LEVEL
Max
VS− + 1
VS− + 0.5
1.00
2.00
−1.00
1.15
2.20
−0.85
V
V
V/V
V/V
V/V
AD8141/AD8142
Parameter
POWER SUPPLY
Operating Range
Quiescent Current
PSRR
OUTPUT HIGH-Z PERFORMANCE
DIS Input Low Voltage
DIS Input High Voltage
DIS Assert Time
DIS Deassert Time
Differential Output Impedance Magnitude
With DIS Asserted
ISOLATION
Input-to-Output
Data Sheet
Test Conditions/Comments
Min
Positive supply
AD8141/AD8142
Disabled
4.5
Typ
44/47
1.2
−77
Max
Unit
5.5
56/57
1.6
V
mA
mA
dB
1 MHz, each output, DIS input at VS+
0 to 1.6
1.9 to VS+
5
50
11
V
V
ns
ns
kΩ
10 MHz, each output, DIS input at VS+
1.9
kΩ
1 MHz, each output, DIS input at VS+
10 MHz, each output, DIS input at VS+
−78
−58
dB
dB
Rev. B | Page 4 of 24
Data Sheet
AD8141/AD8142
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
HSYNC, VSYNC, SYNC LEVEL
Power Dissipation
Input Common-Mode Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
Rating
5.5 V
VS−/VS+
See Figure 3
VS−/VS+
−65°C to +125°C
−40°C to +85°C
300°C
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
common-mode currents flowing to the loads, as well as currents
flowing through the internal differential and common-mode
feedback loops. The internal resistor tap used in the commonmode feedback loop places a 12.5 kΩ differential load on the
output. RMS output voltages should be considered when
dealing with ac signals.
Airflow reduces θJA. In addition, more metal directly in contact
with the package leads from metal traces, through holes, ground,
and power planes reduce the θJA. The exposed pad on the underside
of the package must be soldered to a pad on the PCB surface that is
thermally connected to a PCB plane to achieve the specified θJA.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 24-lead LFCSP
(38°C/W) on a JEDEC standard 4-layer board with the underside
paddle soldered to a pad that is thermally connected to a PCB
plane. θJA values are approximations.
6
MAXIMUM POWER DISSIPATION (W)
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for the device soldered in a circuit board in still air.
Table 3. Thermal Resistance with the Underside Pad
Thermally Connected to a Copper Plane
Package Type/PCB Type
24-Lead LFCSP/4-Layer
θJA
38
θJC
4.7
Unit
°C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8141/AD8142
package is limited by the associated rise in junction temperature
(TJ) on the die. At approximately 150°C, which is the glass
transition temperature, the plastic changes its properties. Even
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the AD8141/AD8142. Exceeding
a junction temperature of 175°C for an extended period can result
in changes in the silicon devices potentially causing failure.
5
4
3
2
1
0
–40
–20
0
20
40
AMBIENT TEMPERATURE (°C)
60
80
09461-055
Table 2.
Figure 3. Maximum Power Dissipation vs. Ambient Temperature for a
4-Layer Board
ESD CAUTION
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The load current consists of differential and
Rev. B | Page 5 of 24
AD8141/AD8142
Data Sheet
19 VOCMB
21 VS–/GND
20 VOCMA
23 –IN B
22 +IN B
24 VS+
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
18 VOCMC
17 VS+
DIS 1
VS–/GND 2
–IN A 3
AD8141
+IN A 4
TOP VIEW
(Not to Scale)
15 +IN C
14 VS– /GND
–OUT A 6
+OUT C 12
VS+ 11
–OUT B 10
+OUT B 9
+OUT A 7
VS+ 8
13 –OUT C
NOTES
1. CONNECT EXPOSED PADDLE TO GROUND.
09461-004
VS–/GND 5
16 –IN C
Figure 4. AD8141 Pin Configuration
Table 4. AD8141 Pin Function Descriptions
Pin No.
1
2, 5, 14, 21
3
4
6
7
8, 11, 17, 24
9
10
12
13
15
16
18
19
20
22
23
Mnemonic
DIS
VS−/GND
−IN A
+IN A
−OUT A
+OUT A
VS+
+OUT B
−OUT B
+OUT C
−OUT C
+IN C
−IN C
VOCMC
VOCMB
VOCMA
+IN B
−IN B
EPAD
Description
Disable. This pin places outputs in high-Z condition and lowers supply current.
Negative Power Supply Voltage.
Inverting Input, Amplifier A.
Noninverting Input, Amplifier A.
Negative Output, Amplifier A.
Positive Output, Amplifier A.
Positive Power Supply Voltage.
Positive Output, Amplifier B.
Negative Output, Amplifier B.
Positive Output, Amplifier C.
Negative Output, Amplifier C.
Noninverting Input, Amplifier C.
Inverting Input, Amplifier C.
The voltage applied to this pin controls the output common-mode voltage for Amplifier C.
The voltage applied to this pin controls the output common-mode voltage for Amplifier B.
The voltage applied to this pin controls the output common-mode voltage for Amplifier A.
Noninverting Input, Amplifier B.
Inverting Input, Amplifier B.
Connect Exposed Paddle to Ground.
Rev. B | Page 6 of 24
20 VSYNC
19 H SYNC
22 +IN G
21 VS– /GND
AD8141/AD8142
24 VS+
23 –IN G
Data Sheet
18 SYNC LEVEL
17 VS+
DIS 1
VS–/GND 2
AD8142
16 –IN B
TOP VIEW
(Not to Scale)
15 +IN B
14 VS–/GND
13 –OUT B
VS+ 11
+OUT B 12
+OUT G 9
–OUT G 10
+OUT R 7
VS+ 8
–OUT R 6
NOTES
1. CONNECT EXPOSED PADDLE TO GROUND.
09461-005
–IN R 3
+IN R 4
VS–/GND 5
Figure 5. AD8142 Pin Configuration
Table 5. AD8142 Pin Function Descriptions
Pin No.
1
2, 5, 14, 21
3
4
6
7
8, 11, 17, 24
9
10
12
13
15
16
18
Mnemonic
DIS
VS−/GND
−IN R
+IN R
−OUT R
+OUT R
VS+
+OUT G
−OUT G
+OUT B
−OUT B
+IN B
−IN B
SYNC LEVEL
19
20
22
23
HSYNC
VSYNC
+IN G
−IN G
EPAD
Description
Disable. This pin places outputs in high-Z condition and lowers supply current.
Negative Power Supply Voltage. GND is for single 5 V applications.
Inverting Input, Red Amplifier.
Noninverting Input, Red Amplifier.
Negative Output, Red Amplifier.
Positive Output, Red Amplifier.
Positive Power Supply Voltage.
Positive Output, Green Amplifier.
Negative Output, Green Amplifier.
Positive Output, Blue Amplifier.
Negative Output, Blue Amplifier.
Noninverting Input, Blue Amplifier.
Inverting Input, Blue Amplifier.
The voltage applied to this pin with respect to VS−/GND controls the amplitude of the sync pulses
that are applied to the common-mode voltages.
Horizontal Sync Pulse Input with Respect to Ground.
Vertical Sync Pulse Input with Respect to Ground.
Noninverting Input, Green Amplifier.
Inverting Input, Green Amplifier.
Connect Exposed Paddle to Ground.
Rev. B | Page 7 of 24
AD8141/AD8142
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VS+ = 5 V, VS− = 0 V, RL, dm = 200 Ω, TA = 25°C, VOCM = 1.5 V (AD8141), HSYNC, VSYNC, and SYNC LEVEL = 0 V (AD8142), unless otherwise noted.
9
9
VOUT, dm = 2V p-p
6
6
3
3
GAIN (dB)
0
–3
AD8142
AD8141
1
10
100
FREQUENCY (MHz)
1k
AD8142
–6
09461-007
AD8141
–6
1
Figure 6. Small Signal Frequency Response
10
100
FREQUENCY (MHz)
Figure 9. Large Signal Frequency Response
9
9
VOUT, dm = 2V p-p
6
3
3
0
–3
0
–3
–6
–6
–9
–9
–12
1
10
100
FREQUENCY (MHz)
1k
–12
1
Figure 7. Small Signal Frequency Response at VOCM = 2.5 V (AD8141)
1k
Figure 10. Large Signal Frequency Response at VOCM = 2.5 V (AD8141)
6.7
6.7
VOUT, dm = 200mV p-p
VOUT, dm = 2V p-p
6.6
6.5
6.5
6.4
6.4
6.3
6.3
GAIN (dB)
6.6
6.2
6.1
6.2
6.1
6.0
6.0
5.9
5.9
5.8
5.8
AD8141
1
AD8142
10
100
FREQUENCY (MHz)
AD8141
1k
5.7
09461-009
GAIN (dB)
10
100
FREQUENCY (MHz)
09461-011
GAIN (dB)
6
09461-008
GAIN (dB)
VOUT, dm = 200mV p-p
5.7
1k
09461-010
–3
0
Figure 8. Small Signal 0.1 dB Flatness
1
AD8142
10
100
FREQUENCY (MHz)
Figure 11. Large Signal 0.1 dB Flatness
Rev. B | Page 8 of 24
1k
09461-012
GAIN (dB)
VOUT, dm = 200mV p-p
Data Sheet
0
100k
ΔVOUT, cm/ΔVOUT, dm
ΔVOUT, dm = 2V p-p
–10
–20
OUTPUT NOISE (nV/ Hz)
OUTPUT BALANCE ERROR (dB)
AD8141/AD8142
–30
–40
–50
–60
10k
1k
100
1
10
100
FREQUENCY (MHz)
1k
10
10
09461-013
–80
10k
100k
FREQUENCY (Hz)
1M
10M
100M
–30
–30
VOUT, dm = 2V p-p
VOUT, dm = 2V p-p
–40
–40
–50
–50
HD2
HD2
DISTORTION (dBc)
–60
–70
HD3
–80
–90
–60
HD3
–70
–80
–90
–100
1
10
FREQUENCY (MHz)
100
–110
0.1
09461-014
–120
0.1
1
10
FREQUENCY (MHz)
100
09461-017
–100
–110
Figure 16. AD8142 Harmonic Distortion vs. Frequency
Figure 13. AD8141 Harmonic Distortion vs. Frequency
–30
–20
DIS INPUT VOLTAGE = 5V
GREEN TO RED,
ΔVOUT, dm R/ΔVIN, dm G
–40
–60
–50
ISOLATION (dB)
–40
–80
RED
–100
–120
–60
–70
–80
1
10
100
FREQUENCY (MHz)
1k
–90
09461-015
–140
1
10
100
FREQUENCY (MHz)
1k
Figure 17. Disabled Input-to-Output Isolation vs. Frequency
Figure 14. Channel-to-Channel Isolation vs. Frequency
Rev. B | Page 9 of 24
09461-018
DISTORTION (dBc)
1k
Figure 15. Output Voltage Noise Density vs. Frequency
Figure 12. Output Balance Error vs. Frequency
ISOLATION (dB)
100
09461-016
–70
AD8141/AD8142
–30
ΔVOUT, dm/ΔVIN, cm
ΔVIN, cm = 1V p-p
–30
–40
–50
–60
–70
1k
–60
–70
–80
AD8141 V S+
AD8142 V S+
–90
1
Figure 18. Common-Mode Rejection vs. Frequency
10
100
FREQUENCY (MHz)
30
2.0
VS+ = +2.5V
VS– = –2.5V
VIN = 0.7VDC
VOCM = GND
DIFFERENTIAL OUTPUT VOLTAGE (V)
DIRECTLY AT DRIVER OUTPUT
10k
1k
100
10
1
10
100
FREQUENCY (MHz)
1k
09461-020
DIFFERENTIAL OUTPUT
1.5
25
1.0
20
0.5
15
0
10
–0.5
5
DIS PIN
–1.0
0
–1.5
0
40
80
120
160
200
240
280
320
360
–5
400
TIME (ns)
Figure 19. Disabled Output Impedance Magnitude vs. Frequency
Figure 22. Disable Response Time
0.15
1.5
AD8142
AD8141
DIFFERENTIAL OUTPUT VOLTAGE (V)
AD8141
0.10
0.05
0
–0.05
–0.15
0
5
10
15
20
25
30
TIME (ns)
35
40
45
50
09461-021
–0.10
Figure 20. Small Signal Transient Response
AD8142
1.0
0.5
0
–0.5
–1.0
–1.5
0
5
10
15
20
25
30
TIME (ns)
35
40
Figure 23. Large Signal Transient Response
Rev. B | Page 10 of 24
45
50
09461-024
DIFFERENTIAL OUTPUT
IMPEDANCE MAGNITUDE (Ω)
1k
Figure 21. Power Supply Rejection vs. Frequency
100k
DIFFERENTIAL OUTPUT VOLTAGE (V)
AD8141 VS–
AD8142 VS–
DIS PIN VOLTAGE (V)
10
100
FREQUENCY (MHz)
–50
09461-051
1
–40
09461-022
POWER SUPPLY REJECTION (dB)
±2.5V SUPPLIES
ΔSUPPLY = ±0.5V
09461-019
COMMON-MODE REJECTION (dB)
–20
Data Sheet
Data Sheet
AD8141/AD8142
1.5
0.10
0.05
0
–0.05
–0.10
5
10
15
20
25
30
TIME (ns)
35
40
45
50
4
0.25
2
ERROR
0
0
–0.25
–2
0.1% SETTLED POINT
–0.50
–4
–0.75
–6
–1.00
16
12
20
24
28
32
36
TIME (ns)
40
45
50
VS+ = +2.5V
VS– = –2.5V
VOCM = 0V
SINGLE-ENDED DRIVE
4
3
2
1
0
–1
–2
–3
2× INPUT
VOUT_DIFF
–4
0
100
200
300
400 500 600
TIME (ns)
700
800
900
1000
Figure 28. AD8141 Differential Overdrive Recovery
Figure 25. Differential Settling Time
–35
58
RL, dm = OPEN CIRCUIT
RL, dm = OPEN CIRCUIT
–37
POWER SUPPLY CURRENT (mA)
56
54
52
AD8142
50
48
AD8141
46
44
42
–39
–41
–43
AD8141
–45
AD8142
–47
–49
0
20
40
TEMPERATURE (°C)
60
80
100
–53
–40
09461-027
–20
–20
0
20
40
TEMPERATURE (°C)
60
80
100
Figure 29. Negative Power Supply Current vs. Temperature
Figure 26. Positive Power Supply Current vs. Temperature
Rev. B | Page 11 of 24
09461-030
–51
40
38
–40
35
–7
09461-054
–10
8
25
30
TIME (ns)
–6
–1.25
4
20
–5
–8
0
15
5
0.5% SETTLED POINT
–4
10
6
DIFFERENTIAL VOLTAGE (V)
0.50
5
7
SETTLING ERROR VOLTAGE (mV)
6
INPUT
–1.0
Figure 27. Large Signal Transient Response, VOCM = 2.5 V (AD8141)
8
0.75
POWER SUPPLY CURRENT (mA)
INPUT AND OUTPUT VOLTAGE (V)
1.00
–0.5
0
10
OUTPUT
0
–1.5
Figure 24. Small Signal Transient Response, VOCM = 2.5 V (AD8141)
1.25
0.5
09461-029
0
09461-025
–0.15
1.0
09461-028
DIFFERENTIAL OUTPUT VOLTAGE (V)
DIFFERENTIAL OUTPUT VOLTAGE (V)
0.15
AD8141/AD8142
Data Sheet
0.14
4.70
0.12
4.65
NEGATIVE SWING
0.10
4.60
0.08
4.55
0.06
4.50
–40
–20
0
20
40
TEMPERATURE (°C)
60
80
0.04
100
VOCM = 1.5V
2.5
2.0
1.5
1.0
0.5
0
0
–40
3
VOCM COMMON-MODE REJECTION (dB)
∆VOUT, cm/∆VOCM
VOUT, cm = 100mV p-p
0
–3
–6
10
100
FREQUENCY (MHz)
1k
20
30
40
50
60
TIME (ns)
70
80
90
100
∆VOUT, dm/∆VOCM
∆VOCM = 2V p-p
–45
–50
–55
–60
–65
–70
–75
09461-032
–9
1
10
Figure 32. VOCM Large Signal Transient Response (AD8141)
Figure 30. Output Saturation vs. Temperature
–12
3.0
09461-033
0.16
3.5
1
10
100
FREQUENCY (MHz)
Figure 33. VOCM Common-Mode Rejection vs. Frequency
Figure 31. VOCM Frequency Response (AD8141)
Rev. B | Page 12 of 24
1k
09461-044
POSITIVE SWING
4.75
VS+ = 5V
VS– = 0V
VOCM = 2.5V
DIFFERENTIAL OUTPUT VOLTAGE (V)
4.80
NEGATIVE OUTPUT SATURATION VOLTAGE (V)
0.18
4.0
09461-031
0.20
SINGLE-ENDED OUTPUT VOLTAGE
GAIN (dB)
POSITIVE OUTPUT SATURATION VOLTAGE (V)
4.85
Data Sheet
AD8141/AD8142
2.25
17.5
SYNC LEVEL = 0.5V
GCM
2.00
12.5
RCM
1.50
BCM
1.25
7.5
1.00
SYNC INPUT VOLTAGE (V)
CHANNEL OUTPUT COMMON-MODE VOLTAGE (V)
1.75
0.75
HSYNC
VSYNC
2.5
0.50
0
0
10
20
30
40
50
60
70
80
90
TIME (ns)
Figure 34. AD8142 Output Common-Mode Signals for Various Sync Pulse Inputs
BASIC TEST CIRCUIT
+5V
VS+
0.1µF ON ALL VS+ PINS
AD8141/AD8142
50Ω
2kΩ
52.3Ω
–
RL, dm 200Ω
50Ω
52.3Ω
MIDSUPPLY
1kΩ
2kΩ
VS–
Figure 35. Basic Test Circuit
Rev. B | Page 13 of 24
VOUT, dm
+
09461-006
VTEST
TEST
SIGNAL
SOURCE
1kΩ
–2.5
100
09461-050
0.25
AD8141/AD8142
Data Sheet
TERMINOLOGY
Differential Voltage
Differential voltage refers to the difference between two node
voltages that are balanced with respect to each other. For example,
in Figure 36, the output differential voltage (or output differential
mode voltage) is defined as
VOUT, dm = (VOP − VON)
Common-mode voltage refers to the average of two node voltages
with respect to a common reference (usually the local ground).
The output common-mode voltage is defined as
VOUT , cm =
(VOP + VON )
2
Output Balance
Output balance is a measure of how well the differential output
signals are matched in amplitude and how close they are to exactly
180° apart in phase. Balance can be easily determined by placing a
well-matched resistor divider between the differential output
voltage nodes and comparing the magnitude of the signal at the
divider’s midpoint with the magnitude of the differential signal.
By this definition, output balance error is the magnitude of the
change in output common-mode voltage divided by the magnitude
of the change in output differential-mode voltage in response to
a differential input signal.
Output Balance Error =
Rev. B | Page 14 of 24
∆VOUT , cm
∆VOUT , dm
Data Sheet
AD8141/AD8142
THEORY OF OPERATION
Previous differential drivers, both discrete and integrated designs,
have been based on using two independent amplifiers and two
independent feedback loops, one to control each of the outputs.
When these circuits are driven from a single-ended source, the
resulting outputs are typically not well balanced. Achieving a
balanced output has generally required exceptional matching
of the amplifiers and feedback networks.
DC common-mode level-shifting has also been difficult with
previous differential drivers. Level-shifting has required the
use of a third amplifier and feedback loop to control the output
common-mode level. Sometimes, the third amplifier has also
been used to attempt to correct an inherently unbalanced circuit.
Excellent performance over a wide frequency range has proven
difficult with this approach.
Each AD8141/AD8142 driver uses two feedback loops to
separately control the differential and common-mode output
voltages. The differential feedback, set by the internal resistors,
controls the differential output voltage only. The internal commonmode feedback loop controls the common-mode output voltage
only. This architecture makes it easy to arbitrarily set the output
common-mode level by simply applying a voltage to the VOCM
input. The output common-mode voltage is forced, by internal
common-mode feedback, to equal the voltage applied to the VOCM
input, while simultaneously balancing the differential output voltage.
The AD8141 VOCM inputs are available to the user, whereas the
AD8142 VOCM inputs are internally connected to sync-on-commonmode circuitry that automatically imbeds the HSYNC and VSYNC
signals on the three output common-mode voltages.
The overall driver architecture produces outputs that are highly
balanced over a wide frequency range without requiring external
components or adjustments. The common-mode feedback loop
forces the signal component of the output common-mode voltage
to be zeroed. The result is nearly perfectly balanced differential
outputs of identical amplitude that are 180° apart in phase.
ANALYZING AN APPLICATION CIRCUIT
The drivers use two negative feedback loops, each with high
open-loop gain, to force their differential and common-mode
output voltages in such a way as to minimize the differential
and common-mode input error voltages. The differential input
error voltage is defined as the voltage between the differential
inputs labeled VAP and VAN in Figure 36. For most purposes, this
voltage can be assumed to be zero. Similarly, the difference between
the actual output common-mode voltage and the voltage applied to
VOCM can also be assumed to be zero. Starting from these two
assumptions, any application circuit can be analyzed.
CLOSED-LOOP GAIN
The differential mode gain of the circuit in Figure 36 can be
described by
VOUT, dm
VIN, dm
RF
2
RG
where RF = 2.0 kΩ and RG = 1.0 kΩ nominally.
RF
+
VIP
VIN, dm VOCM
– VIN
RG
VAP
RL, dm
RG
VAN
RF
VON
VOUT, dm
VOP
09461-034
The differential drivers contained in the AD8141 and AD8142
differ from conventional op amps in that they have two outputs
whose voltages move in opposite directions. Like op amps, they
rely on high open-loop gain and negative feedback to force these
outputs to the desired voltages. The AD8141 and AD8142
drivers make it easy to perform single-ended-to-differential
conversion, common-mode level-shifting, and amplification
of differential signals.
Figure 36. Circuit Definitions
CALCULATING AN APPLICATION CIRCUIT’S INPUT
IMPEDANCE
The effective input impedance of a circuit such as that in Figure 36
at VIP and VIN depends on whether the amplifier is being driven
by a single-ended or differential signal source. For balanced
differential input signals, the differential input impedance, RIN, dm
between the inputs VIP and VIN is simply
RIN, dm = 2 × RG = 2.0 kΩ
In the case of a single-ended input signal (for example, if VIN
is grounded and the input signal is applied to VIP), the input
impedance becomes
RIN
RG
1.5 kΩ
RF
1
2 RG RF
The input impedance of the circuit is higher than for a
conventional op amp connected as an inverter because a
fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor RG.
Rev. B | Page 15 of 24
AD8141/AD8142
Data Sheet
RF
2kΩ
INPUT COMMON-MODE VOLTAGE RANGE IN
SINGLE-SUPPLY APPLICATIONS
The driver inputs are designed to facilitate level-shifting of ground
referenced input signals on a single power supply. For a singleended input, this implies, for example, that the voltage at VIN in
Figure 36 is 0 V when the amplifier’s negative power supply
voltage is also set to 0 V.
RF
2kΩ
RG
1kΩ
RG
1kΩ
RTS
38.3Ω
+
RL
VOUT, dm
–
RG
1kΩ
+VS
+
AD8141/
AD8142
RL VOUT, dm
–
–VS
RF
2kΩ
09461-038
VTH
0.725V p-p
+5V
AD8141/
AD8142
09461-036
1. RTH = RS||RT = 38.8 Ω, and RTS = 38.3 Ω. Note that VTH
is greater than 0.7 V p-p, which was obtained with RT = 75
Ω alone. The modified circuit with the Thevenin equivalent
of the terminated source and RTS in the lower feedback loop
is shown in Figure 40.
RTH
38.8Ω
Figure 40. Thevenin Equivalent and Matched Gain Resistors
RF
2kΩ
09461-035
RG
1kΩ
VTH
0.725V p-p
Figure 39. Calculating the Thevenin Equivalent
RF
2kΩ
Figure 37. Calculating Single-Ended Input Impedance, RIN
2.
RTH
38.8Ω
RT
80.6Ω
VS
1.4V p-p
The single-ended input impedance is calculated as
RIN = 1.5 kΩ.
VS
1.4V p-p
–
RS
75Ω
Each driver has a nominal fixed gain of 2, with RF = 2.0 kΩ and
RG = 1.0 kΩ. A typical single-ended video signal source applied to
the AD8141/AD8142 input has a maximum terminated output
voltage of 0.7 V p-p and source resistance of 75 Ω. Because the
terminated output voltage of the source is 0.7 V p-p, the opencircuit output voltage of the source is 1.4 V p-p. The source shown
in Figure 37 indicates this open-circuit voltage. The following
three steps illustrate how to terminate a signal from a typical
single-ended 75 Ω video source.
RS
75Ω
RL VOUT, dm
It can be seen from Figure 38 that the effective RG in the
upper feedback loop is now greater than the RG in the
lower loop due to the addition of the termination resistors.
To compensate for the imbalance of the gain resistors, a
correction resistor (RTS) is added in series with RG in the
lower loop. RTS is the closest 1% resistor to the Thevenin
equivalent of the source resistance RS and the termination
resistance RT, equal to RS||RT.
VIP VIN
2
RIN
1.5kΩ
AD8141/
AD8142
RG
1kΩ
09461-037
3.
VOCM 2VICM
3
VIDEO SOURCE
+
Figure 38. Adding Termination Resistor RT
TERMINATING A SINGLE-ENDED INPUT
1.
+VS
RG
1kΩ
RT
80.6Ω
VS
1.4V p-p
where VICM is the common-mode voltage of the input signal,
that is,
VICM
RIN
75Ω
–VS
RF
2kΩ
It is important to ensure that the common-mode voltage at the
amplifier inputs, VAP and VAN, stays within its specified range.
Because the VAP and VAN voltages are driven to be essentially
equal by negative feedback, the amplifier’s input common-mode
voltage can be expressed as a single term, VACM. VACM can be
calculated as
VACM
RS
75Ω
To match the 75 Ω source resistance, the termination resistor,
RT, is calculated using RT||1.125 kΩ = 75 Ω. The closest
standard 1% value for RT is 80.6 Ω.
Figure 40 presents a tractable circuit with matched feedback
loops that can be easily evaluated.
It is useful to point out two effects that occur with a terminated
input. The first is that the value of RG is increased in both loops,
lowering the overall closed-loop gain. The second is that VTH is
a little larger than 0.7 V p-p, as it is if RT = 75 Ω alone. These
two effects have opposite impacts on the output voltage, and for
large resistor values in the feedback loops, the effects essentially
cancel each other out. For smaller RF and RG, however, the
diminished closed-loop gain is not canceled completely by the
increased VTH.
Rev. B | Page 16 of 24
Data Sheet
AD8141/AD8142
The desired differential output in this example is 1.4 V p-p
because the terminated input signal is 0.7 V p-p and the closedloop gain = 2. The actual differential output voltage is equal to
(0.725 V p-p)(2 kΩ/1038.3 Ω) = 1.4 V p-p. This illustrates how
the two aforementioned effects cancel for large RF and RG.
AD8142 SYNC-ON-COMMON-MODE
The AD8142 includes on-chip, sync-on-common-mode circuitry
that encodes externally applied HSYNC and VSYNC signals onto the
common-mode output voltages of each of the R, G, and B drivers.
The circuit encodes the horizontal and vertical sync pulses in a
way that results in low radiated energy. A simplified circuit that
illustrates how the pulses are encoded is shown in Figure 41.
For a more detailed description of the sync scheme, see the
Applications Information section.
DRIVING A CAPACITIVE LOAD
A purely capacitive load can react with the output impedance of
the drivers to reduce phase margin, resulting in high frequency
ringing in the pulse response. The best way to minimize this effect
is to place the source termination resistors immediately at the
amplifier outputs to minimize parasitic capacitances formed by
unnecessarily long traces.
The sync-on-common-mode circuit generates a current based
on the voltage applied to the SYNC LEVEL input pin (Pin 18)
with respect to the negative supply. With SYNC LEVEL input
tied to VS−, the common-mode output of all drivers is set at 1.5 V
above the negative supply. Using a resistor divider, a voltage can
be applied between VS− and SYNC LEVEL that determines the
maximum deviation of the common-mode outputs from their
midsupply level. If, for instance, SYNC LEVEL − VS− = 0.5 V
and the supply voltage is 5 V, then the common-mode outputs
fall within an envelope of 1.5 V ± 0.5 V. The state of each VOUT, cm
output based on the HSYNC and VSYNC inputs is determined by
the equations defined in the Applications Information section.
DISABLE
The AD8141 and AD8142 have disable pins that, when pulled high,
significantly reduce the power consumed while simultaneously
placing the outputs in high-Z states. The disable feature can be
used to multiplex two drivers. See Figure 17, Figure 19, and
Figure 22 for the disabled input-to-output isolation, output
impedance, and response performance. The threshold levels
for the disable pin are listed in Table 1.
An output glitch occurs whenever the disable feature is asserted or
deasserted. See the Applications Information section for details.
For the positive supplies between 2.5 V and 5 V, the sync-oncommon-mode circuit can be used by directly applying standard
HSYNC and VSYNC signals to the respective AD8142 inputs. These
inputs adhere to standard logic thresholds (see Table 1 for the
exact levels). The HSYNC and VSYNC inputs, therefore, can be
driven directly off the output of a computer video card without
concern of being overdriven. The input path from the HSYNC and
VSYNC inputs to the switches in the current mode level-shifting
circuit are well matched to eliminate false switching transients. This
maximizes common-mode balance and minimizes radiated energy.
VS+
MIRROR
H
HSYNC
V
V
V
V
R
R
RED VOCM
V
H
R
GREEN VOCM
BLUE VOCM
H
SYNC LEVEL
H
H
V
V
MIRROR
R
VS–
Figure 41. Sync-On-Common-Mode Simplified Circuit
Rev. B | Page 17 of 24
V
R
R
R
09461-039
VSYNC
H
AD8141/AD8142
Data Sheet
APPLICATIONS INFORMATION
DRIVING RGB VIDEO OVER CAT-5 CABLE
automatically compensates for the losses incurred by the source
and load terminations. Figure 42 shows the AD8141/AD8142 in
a triple, single-ended-to-differential application when driven from
a 75 Ω video source.
The AD8141 and AD8142 are devices whose foremost application
is driving RGB and component video signals over unshielded
twisted pair (UTP) cable in video distribution networks. Singleended video signals are easily converted to differential signals
for transmission over the cable, and the internally fixed gain of 2
+5V
VS–
AD8141/AD8142
0.1µF ON ALL VS+
PINS
2kΩ
1kΩ
75Ω
RED
VIDEO
SOURCE
80.6Ω
1kΩ
38.3Ω
49.9Ω
+
R
–
49.9Ω
RED UTP
2kΩ
2kΩ
1kΩ
75Ω
GREEN
VIDEO
SOURCE
80.6Ω
1kΩ
38.3Ω
49.9Ω
+
G
–
49.9Ω
GREEN UTP
2kΩ
2kΩ
1kΩ
BLUE
VIDEO
SOURCE
80.6Ω
DIS
1kΩ
38.3Ω
49.9Ω
+
B
–
49.9Ω
BLUE UTP
2kΩ
DISABLE
VS–
09461-040
75Ω
Figure 42. AD8141/AD8142 in Single-Ended-to-Differential Application on Single 5 V Supply (Sync Pulse Encoding Not Shown)
Rev. B | Page 18 of 24
Data Sheet
AD8141/AD8142
In Figure 43, VR, CM = VO, CM + VSHIFT. If VO, CM = 0 V and VSHIFT =
2 V, VR, CM is 2 V. This is because the receiver ground is shifted
down by 2 V relative to the driver ground, and the commonmode level on the cable stays constant. It can be seen from this
example that the most margin to absorb ground shifts exists
when the center of the receiver input common-mode voltage
range relative to its ground is the same as the output commonmode voltage of the driver with respect to its ground.
SINGLE 5 V SUPPLY APPLICATION INFORMATION
The AD8141 and AD8142 require a nominal voltage of 5 V
across their VS+ and VS− power supply pins, and that their EPADs
be connected to system ground; the voltage between VS+ and the
local system ground must be greater than or equal to 2.5 V and
less than or equal to 5 V. These requirements can be met by a
single +5 V supply, or split supplies such as ±2.5 V, +3 V/−2 V,
and so on. Operating the AD8141 and AD8142 with ±2.5 V
supplies provides considerable power savings compared with
other drivers operating at ±5 V supplies, without any disadvantages
with regard to input and output ranges in most cases.
Most receivers operate with their input common-mode ranges
centered at 0 V; therefore, the best case for the driver is to set its
output common-mode voltage to 0 V. This is not possible for
the AD8141 or AD8142 on a single 5 V supply, but it can be
accomplished using split supplies. If a single 5 V supply is required,
the rail-to-rail output allows the AD8141 output common-mode
voltage to be set to less than 1 V to be as close as possible to the
ideal setting of 0 V. Whereas the AD8141 has uncommitted
VOCM inputs, the AD8142 has internal sync-encoding circuitry
that fixes the nominal output common-mode voltage at 1.5 V
above the negative rail. Each part has a resistive divider on the
VOCM input that sets the nominal output common-mode voltage
to 1.5 V above the negative rail when no external voltage is applied.
The divider consists of a 8.75 kΩ resistor to VS+ and a 3.75 kΩ
resistor to VS−, forming a Thevenin equivalent load of 2.6 kΩ to
30% of the voltage across the supplies. In the single 5 V supply
case, the Thevenin load voltage is 30% of 5 V above 0 V, or 1.5 V.
The receivers used with the AD8141 and AD8142, such as the
AD8145, AD8143, AD8123, and AD8128, generally operate
with split supplies, ranging from ±5 V to ±12 V. The split supply
arrangement results in a receiver input common-mode range
that is centered at 0 V relative to the local ground reference and
ranges to within a volt or two from each rail. Ground potential
differences normally exist between the driver end and the receiver
end, and these differences cause the relative common-mode
voltages between the driver and receiver to shift. See Figure 43
for an example.
DRIVER
AD8141/AD8142
49.9Ω
VOCM
–
49.9Ω
–
100Ω
UTP
100Ω
+
+
+
VO, CM
VR, CM
–
–
+–
VSHIFT
Figure 43. End-to-End Common-Mode Shifts due to Ground Shifts
Rev. B | Page 19 of 24
09461-041
+
AD8141/AD8142
Data Sheet
The disable pin is a binary input that controls the state of the
AD8141/AD8142 outputs. Its binary input levels are compatible
with most TTL and CMOS families (see Table 1 for the logic
levels). The AD8141/AD8142 output is disabled when the
disable input is driven to its high state, and the AD8141/AD8142
operates in its normal fashion when the disable input is driven to
its low state.
AD8142 SIGNAL LEVELS ON VARIOUS SUPPLIES
Figure 44 and Figure 45 illustrate the key video signal levels
seen in typical applications operating on a single +5 V supply
and ±2.5 V supplies; common-mode sync pulses are omitted
from the circuit drawing for clarity but are shown in a separate
waveform drawing of the signals directly at the AD8142 outputs,
shown just below the associated circuit drawing. The sync pulses
are common-mode, that is, they move in the same direction on
each output polarity. In Figure 44 and Figure 45, this means that
the HSYNC pulses are either both green or both blue for the red
and black video signals.
An unavoidable common-mode glitch occurs at the outputs
when switching between disabled and enabled states and vice
versa. The glitch lasts for a few tens of nanoseconds and is
on the order of 2 V or 3 V. If the disable feature is used, it is
recommended that common-mode protection be used on the
receiver (see the AD8143 data sheet for a detailed description of
common-mode protection)
DISABLE FEATURE
When asserted, the disable feature minimizes quiescent current
consumption and provides a high-Z output. It offers a convenient
means to connect two driver outputs together in parallel to form a
tristate multiplexed application. The disable feature can also be
used to minimize quiescent current drawn when a particular
device is not being used.
AD8142 KEY SIGNAL LEVELS ON SINGLE +5V SUPPLY
+5V
0.7V
0V
AD8142
2kΩ
1kΩ
75Ω
VIDEO
SOURCE
80.6Ω
49.9Ω
–
38.3Ω
0.8V
49.9Ω
+
1kΩ
1.5V
100Ω
UTP
100Ω
0.7V
1.5V
2kΩ
2.2V
1.5V
0.76V
0.52V
AD8142 OUTPUT SIGNAL LEVELS INCLUDING COMMON-MODE HSYNC PULSES
1.5V
0.5V
1.4V
0.8V
09461-042
2.2V
Figure 44. AD8142 Key Signal Levels on Single 5 V Supply; Upper Drawing Shows Schematic, and Lower Drawing Shows Output Signals with HSYNC Pulses
Rev. B | Page 20 of 24
Data Sheet
AD8141/AD8142
AD8142 KEY SIGNAL LEVELS ON SINGLE ±2.5V SUPPLIES
+2.5V
0.7V
0V
AD8142
2kΩ
1kΩ
75Ω
VIDEO
SOURCE
80.6Ω
49.9Ω
–
38.3Ω
–1.7V
49.9Ω
+
1kΩ
–1.0V
100Ω
UTP
100Ω
0.7V
–1.0V
2kΩ
–0.3V
–1.0V
–2.5V
–0.10V
–0.34V
AD8142 OUTPUT SIGNAL LEVELS INCLUDING COMMON-MODE HSYNC PULSES
0.5V
–1.0V
09461-043
–0.3V
1.4V
–1.7V
Figure 45. AD8142 Key Signal Levels on ±2.5 V Supplies; Upper Drawing Shows Schematic, and Lower Drawing Shows Output Signals with HSYNC Pulses
DRIVING MULTIPLE OUTPUTS
The AD8141/AD8142 can drive four parallel UTP cables (50 Ω
differential load) with only 1.5% reduction in output swing (see
Figure 46). As is expected, driving fewer parallel cables results in
less output swing reduction.
49.9Ω
AD8141/AD8142
49.9Ω
100Ω
UTP
100Ω
100Ω
UTP
100Ω
100Ω
UTP
100Ω
100Ω
UTP
100Ω
49.9Ω
+
VOCM
–
49.9Ω
49.9Ω
49.9Ω
49.9Ω
09461-046
49.9Ω
Figure 46. Driving Four UTP Cables in Parallel
VIDEO SYNC-ON-COMMON-MODE (AD8142)
Cat-5 type cable contains four balanced twisted-pair physical
channels that can support both differential and common-mode
signals. Transmitting typical computer monitor video over this
cable can be accomplished by using three of the twisted pairs for
the RGB and sync signals. Each color is transmitted differentially,
one on each of the three pairs. The encoded sync signals are
transmitted among the common-mode signals of each of the
three pairs. To minimize EMI from the sync signals, the commonmode signals on each of the three pairs produced by the sync
encoding scheme induce electric and magnetic fields that, for
the most part, cancel each other. A conceptual block diagram
of the sync encoding scheme is presented in Figure 47. Because
the AD8142 has the sync encoding scheme implemented internally,
the user simply applies the horizontal and vertical sync signals
directly to the appropriate inputs. As described in the Theory of
Operation section, the AD8142 accepts ground-referenced logiclevel sync pulses (see Table 1 for the exact levels). In many cases,
the sync pulses can be applied directly from video card VGA
connector outputs.
In computer video applications, the horizontal and vertical sync
signals are most often separate from the video information signals.
For example, in typical computer monitor applications, the red,
green, and blue (RGB) color signals are transmitted over separate
cables, as are the vertical and horizontal sync signals. When
transmitting these types of video signals over long distances
on UTP cable, it is desirable to reduce the required number of
physical channels. One way to do this is to encode the vertical and
horizontal sync signals as weighted sums and differences of the
output common-mode signals. The RGB color signals are each
transmitted differentially over separate physical channels. The
fact that the differential and common-mode signals are orthogonal
allows the RGB color and sync signals to be separated at the
channel’s receiver.
Rev. B | Page 21 of 24
Data Sheet
AD8142
1kΩ
+IN R
+
–OUT R
VOCM R
–IN R
1kΩ
VSYNC
–
+OUT R
2kΩ
HSYNC
2kΩ
SYNC LEVEL
1kΩ
+IN G
–IN G
+
–OUT G
VOCM G
×2
1kΩ
–
+OUT G
2.25
1.75
+
1kΩ
–
12.5
BCM
1.25
7.5
1.00
0.75
HSYNC
VSYNC
2.5
0.50
0.25
0
0
40
80
120
160
200
240
280
320
360
–2.5
400
TIME (ns)
LAYOUT AND POWER SUPPLY DECOUPLING
CONSIDERATIONS
–OUT B
VOCM B
–IN B
17.5
Figure 48. AD8142 Sync-On-Common-Mode Signals in Single 5 V Application
2kΩ
1kΩ
RCM
1.50
2kΩ
+IN B
SYNC LEVEL = 0.5V
GCM
2.00
SYNC INPUT VOLTAGE (V)
2kΩ
09461-048
CHANNEL OUTPUT COMMON-MODE VOLTAGE (V)
AD8141/AD8142
+OUT B
2kΩ
DIS
VOCM WEIGHTING EQUATIONS ON +5V SUPPLY:
09461-047
RED VOCM = K (VSYNC – HSYNC ) + 1.5V
2
K
GREEN VOCM = (–2VSYNC ) + 1.5V
2
K
BLUE VOCM = (VSYNC + HSYNC ) + 1.5V
2
Figure 47. AD8142 Conceptual Sync-On-Common-Mode Encoding Scheme
The transmitted common-mode sync signal magnitudes are
scaled by applying a dc voltage to the SYNC LEVEL input,
referenced to the negative supply. The difference between the
voltage applied to the SYNC LEVEL input and the negative supply
sets the peak deviation of the encoded sync signals about the
midsupply common-mode voltage. For example, with the SYNC
LEVEL input set at VS− + 500 mV, the deviation of the encoded
sync pulses about the nominal midsupply common-mode voltage
is nominally ±500 mV. The equations in Figure 47 describe how
the VSYNC and HSYNC signals are encoded on each color’s midsupply
common-mode signal. In these equations, the weights of the VSYNC
and HSYNC signals are ±1 (that is, +1 for high, −1 for low), and the
constant, K, is equal to the peak deviation of the encoded sync
signals.
When designing with the AD8141 and AD8142, adhere to
standard high speed printed circuit board (PCB) layout practices.
A solid ground plane is recommended and good wideband power
supply decoupling networks should be placed as close as possible
to the supply pins. Small surface-mount ceramic capacitors are
recommended for these networks, and tantalum capacitors are
recommended for bulk supply decoupling.
AMPLIFIER-TO-AMPLIFIER ISOLATION
The least amount of isolation between the three AD8142 amplifiers
exists between the green and red channels (Amplifier A and
Amplifier B for the AD8141). This is, therefore, viewed as the
worst-case isolation, which is reflected in Table 1 and the
Theory of Operation section.
EXPOSED PADDLE (EPAD)
The 24-lead LFCSP package has an exposed paddle on the
underside of its body. To achieve the specified thermal resistance, it
must have a good thermal connection to one of the PCB planes.
The exposed paddle must be soldered to a pad on top of the board
that is connected with several thermal vias to a ground plane.
Figure 48 shows how the sync signals appear on each commonmode voltage in a single 5 V supply application when the voltage
applied to the SYNC LEVEL input is set to VS− + 500 mV.
Although the typical setting for the SYNC LEVEL voltage is
500 mV above the negative supply, it can be increased, if
necessary, in extremely noisy environments. Increasing the
SYNC LEVEL voltage too much has the potential to produce
excessive EMI.
Rev. B | Page 22 of 24
Data Sheet
AD8141/AD8142
TYPICAL AD8142 5 V APPLICATION CIRCUIT
Figure 49 illustrates a typical AD8142 application circuit on a single 5 V supply.
BLUE VIDEO IN
+5V
80.6Ω
17.8kΩ
38.3Ω
0.01µF
2kΩ
49.9Ω
+5V
+5V
–
0.01µF
20
B
×2
21
–
9
8
–
23
+5V
10
G
22
38.3Ω
11
R
24
7
+
GREEN VIDEO IN
12
+
VSYNC
AD8142
–
19
+
HSYNC
80.6Ω
DIFFERENTIAL BLUE VIDEO OUT
18 17 16 15 14 13
49.9Ω
49.9Ω
49.9Ω
+
–
+
DIFFERENTIAL GREEN VIDEO OUT
+
0.01µF
0.01µF
1
RED VIDEO IN
DISABLE
49.9Ω
2
3
4
5
DIFFERENTIAL RED VIDEO OUT
6
49.9Ω
80.6Ω
–
38.3Ω
Figure 49. Typical AD8142 Application Circuit on a Single 5 V Supply
Rev. B | Page 23 of 24
09461-049
0.01µF
AD8141/AD8142
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.30
0.25
0.18
1
0.50
BSC
2.85
2.70 SQ
2.45
EXPOSED
PAD
13
TOP VIEW
0.80
0.75
0.70
6
12
7
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
PKG-005185
0.50
0.40
0.30
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
24
19
18
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8.
03-09-2017-C
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
Figure 50. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD8141ACPZ-R2
AD8141ACPZ-RL
AD8141ACPZ-R7
AD8142ACPZ-R2
AD8142ACPZ-RL
AD8142ACPZ-R7
1
Temperature Package
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
Z = RoHS Compliant Part.
©2011–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09461-0-3/17(B)
Rev. B | Page 24 of 24
Package Option
CP-24-8
CP-24-8
CP-24-8
CP-24-8
CP-24-8
CP-24-8
工商网监
湘ICP备2023018690号
