3.2 Gbps
Single Buffered Mux/Demux Switch
AD8153
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
TRANSMIT
PRE-EMPHASIS
RECEIVE
EQUALIZATION
INPUT A
EQ
INPUT B
EQ
OUTPUT C
RECEIVE
EQUALIZATION
OUTPUT A
EQ
TRANSMIT
PRE-EMPHASIS
2:1 MULTIPLEXER/
1:2 DEMULTIPLEXER
CONTROL
LOGIC
AD8153
APPLICATIONS
The AD8153 is an asynchronous, protocol agnostic, single-lane
2:1 switch with three differential CML inputs and three differential
CML outputs. The AD8159, another member of the Xstream
line of products, is suitable for similar applications that require
more than one lane.
The AD8153 is optimized for NRZ signaling with data rates of
up to 3.2 Gbps per port. Each port offers two levels of input
equalization and four levels of output pre-emphasis.
The device consists of a 2:1 multiplexer and a 1:2 demultiplexer.
There are three operating modes: pin mode, serial mode, and
mixed mode. In pin mode, lane switching, equalization, and
pre-emphasis are controlled exclusively using external pins. In
serial mode, an I2C interface is used to control the device and to
Rev. A
SEL
BICAST
LB_A
LB_B
LB_C
MODE
RESETB
EQ_A/(SCL)
EQ_B/(SDA)
EQ_C
PE_A/(I2C_A[0])
PE_B/(I2C_A[1])
PE_C/(I2C_A[2])
Figure 1.
Low cost redundancy switch
SONET OC48/SDH16 and lower data rates
Gigabit Ethernet over backplane
Fibre Channel 1.06 Gbps and 2.12 Gbps over backplane
Serial RapidIO
PCI Express Gen 1
Infiniband over backplane
GENERAL DESCRIPTION
INPUT C
OUTPUT B
06393-001
Single lane 2:1 mux/1:2 demux
3.2 Gbps to dc data rates
Compensates over 40 inches of FR4 at 3.2 Gbps through
Two levels of input equalization, or
Four levels of output pre-emphasis
Operates with ac- or dc-coupled differential I/O
Low deterministic jitter, typically 16 ps p-p
Low random jitter, typically 500 fs rms
On-chip terminations
Unicast or bicast on 1:2 demux function
Loopback capability on all ports
3.3 V core supply
Flexible I/O supply
Low power, typically 200 mW in basic configuration1
32-lead LFCSP package
−40°C to +85°C operating temperature range
provide access to advanced features, such as additional preemphasis settings and output disable. In mixed mode, the user
accesses the advanced features using I2C, but controls lane
switching using the external pins.
The main application of the AD8153 is to support redundancy
on both the backplane side and the line interface side of a serial
link. The device has unicast and bicast capability, so it is capable
of supporting either 1 + 1 or 1:1 redundancy.
Using a mixture of bicast and loopback modes, the AD8153 can
also be used to test high speed serial links by duplicating the
incoming data and transmitting it to the destination port and
test equipment simultaneously.
1
Two ports active with no pre-emphasis.
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 ©2007–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD8153
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Transmit Pre-Emphasis ............................................................. 14
Applications ....................................................................................... 1
I C Serial Control Interface ........................................................... 15
Functional Block Diagram .............................................................. 1
Register Set .................................................................................. 15
General Description ......................................................................... 1
General Functionality ................................................................ 15
Revision History ............................................................................... 2
I2C Data Write............................................................................. 16
Specifications..................................................................................... 3
I2C Data Read.............................................................................. 17
I2C Timing Specifications ............................................................ 4
Applications Information .............................................................. 18
Absolute Maximum Ratings ............................................................ 5
PCB Design Guidelines ................................................................. 19
ESD Caution .................................................................................. 5
Interfacing to the AD8153............................................................. 20
Pin Configuration and Function Descriptions ............................. 6
Termination Structures.............................................................. 20
Typical Performance Characteristics ............................................. 7
Input Compliance ....................................................................... 20
Theory of Operation ...................................................................... 13
Output Compliance ................................................................... 21
Switch Configurations ............................................................... 13
Outline Dimensions ....................................................................... 22
Receive Equalization .................................................................. 14
Ordering Guide .......................................................................... 22
2
REVISION HISTORY
5/15—Rev. 0 to Rev. A
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 22
4/07—Revision 0: Initial Version
Rev. A | Page 2 of 24
Data Sheet
AD8153
SPECIFICATIONS
VCC = VTTI = VTTO = 3.3 V, VEE = 0 V, RL = 50 Ω, two outputs active with no pre-emphasis, data rate = 3.2 Gbps, ac-coupled, PRBS7 test
pattern, VID = 800 mV p-p, TA = 25°C, unless otherwise noted. 1
Table 1.
Parameter
DYNAMIC PERFORMANCE
Data Rate/Channel (NRZ)
Deterministic Jitter
Random Jitter
Propagation Delay
Lane-to-Lane Skew
Switching Time
Output Rise/Fall Time
INPUT CHARACTERISTICS
Input Voltage Swing
Input Voltage Range
Input Capacitance
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage Range
Output Current
Output Current
Output Capacitance
TERMINATION CHARACTERISTICS
Resistance
Temperature Coefficient
POWER SUPPLY
Operating Range
VCC
VTTI
VTTO
Supply Current
ICC
II/O = ITTO + ITTI
Supply Current
ICC
II/O = ITTO + ITTI
THERMAL CHARACTERISTICS
Operating Temperature Range
θJA
LOGIC INPUT CHARACTERISTICS
Input High (VIH)
Input Low (VIL)
1
Conditions
Min
Typ
Max
Unit
3.2
Gbps
ps p-p
fs
ps
ps
ns
ps
2000
VCC + 0.3
mV p-p
V
pF
900
Vcc + 0.6
16
28
2
mV p-p
V
mA
mA
pF
100
0.1
Ω
Ω/°C
DC
Data rate = 3.2 Gbps, high EQ
RMS, high EQ
Input to output
16
500
640
55
5
85
20% to 80%
Differential
Common mode, VID = 800 mV p-p
200
VEE + 1.0
2
Differential, @ dc
Single-ended absolute voltage level
No pre-emphasis
Maximum pre-emphasis, all ports
700
Vcc − 1.6
Differential
VEE = 0 V
VEE = 0 V
VEE = 0 V
Two outputs active, no pre-emphasis, 400 mV I/O swings
(800 mV p-p differential)
Three outputs active, maximum pre-emphasis, 400 mV
I/O swings (800 mV p-p differential)
800
3.0
3.3
VCC
VCC
3.6
V
V
V
27
26
31
32
35
39
mA
mA
53
74
58
84
63
95
mA
mA
+85
°C
°C/W
VCC
0.8
V
V
−40
Still air
30.0
2.4
VEE
VID: Input differential voltage swing.
Rev. A | Page 3 of 24
AD8153
Data Sheet
I2C TIMING SPECIFICATIONS
SDA
tf
tLOW
tSU;DAT
tr
tf
tHD;STA
tSP
tBUF
tr
tHD;STA
S
tHD;DAT
tSU;STO
tSU;STA
tHIGH
Sr
P
S
06393-006
SCL
Figure 2. I2C Timing Diagram
Table 2.
Parameter
SCL Clock Frequency
Hold Time for a Start Condition
Set-up Time for a Repeated Start Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Data Hold Time
Data Set-Up Time
Rise Time for Both SDA and SCL
Fall Time for Both SDA and SCL
Set-Up Time for Stop Condition
Bus Free Time Between a Stop Condition and a Start Condition
Capacitance for Each I/O Pin
Rev. A | Page 4 of 24
Symbol
fSCL
tHD;STA
tSU;STA
tLOW
tHIGH
tHD;DAT
tSU;DAT
tr
tf
tSU;STO
tBUF
Ci
Min
0
0.6
0.6
1.3
0.6
0
10
1
1
0.6
1
5
Max
400+
–
–
–
–
–
–
300
300
–
–
7
Unit
kHz
μs
μs
μs
μs
μs
ns
ns
ns
μs
ns
pF
Data Sheet
AD8153
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VCC to VEE
VTTI
VTTO
Internal Power Dissipation
Differential Input Voltage
Logic Input Voltage
Storage Temperature Range
Lead Temperature
Junction Temperature
Rating
3.7 V
VCC + 0.6 V
VCC + 0.6 V
4.1 W
2.0 V
VEE − 0.3V < VIN < VCC + 0.6 V
−65°C to +125°C
300°C
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. A | Page 5 of 24
AD8153
Data Sheet
32
31
30
29
28
27
26
25
VEE
IPC
INC
PE_A/(I2C_A[0])
OPC
ONC
PE_B/(I2C_A[1])
PE_C/(I2C_A[2])
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
AD8153
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
MODE
RESETB
SEL
BICAST
LB_A
LB_B
LB_C
EQ_A/(SCL)
NOTES
1. EPAD NEEDS TO BE ELECTRICALLY CONNECTED TO VEE.
06393-002
VCC
ONB
OPB
VCC
INB
IPB
EQ_C
EQ_B/(SDA)
9
10
11
12
13
14
15
16
VCC
VTTO
ONA
OPA
VTTI
INA
IPA
VEE
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1, 9, 12
2
3
4
5
6
7
8, 32, EPAD
10
11
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Mnemonic
VCC
VTTO
ONA
OPA
VTTI
INA
IPA
VEE
ONB
OPB
INB
IPB
EQ_C
EQ_B/(SDA)
EQ_A/(SCL)
LB_C
LB_B
LB_A
BICAST
SEL
RESETB
MODE
PE_C/(I2C_A[2])
PE_B/(I2C_A[1])
ONC
OPC
PE_A/(I2C_A[0])
INC
IPC
EPAD
Type
Power
Power
I/O
I/O
Power
I/O
I/O
Power
I/O
I/O
I/O
I/O
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
I/O
I/O
Control
I/O
I/O
Description
Positive Supply.
Output Termination Supply.
High Speed Output Complement.
High Speed Output.
Input Termination Supply.
High Speed Input Complement.
High Speed Input.
Negative Supply.
High Speed Output Complement.
High Speed Output.
High Speed Input Complement.
High Speed Input.
Port C Input Equalization Control.
Port B Input Equalization Control/(I2C Data when MODE = 1).
Port A Input Equalization Control/(I2C Clock when MODE = 1).
Port C Loopback Enable.
Port B Loopback Enable.
Port A Loopback Enable.
Bicast Enable.
A/B Select.
Configuration Registers Reset.
Configuration Mode. 1 for Serial/Mixed Mode, 0 for Pin Mode.
Port C Pre-Emphasis Control/(I2C Slave Address Bit 2 when MODE = 1).
Port B Pre-Emphasis Control/(I2C Slave Address Bit 1 when MODE = 1).
High Speed Output Complement.
High Speed Output.
Port A Pre-Emphasis Control/(I2C Slave Address Bit 0 when MODE = 1).
High Speed Input Complement.
High Speed Output.
Exposed Pad. The EPAD needs to be electrically connected to VEE.
Rev. A | Page 6 of 24
Data Sheet
AD8153
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = VTTI = VTTO =3.3 V, VEE = 0 V, RL = 50 Ω, two outputs active with no pre-emphasis, high EQ, data rate = 3.2 Gbps, ac-coupled,
PRBS7 test pattern, VID = 800 mV p-p, TA = 25°C, unless otherwise noted.
2
PATTERN
GENERATOR
50Ω CABLES
2
INPUT
PIN
OUTPUT 2
PIN
50Ω CABLES
2
50Ω
AD8153
AC COUPLED
EVALUATION
BOARD
TP1
TP2
HIGH-SPEED
SAMPLING
OSCILLOSCOPE
06393-014
DATA OUT
40ps/DIV
Figure 6. 3.2 Gbps Output Eye, No Channel
(TP2 from Figure 4)
Figure 5. 3.2 Gbps Input Eye
(TP1 from Figure 4)
Rev. A | Page 7 of 24
06393-022
40ps/DIV
06393-021
150mV/DIV
150mV/DIV
Figure 4. Standard Test Circuit (No Channel)
AD8153
Data Sheet
150mV/DIV
DATA OUT
2
50Ω CABLES
2
FR4 TEST BACKPLANE
50Ω CABLES
2
2
DIFFERENTIAL
STRIPLINE TRACES
TP1
8mils WIDE, 8mils SPACE,
8mils DIELECTRIC HEIGHT
TRACE LENGTHS = 20 INCHES,
40 INCHES
50Ω CABLES
2
50Ω
AD8153
TP2
AC COUPLED
EVALUATION
BOARD
TP3
HIGHSPEED
SAMPLING
OSCILLOSCOPE
06393-015
PATTERN
GENERATOR
INPUT OUTPUT 2
PIN
PIN
40ps/DIV
REFERENCE EYE DIAGRAM AT TP1
40ps/DIV
Figure 10. 3.2 Gbps Output Eye, 20 Inch FR4 Input Channel, High EQ
(TP3 from Figure 7)
40ps/DIV
06393-027
40ps/DIV
06393-025
150mV/DIV
150mV/DIV
Figure 8. 3.2 Gbps Input Eye, 20 Inch FR4 Input Channel
(TP2 from Figure 7)
06393-026
40ps/DIV
06393-024
150mV/DIV
150mV/DIV
Figure 7. Input Equalization Test Circuit
Figure 11. 3.2 Gbps Output Eye, 40 Inch FR4 Input Channel, High EQ
(TP3 from Figure 7)
Figure 9. 3.2 Gbps Input Eye, 40 Inch FR4 Input Channel
(TP2 from Figure 7)
Rev. A | Page 8 of 24
Data Sheet
AD8153
150mV/DIV
DATA OUT
2
50Ω CABLES
2
50Ω CABLES
2
INPUT OUTPUT 2
PIN
PIN
AD8153
PATTERN
GENERATOR
2
50Ω CABLES
2
50Ω
DIFFERENTIAL
STRIPLINE TRACES
TP2
8mils WIDE, 8mils SPACE,
8mils DIELECTRIC HEIGHT
TRACE LENGTHS = 20 INCHES,
40 INCHES
AC COUPLED
EVALUATION
BOARD
TP3
HIGHSPEED
SAMPLING
OSCILLOSCOPE
06393-013
TP1
FR4 TEST BACKPLANE
40ps/DIV
REFERENCE EYE DIAGRAM AT TP1
40ps/DIV
06393-019
40ps/DIV
06393-017
150mV/DIV
150mV/DIV
Figure 12. Output Pre-Emphasis Test Circuit
Figure 15. 3.2 Gbps Output Eye, 20 Inch FR4 Output Channel, PE = 2
(TP3 from Figure 12)
40ps/DIV
Figure 14. 3.2 Gbps Output Eye, Pre-Channel, PE = 3
(TP2 from Figure 12)
06393-020
40ps/DIV
06393-018
150mV/DIV
150mV/DIV
Figure 13. 3.2 Gbps Output Eye, Pre-Channel, PE = 2
(TP2 from Figure 12)
Figure 16. 3.2 Gbps Output Eye, 40 Inch FR4 Output Channel, PE = 3
(TP3 from Figure 12)
Rev. A | Page 9 of 24
AD8153
Data Sheet
80
80
70
70
PE = 0
DETERMINISTIC JITTER (ps)
60
LOW EQ
50
40
HIGH EQ
30
20
60
PE = 2
50
PE = 3
40
30
20
10
40
30
10
20
FR4 INPUT CHANNEL LENGTH (IN)
0
06393-028
0
10
0
30
20
10
FR4 OUTPUT CHANNEL LENGTH (IN)
0
Figure 17. Deterministic Jitter vs. FR4 Input Channel Length
Figure 20. Deterministic Jitter vs. FR4 Output Channel Length
80
20
SAMPLES: 557k
70
60
JITTER (ps)
40
06393-041
DETERMINISTIC JITTER (ps)
PE = 1
15
50
40
10
DETERMINISTIC JITTER
30
20
5
1.5
2.5
3.0
2.0
DATA RATE (Gbps)
4.0
3.5
06393-038
RANDOM JITTER
0
1.0
0
–2ps
80
70
70
60
60
50
50
JITTER (ps)
80
40
30
DETERMINISTIC JITTER
20
0.0s
1ps
2ps
Figure 21. Random Jitter Histogram, 3.2 Gbps
40
30
20
DETERMINISTIC JITTER
10
10
RANDOM JITTER
0
0.2
0.4
0.6
0.8
1.0
1.2
1.6
1.4
DIFFERENTIAL INPUT SWING (V)
RANDOM JITTER
1.8
2.0
0
0.8
1.3
1.8
2.3
2.8
3.3
INPUT COMMON-MODE VOLTAGE (V)
Figure 22. Jitter vs. Input Common-Mode Voltage
Figure 19. Jitter vs. Differential Input Swing
Rev. A | Page 10 of 24
3.8
06393-035
0
06393-032
JITTER (ps)
Figure 18. Jitter vs. Data Rate
–1ps
06393-039
10
AD8153
80
80
70
70
60
60
50
50
JITTER (ps)
40
30
DETERMINISTIC JITTER
20
40
30
DETERMINISTIC JITTER
20
10
10
3.3
VCC (V)
3.4
3.5
3.6
0
2
2.2
2.4
2.6
2.8
3.0
VTTO (V)
3.2
3.4
3.6
06393-031
3.2
3.1
06393-033
0
3.0
100
06393-029
RANDOM JITTER
RANDOM JITTER
100
06393-040
JITTER (ps)
Data Sheet
Figure 26. Jitter vs. Output Termination Voltage
Figure 23. Jitter vs. Core Supply Voltage
100
80
70
95
RISE/FALL TIME (ps)
JITTER (ps)
60
50
40
30
20
DETERMINISTIC JITTER
90
85
80
10
RANDOM JITTER
–20
0
20
40
TEMPERATURE (°C)
60
80
100
75
–40
06393-037
0
–40
Figure 24. Jitter vs. Temperature
0
60
20
40
TEMPERATURE (°C)
80
Figure 27. Rise/Fall Time vs. Temperature
700
PROPAGATION DELAY (ps)
700
650
600
550
500
3.0
3.1
3.2
3.3
VCC (V)
3.4
3.5
3.6
650
600
550
500
–40
06393-030
PROPAGATION DELAY (ps)
–20
–20
0
60
20
40
TEMPERATURE (°C)
80
Figure 28. Propagation Delay vs. Temperature
Figure 25. Propagation Delay vs. Core Supply Voltage
Rev. A | Page 11 of 24
AD8153
Data Sheet
1000
900
900
800
800
EYE HEIGHT (mV)
700
600
500
400
300
700
600
500
400
200
200
100
100
0
3.0
3.1
3.2
3.3
VCC (V)
3.4
3.5
3.6
0
0
0.5
1.0
1.5
2.0
2.5
DATA RATE (Gbps)
3.0
Figure 30. Eye Height vs. Data Rate
Figure 29. Eye Height vs. Core Supply Voltage
Rev. A | Page 12 of 24
3.5
4.0
06393-036
300
06393-034
EYE HEIGHT (mV)
1000
Data Sheet
AD8153
THEORY OF OPERATION
The AD8153 consists of a 2:1 multiplexer and a 1:2 demultiplexer.
There are three operating modes: pin mode, serial mode, and
mixed mode. In pin mode, lane switching, equalization, and
pre-emphasis are controlled using external pins. In serial mode,
an I2C interface is used to control the device and to provide
access to advanced features, such as additional pre-emphasis
settings and output disable. In mixed mode, the user accesses
the advanced features using I2C but controls lane switching
using external pins.
side, the device relays received data on either Input Port A or Input
Port B to Output Port C, depending on the state of the SEL bit.
When bicast mode is off, the outputs of either Port A or Port B
are in an idle state. In the idle state, the output tail current is set
to 0, and the P and N sides of the lane are pulled up to the output
termination voltage through the on-chip termination resistors.
SWITCH CONFIGURATIONS
The device also supports loopback on all ports, illustrated in
Figure 31. Enabling loopback on any port overrides configurations
set by the BICAST and SEL control bits. Table 5 summarizes the
possible switch configurations.
On the demultiplexer side, the AD8153 relays received data on
Input Port C to Output Port A and/or Output Port B, depending
on the state of the BICAST and SEL bits. On the multiplexer
The AD8153 output disable feature can be used to force an
output into the idle (powered-down) state. This feature is only
accessible through the serial control interface.
OUTPUT A
1:2 DEMUX
INPUT C
OUTPUT B
PORT A LOOPBACK
PORT B LOOPBACK
PORT C LOOPLOCK
INPUT A
2:1 MUX
OUTPUT C
06393-003
INPUT B
Figure 31. Loopback Configurations
Table 5. Switch Configurations
LB_A
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
LB_B
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
LB_C
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
SEL
0
0
1
1
0
X
1
0
1
1
0
1
X
0
0
1
0
BICAST
0
1
0
1
0
1
0
X
0
1
X
0
1
0
1
X
0
Rev. A | Page 13 of 24
Output A
Input C
Input C
Idle
Input C
Input C
Input C
Idle
Input C
Idle
Input C
Input C
Idle
Input C
Input A
Input A
Input A
Input A
Output B
Idle
Input C
Input C
Input C
Idle
Input C
Input C
Input B
Input B
Input B
Input B
Input B
Input B
Idle
Input C
Input C
Idle
Output C
Input A
Input A
Input B
Input B
Input C
Input C
Input C
Input A
Input B
Input B
Input C
Input C
Input C
Input A
Input A
Input B
Input C
AD8153
LB_A
1
1
1
1
1
Data Sheet
LB_B
0
0
1
1
1
LB_C
1
1
0
0
1
SEL
X
1
0
1
X
BICAST
1
X
X
X
X
Output A
Input A
Input A
Input A
Input A
Input A
Output B
Input C
Input C
Input B
Input B
Input B
Output C
Input C
Input C
Input A
Input B
Input C
RECEIVE EQUALIZATION
TRANSMIT PRE-EMPHASIS
In backplane applications, the AD8153 needs to compensate for
signal degradation caused by long traces. The device supports
two levels of input equalization, configured on a per-port basis.
Table 6 summarizes the high-frequency asymptotic gain boost
for each setting.
Transmitter pre-emphasis levels can be set by pin control or
through the control registers when using the I2C interface. Pin
control allows two settings of PE. The control registers provide
two additional settings.
Table 6. Receive Equalization Settings
Serial Mode
PE_A/B/C Setting
0
1
2
3
EQ_A/B/C
0
1
EQ Boost
6 dB
12 dB
Table 7. Pre-Emphasis Settings
Rev. A | Page 14 of 24
Pin Mode
PE_A/B/C
0
N/A
1
N/A
PE Boost (%)
0
25
50
75
PE Boost (dB)
0
1.9
3.5
4.9
Data Sheet
AD8153
I2C SERIAL CONTROL INTERFACE
REGISTER SET
pins or the internal register set. The source of the control is
selected using the mask bits (Register 0x00). If a mask bit is set
to 0, the external pin acts as the source for that specific control.
If a mask bit is set to 1, the associated internal register acts as
the source for that specific control. As an example, if Register 0x00
were set to the value 0x0C, the SEL and LB_C controls would
come from the internal register set (Bit 0 of Register 0x04 and Bit
3 of Register 0x03, respectively), and the BICAST, LB_A, and
LB_B controls would come from the external pins.
The AD8153 can be controlled in one of three modes: pin
mode, serial mode, and mixed mode. In pin mode, the AD8153
control is derived from the package pins, whereas in serial
mode a set of internal registers controls the AD8153. There is
also a mixed mode where switching is controlled via external
pins, and equalization and pre-emphasis are controlled via the
internal registers. The methods for writing data to and reading
data from the AD8153 are described in the I2C Data Write
section and the I2C Data Read section.
GENERAL FUNCTIONALITY
The mode is controlled via the MODE pin. To set the part in
pin mode, MODE should be driven low to VEE. When MODE
is driven high to VCC, the part is set to serial or mixed mode.
In pin mode, all controls are derived from the external pins. In
serial mode, each channel’s equalization and pre-emphasis are
controlled only through the registers, as described in Table 8.
Additionally, further functionality is available in serial mode as
each channel’s output can be enabled/disabled with the Output
Enable control bits, which is not possible in pin mode. To
change the switching in the AD8153 to serial mode, the mask
bits (Register 0x00) must be set to 1 by writing the value 0x1F to
this register, as explained in the following sections. Once all the
mask bits are set to 1, switching is controlled via the LB_A,
LB_B, LB_C, SEL, and BICAST bits in the register set.
In mixed mode, each channel’s equalization and pre-emphasis
are controlled through the registers as described above. The
switching, however, can be controlled using either the external
The AD8153 register set is controlled through a 2-wire I2C
interface. The AD8153 acts only as an I2C slave device. Therefore,
the I2C bus in the system needs to include an I2C master to
configure the AD8153 and other I2C devices that may be on the
bus. When the MODE pin is set to a Logic 1, data transfers are
controlled through the use of the two I2C wires: the input clock
pin, SCL, and the bidirectional data pin, SDA.
The AD8153 I2C interface can be run in the standard (100 kHz)
and fast (400 kHz) modes. The SDA line only changes value
when the SCL pin is low with two exceptions. To indicate the
beginning or continuation of a transfer, the SDA pin is driven
low while the SCL pin is high, and to indicate the end of a
transfer, the SDA line is driven high while the SCL line is high.
Therefore, it is important to control the SCL clock to only
toggle when the SDA line is stable unless indicating a start,
repeated start, or stop condition.
Table 8. Register Map
Address
00000000
(0x00)
00000001
(0x01)
00000010
(0x02)
00000011
(0x03)
0000100
(0x04)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BICAST MASK
SEL MASK
LB_C MASK
LB_B MASK
LB_A MASK
OUTPUT DISABLE A
LB_A
EQ_A
PE_A [1]
PE_A [0]
OUTPUT DISABLE B
LB_B
EQ_B
PE_B [1]
PE_B [0]
OUTPUT DISABLE C
LB_C
EQ_C
PE_C [1]
PE_C [0]
BICAST
SEL
Rev. A | Page 15 of 24
Default
00000000
(0x00)
00000000
(0x00)
00000000
(0x00)
00000000
(0x00)
00000000
(0x00)
AD8153
Data Sheet
I2C DATA WRITE
To write data to the AD8153 register set, a microcontroller, or
any other I2C master, needs to send the appropriate control
signals to the AD8153 slave device. The steps that need to be
followed are listed below, where the signals are controlled by the
I2C master unless otherwise specified. A diagram of the procedure
is shown in Figure 32.
1. Send a start condition (while holding the SCL line high, pull
the SDA line low).
2. Send the AD8153 part address (seven bits) whose upper
four bits are the static value b1001 and whose lower three
bits are controlled by the input pins I2C_A[2:0]. This
transfer should be MSB first.
3. Send the write indicator bit (0).
4. Wait for the AD8153 to acknowledge the request.
5. Send the register address (eight bits) to which data is to be
written. This transfer should be MSB first.
6. Wait for the AD8153 to acknowledge the request.
7. Send the data (eight bits) to be written to the register whose
address was set in Step 5. This transfer should be MSB first.
8. Wait for the AD8153 to acknowledge the request.
9. Send a stop condition (while holding the SCL line high, pull
the SDA line high) and release control of the bus.
10. Send a repeated start condition (while holding the SCL line
high, pull the SDA line low) and continue with Step 2 in this
procedure to perform another write.
11. Send a repeated start condition (while holding the SCL line
high, pull the SDA line low) and continue with Step 2 of the
read procedure (in the I2C Data Read section) to perform a
read from another address.
12. Send a repeated start condition (while holding the SCL line
high, pull the SDA line low) and continue with step 8 of the
read procedure (in the I2C Data Read section) to perform a
read from the same address set in Step 5.
The AD8153 write process is shown in Figure 32. The SCL
signal is shown along with a general write operation and a
specific example. In the example, data 0x92 is written to
Address 0x6D of an AD8153 part with a part address of 0x4B.
The part address is seven bits wide and is composed of the
AD8153 static upper four bits (b1001) and the pin
programmable lower three bits (I2C_ADDR[2:0]). In this
example, the I2C_ADDR bits are set to b011. In Figure 32, the
corresponding step number is visible in the circle under the
waveform. The SCL line is driven by the I2C master and never
by the AD8153 slave. As for the SDA line, the data in the shaded
polygons is driven by the AD8153, whereas the data in the nonshaded polygons is driven by the I2C master. The end phase case
shown is that of 9a.
It is important to note that the SDA line only changes when the
SCL line is low, except for the case of sending a start, stop, or
repeated start condition, Step 1 and Step 9 in this case.
SCL
SDA
(GENERAL CASE)
START
FIXED PART ADDR
ADDR
[2:0]
RW ACK
REGISTER ADDR
ACK
DATA
ACK
STOP
1
2
2
3
4
5
Figure 32. I2C Write Diagram
Rev. A | Page 16 of 24
6
7
8
9a
06393-004
SDA
(EXAMPLE)
Data Sheet
AD8153
I2C DATA READ
12. Acknowledge the data.
To read data from the AD8153 register set, a microcontroller, or
any other I2C master, needs to send the appropriate control
signals to the AD8153 slave device. The steps to be followed are
listed below, where the signals are controlled by the I2C master
unless otherwise specified. A diagram of the procedure can be
seen in Figure 33.
13. Send a stop condition (while holding the SCL line high, pull
the SDA line high) and release control of the bus.
1. Send a start condition (while holding the SCL line high, pull
the SDA line low).
15. Send a repeated start condition (while holding the SCL line
high, pull the SDA line low) and continue with Step 2 of this
procedure to perform a read from another address.
14. Send a repeated start condition (while holding the SCL line
high, pull the SDA line low) and continue with Step 2 of the
write procedure (see the I2C Data Write section) to perform
a write.
2. Send the AD8153 part address (seven bits) whose upper
four bits are the static value b1001 and whose lower three
bits are controlled by the input pins I2C_ADDR[2:0]. This
transfer should be MSB first.
16. Send a repeated start condition (while holding the SCL line
high, pull the SDA line low) and continue with Step 8 of this
procedure to perform a read from the same address.
3. Send the write indicator bit (0).
The AD8153 read process is shown in Figure 33. The SCL signal
is shown along with a general read operation and a specific
example. In the example, Data 0x49 is read from Address 0x6D
of an AD8153 part with a part address of 0x4B. The part address is
seven bits wide and is composed of the AD8153 static upper
four bits (b1001) and the pin programmable lower three bits
(I2C_ADDR[2:0]). In this example, the I2C_ADDR bits are set
to b011. In Figure 33, the corresponding step number is visible
in the circle under the waveform. The SCL line is driven by the
I2C master and never by the AD8153 slave. As for the SDA line,
the data in the shaded polygons is driven by the AD8153,
whereas the data in the nonshaded polygons is driven by the I2C
master. The end phase case shown is that of 13a.
4. Wait for the AD8153 to acknowledge the request.
5. Send the register address (eight bits) from which data is to
be read. This transfer should be MSB first. The register
address is kept in memory in the AD8153 until the part is
reset or the register address is written over with the same
procedure (Step 1 to Step 6).
6. Wait for the AD8153 to acknowledge the request.
7. Send a repeated start condition (while holding the SCL line
high, pull the SDA line low).
8. Send the AD8153 part address (seven bits) whose upper
four bits are the static value b1001 and whose lower three
bits are controlled by the input pins I2C_ADDR[1:0]. This
transfer should be MSB first.
It is important to note that the SDA line only changes when the
SCL line is low, except for the case of sending a start, stop, or
repeated start condition, as in Step 1, Step 7, and Step 13. In
Figure 33, A is the same as ACK in Figure 32. Equally, Sr
represents a repeated start where the SDA line is brought high
before SCL is raised. SDA is then dropped while SCL is still high.
9. Send the read indicator bit (1).
10. Wait for the AD8153 to acknowledge the request.
11. The AD8153 then serially transfers the data (eight bits) held
in the register indicated by the address set in Step 5.
SCL
SDA
(GENERAL CASE)
START
FIXED PART
ADDR
ADDR R
A
[2:0] W
REGISTER ADDR
A Sr
FIXED PART
ADDR
ADDR
[2:0]
R
W A
DATA
A
STOP
11
12
13a
1
2
2
3
4
5
6
7
Figure 33. I2C Read Diagram
Rev. A | Page 17 of 24
8
8
9
10
06393-005
SDA
(EXAMPLE)
AD8153
Data Sheet
APPLICATIONS INFORMATION
The main application of the AD8153 is to support redundancy
on both the backplane side and the line interface side of a serial
link. Figure 34 illustrates redundancy in a typical backplane
system. Each line card is connected to two switch fabrics
(primary and redundant). The device can be configured to
support either 1 + 1 or 1:1 redundancy.
PHYSICAL
INTERFACE
Another application for the AD8153 is in test equipment for
evaluating high speed serial links. Figure 36 illustrates a
possible application of the AD8153 in a simple link tester.
PRIMARY
SWITCH
FABRIC
DIGITAL ENGINE
AD8153
LINE CARDS
DIGITAL ENGINE
AD8153
FABRIC CARDS
BACKPLANE
Figure 34. Switch Redundancy Application
SFP
CDR
SFP
CDR
PROCESSING
ENGINE/CROSSBAR/
BACKPLANE
06393-008
AD8153
Figure 35. Line Interface Redundancy Application
DUT
CONNECTOR
FPGA
06393-009
PROTOCOL
ANALYZER
CONNECTOR
AD8153
Figure 36. Test Equipment Application
Rev. A | Page 18 of 24
06393-007
PHYSICAL
INTERFACE
REDUNDANT
SWITCH
FABRIC
Data Sheet
AD8153
PCB DESIGN GUIDELINES
Transmission Lines
Proper RF PCB design techniques must be used for optimal
performance.
Power Supply Connections and Ground Planes
Use of one low impedance ground plane is recommended. The
VEE pins should be soldered directly to the ground plane to
reduce series inductance. If the ground plane is an internal
plane and connections to the ground plane are made through
vias, multiple vias can be used in parallel to reduce the series
inductance. The exposed pad should be connected to the VEE
plane using plugged vias so that solder does not leak through
the vias during reflow.
Use of a 10 µF electrolytic capacitor between VCC and VEE is
recommended at the location where the 3.3 V supply enters the
PCB. It is recommended that 0.1 µF and 1 nF ceramic chip
capacitors be placed in parallel at each supply pin for high
frequency power supply decoupling. When using 0.1 µF and 1 nF
ceramic chip capacitors, they should be placed between the IC
power supply pins (VCC, VTTI, VTTO) and VEE, as close as
possible to the supply pins.
Use of 50 Ω transmission lines is required for all high frequency
input and output signals to minimize reflections. It is also
necessary for the high speed pairs of differential input traces to
be matched in length, as well as the high speed pairs of differential
output traces, to avoid skew between the differential traces.
Soldering Guidelines for Chip Scale Package
The lands on the 32-lead LFCSP are rectangular. The printed
circuit board pad for these should be 0.1 mm longer than the
package land length and 0.05 mm wider than the package land
width. The land should be centered on the pad. This ensures
that the solder joint size is maximized. The bottom of the chip
scale package has a central exposed pad. The pad on the printed
circuit board should be at least as large as this exposed pad. The
user must connect the exposed pad to VEE using plugged vias
so that solder does not leak through the vias during reflow. This
ensures a solid connection from the exposed pad to VEE.
By using adjacent power supply and GND planes, excellent high
frequency decoupling can be realized by using close spacing
between the planes. This capacitance is given by
CPLANE = 0.88εr A/d (pF)
where:
εr is the dielectric constant of the PCB material.
A is the area of the overlap of power and GND planes (cm2).
d is the separation between planes (mm).
For FR4, εr = 4.4 and 0.25 mm spacing, C ~15 pF/cm2.
Rev. A | Page 19 of 24
AD8153
Data Sheet
INTERFACING TO THE AD8153
TERMINATION STRUCTURES
To determine the best strategy for connecting to the high speed
pins of the AD8153, the user must first be familiar with the onchip termination structures. The AD8153 contains two types of
these structures: one type for input ports and one type for output
ports (see Figure 37 and Figure 38).
VCC
AC Coupling
One way to simplify the input circuit and make it compatible
with a wide variety of driving devices is to use ac coupling. This
has the effect of isolating the dc common-mode levels of the
driver and the AD8153 input circuitry. AC coupling requires a
capacitor in series with each single-ended input signal, as shown
in Figure 39. This should be done in a manner that does not
interfere with the high speed signal integrity of the PCB.
VCC
VTTI
55Ω
VCC
VTTI
55Ω
50Ω
50Ω
IPX
CP
CN
1173Ω
IP
IN
55Ω
55Ω
1173Ω
INX
VEE
DRIVER
Figure 37. Receiver Simplified Diagram
Figure 39. AC-Coupling Input Signal of AD8153
When ac coupling is used, the common-mode level at the input
of the device is equal to VTTI. The single-ended input signal
swings above and below VTTI equally. The user can then use
the specifications in Table 1 to determine the input signal swing
levels that satisfy the input range of the AD8153.
VCC
VTTO
50Ω
VEE
06393-042
06393-010
AD8153
50Ω
OPX
If dc coupling is required, determining the input commonmode level is less straightforward because the configuration of
the driver must also be considered. In most cases, the user
would set VTTI on the AD8153 to the same level as the driver
output termination voltage. This prevents a continuous dc
current from flowing between the two supply nets. As a
practical matter, both devices can be terminated to the same
physical supply net.
VIP
ONX
IT
VEE
06393-011
VIN
Figure 38. Transmitter Simplified Diagram
For input ports, the termination structure consists of two 55 Ω
resistors connected to a termination supply and an 1173 Ω
resistor connected across the differential inputs, the latter being
a result of the finite differential input impedance of the equalizer.
For output ports, there are two 50 Ω resistors connected to the
termination supply. Note that the differential input resistance
for both structures is the same, 100 Ω.
INPUT COMPLIANCE
The range of allowable input voltages is determined by the
fundamental limitations of the active input circuitry. This range
of signals is normally a function of the common-mode level of
the input signal, the signal swing, and the supply voltage. For a
given input signal swing, there is a range of common-mode
voltages that keeps the high and low voltage excursions within
acceptable limits. Similarly, for a given common-mode input
voltage, there is a maximum acceptable input signal swing.
There is also a minimum signal swing that the active input
circuitry can resolve reliably. The specifications are found in
Table 1.
Consider the following example: a driver is dc-coupled to the
input of the AD8153. The AD8153 input termination voltage
(VTTI) and the driver output termination voltage (VTTOD) are both
set to the same level; that is, VTTI = VTTOD = 3.3 V. If an 800 mV
differential p-p swing is desired, the total output current of the
driver is 16 mA. At balance, the output current is divided evenly
between the two sides of the differential signal path, 8 mA to each
side. This 8 mA of current flows through the parallel combination of the 55 Ω input termination resistor on the AD8153 and
the 50 Ω output termination resistor on the driver, resulting in a
common-mode level of
VTTI − 8 mA × (50 Ω || 55 Ω) = VTTI − 209 mV
The user can then determine the allowable range of values for VTTI
that meets the input compliance range based on an 800 mV p-p
differential swing.
Rev. A | Page 20 of 24
Data Sheet
AD8153
Figure 40 is a graphical depiction of the single-ended waveform
at the output of the AD8153. The common-mode level (VOCM)
and the amplitude (VOSE) of this waveform are a function of the
output tail current (IT), the output termination supply voltage
(VTTO), the topology of the far-end receiver, and whether ac- or
dc-coupling is used. Keep in mind that the output tail current
varies with the pre-emphasis level. The user must ensure that
the high (VH) and low (VL) voltage excursions at the output are
within the single-ended absolute voltage range limits as
specified in Table 1. Failure to understand the implications of
output signal levels and the choice of ac- or dc-coupling may
lead to transistor saturation and poor transmitter performance.
Table 9 shows an example calculation of the output levels for the
typical case, where VCC = VTTO = 3.3 V, with 50 far-end
terminations to a 3.3 V supply.
VTTO
VH
VOCM
VOSE-DC
VOSE-BOOST
VL
~320ps
06393-012
OUTPUT COMPLIANCE
Figure 40. Single-Ended Output Waveform
Table 9. Output Voltage Levels
PE Setting
0
1
2
3
IT (mA)
16
20
24
28
VOSE-DC (mV p-p)
400
400
400
400
VOSE-BOOST (mV p-p)
400
500
600
700
VOCM (V)
3.1
3.05
3
2.95
DC-Coupled
VH (V)
3.3
3.3
3.3
3.3
VL (V)
2.9
2.8
2.7
2.6
VOCM (V)
2.9
2.8
2.7
2.6
AC-Coupled
VH (V)
3.1
3.05
3
2.95
Table 10. Symbol Definitions
Symbol
VOSE-DC
Formula
VOSE-BOOST
I T 25
VOCM (dc-coupled)
VOCM (ac-coupled)
IT
PE 0
25
Definition
Single-ended output voltage swing after settling
Boosted single-ended output voltage swing
VTTO
IT
25
2
Common-mode voltage when the output is dc-coupled
VTTO
IT
50
2
Common-mode voltage when the output is ac-coupled
VH
VOCM + VOSE-BOOST/2
High single-ended output voltage excursion
VL
VOCM - VOSE-BOOST/2
Low single-ended output voltage excursion
Rev. A | Page 21 of 24
VL (V)
2.7
2.55
2.4
2.25
AD8153
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00 SQ
4.90
PIN 1
INDICATOR
0.30
0.25
0.18
PIN 1
INDICATOR
32
25
24
1
0.50
BSC
2.85
2.70 SQ
2.55
EXPOSED
PAD
17
8
0.80
0.75
0.70
16
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
PKG-004332
SEATING
PLANE
9
BOTTOM VIEW
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-2.
08-22-2013-A
TOP VIEW
0.50
0.40
0.30
Figure 41. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-21)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD8153ACPZ
AD8153ACPZ-RL7
AD8153-EVALZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board
Z = RoHS Compliant Part.
Rev. A | Page 22 of 24
Package Option
CP-32-21
CP-32-21
Data Sheet
AD8153
NOTES
Rev. A | Page 23 of 24
AD8153
Data Sheet
NOTES
©2007–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06393-0-5/15(A)
Rev. A | Page 24 of 24
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