AD8170ARZ

250 MHz, 10 ns Switching Multiplexers w/Amplifier AD8170/AD8174 a FEATURES Fully Buffered Inputs and Outputs Fast Channel Switching: 10 ns Internal Current Feedback Output Amplifier High Output Drive: 50 mA Flexible Gain Setting via External Resistor(s) High Speed 250 MHz Bandwidth, G = +2 1000 V/ms Slew Rate Fast Settling Time of 15 ns to 0.1% Low Power: < 10 mA Excellent Video Specifications (RL = 150 V, G = +2) Gain Flatness of 0.1 dB Beyond 80 MHz 0.02% Differential Gain Error 0.058 Differential Phase Error Low Crosstalk of –78 dB @ 5 MHz High Disable Isolation of –88 dB @ 5 MHz High Shutdown Isolation of –92 dB @ 5 MHz Low Cost Fast Output Disable Feature for Connecting Multiple Devices (AD8174 Only) Shutdown Feature Reduces Power to 1.5 mA (AD8174 Only) The AD8170(2:1) and AD8174(4:1) are very high speed buffered multiplexers. These multiplexers offer an internal current feedback output amplifier whose gain can be programmed via external resistors and is capable of delivering 50 mA of output current. They offer –3 dB signal bandwidth of 250 MHz and slew rate of greater than 1000 V/µs. Additionally, the AD8170 and AD8174 have excellent video specifications with low differential gain and differential phase error of 0.02% and 0.05° and 0.1 dB flatness out to 80 MHz. With a low 78 dB of crosstalk and better than 88 dB isolation, these devices are useful in many high speed applications. These are low power devices consuming only 9.7 mA from a ± 5 V supply. LOGIC GND 2 8 VOUT 7 –VS 3 –VIN 6 +VS +1 IN0 1 +1 14 +VS +1 12 –VIN +1 5 IN1 IN0 4 AD8174 GND 2 13 VOUT 2 GND 4 IN2 5 11 SD LOGIC IN1 3 +1 –VS 6 IN3 7 +1 2 10 ENABLE 9 A1 8 A0 The AD8174 offers a high speed disable feature allowing the output to be put into a high impedance state for cascading stages so that the off channels do not load the output bus. Additionally, the AD8174 can be shut down (SD) when not in use to minimize power consumption (IS = 1.5 mA). These products will be offered in 8-lead and 14-lead PDIP and SOIC packages. 0 VIN = 50mV rms G = +2 RF = 499Ω (AD8170R) 0.1 RF = 549Ω (AD8174R) RL = 100Ω –1 –2 –3 0 –4 –0.1 –5 –0.2 –6 –0.3 –7 –0.4 –8 –0.5 1M 10M 100M FREQUENCY – Hz NORMALIZED OUTPUT – dB PRODUCT DESCRIPTION AD8170 SELECT 1 NORMALIZED FLATNESS – dB APPLICATIONS Pixel Switching for “Picture-In-Picture” LCD and Plasma Displays Video Routers FUNCTIONAL BLOCK DIAGRAM –9 1G Figure 1. Small Signal Frequency Response REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1996 (@ T = +258C, V = 65 V, R = 150 V, G = +2, R = 499 V AD8170/AD8174–SPECIFICATIONS (AD8170R), R = 549 V (AD8174R) unless otherwise noted) A S L F F Parameter SWITCHING CHARACTERISTICS Switching Time1 50% Logic to 10% Output Settling 50% Logic to 90% Output Settling 50% Logic to 99.9% Output Settling ENABLE to Channel ON Time2 (AD8174R) 50% Logic to 90% Output Settling ENABLE to Channel OFF Time2 (AD8174R) 50% Logic to 90% Output Settling Shutdown to Channel ON Time3 (AD8174R) 50% Logic to 90% Output Settling Shutdown to Channel OFF Time3 (AD8174R) 50% Logic to 90% Output Settling Channel Switching Transient (Glitch)4 DIGITAL INPUTS Logic “1” Voltage Logic “0” Voltage Logic “1” Input Current DYNAMIC PERFORMANCE –3 dB Bandwidth (Small Signal)5 –3 dB Bandwidth (Large Signal)5 0.1 dB Bandwidth5 Rise and Fall Time (10% to 90%) Slew Rate Settling Time to 0.1% DISTORTION/NOISE PERFORMANCE Differential Gain Differential Phase All Hostile Crosstalk6 AD8170R All Hostile Crosstalk6 AD8174R Disable Isolation7 AD8174R Shutdown Isolation8 AD8174R Input Voltage Noise +Input Current Noise –Input Current Noise Total Harmonic Distortion DC/TRANSFER CHARACTERISTICS Transresistance Open-Loop Voltage Gain Gain Accuracy9 Gain Matching Input Offset Voltage Input Bias Current Drift Units Channel-to-Channel IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V 7.5 9.1 25 ns ns ns IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V 17 ns IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V 120 ns IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V 20 ns IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V All Inputs Grounded 115 138 /104 ns mV p-p SELECT, A0, A1, ENABLE, SD Inputs, TMIN–TMAX SELECT, A0, A1, ENABLE, SD Inputs, TMIN–TMAX SELECT, A0, A1 Inputs, TMIN–TMAX ENABLE, SD Inputs, TMIN–TMAX SELECT, A0, A1 Inputs, TMIN–TMAX ENABLE, SD Inputs, TMIN–TMAX Logic “0” Input Current Input Offset Voltage Matching Input Offset Voltage Drift Input Bias Current AD8170A/AD8174A Min Typ Max Conditions 2.0 50 1 3 30 0.8 300 5 5 300 V V nA µA µA nA VO = 50 mV rms, RL = 100 Ω VO = 1 V rms, RL = 100 Ω VO = 50 mV rms, RF = 499 Ω (AD8170R), RL = 100 Ω VO = 50 mV rms, RF = 549 Ω (AD8174R), RL = 100 Ω 2 V Step 2 V Step 2 V Step 250 100 MHz MHz 85 1.6 1000 15 MHz ns V/µs ns ƒ = 3.58 MHz ƒ = 3.58 MHz ƒ = 5 MHz, RL = 100 Ω ƒ = 30 MHz, RL = 100 Ω ƒ = 5 MHz, RL = 100 Ω ƒ = 30 MHz, RL = 100 Ω ƒ = 5 MHz, RL = 100 Ω ƒ = 30 MHz, RL = 100 Ω ƒ = 5 MHz, RL = 100 Ω ƒ = 30 MHz, RL = 100 Ω ƒ = 10 kHz to 30 MHz ƒ = 10 kHz to 30 MHz ƒ = 10 kHz to 30 MHz ƒC = 10 MHz, VO = 2 V p-p, RL = 150 Ω ƒC = 10 MHz, VO = 2 V p-p, RL = 1 kΩ 0.02 0.05 –80 –65 –78 –63 –88 –72 –92 –77 10 1.6 8.5 –60 –72 % Degrees dB dB dB dB dB dB dB dB nV/√Hz pA/√Hz pA/√Hz dBc dBc 600 6000 0.4 0.05 5 kΩ V/V % % mV mV mV µV/°C µA µA µA µA nA/°C 400 2000 G = +1, RF = 1 kΩ Channel-to-Channel TMIN to TMAX Channel-to-Channel (+) Switch Input TMIN to TMAX (–) Buffer Input TMIN to TMAX (+) Switch and (–) Buffer Input –2– 1.5 11 7 3 20 9 12 5 15 15 10 14 REV. 0 AD8170/AD8174 Parameter AD8170A/AD8174A Min Typ Max Conditions INPUT CHARACTERISTICS Input Resistance (+) Switch Input (–) Buffer Input Channel Enabled (R Package) Channel Disabled (R Package) Input Capacitance Input Voltage Range Input Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short Circuit Current Output Resistance +CMRR, ∆VCM = 1 V –CMRR, ∆VCM = 1 V 51 50 RL = 1 kΩ, TMIN–TMAX RL = 150 Ω, TMIN–TMAX RL = 10 Ω ± 4.0 ± 3.5 Enabled Disabled (AD8174) Disabled (AD8174) Output Capacitance POWER SUPPLY Operating Range Power Supply Rejection Ratio +PSRR Power Supply Rejection Ratio –PSRR Quiescent Current +VS = +4.5 V to +5.5 V, –VS = –5 V TMIN–TMAX –VS = –4.5 V to –5.5 V, +VS= +5 V TMIN–TMAX All Channels “ON”, TMIN–TMAX AD8174 Disabled, TMIN–TMAX AD8174 Shutdown, TMIN–TMAX OPERATING TEMPERATURE RANGE ±4 58 55 52 50 Units 1.7 100 1.1 1.1 ± 3.3 56 52 MΩ Ω pF pF V dB dB ± 4.26 ± 4.0 50 180 10 10 7.5 V V mA mA mΩ MΩ pF ±6 11/13 5 2.5 V dB dB dB dB mA mA mA +85 °C 66 58 8.7/9.7 4.1 1.5 –40 NOTES 1 Shutdown (SD) and ENABLE pins are grounded (AD8174). IN0 (or IN2) = +0.5 V dc, IN1 (or IN3) = –0.5 V dc. SELECT (A0 or A1 for AD8174) input is driven with 0 V to +5 V pulse. Measure transition time from 50% of SELECT (A0 or A1) input value (+2.5 V) and 10% (or 90%) of the total output voltage transition from IN0 (or IN2) channel voltage (+0.5 V) to IN1 (or IN3 = –0.5 V) or vice versa. 2 AD8174 only. Shutdown (SD) pin is grounded. ENABLE pin is driven with 0 V to +5 V pulse (5 ns rise and fall times). State of A0 and A1 logic inputs determines which channel is activated (i.e., if A0 = Logic 0 and A1 = Logic 1, then IN2 input is selected). Set IN0 (or IN2) = +0.5 V dc, IN1 (or IN3) = –0.5 V dc, and measure transition time from 50% of ENABLE pulse (+2.5 V) to 90% of the total output voltage change. In Figure 5, ∆tOFF is the disable time, ∆tON is the enable time. 3 AD8174 only. ENABLE pin is grounded. Shutdown (SD) pin is driven with 0 V to +5 V pulse (5 ns rise and fall times). State of A0 and A1 logic inputs determines which channel is activated (i.e., if A0 = Logic 1 and A1 = Logic O, then IN1 input is selected). Set IN0 (or IN2) = +0.5 V dc, IN1 (or IN3) = –0.5 V dc, and measure transition time from 50% of SD pulse (+2.5 V) to 90% of the total output voltage change. In Fig ure 6, ∆tOFF is the shutdown assert time, ∆tON is the shutdown release time. 4 All inputs are grounded. SELECT (A0 or A1 for AD8174) input is driven with 0 V to +5 V pulse. The outputs are monitored. Speeding the edges of the SELECT (A0 or A1) pulse increases the glitch magnitude due to coupling via the ground plane. 5 Bandwidth of the multiplexer is dependent upon the resistor feedback network. Refer to Table III for recommended feedback component values, which give the best compromise between a wide and a flat frequency response. 6 Select input(s) that is (are) not being driven (i.e., if SELECT is Logic 1, activated input is IN1; in AD8174, if A0 = Logic 0, A1 = Logic 1, activated input is IN2). Drive all other inputs with V IN = 0.707 V rms, and monitor output at f = 5 MHz and 30 MHz; RL = 100 Ω (see Figure 13). 7 AD8174 only. Shutdown (SD) pin is grounded. Mux is disabled, (i.e., ENABLE = Logic 1) and all inputs are driven simultaneously with V IN = 0.354 V rms. Output is monitored at f = 5 MHz and 30 MHz; R L = 100 Ω. In this mode, the output impedance of the disabled mux is very high (typ 10 M Ω), and the signal couples across the package; the load impedance and the feedback network determine the crosstalk. For instance, in a closed-loop gain of +1, r OUT ù 10 MΩ, in a gain of +2 (RF = RG = 549 Ω), rOUT = 1.1 kΩ (see Figure 14). 8 AD8174 only. ENABLE pin is grounded. Mux is shutdown (i.e., SD = Logic 1), and all inputs are driven simultaneously with V IN = 0.354 V rms. Output is monitored at f = 5 MHz and 30 MHz; RL = 100 Ω. (see Figure 14). The mux output impedance in shutdown mode is the same as the disabled mux output impedance. 9 For Gain Accuracy expression, refer to Equation 4. Specifications subject to change without notice. Table II. AD8174 Truth Table Table I. AD8170 Truth Table REV. 0 SELECT VOUT 0 1 IN0 IN1 A0 0 1 0 1 X X –3– A1 0 0 1 1 X X ENABLE 0 0 0 0 1 X SD 0 0 0 0 0 1 VOUT IN0 IN1 IN2 IN3 HIGH Z, IS = 4.1 mA HIGH Z, IS = 1.5 mA AD8170/AD8174 ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.6 V Internal Power Dissipation2 AD8170 8-Lead Plastic (N) . . . . . . . . . . . . . . . . . 1.3 Watts AD8170 8-Lead Small Outline (R) . . . . . . . . . . . 0.9 Watts AD8174 14-Lead Plastic (N) . . . . . . . . . . . . . . . . 1.6 Watts AD8174 14-Lead Small Outline (R) . . . . . . . . . . 1.0 Watts Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ± VS Output Short Circuit Duration . . Observe Power Derating Curves Storage Temperature Range N & R Packages . . . . . . . . . . . . . . . . . . . . –65°C to +125°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C The maximum power that can be safely dissipated by the AD8170 and AD8174 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150°C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175°C for an extended period can result in device failure. ORDERING GUIDE Model Temperature Range Package Description Package Option AD8170AN AD8170AR AD8170AR-REEL AD8174AN AD8174AR AD8174AR-REEL AD8170-EB AD8174-EB –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Evaluation Board Evaluation Board 8-Pin Plastic DIP 8-Pin SOIC Reel 8-Pin SOIC 14-Pin Plastic DIP 14-Pin Narrow SOIC Reel 14-Pin SOIC For AD8170R For AD8174R N-8 SO-8 SO-8 N-14 R-14 R-14 2.0 MAXIMUM POWER DISSIPATION – Watts NOTES 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-Pin Plastic Package: θJA = 90°C/Watt; 8-Pin SOIC Package: θJA = 160°C/Watt; 14-Pin Plastic Package: θJA = 90°C/Watt 14-Pin SOIC Package: θJA = 120°C/Watt, where P D = (TJ–TA)/θJA. While the AD8170 and AD8174 are internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (+150°C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves shown in Figures 2 and 3. 8-PIN MINI-DIP PACKAGE TJ = +150°C 1.5 1.0 8-PIN SOIC PACKAGE 0.5 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 AMBIENT TEMPERATURE – °C 70 80 90 Figure 2. AD8170 Maximum Power Dissipation vs. Temperature MAXIMUM POWER DISSIPATION – Watts 2.5 TJ = +150°C 2.0 14-PIN DIP PACKAGE 1.5 14-PIN SOIC 1.0 0.5 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE – °C 80 90 Figure 3. AD8174 Maximum Power Dissipation vs. Temperature CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8170/AD8174 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. 0 Typical Performance Characteristics – AD8170/AD8174 500mV/DIV IN0, IN2 = +0.5V IN1, IN3 = +0.5V G = +2 RF = RG = 499V RL = 100V SEL SWITCHING RF = 549V (AD8174R) RL = 100V G = +2 RF = 499V (AD8170R) OUTPUT 50mV/DIV DUT OUT OUTPUT (AD8170R) ∆tRISE = 7.5ns ∆tFALL = 9.1ns A0 SWITCHING OUTPUT (AD8174R) A1 SWITCHING SELECT PULSE 0 TO +5V SEL, A0, A1 PULSE 0 TO +5V 5ns/DIV 10ns/DIV Figure 4. Channel Switching Characteristics Figure 7. Switching Transient (Glitch) Response 4 AD8174R INØ = +0.5VDC G = +2 RF = 549V RL = 100V G = +2 RF = RG = 1kΩ RL = 150Ω 2 VOUT – Volts 200mV/DIV OUTPUT 3 ∆tOFF = 120ns 1 0 –1 ∆tON = 17ns –2 ENABLE PULSE 0 TO +5V (5nsec EDGES) –3 –4 –3 50ns/DIV –1 0 VIN – Volts 1 2 Figure 8. Output Voltage vs. Input Voltage, G = +2 9 9 6 VIN = 1.0V rms AD8174R OUTPUT 3 OUTPUT LEVEL – dBV 200mV/DIV INØ = +0.5VDC G = +2 RF = 549V RL = 100V ∆tON = 20ns ∆tOFF = 115ns VIN = 0.5V rms 0 –6 VIN = 0.25V rms –18 –21 1M 50ns/DIV Figure 6. Shutdown Switching Characteristics 0 –3 –6 –12 –15 –9 –12 G = +2 RF = 549Ω RL = 100Ω –9 –3 VIN = 125mV rms –18 –21 –15 SHUTDOWN PULSE 0 TO +5V (5nsec EDGES) REV. 0 3 VIN = 625mV rms 10M 100M FREQUENCY – Hz –24 –27 1G Figure 9. Large Signal Frequency Response –5– INPUT LEVEL – dBV Figure 5. Enable and Disable Switching Characteristics –2 AD8170/AD8174 –10 G = +2 RF = 499V (AD8170R) RF = 549V (AD8174R) RL = 100V –20 –30 20mV/DIV CROSSTALK – dB –40 VIN = +0.707V rms G = +2 RF = 499Ω (AD8170R) RF = 549Ω (AD8174R) RL = 100Ω –50 AD8170R –60 –70 AD8174R –80 –90 –100 –110 0.1 20ns/DIV Figure 10. Small Signal Pulse Response 1M 10M FREQUENCY – Hz 100M 1G Figure 13. All-Hostile Crosstalk vs. Frequency –20 –30 –40 VIN = +0.354V rms G = +2 RF = 549Ω RL = 100Ω –50 ISOLATION – dB 800mV/DIV VOUT = 4V p-p G = +2 RF = 499V (AD8170R) RF = 549V (AD8174R) RL = 100V ENABLE = LOGIC 1 SD = LOGIC 0 –60 –70 –80 –90 SD = LOGIC 1 ENABLE = LOGIC 0 DISABLE ISOLATION –100 –110 –120 0.03 10ns/DIV 1 10 FREQUENCY – MHz 100 100 G = +2 RL = 150Ω RF = 499Ω (AD8170R) RF = 549Ω (AD8174R) 1 2 3 4 5 6 IRE 7 8 9 10 500 11 100 VNOISE 10 10 INVERTING INPUT I CURRENT NOISE – pA/√Hz 0.05 0.04 0.03 0.02 0.01 0.00 –0.01 –0.02 –0.03 0.1 Figure 14. AD8174R Disable and Shutdown Isolation vs. Frequency VOLTAGE NOISE – nV/√Hz DIFF GAIN – % 0.04 0.03 0.02 0.01 0.00 –0.01 –0.02 –0.03 –0.04 DIFF PHASE – Degrees Figure 11. Large Signal Transient Response SHUTDOWN ISOLATION SWITCHING INPUT I 1 2 3 4 5 6 IRE 7 8 9 10 11 1 10 Figure 12. Differential Gain and Phase Error 100 1k 10k FREQUENCY – Hz 100k 1 1M Figure 15. Noise vs. Frequency –6– REV. 0 AD8170/AD8174 –30 –60 NORMALIZED FLATNESS – dB –70 2ND HARMONIC –80 –90 –100 3RD HARMONIC –110 *WORST CHANNEL –120 10 FREQUENCY – MHz 1 100 Figure 16. Harmonic Distortion vs. Frequency 1M ENABLED (OR DISABLED) INPUT IMPEDANCE 316k 100k –0.2 NORMALIZED FLATNESS – dB IMPEDANCE – Ω ENABLE, SD = LOGIC 1; G = +1 OUTPUT IMPEDANCE (G= +2) 316 100 ENABLED OUTPUT IMPEDANCE (G = +2) 31.6 ENABLE, SD = LOGIC 0, RS(OUT) = 50Ω 1 10 FREQUENCY – MHz 100 500 Figure 17. Input & Output Impedance vs. Frequency –0.3 PSRR – dB –9 1G 10M 100M FREQUENCY – Hz 0.1 VIN = 50mV rms G = +2 RF = 499Ω (AD8170R) RF = 549Ω (AD8174R) RL = 100Ω –1 –2 –3 0 –4 –0.1 –5 –0.2 –6 –0.3 –7 –0.4 –8 –0.5 1M –9 1G 10M 100M FREQUENCY – Hz 180 100k 135 TRANSIMPEDANCE –30 –PSRR –40 –50 –60 –7 –8 –0.4 1M 1M VIN = 200mV rms G = +2 RF = 499Ω (AD8170R) RF = 549Ω (AD8174R) RL = 100Ω TRANSIMPEDANCE – Ω –20 CL = 50pF CL = 100pF Figure 20. Small Signal Frequency Response 0 –10 –6 CL = 300pF 0 ENABLE, SD = LOGIC 1; G = +2 0.1 –5 Figure 19. Frequency Response vs. Capacitive Load, G = +2 1k DISABLED (OR SHUTDOWN) 10 0.03 –4 CL = 100pF –0.1 31.6k DISABLED 3.16k CL = 50pF 0 VIN = +0.221V rms G = +2 RF = 499Ω (AD8170R) RF = 549Ω (AD8174R) (OR SHUTDOWN) OUTPUT IMPEDANCE 10k (G = +1) –3 CL = 300pF +0.1 –2 NORMALIZED OUTPUT – dB 0.5 –1 CL = 0 +PSRR PHASE 10k 90 1k 45 PHASE – Degrees HARMONIC DISTORTION – dB –50 0 CL = 20pF VOUT = 2V p-p G = +2 RF = 1kΩ RS(OUT) = 20Ω NORMALIZED OUTPUT – dB VOUT = 2V p-p G = +2 RF = 499Ω (AD8170R) RF = 549Ω (AD8174R) RL = 100Ω –40 0 100 –70 –80 0.03 0.1 1 10 FREQUENCY – MHz 100 10 1k 500 Figure 18. Power Supply Rejection vs. Frequency REV. 0 10k 100k 1M 10M FREQUENCY – Hz 100M –45 1G Figure 21. Open-Loop Transresistance and Phase vs. Frequency –7– AD8170/AD8174 THEORY OF OPERATION General Bringing SD high shuts off the supply current for all the switches, that some of the logic control circuitry and the amplifier, reducing the quiescent current drain to 1.5 mA. If the ENABLE and SD functions are not to be used, those respective pins must be tied to ground for proper operation. Any unused channel input should also be tied to ground. The AD8170/AD8174 multiplexers integrate wideband analog switches with a high speed current feedback amplifier. The input switches are complementary bipolar follower stages that are turned on and off by using a current steering technique that attains switch times of less than 10 ns and ensures low switching transients. The 250 MHz current feedback amplifier provides up to 50 mA of drive current. Overall gain and frequency response are set by external resistors for maximum versatility. The AD8170 has two switches driving an amplifier to form a 2:1 multiplexer. No disable or shutdown functions are provided. DC Performance and Noise Considerations Figure 23 shows the different contributors to total output offset and noise. Total expected output offset can be calculated using Equation 1 below: Figure 22 is a block diagram of the multiplexer signal chain, with a simplified schematic of an input switch. When the channel is on (i.e., VONB more positive than VREFB, VONT more negative than VREFT), I2 flows through Q1 and Q2, and I3 flows through Q3 and Q4. This biases up Q5 through Q8 to form the unity gain follower. I1 and I4 (the “off” currents) are steered, either to another switch or to the power supply. When the channel turns off, I2 and I3 are steered away while I1 switches over to pull the base of Q8 up to VCLT + 1 VBE (about 2.7 volts from ground reference) and I4 switches over to pull the base of Q5 down to VCLB – 1 VBE (about –2.7 volts away from ground reference). Clamping the bases of the reverse biased output transistors to a low impedance point greatly improves isolation performance.  R  V OS (out ) = ( I B + × RS ) +V OS 1+ F  + ( I B − × RF )  RG  [ RS VIN ( ) (  +  IEN × RS  ) ( ) 2 SWITCH (1) BUFFER IB+/Ien+ RF VOS/Ven VOUT RG IB–/Ien– The AD8174 has four switches with outputs wired together and driving the positive input of a current feedback amplifier to form a 4:1 multiplexer. It is designed so that only one channel is on at a time. By bringing ENABLE high, the supply current for the amplifier is shut off. This turns the output of the amplifier into a high impedance, allowing the AD8174 to be used in larger arrays. In practice, the disabled output impedance of the mux will be determined by the amplifier’s feedback network. V EN(OUT ) nV / Hz = ] Figure 23. DC Errors for Buffered Multiplexer Equations 2 and 3 below can be used to predict the output voltage noise of the multiplexer for different choices of gains and external resistors. The different contributions to output noise are root-sum-squared to calculate total output noise spectral density in Equation 2. As there is no peaking in the multiplier’s noise characteristic, the total peak-to-peak output noise will be accurately predicted using Equation 3. 2 ( 2  R  + V EN  1+ F  + I EN – × RF   RG  ) 2  + 4KT  RF + RS   2  RF   RF  1+ R  + RG  R   G G   2 V EN p−p =V EN × f −3 dB × 6.2 ×1.26    (2) (3) IN0 IN1 VOUT IN2 VFB I1 I3 I6 VREFT VOFFT VONT VREFT Q5 Q3 IN3 Q1 Q6 Q4 VCLB Q2 Q7 Q8 VCLT VONB VREFB I2 VOFFB VREFB I4 Figure 22. Block Diagram and Simplified Schematic of the AD8170 –8– REV. 0 AD8170/AD8174 Equation 4 can be used to calculate expected gain error due to the current feedback amplifier’s finite transimpedance and common mode rejection. For low gains and recommended feedback resistors, this will be typically less than 0.4%. For most applications with gain greater than 1, the dominant source of gain error will most likely be the ratio-match of the external resistors. All of the dominant contributors to gain error are associated with the buffer amplifier and external resistors. These do not change as different channels are selected, so channel-to-channel gain match of less than 0.05% is easily attained.  R  RT G = 1+ F  1− CMRR   RF   RG    RT + RIN 1+  + RF   RG    [ ↑ ↑ Ideal Gain Error Terms ACL = Closed Loop Gain CT = Transcapacitance > 0.8 pF RF = Feedback Resistor G = Ideal Closed Loop Gain GN = (1 + RF/RG) = Noise Gain RIN = Inverting Terminal Input Resistance ≅ 100 Ω The –3 dB bandwidth is determined from this model as: f –3 dB ≅ This model is typically good to within 15%. ] Table III. Recommended Component Values (4) Small Signal Large Signal VOUT = 50 mV rms VOUT = 0.707 V rms Gain RF (V) RG (V) –3 dB BW (MHz) –3 dB BW (MHz) RT = Amplifier Transresistance = 600 kΩ RIN = Amplifier Input Resistance ≅ 100 Ω CMRR = Amplifier Common-Mode Rejection ≅ –52 dB Choice of External Resistors The gain and bandwidth of the multiplexer are determined by the closed-loop gain and bandwidth of the onboard current feedback amplifier. These both may be customized by the external resistor feedback network. Table III shows typical bandwidths at some common closed loop gains for given feedback and gain resistors (RF and RG, respectively). AD8170R +1 +2 +10 +20 1k 499 499 499 — 499 54.9 26.3 710 250 50 27 270 290 55 27 AD8174R +1 +2 +10 +20 1k 549 499 499 — 549 54.9 26.3 780 235 50 27 270 280 55 27 Capacitive Load The general rule for current feedback amplifiers is that the higher the load capacitance, the higher the feedback resistor required for stable operation. For the best combination of wide bandwidth and clean pulse response, a small output resistor is also recommended, as shown in Figure 24. Table IV contains values of feedback and series resistors that result in the best pulse response for a given load capacitance. The choice of RF is not critical unless the widest and flattest frequency response must be maintained. The resistors recommended in the table result in the widest 0.1 dB bandwidth with the least peaking. 1% resistors are recommended for applications requiring the best control of bandwidth. Packaging parasitics vary between DIP and SOIC packages, which may result in a slightly different resistor value for optimum frequency performance. Wider bandwidths than those listed in the table can be attained by reducing RF at the expense of increased peaking. RF 10µF +VS RG 0.1µF To estimate the –3 dB bandwidth for feedback resistors not listed in Table III, the following single-pole model for the current feedback amplifier may be used: ACL 1 2π CT ( RF +G N RIN ) RS(OUT) BUFFER VIN G = 1+ sCT ( RF +GN RIN ) 0.1µF RT 50Ω CL VOUT (TO FET PROBE) SWITCH –VS 10µF Figure 24. Circuit for Driving a Capacitive Load Table IV. Recommended Feedback and Series Resistors and Bandwidth vs. Capacitive Load and Gain CL (pF) RF (V) G = +1 VOUT = 2 V p-p RSOUT –3 dB BW (V) (MHz) 20 50 100 300 1k 1k 2k 2k 50 30 20 20 REV. 0 149 104 73 27 RF (V) G = +2 VOUT = 2 V p-p RSOUT –3 dB BW (V) (MHz) 1k 1k 1k 1k 20 15 15 15 174 117 80 34 –9– G r +4 RF (V) G = +3 VOUT = 2 V p-p RSOUT –3 dB BW (V) (MHz) RF (V) RSOUT (V) 499 1k 1k 1k 25 15 15 15 499 499 499 499 20 20 15 15 170 98 71 33 AD8170/AD8174 Signal traces should be as short as possible. Stripline or microstrip techniques should be used for long signal traces (longer than about 1 inch). These should be designed with a characteristic impedance of 50 Ω or 75 Ω and be properly terminated at each end using surface mount components. Careful layout is imperative to minimize crosstalk. Guards (ground or supply traces) must be run between all signal traces to limit direct capacitive coupling. Input and output signal lines should fan out away from the mux as much as possible. If multiple signal layers are available, a buried stripline structure having ground plane above, below, and between signal traces will have the best crosstalk performance. Return currents flowing through termination resistors can also increase crosstalk if these currents flow in sections of the finiteimpedance ground circuit that is shared between more than one input or output. Minimizing the inductance and resistance of the ground plane can reduce this effect, but further care should be taken in positioning the terminations. Terminating cables directly at the connectors will minimize the return current flowing on the board, but the signal trace between the connector and the mux will look like an open stub and will degrade the frequency response. Moving the termination resistors close to the input pins will improve the frequency response, but the terminations from neighboring inputs should not have a common ground return. 500mV/DIV VOUT = 2V p-p G = +2 RF = 499V (AD8170R) RF = 549V (AD8174R) CL = 300PF RS(OUT) = 15V OUTPUT VOUT = ±1V INPUT VIN = ±0.5V 20ns/DIV Figure 25. Pulse Response Driving a Large Load Capacitor, CL = 300 pF Overload Behavior and Recovery There are three important overload conditions: input voltage overdrive, output voltage overdrive and current overload at the amplifier’s negative feedback input. At a gain of 1, recovery from driving the input voltages beyond the voltage range of the input switches is very quick, typically less than 30 ns. Recovery from output overdrive is somewhat slower and depends on how much the output is overdriven. Recovery from 15% overdrive is under 60 ns. 50% overdrive produces recovery times of about 85 ns. APPLICATIONS 8-to-1 Video Multiplexer Input overdrive in a high gain application can result in a large current flow in the input stage. This current is internally limited to 40 mA. The effect on total power dissipation should be taken into account. LAYOUT CONSIDERATIONS: Realizing the high speed performance attainable with the AD8170 and AD8174 requires careful attention to board layout and component selection. Proper RF design techniques and low parasitic component selection are mandatory. Wire wrap boards, prototype boards, and sockets are not recommended because of their high parasitic inductance and capacitance. Instead, surface-mount components should be soldered directly to a printed circuit board (PCB). The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance ground path. The ground plane should be removed from the area near input and output pins to reduce stray capacitance. Chip capacitors should be used for supply bypassing. One end of the capacitor should be connected to the ground plane and the other within 1/4 inch of each power pin. An additional large (4.7 µF–10 µF) tantalum capacitor should be connected in parallel with each of the smaller capacitors for low impedance supply bypassing over a broad range of frequencies. Two AD8174 4-to-1 multiplexers can be combined with a single digital inverter to yield an 8-to-1 multiplexer as shown in Figure 26. The ENABLE control pin allows the two op amp outputs to be connected together directly. Taking the ENABLE pin high shuts off the supply current to the output op amp and places the op amp’s output and inverting input (Pin 12, –VIN) in high impedance states. The two least significant bits (LSBs) of the address lines connect directly to the A0 and A1 inputs of both AD8174 devices. The third address line connects directly to the ENABLE input on one device and is inverted before being applied to the ENABLE input on the second device. As a result, when one device is enabled, the second device presents a high impedance. The op amp of the enabled device must however drive both feedback networks ((549 Ω + 549 Ω)/2). The gain of this multiplexer has been set to +2 in this example. This gives an overall gain of +1 when back terminated lines are used. In applications where switching and settling times are critical, the digital control pins (A0, A1 and ENABLE) should also be appropriately terminated (with either 50 Ω or 75 Ω). –10– REV. 0 AD8170/AD8174 + IN0 10µF AD8174 75Ω 1 IN1 0.1µF +VS 14 +1 2 GND +5V VOUT 75Ω +1 4 GND 75Ω 0.1µF –5V 5 11 +1 + 6 –VS 10µF 7 549Ω 12 2 LOGIC 3 IN2 RBT 75Ω 13 +1 10 9 8 2 SD 549Ω +5V ENABLE A2 RT* A1 A0 A1 IN3 RT* 75Ω A0 RT* + IN4 10µF AD8174 75Ω 1 IN5 0.1µF +VS 14 +1 2 GND 13 3 12 +5V 75Ω 4 GND 75Ω 0.1µF –5V 5 11 2 +1 + 6 –VS 10µF 7 +1 LOGIC IN6 +1 2 10 9 8 549Ω SD 549Ω +5V ENABLE A1 A0 IN7 *OPTIONAL 75Ω Figure 26. 8-to-1 Multiplexer Color Document Scanner Charge Coupled Devices (CCDs) find widespread use in scanner applications. A monochrome CCD delivers a serial stream of voltage levels, each level being proportional to the light shining on that cell. In the case of the color image scanner shown, there are three output streams, representing red, green and blue. Interlaced with the stream of voltage levels is a voltage representing the reset level (or black level) of each cell. A Correlated Double Sampler (CDS) subtracts these two voltages from each other in order to eliminate the relatively large offsets which are common with CCDs. The next step in the data acquisition process involves digitizing the three signal streams. Assuming that the analog to digital converter chosen has a fast enough sample rate, multiplexing the three streams into a single ADC is generally more economic than using one ADC per channel. In the example shown, the AD8174 is used to multiplex the red, green and blue channels into the AD876, an 8- or 10-bit 20 MSPS ADC. Because of its high bandwidth, the AD8174 is capable of driving the switched capacitor input stage of the AD876 without additional buffering. In addition to the bandwidth, it is necessary to consider the settling time of the multiplexer. In this case, the ADC has a sample rate of 20 MHz which corresponds to a sampling period of 50 ns. Typically, one phase of the sampling clock is used for conversion (i.e., all levels are held steady) and the other REV. 0 phase is used for switching and settling to the next channel. Assuming a 50% duty cycle, the signal chain must settle within 25 ns. With a settling time to 0.1% of 15 ns, the multiplexer easily satisfies this criterion. In the example shown, the fourth (spare) channel of the AD8174 is used to measure a reference voltage. This voltage would probably be measured less frequently than the R, G and B signals. Multiplexing a reference voltage offers the advantage that any temperature drift effects caused by the multiplexer will equally impact the reference voltage and the to-be-measured signals. If the fourth channel is unused, it is good design practice to tie the input permanently to ground. CONTROL AND TIMING A0 A1 SD ENABLE R CCD CDS IN0 CDS IN1 AD8174 G B VOUT CDS IN2 REFERENCE IN3 1kΩ (G = +1) –VIN Figure 27. Color Document Scanner –11– AD876 8/10-BIT 20MSPS A/D AD8170/AD8174 EVALUATION BOARD Evaluation boards for the AD8170 and AD8174 are available that have been carefully laid out and tested to demonstrate the specified high speed performance of the devices. Figure 28 and Figure 32 show the schematics of the AD8170 and AD8174 evaluation boards respectively. For ordering information, please refer to the Ordering Guide. Figure 29 shows the silkscreen of the component side of the solder side of the AD8170 evaluation board. Figures 30 and 31 show the layout of the component side and solder side respectively. The silkscreens and layout of the AD8174 evaluation board are shown in Figures 33, 34, 35 and 36. Both evaluation boards ship with 75 Ω termination resistors on their analog inputs and analog outputs. To use the evaluation board in nonvideo applications where 50 Ω termination is more popular, these resistors can be replaced with 50 Ω values. The digital control pins are terminated with 50 Ω resistors to allow easy connection to laboratory equipment. The gain of the output current feedback op amp on both boards has been set to +2. For other gains the two gain resistors can be easily replaced. Refer to Table III for appropriate values at gains other than +2. For connection to external instruments, side-launched SMA type connectors are provided. Space is also provided on the board for the installation of SMB of SMC type connectors. R6 75Ω VOUT SELECT + C2 0.1µF IN0 LOGIC 1 C1 10µF –VS R5 549Ω AD8170 R1 50Ω GND 2 8 7 3 –VS +VS 6 4 +1 +1 5 C3 10µF + R4 549Ω +VS C4 0.1µF R2 75Ω IN1 R3 75Ω Figure 28. AD8170 Evaluation Board Figure 29. AD8170 Component Side Silkscreen Figure 31. AD8170 Board Layout (Solder Side) Figure 30. AD8170 Board Layout (Component Side) –12– REV. 0 AD8170/AD8174 IN0 AD8174 R1 75Ω 1 IN1 2 GND 3 IN2 C1 10µF + –VS C2 0.1µF 5 R11 75Ω VOUT R10 549Ω +1 +1 R9 549Ω 11 2 6 –VS 7 +VS 12 +1 4 GND C3 10µF 13 LOGIC R2 75Ω R3 75Ω +VS 14 +1 C4 0.1µF 2 10 SD 9 R8 50Ω 8 ENABLE IN3 R7 50Ω R4 75Ω A0 R5 50Ω A1 R6 50Ω Figure 32. AD8174 Evaluation Board Figure 33. AD8174 Component Side Silkscreen Figure 35. AD8174 Solder Side Silkscreen Figure 34. AD8174 Board Layout (Component Side) Figure 36. AD8174 Board Layout (Solder Side) REV. 0 –13– AD8170/AD8174 NOTES 1. AD8170R/AD8174R Evaluation Board inputs are configured with 50 Ω impedance striplines. This FR4 board type has the following stripline dimensions: 60-mil width, 12-mil gap between center conductor and outside ground plane “islands,” and 62-mil board thickness. 2. Several types of SMA connectors can be mounted on this board: the side-mount type, which can be easily installed at the edges of the board; and the top-mount type, which is placed on top. When using the top-mount SMA connector, it is recommended that the stripline on the outside 1/8" of the board edge be removed with an X-Acto blade as this unused stripline acts as an open stub, which could degrade the smallsignal frequency response of the mux. 3. Input termination resistor placement on the evaluation board is critical to reducing crosstalk. Each termination resistor is oriented so that ground return currents flow counterclockwise to a ground plane “island.” Although the direction of this ground current flow is arbitrary, it is important that no two input or output termination resistors share a connection to the same ground “island.” –14– REV. 0 AD8170/AD8174 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 14-Lead Plastic DIP (N-14) 8-Lead Plastic DIP (N-8) 0.795 (20.19) 0.725 (18.42) 0.430 (10.92) 0.348 (8.84) 8 5 14 8 1 7 0.280 (7.11) 0.240 (6.10) 1 4 0.060 (1.52) 0.015 (0.38) PIN 1 0.210 (5.33) MAX 0.325 (8.25) 0.300 (7.62) 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.100 0.070 (1.77) 0.014 (0.356) (2.54) 0.045 (1.15) BSC 0.210 (5.33) MAX 0.100 0.070 (1.77) (2.54) 0.045 (1.15) BSC 0.3444 (8.75) 0.3367 (8.55) 0.1968 (5.00) 0.1890 (4.80) PIN 1 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE REV. 0 8 5 1 4 0.015 (0.381) 0.008 (0.204) SEATING PLANE 14-Lead SOIC (R-14) 8-Lead Plastic SOIC (SO-8) 0.1574 (4.00) 0.1497 (3.80) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.130 (3.30) MIN 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.015 (0.381) 0.008 (0.204) SEATING PLANE 0.060 (1.52) 0.015 (0.38) PIN 1 0.195 (4.95) 0.115 (2.93) 0.130 (3.30) MIN 0.280 (7.11) 0.240 (6.10) 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) 0.0688 (1.75) 0.0532 (1.35) 0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) BSC 8° 0° 8 1 7 PIN 1 0.0196 (0.50) x 45° 0.0099 (0.25) 0.0098 (0.25) 0.0075 (0.19) 14 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE 0.0500 (1.27) 0.0160 (0.41) –15– 0.0500 (1.27) BSC 0.2440 (6.20) 0.2284 (5.80) 0.0688 (1.75) 0.0532 (1.35) 0.0192 (0.49) 0.0138 (0.35) 0.0099 (0.25) 0.0075 (0.19) 0.0196 (0.50) x 45° 0.0099 (0.25) 8° 0° 0.0500 (1.27) 0.0160 (0.41) –16– PRINTED IN U.S.A. C2205–9–10/96