AD8175ABPZ

Data Sheet 500 MHz, Triple 16 × 9 Video Crosspoint Switch AD8175 FEATURES FUNCTIONAL BLOCK DIAGRAM RGB video switching KVM Professional video DGND AD8175 A0 A1 A2 SERIN A3 SER/PAR WE 1 CLK 0 45-BIT SHIFT REGISTER WITH 5-BIT PARALLEL LOADING SEROUT UPDATE SET INDIVIDUAL, OR RESET ALL OUTPUTS TO OFF 45 CS PARALLEL LATCH RST CMENC 45 9 DECODE 9 × 5:16 DECODERS INPUT RECEIVER G = +1 R G B 144 OUTPUT BUFFER G = +1 2 2 2 2 2 2 R G B R G B 2 V 9 x RGB, HV CHANNELS SWITCH MATRIX G = +2 ENABLE/DISABLE H 2 2 2 2 2 R G B H V VBLK VOCM_CMENCON VOCM_CMENCOFF 06478-001 APPLICATIONS D0 D1 D2 D3 D4 VPOS VNEG VDD 16 x RGB CHANNELS High channel count, triple 16 × 9 high speed, non-blocking switch array Differential or single-ended operation Supports sync-on common-mode and sync-on color operating modes Decoded HV sync outputs available G = +2 operation (differential input to differential output) Flexible power supplies: +5 V or ±2.5 V Logic ground for convenient control interface Serial or parallel programming of switch array High impedance output disable allows connection of multiple devices with minimal loading on output bus Adjustable output CM and black level through external pins Excellent ac performance (to support 1600 × 1200 @ 85 Hz) Bandwidth: 500 MHz Slew rate: 1800 V/µs Settling time: 4 ns to 1% Low power of 3.5 W Low all-hostile crosstalk −88 dB @ 5 MHz −46 dB @ 500 MHz Wide input common-mode range of 4 V Reset pin allows disabling of all outputs Fully populated 26 x 26 ball PBGA package (27 mm x 27 mm, 1 mm ball pitch) Convenient grouping of RGB signals for easy routing Figure 1. GENERAL DESCRIPTION with CM signaling removed through the switch. The output CM and black level can be conveniently set via external pins. The AD8175 is a high speed, triple 16 × 9 video crosspoint switch matrix. It supports 1600 × 1200 RGB displays @ 85 Hz refresh rate, by offering a 500 MHz bandwidth and a slew rate of 1800 V/µs. With −88 dB of crosstalk and −94 dB isolation (@ 5 MHz), the AD8175 is useful in many high speed video applications. The independent output buffers of the AD8175 can be placed into a high impedance state to create larger arrays by paralleling crosspoint outputs. Inputs can be paralleled as well. The AD8175 offers both serial and parallel programming modes. The AD8175 supports two modes of operation: differential-in to differential-out mode with sync-on CM signaling passed through the switch and differential-in to differential-out mode The AD8175 is packaged in a fully-populated 26 × 26 ball PBGA package and is available over the extended industrial temperature range of −40°C to +85°C. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007–2011 Analog Devices, Inc. All rights reserved. AD8175 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................8 Applications ....................................................................................... 1 Truth Table and Logic Diagram ............................................... 17 Functional Block Diagram .............................................................. 1 Equivalent Circuits ......................................................................... 19 General Description ......................................................................... 1 Typical Performance Characteristics ........................................... 21 Revision History ............................................................................... 2 Theory of Operation ...................................................................... 26 Specifications..................................................................................... 3 Applications..................................................................................... 27 Timing Characteristics (Serial Mode) ....................................... 5 Operating Modes ........................................................................ 27 Timing Characteristics (Parallel Mode) .................................... 6 Programming .............................................................................. 28 Absolute Maximum Ratings ............................................................ 7 Differential and Single-Ended Operation ............................... 30 Thermal Resistance ...................................................................... 7 Outline Dimensions ....................................................................... 39 Power Dissipation ......................................................................... 7 Ordering Guide .......................................................................... 39 ESD Caution .................................................................................. 7 REVISION HISTORY 10/11—Rev. A to Rev. B Changes to Table 15 ........................................................................ 17 Changes to Parallel Programming Description Section ............ 29 2/09—Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 39 5/07—Revision 0: Initial Version Rev. B | Page 2 of 40 Data Sheet AD8175 SPECIFICATIONS VS = ±2.5 V at TA = 25°C, G = +2, RL = 100 Ω (each output), VBLK = 0 V, output CM voltage = 0 V, differential I/O mode, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Gain Flatness Propagation Delay Settling Time Slew Rate, Differential Output Slew Rate, RGB Common Mode Slew Rate, HV Outputs NOISE/DISTORTION PERFORMANCE Crosstalk, All Hostile Off Isolation, Input-Output Input Voltage Noise DC PERFORMANCE Gain Error Gain Matching Gain Temperature Coefficient OUTPUT CHARACTERISTICS Output Offset Voltage Output Offset Voltage, RGB Common Mode Output Impedance Output Disable Capacitance Output Leakage Current Output Voltage Range Output Current INPUT CHARACTERISTICS Input Voltage Range, Differential Mode Input Voltage Range, Common Mode CMR, RGB Input CM Gain, RGB Input Input Capacitance Input Resistance Input Offset Current Conditions Min Typ Max Unit 200 mV p-p 2 V p-p 0.1 dB, 200 mV p-p 2 V p-p 1% , 2 V step 2 V step 2 V step, 10% to 90% 1 V step, 10% to 90% Rail-to-rail, TTL load 500 450 25 1.3 4 1800 1500 300 400 MHz MHz MHz ns ns V/µs V/µs V/µs V/µs ƒ = 5 MHz ƒ = 10 MHz ƒ = 100 MHz ƒ = 500 MHz ƒ = 5 MHz, RL = 100 Ω, one channel 0.01 MHz to 100 MHz −88 −82 −58 −46 −94 40 dB dB dB dB dB nV/√Hz R, G, B same channel 1 0.5 40 % % ppm/°C CMENC on or off Temperature coefficient CMENC on or off 10 31 10 mV µV/°C mV Temperature coefficient Enabled, differential Disabled, differential Disabled Disabled No load, differential Short circuit −7.6 1.5 2.7 2 1 45 µV/°C Ω kΩ pF µA V p-p mA 1.2 V p-p VIN = 1 V p-p, differential ±2.25 V ΔVOUT, DM/ΔVIN, CM, ΔVIN, CM = ±0.5 V, CMENC off ΔVOUT, DM/ΔVIN, CM, ΔVIN, CM = ±0.5 V, CMENC on ΔVOUT, CM/ΔVIN, CM, ΔVIN, CM = ±0.5 V CMENC off ΔVOUT, CM/ΔVIN, CM, ΔVIN, CM = ±0.5 V, CMENC on Any switch configuration Differential –62 −45 −70 0 2 3.33 1 dB dB dB dB pF kΩ µA 4 1 Rev. B | Page 3 of 40 AD8175 Parameter SWITCHING CHARACTERISTICS Enable On Time Switching Time, 2 V Step POWER SUPPLIES Supply Current Supply Voltage Range PSR OPERATING TEMPERATURE RANGE Temperature Range θJA Data Sheet Conditions Min Typ Max Unit 50% UPDATE to 50% output 50% UPDATE to 50% output 80 70 ns ns VPOS, outputs enabled, no load Outputs disabled VNEG, outputs enabled, no load Outputs disabled DVDD, outputs enabled, no load VPOS − VNEG VDD to DGND ΔVOUT, DM/ΔVPOS, ΔVPOS = ±0.5 V ΔVOUT, DM/ΔVNEG, ΔVNEG = ±0.5 V 600 290 600 290 4 4.5 to 5.5 3.3 to 5.5 −55 −55 mA mA mA mA mA V V dB dB Operating (still air) Operating (still air) −40 to +85 15 °C °C/W Rev. B | Page 4 of 40 Data Sheet AD8175 TIMING CHARACTERISTICS (SERIAL MODE) Specifications subject to change without notice. Table 2. Parameter Serial Data Setup Time CLK Pulse Width Serial Data Hold Time CLK Pulse Separation CLK to UPDATE Delay UPDATE Pulse width CLK to SEROUT Valid Propagation Delay, UPDATE to Switch On Data Load Time, CLK = 5 MHz, Serial Mode RST Time Symbol t1 t2 t3 t4 t5 t6 t7 Min 40 60 50 140 10 90 120 Limit Typ Max Unit ns ns ns ns ns ns ns ns µs ns 80 9 140 t2 200 t4 1 CLK LOAD DATA INTO SERIAL REGISTER ON FALLING EDGE 0 t1 t3 1 SERIN OUT8 (D3) OUT8 (D4) OUT00 (D0) 0 t5 1 = LATCHED t6 TRANSFER DATA FROM SERIAL REGISTER TO PARALLEL LATCHES DURING LOW LEVEL UPDATE 0 = TRANSPARENT 06478-002 t7 SEROUT Figure 2. Timing Diagram, Serial Mode Table 3. Logic Levels, VDD = 3.3 V VIH SER/PAR, CLK, SERIN, UPDATE VIL SER/PAR, CLK, SERIN, UPDATE VOH SEROUT VOL SEROUT IIH SER/PAR, CLK, SERIN, UPDATE IIL SER/PAR, CLK, SERIN, UPDATE IOH SEROUT IOL SEROUT 2.0 V min 0.6 V max 2.8 V min 0.4 V max 20 µA max –20 µA max –1 mA min 1 mA min Table 4. H and V Logic Levels, VDD = 3.3 V VOH 2.7 V min VOL 0.5 V max IOH –3 mA max IOL 3 mA max IIH −60 µA max IIL −120 µA max IIH 100 µA max IOL 40 µA max Table 5. RST Logic Levels, VDD = 3.3 V VIH 2.0 V min VIL 0.6 V max Table 6. CS Logic Levels, VDD = 3.3 V VOH 2.0 V min VOL 0.6 V max Rev. B | Page 5 of 40 AD8175 Data Sheet TIMING CHARACTERISTICS (PARALLEL MODE) Specifications subject to change without notice. Table 7. Parameter Parallel Data Setup Time WE Pulse Width Parallel Hold Time WE Pulse Separation WE to UPDATE Delay UPDATE Pulse Width Propagation Delay, UPDATE to Switch On RST Time Symbol t1 t2 t3 t4 t5 t6 t2 Min 80 110 150 90 10 90 Limit Typ Max 80 140 200 Unit ns ns ns ns ns ns ns ns t4 1 WE 0 t1 t3 1 D0 TO D4 A0 TO A4 0 t5 t6 06478-003 1 = LATCHED UPDATE 0 = TRANSPARENT Figure 3. Timing Diagram, Parallel Mode Table 8. Logic Levels, VDD = 3.3 V VIH SER/PAR, WE, D0, D1, D2, D3, D4, A0, A1, A2, A3, UPDATE 2.0 V min VIL SER/PAR, WE, D0, D1, D2, D3, D4, A0, A1, A2, A3, UPDATE 0.6 V max VOH SEROUT VOL SEROUT Disabled Disabled IIH SER/PAR, WE, D0, D1, D2, D3, D4, A0, A1, A2, A3, UPDATE 20 µA max IIL SER/PAR, WE, D0, D1, D2, D3, D4, A0, A1, A2, A3, UPDATE −20 µA max IOH SEROUT IOL SEROUT Disabled Disabled Table 9. H and V Logic Levels, VDD = 3.3 V VOH 2.7 V min VOL 0.5 V max IOH –3 mA max IOL 3 mA max IIH −60 µA max IIL −120 µA max IIH 100 µA max IOL 40 µA max Table 10. RST Logic Levels, VDD = 3.3 V VIH 2.0 V min VIL 0.6 V max Table 11. CS Logic Levels, VDD = 3.3 V VOH 2.0 V min VOL 0.6 V max Rev. B | Page 6 of 40 Data Sheet AD8175 ABSOLUTE MAXIMUM RATINGS POWER DISSIPATION Table 12. Parameter Analog Supply Voltage (VPOS – VNEG) Digital Supply Voltage (VDD – DGND) Ground Potential Difference (VNEG – DGND) Maximum Potential Difference (VDD – VNEG) Common-Mode Analog Input Voltage Differential Analog Input Voltage Digital Input Voltage Output Voltage (Disabled Analog Output) Output Short-Circuit Duration Storage Temperature Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature Rating +6 V +6 V +0.5 V to −2.5 V The AD8175 is operated with ±2.5 V or +5 V supplies and can drive loads down to 100 Ω, resulting in a large range of possible power dissipations. For this reason, extra care must be taken derating the operating conditions based on ambient temperature. +8 V (VNEG – 0.5 V) to (VPOS + 0.5 V) ±2 V VDD (VPOS – 1 V) to (VNEG + 1 V) Momentary −65°C to +125°C −40°C to +85°C 300°C 150°C Packaged in a 676-lead BGA, the AD8175 junction-to-ambient thermal impedance (θJA) is 15°C/W. For long-term reliability, the maximum allowed junction temperature of the die should not exceed 150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure. The following curve shows the range of allowed internal die power dissipations that meet these conditions over the −40°C to +85°C ambient temperature range. When using Table 12, do not include external load power in the Maximum Power calculation, but do include load current dropped on the die output transistors. 10 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TJ = 150°C THERMAL RESISTANCE 8 7 6 5 θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. 4 Table 13. Thermal Resistance 3 15 Package Type PBGA θJA 15 Unit °C/W 25 35 45 55 65 AMBIENT TEMPERATURE (°C) 75 85 06478-004 MAXIMUM POWER (W) 9 Figure 4. Maximum Die Power Dissipation vs. Ambient Temperature ESD CAUTION Rev. B | Page 7 of 40 AD8175 Data Sheet A 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VNEG VNEG VNEG OPR7 ONB7 VNEG OPR8 ONB8 VPOS IPR8 INB8 VNEG IPR9 INB9 VPOS IPR10 INB10 VNEG IPR11 INB11 VPOS IPR12 INB12 VNEG VNEG VNEG A B B VNEG VNEG VNEG ONR7 OPB7 VNEG ONR8 OPB8 VPOS INR8 IPB8 VNEG INR9 IPB9 VPOS INR10 IPB10 VNEG INR11 IPB11 VPOS INR12 IPB12 VNEG VNEG VNEG C VNEG VNEG VNEG OPG7 ONG7 VNEG OPG8 ONG8 VPOS IPG8 ING8 VNEG IPG9 ING9 VPOS IPG10 ING10 VNEG IPG11 ING11 VPOS IPG12 ING12 VNEG VNEG VNEG C D VNEG VNEG VNEG H7 V7 VPOS H8 V8 VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS IPG13 INR13 IPR13 D E VNEG VNEG VNEG VPOS VPOS VPOS VPOS VPOS DGND VDD SEROUT CS CLK SERIN SER/PAR A3 A2 A1 A0 VDD DGND VPOS VPOS ING13 IPB13 INB13 E F VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS F G ONB6 OPB6 ONG6 V6 VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS G H OPR6 ONR6 OPG6 H6 VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VPOS IPG14 INR14 IPR14 H J VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VPOS ING14 IPB14 INB14 J K ONB5 OPB5 ONG5 V5 VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VPOS VNEG VNEG VNEG K L OPR5 ONR5 OPG5 H5 VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VPOS IPG15 INR15 IPR15 L M VPOS VPOS VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VPOS ING15 IPB15 INB15 M N ONB4 OPB4 ONG4 V4 VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VOCM_ CMENCON VPOS VPOS VPOS VPOS N P OPR4 ONR4 OPG4 H4 VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VBLK VPOS VPOS VPOS VPOS P VPOS IPG7 INR7 IPR7 R R VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VOCM_ CMENCOFF T ONB3 OPB3 ONG3 V3 VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VPOS ING7 IPB7 INB7 T U OPR3 ONR3 OPG3 H3 VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VPOS VNEG VNEG VNEG U V VPOS VPOS VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VPOS IPG6 INR6 IPR6 V W ONB2 OPB2 ONG2 V2 VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VPOS ING6 IPB6 INB6 W Y OPR2 ONR2 OPG2 H2 VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS Y AA VNEG VNEG VNEG VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS AA AB VNEG VNEG VNEG VPOS VPOS VPOS VPOS VPOS DGND VDD RST UPDATE WE CMENC D4 D3 D2 D1 D0 VDD DGND VPOS VPOS IPG5 INR5 IPR5 AB AC VNEG VNEG VNEG V1 H1 VPOS V0 H0 VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS ING5 IPB5 INB5 AC AD VNEG VNEG VNEG ONG1 OPG1 VPOS ONG0 OPG0 VNEG ING0 IPG0 VPOS ING1 IPG1 VNEG ING2 IPG2 VPOS ING3 IPG3 VNEG ING4 IPG4 VNEG VNEG VNEG AD AE VNEG VNEG VNEG OPB1 ONR1 VPOS OPB0 ONR0 VNEG IPB0 INR0 VPOS IPB1 INR1 VNEG IPB2 INR2 VPOS IPB3 INR3 VNEG IPB4 INR4 VNEG VNEG VNEG AE AF VNEG VNEG VNEG ONB1 OPR1 VPOS ONB0 OPR0 VNEG INB0 IPR0 VPOS INB1 IPR1 VNEG INB2 IPR2 VPOS INB3 IPR3 VNEG INB4 IPR4 VNEG VNEG VNEG AF 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 5. Package Bottom View Rev. B | Page 8 of 40 06478-005 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD8175 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A VNEG VNEG VNEG INB12 IPR12 VPOS INB11 IPR11 VNEG INB10 IPR10 VPOS INB9 IPR9 VNEG INB8 IPR8 VPOS ONB8 OPR8 VNEG ONB7 OPR7 VNEG VNEG VNEG A B VNEG VNEG VNEG IPB12 INR12 VPOS IPB11 INR11 VNEG IPB10 INR10 VPOS IPB9 INR9 VNEG IPB8 INR8 VPOS OPB8 ONR8 VNEG OPB7 ONR7 VNEG VNEG VNEG B C VNEG VNEG VNEG ING12 IPG12 VPOS ING11 IPG11 VNEG ING10 IPG10 VPOS ING9 IPG9 VNEG ING8 IPG8 VPOS ONG8 OPG8 VNEG ONG7 OPG7 VNEG VNEG VNEG C D IPR13 INR13 IPG13 VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS V8 H8 VPOS V7 H7 VNEG VNEG VNEG D E INB13 IPB13 ING13 VPOS VPOS DGND VDD A0 A1 A2 A3 SER/PAR SERIN CLK CS SEROUT VDD DGND VPOS VPOS VPOS VPOS VPOS VNEG VNEG VNEG E F VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS F G VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS V6 ONG6 OPB6 ONB6 G H IPR14 INR14 IPG14 VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS H6 OPG6 ONR6 OPR6 H IPB14 ING14 VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG J J INB14 K VNEG VNEG VNEG VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS V5 ONG5 OPB5 ONB5 K L IPR15 INR15 IPG15 VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS H5 OPG5 ONR5 OPR5 L M INB15 IPB15 ING15 VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VPOS VPOS VPOS M N VPOS VPOS VPOS VPOS VOCM_ CMENCON VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS V4 ONG4 OPB4 ONB4 N P VPOS VPOS VPOS VPOS VBLK VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS H4 OPG4 ONR4 OPR4 P R IPR7 INR7 IPG7 VPOS VOCM_ CMENCOFF VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG R T INB7 IPB7 ING7 VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS V3 ONG3 OPB3 ONB3 T U VNEG VNEG VNEG VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS H3 OPG3 ONR3 OPR3 U V IPR6 INR6 IPG6 VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VPOS VPOS VPOS V W INB6 IPB6 ING6 VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS V2 ONG2 OPB2 ONB2 W VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS H2 OPG2 ONR2 OPR2 Y Y VPOS VPOS VPOS AA VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VNEG VNEG VNEG AA AB IPR5 INR5 IPG5 VPOS VPOS DGND VDD D0 D1 D2 D3 D4 CMENC WE UPDATE RST VDD DGND VPOS VPOS VPOS VPOS VPOS VNEG VNEG VNEG AB AC INB5 IPB5 ING5 VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS H0 V0 VPOS H1 V1 VNEG VNEG VNEG AC AD VNEG VNEG VNEG IPG4 ING4 VNEG IPG3 ING3 VPOS IPG2 ING2 VNEG IPG1 ING1 VPOS IPG0 ING0 VNEG OPG0 ONG0 VPOS OPG1 ONG1 VNEG VNEG VNEG AD AE VNEG VNEG VNEG INR4 IPB4 VNEG INR3 IPB3 VPOS INR2 IPB2 VNEG INR1 IPB1 VPOS INR0 IPB0 VNEG ONR0 OPB0 VPOS ONR1 OPB1 VNEG VNEG VNEG AE AF VNEG VNEG VNEG IPR4 INB4 VNEG IPR3 INB3 VPOS IPR2 INB2 VNEG IPR1 INB1 VPOS IPR0 INB0 VNEG OPR0 ONB0 VPOS OPR1 ONB1 VNEG VNEG VNEG AF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Figure 6. Package Top View Rev. B | Page 9 of 40 06478-006 Data Sheet AD8175 Data Sheet Table 14. Ball Grid Description Ball No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 Mnemonic VNEG VNEG VNEG INB12 IPR12 VPOS INB11 IPR11 VNEG INB10 IPR10 VPOS INB9 IPR9 VNEG INB8 IPR8 VPOS ONB8 OPR8 VNEG ONB7 OPR7 VNEG VNEG VNEG VNEG VNEG VNEG IPB12 INR12 VPOS IPB11 INR11 VNEG IPB10 INR10 VPOS IPB9 INR9 VNEG IPB8 INR8 VPOS OPB8 ONR8 VNEG OPB7 ONR7 VNEG VNEG Description Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Input Number 12, Negative Phase. Input Number 12, Positive Phase. Positive Analog Power Supply. Input Number 11, Negative Phase. Input Number 11, Positive Phase. Negative Analog Power Supply. Input Number 10, Negative Phase. Input Number 10, Positive Phase. Positive Analog Power Supply. Input Number 9, Negative Phase. Input Number 9, Positive Phase. Negative Analog Power Supply. Input Number 8, Negative Phase. Input Number 8, Positive Phase. Positive Analog Power Supply. Output Number 8, Negative Phase. Output Number 8, Positive Phase. Negative Analog Power Supply. Output Number 7, Negative Phase. Output Number 7, Positive Phase. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Input Number 12, Positive Phase. Input Number 12, Negative Phase. Positive Analog Power Supply. Input Number 11, Positive Phase. Input Number 11, Negative Phase. Negative Analog Power Supply. Input Number 10, Positive Phase. Input Number 10, Negative Phase. Positive Analog Power Supply. Input Number 9, Positive Phase. Input Number 9, Negative Phase. Negative Analog Power Supply. Input Number 8, Positive Phase. Input Number 8, Negative Phase. Positive Analog Power Supply. Output Number 8, Positive Phase. Output Number 8, Negative Phase. Negative Analog Power Supply. Output Number 7, Positive Phase. Output Number 7, Negative Phase. Negative Analog Power Supply. Negative Analog Power Supply. Ball No. B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 Rev. B | Page 10 of 40 Mnemonic VNEG VNEG VNEG VNEG ING12 IPG12 VPOS ING11 IPG11 VNEG ING10 IPG10 VPOS ING9 IPG9 VNEG ING8 IPG8 VPOS ONG8 OPG8 VNEG ONG7 OPG7 VNEG VNEG VNEG IPR13 INR13 IPG13 VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS V8 H8 VPOS V7 H7 VNEG Description Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Input Number 12, Negative Phase. Input Number 12, Positive Phase. Positive Analog Power Supply. Input Number 11, Negative Phase. Input Number 11, Positive Phase. Negative Analog Power Supply. Input Number 10, Negative Phase. Input Number 10, Positive Phase. Positive Analog Power Supply. Input Number 9, Negative Phase. Input Number 9, Positive Phase. Negative Analog Power Supply. Input Number 8, Negative Phase. Input Number 8, Positive Phase. Positive Analog Power Supply. Output Number 8, Negative Phase. Output Number 8, Positive Phase. Negative Analog Power Supply. Output Number 7, Negative Phase. Output Number 7, Positive Phase. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Input Number 13, Positive Phase. Input Number 13, Negative Phase. Input Number 13, Positive Phase. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Output Number 8, V Sync. Output Number 8, H Sync. Positive Analog Power Supply. Output Number 7, V Sync. Output Number 7, H Sync. Negative Analog Power Supply. Data Sheet Ball No. D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 Mnemonic VNEG VNEG INB13 IPB13 ING13 VPOS VPOS DGND VDD A0 A1 A2 A3 SER/PAR SERIN CLK CS SEROUT VDD DGND VPOS VPOS VPOS VPOS VPOS VNEG VNEG VNEG VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS AD8175 Description Negative Analog Power Supply. Negative Analog Power Supply. Input Number 13, Negative Phase. Input Number 13, Positive Phase. Input Number 13, Negative Phase. Positive Analog Power Supply. Positive Analog Power Supply. Digital Power Supply. Digital Power Supply. Control Pin 0, Output Address Bit 0. Control Pin 1, Output Address Bit 1. Control Pin 2, Output Address Bit 2. Control Pin 3, Output Address Bit 3. Control Pin: Serial Parallel Select Mode. Control Pin: Serial Data In. Control Pin: Serial Data Clock. Control Pin: Chip Select. Control Pin: Serial Data Out. Digital Power Supply. Digital Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Ball No. F25 F26 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 Rev. B | Page 11 of 40 Mnemonic VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS V6 ONG6 OPB6 ONB6 IPR14 INR14 IPG14 VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS H6 OPG6 Description Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Output Number 6, V Sync. Output Number 6, Negative Phase. Output Number 6, Positive Phase. Output Number 6, Negative Phase. Input Number 14, Positive Phase. Input Number 14, Negative Phase. Input Number 14, Positive Phase. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Output Number 6, H Sync. Output Number 6, Positive Phase. AD8175 Ball No. H25 H26 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 Mnemonic ONR6 OPR6 INB14 IPB14 ING14 VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS V5 ONG5 Data Sheet Description Output Number 6, Negative Phase. Output Number 6, Positive Phase. Input Number 14, Negative Phase. Input Number 14, Positive Phase. Input Number 14, Negative Phase. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Output Number 5, V Sync. Output Number 5, Negative Phase. Ball No. K25 K26 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 Rev. B | Page 12 of 40 Mnemonic OPB5 ONB5 IPR15 INR15 IPG15 VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS H5 OPG5 ONR5 OPR5 INB15 IPB15 ING15 VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VPOS Description Output Number 5, Positive Phase. Output Number 5, Negative Phase. Input Number 15, Positive Phase. Input Number 15, Negative Phase. Input Number 15, Positive Phase. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Output Number 5, H Sync. Output Number 5, Positive Phase. Output Number 5, Negative Phase. Output Number 5, Positive Phase. Input Number 15, Negative Phase. Input Number 15, Positive Phase. Input Number 15, Negative Phase. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Data Sheet Ball No. M25 M26 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 Mnemonic VPOS VPOS VPOS VPOS VPOS VPOS VOCM_ CMENCON VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS V4 ONG4 OPB4 ONB4 VPOS VPOS VPOS VPOS VBLK VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS H4 OPG4 AD8175 Description Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Output CM Reference with CM Encoding On. Positive Analog Power Supply. Positive Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Output Number 4, V Sync. Output Number 4, Negative Phase. Output Number 4, Positive Phase. Output Number 4, Negative Phase. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Output Blank Level. Positive Analog Power Supply. Positive Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Output Number 4, H Sync. Output Number 4, Positive Phase. Ball No. P25 P26 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 Rev. B | Page 13 of 40 Mnemonic ONR4 OPR4 IPR7 INR7 IPG7 VPOS VOCM_ CMENCOFF VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG INB7 IPB7 ING7 VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS V3 ONG3 Description Output Number 4, Negative Phase. Output Number 4, Positive Phase. Input Number 7, Positive Phase. Input Number 7, Negative Phase. Input Number 7, Positive Phase. Positive Analog Power Supply. Output Reference with CM Encoding Off. Positive Analog Power Supply. Positive Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Input Number 7, Negative Phase. Input Number 7, Positive Phase. Input Number 7, Negative Phase. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Output Number 3, V Sync. Output Number 3, Negative Phase. AD8175 Ball No. T25 T26 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 Mnemonic OPB3 ONB3 VNEG VNEG VNEG VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS H3 OPG3 ONR3 OPR3 IPR6 INR6 IPG6 VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VPOS Data Sheet Description Output Number 3, Positive Phase. Output Number 3, Negative Phase. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Output Number 3, H Sync. Output Number 3, Positive Phase. Output Number 3, Negative Phase. Output Number 3, Positive Phase. Input Number 6, Positive Phase. Input Number 6, Negative Phase. Input Number 6, Positive Phase. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Ball No. V25 V26 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Rev. B | Page 14 of 40 Mnemonic VPOS VPOS INB6 IPB6 ING6 VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS V2 ONG2 OPB2 ONB2 VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS H2 OPG2 Description Positive Analog Power Supply. Positive Analog Power Supply. Input Number 6, Negative Phase. Input Number 6, Positive Phase. Input Number 6, Negative Phase. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Output Number 2, V Sync. Output Number 2, Negative Phase. Output Number 2, Positive Phase. Output Number 2, Negative Phase. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Output Number 2, H Sync. Output Number 2, Positive Phase. Data Sheet Ball No. Y25 Y26 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 Mnemonic ONR2 OPR2 VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VNEG VNEG VNEG IPR5 INR5 IPG5 VPOS VPOS DGND VDD D0 D1 D2 D3 D4 CMENC WE UPDATE RST VDD DGND VPOS VPOS VPOS VPOS VPOS VNEG AD8175 Description Output Number 2, Negative Phase. Output Number 2, Positive Phase. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Input Number 5, Positive Phase. Input Number 5, Negative Phase. Input Number 5, Positive Phase. Positive Analog Power Supply. Positive Analog Power Supply. Digital Power Supply. Digital Power Supply. Control Pin, Input Address Bit 0. Control Pin, Input Address Bit 1. Control Pin, Input Address Bit 2. Control Pin, Input Address Bit 3. Control Pin, Input Address Bit 4. Control Pin, Pass/Stop CM Encoding. Control Pin, 1st Rank Write Strobe. Control Pin, 2nd Rank Write Strobe. Control Pin, 2nd Rank Data Reset. Digital Power Supply. Digital Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Negative Analog Power Supply. Ball No. AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 Rev. B | Page 15 of 40 Mnemonic VNEG VNEG INB5 IPB5 ING5 VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS H0 V0 VPOS H1 V1 VNEG VNEG VNEG VNEG VNEG VNEG IPG4 ING4 VNEG IPG3 ING3 VPOS IPG2 ING2 VNEG IPG1 ING1 VPOS IPG0 ING0 VNEG OPG0 ONG0 VPOS OPG1 ONG1 VNEG Description Negative Analog Power Supply. Negative Analog Power Supply. Input Number 5, Negative Phase. Input Number 5, Positive Phase. Input Number 5, Negative Phase. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Output Number 1, H Sync. Output Number 0, V Sync. Positive Analog Power Supply. Output Number 1, H Sync. Output Number 1, V Sync. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Input Number 4, Positive Phase. Input Number 4, Negative Phase. Negative Analog Power Supply. Input Number 3, Positive Phase. Input Number 3, Negative Phase. Positive Analog Power Supply. Input Number 2, Positive Phase. Input Number 2, Negative Phase. Negative Analog Power Supply. Input Number 1, Positive Phase. Input Number 1, Negative Phase. Positive Analog Power Supply. Input Number 0, Positive Phase. Input Number 0, Negative Phase. Negative Analog Power Supply. Output Number 0, Positive Phase. Output Number 0, Negative Phase. Positive Analog Power Supply. Output Number 1, Positive Phase. Output Number 1, Negative Phase. Negative Analog Power Supply. AD8175 Ball No. AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 Mnemonic VNEG VNEG VNEG VNEG VNEG INR4 IPB4 VNEG INR3 IPB3 VPOS INR2 IPB2 VNEG INR1 IPB1 VPOS INR0 IPB0 VNEG ONR0 OPB0 VPOS ONR1 OPB1 VNEG VNEG Data Sheet Description Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Input Number 4, Negative Phase. Input Number 4, Positive Phase. Negative Analog Power Supply. Input Number 3, Negative Phase. Input Number 3, Positive Phase. Positive Analog Power Supply. Input Number 2, Negative Phase. Input Number 2, Positive Phase. Negative Analog Power Supply. Input Number 1, Negative Phase. Input Number 1, Positive Phase. Positive Analog Power Supply. Input Number 0, Negative Phase. Input Number 0, Positive Phase. Negative Analog Power Supply. Output Number 0, Negative Phase. Output Number 0, Positive Phase. Positive Analog Power Supply. Output Number 1, Negative Phase. Output Number 1, Positive Phase. Negative Analog Power Supply. Negative Analog Power Supply. Ball No. AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Rev. B | Page 16 of 40 Mnemonic VNEG VNEG VNEG VNEG IPR4 INB4 VNEG IPR3 INB3 VPOS IPR2 INB2 VNEG IPR1 INB1 VPOS IPR0 INB0 VNEG OPR0 ONB0 VPOS OPR1 ONB1 VNEG VNEG VNEG Description Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Input Number 4, Positive Phase. Input Number 4, Negative Phase. Negative Analog Power Supply. Input Number 3, Positive Phase. Input Number 3, Negative Phase. Positive Analog Power Supply. Input Number 2, Positive Phase. Input Number 2, Negative Phase. Negative Analog Power Supply. Input Number 1, Positive Phase. Input Number 1, Negative Phase. Positive Analog Power Supply. Input Number 0, Positive Phase. Input Number 0, Negative Phase. Negative Analog Power Supply. Output Number 0, Positive Phase. Output Number 0, Negative Phase. Positive Analog Power Supply. Output Number 1, Positive Phase. Output Number 1, Negative Phase. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Data Sheet AD8175 TRUTH TABLE AND LOGIC DIAGRAM Table 15. Operation Truth Table WE X UPDATE X CLK X SERIN X SEROUT X RST 0 SER/PAR X CS X CMENC X 0 1 1 X X 1 0 0 X 1 1 SERINi SERINi-45 1 0 0 X 0 1 1 X X 1 1 X X 1 0 1 X X 1 X 0 X 1 X X X X 1 1 0 X Rev. B | Page 17 of 40 Operation/Comment Asynchronous reset. All outputs are disabled. Contents of 45-bit shift register are unchanged. Broadcast. The data on D0 through D4 is loaded into all locations of the 45-bit shift register. Data is not applied to switch array. Serial mode. The data on the SERIN line is loaded into the 45-bit shift register. The first bit clocked into the shift register appears at SEROUT 45 clock cycles later. Data is not applied to switch array. Parallel mode. The data on parallel lines D0 through D4 is loaded into the shift register location addressed by A0 through A3. Data is not applied to switch array. Chip select feature is not applicable. Switch array update. Data in the 45-bit shift register is transferred to the parallel latches and applied to the switch array. No change in logic. A0 A1 A2 A3 OUTPUT ADDRESS 4 TO 9 DECODER CS CLK WE SERIN Figure 7. Logic Diagram Rev. B | Page 18 of 40 D4 D0 D1 D2 D3 RST CS UPDATE OUT8 EN OUT7 EN OUT6 EN OUT5 EN OUT4 EN OUT3 EN OUT2 EN OUT1 EN OUT0 EN (OUTPUT ENABLE) SER/PAR PARALLEL DATA OUT0 B0 CLR Q ENA D S D1 Q D Q D0 CLK OUT0 B1 CLR Q ENA D S D1 Q D Q D0 CLK OUT0 B2 CLR Q ENA D S D1 Q D Q D0 CLK OUT0 EN CLR Q ENA D S D1 Q D Q D0 CLK 144 SWITCH MATRIX OUT0 B3 CLR Q ENA D S D1 Q D Q D0 CLK OUT1 B0 CLR Q ENA D S D1 Q D Q D0 CLK DECODE OUT7 EN CLR Q ENA D S D1 Q D Q D0 CLK OUT8 B0 CLR Q ENA D S D1 Q D Q D0 CLK OUT8 B2 CLR Q ENA D S D1 Q D Q D0 CLK 9 OUTPUT ENABLE OUT8 B1 CLR Q ENA D S D1 Q D Q D0 CLK OUT8 B3 CLR Q ENA D S D1 Q D Q D0 CLK OUT8 EN CLR Q ENA D S D1 Q D Q D0 CLK SEROUT AD8175 Data Sheet 06478-029 Data Sheet AD8175 EQUIVALENT CIRCUITS VPOS 10kΩ 0.1pF OPn, ONn VBLK, VOCM_CMENCOFF 10kΩ 0.1pF 1kΩ 06478-012 06478-007 1kΩ (VPOS – VNEG) 2 VNEG Figure 13. VBLK and VOCM_CMENCOFF Inputs (see also ESD Protection Map, Figure 19) Figure 8. Enabled Output (see also ESD Protection Map , Figure 19) VPOS VPOS 20kΩ OPn 20kΩ VNEG 3.1kΩ 0.4pF 3.33kΩ 0.3pF 3.4pF VOCM_CMENCON VPOS 3.4pF 3.33kΩ 0.3pF 20kΩ 06478-008 VNEG VNEG Figure 9. Disabled Output (see also ESD Protection Map, Figure 19) 2500Ω IPn 06478-013 ONn 20kΩ Figure 14. VOCM_CMENCON Input (see also ESD Protection Map, Figure 19) 2525Ω VDD 1.3pF 25kΩ 2500Ω 06478-009 1.3pF INn 2525Ω RST 1kΩ DGND Figure 10. Receiver, Differential (see also ESD Protection Map, Figure 19) 06478-014 10kΩ 0.3pF Figure 15. RST Input (see also ESD Protection Map, Figure 19) IPn 1.3pF 2500Ω INn 06478-010 2500Ω 1.3pF 1kΩ DGND Figure 11. Receiver Simplified Equivalent Circuit When Driving Differentially 06478-015 CLK, SER/PAR, WE, UPDATE, SERIN A[3:0], D[4:0], CMENC 10kΩ 0.3pF Figure 16. Logic Input (see also ESD Protection Map, Figure 19) IPn 1kΩ 25kΩ DGND 06478-048 INn CS 2.5kΩ 06478-011 1.6pF Figure 17. CS Input (see also ESD Protection Map, Figure 19) Figure 12. Receiver Simplified Equivalent Circuit When Driving Single-Ended Rev. B | Page 19 of 40 Data Sheet VDD VDD VNEG DGND IPn, INn, OPn, ONn, VBLK, VOCM_CMENCOFF VOCM_CMENCON 06478-016 SEROUT, H, V DGND VPOS Figure 19. ESD Protection Map Figure 18. SEROUT, H, V Logic Outputs (see also ESD Protection Map, Figure 19) Rev. B | Page 20 of 40 CLK, RST, SER/PAR, WE, UPDATE, SERIN, SEROUT, A[3:0], D[4:0], CMENC, CS 06478-017 AD8175 Data Sheet AD8175 TYPICAL PERFORMANCE CHARACTERISTICS VS = ±2.5 V at TA = 25°C, G = +2, RL = 100 Ω (each output), VBLK = 0 V, output CM voltage = 0 V, differential I/O mode, unless otherwise noted. 12 0.15 10 0.10 8 0.05 VOUT, DIFF (V) GAIN (dB) 6 4 2 0 –0.05 0 –2 –0.10 1 10 100 1000 FREQUENCY (MHz) –0.15 06478-031 –6 2 4 6 8 10 12 14 16 18 20 TIME (ns) 06478-033 –4 Figure 23. Small Signal Pulse Response, 200 mV p-p Figure 20. Small Signal Frequency Response, 200 mV p-p 1.5 12 10 1.0 8 0.5 VOUT, DIFF (V) GAIN (dB) 6 4 2 0 –0.5 0 –2 –1.0 –1.5 1 10 100 1000 FREQUENCY (MHz) 2 06478-032 –6 4 6 8 10 12 14 16 18 Figure 24. Large Signal Pulse Response, 2 V p-p Figure 21. Large Signal Frequency Response, 2 V p-p 5 16 14 1.2 VIN 10pF 5pF 12 20 TIME (ns) 06478-034 –4 0 0.8 –5 0.4 0pF 8 6 4 2 –10 0 VOUT –15 VOUT, DIFF (V) GAIN (dB) 10 OUTPUT ERROR (%) 2pF –0.4 ERROR 0 –20 –0.8 1 10 100 FREQUENCY (MHz) 1000 –25 0 1 2 3 4 5 6 7 TIME (ns) Figure 25. Settling Time Figure 22. Small Signal Frequency Response with Capacitive Loads Rev. B | Page 21 of 40 8 9 –1.2 10 06478-035 –4 06478-055 –2 AD8175 Data Sheet 5 0 4 –20 2 CROSSTALK (dB) OUTPUT ERROR (%) 3 1 0 –1 –2 –3 –40 –60 –80 –100 2 3 4 5 6 7 8 9 10 TIME (ns) –120 1 0 4000 –1 3000 –20 1850V/µs PEAK –2 2000 –3 1000 –4 0 –5 3 4 5 6 7 8 9 FEEDTHROUGH (dB) 5000 SLEW RATE (V/µs) 1 0 –40 –60 –80 –100 –1000 10 TIME (ns) –120 06478-046 VOUT, DIFF (V) 6000 2 1000 Figure 29. Crosstalk, All Hostile 2 1 100 FREQUENCY (MHz) Figure 26. Settling Time, 1% Zoom 0 10 1 10 100 1000 06478-037 1 1000 06478-038 0 06478-047 –5 06478-057 –4 FREQUENCY (MHz) Figure 30. Crosstalk, Off Isolation Figure 27. Large Signal Rising Edge Slew Rate 0 0 –10 –20 CMENC HIGH CMR (dB) –30 –60 –40 CMENC LOW –50 –80 –60 –100 –70 –120 1 10 100 FREQUENCY (MHz) 1000 06478-056 CROSSTALK (dB) –20 –40 –80 1 10 100 FREQUENCY (MHz) Figure 31. Common-Mode Rejection Figure 28. Crosstalk, All Hostile, Single-Ended Rev. B | Page 22 of 40 Data Sheet AD8175 10000 600 |Ipos| AND |Ineg| (BROADCAST) |Ipos| AND |Ineg| (mA) 500 IMPEDANCE (Ω) 400 300 |Ipos| AND |Ineg| (ALL OUTPUTS DISABLED) 200 1000 100 10 100 1000 06478-051 1 1000 06478-052 TEMPERATURE (°C) 100 1000 06478-039 10 20 30 40 50 60 70 80 90 100 06478-043 0 –50 –40 –30 –20 –10 0 FREQUENCY (MHz) Figure 32. Quiescent Supply Currents vs. Temperature Figure 35. Input Impedance 3000 10000 2000 IMPEDANCE (Ω) IMPEDANCE (Ω) 2500 1500 1000 1000 500 1 10 100 1000 FREQUENCY (MHz) 100 06478-049 0 1 10 100 FREQUENCY (MHz) Figure 33. Output Impedance, Disabled Figure 36. Input Impedance, Single-Ended 120 0 –10 100 BALANCE ERROR (dB) 60 40 –30 –40 –50 –60 20 –70 0 1 10 100 FREQUENCY (MHz) 1000 06478-050 IMPEDANCE (Ω) –20 80 Figure 34. Output Impedance, Enabled –80 1 10 100 FREQUENCY (MHz) Figure 37. Output Balance Error Rev. B | Page 23 of 40 AD8175 Data Sheet 1.0 20 2500 2250 RED 15 2000 GREEN BLUE 1750 10 –0.5 5 HSYNC 1500 COUNT 0 VOUT (V) VOUT, COMMON MODE (V) 0.5 1000 750 VSYNC –1.0 1250 0 500 100 200 300 400 500 600 700 800 900 0 06478-058 0 –5 1000 TIME (ns) –70 –60 –50 –40 –30 –20 –10 0 Figure 38. Common-Mode Pulse Response Figure 41. VOS Distribution 0 2.0 –10 1.5 1.0 31µV/°C –30 0.5 VOS (mV) –40 –50 –0.5 –60 –1.0 –70 10 100 1000 FREQUENCY (MHz) –2.0 –40 06478-040 1 –20 20 40 60 80 100 60 80 100 TEMPERATURE (°C) Figure 42. VOS Drift, RTO Figure 39. Common-Mode Isolation, CMENC Low 0.6 200 0.4 VOS, COMMON-MODE (mV) 160 120 80 40 0.2 –7.6µV/°C 0 –0.2 –0.4 0 10 20 30 40 50 60 70 FREQUENCY (MHz) 80 90 100 06478-059 0 0 06478-045 –1.5 –80 –90 0 –0.6 –40 –20 0 20 40 TEMPERATURE (°C) Figure 43. VOS Drift, Common Mode, RTO Figure 40. Noise Spectral Density Rev. B | Page 24 of 40 06478-044 FEEDTHROUGH (dB) –20 NOISE SPECTRAL DENSITY (nV/√Hz) 10 20 30 40 50 60 70 VOS (mV) 06478-041 250 –1.5 Data Sheet AD8175 6 0.025 1.2 VOUT UPDATE 5 0.020 1.0 0.6 2 0.4 1 0.2 0 0 NORMALIZED DC GAIN (dB) 3 VOUT, SINGLE-ENDED (V) 0.8 0.010 0.005 0 40ppm/°C –0.005 –0.010 –0.015 0 20 40 60 –0.2 80 100 120 140 160 180 200 220 240 260 280 TIME (ns) Figure 44. Enable Time –0.025 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 45. Normalized DC Gain vs. Temperature Rev. B | Page 25 of 40 100 06478-054 –0.020 –1 06478-042 UPDATE (V) 0.015 4 AD8175 Data Sheet THEORY OF OPERATION The AD8175 is a non-blocking crosspoint with 16 differential RGB input channels and nine differential RGB output channels. Although the AD8175 is primarily meant for differential-in, differential-out middle-of-CAT5-run applications, each differential RGB output channel is complemented by H and V syncs for use in end-of-CAT5-run, single-ended output applications. Processing of common-mode (CM) voltage levels is achieved by placing the AD8175 in either of its two operation modes. In the first operation mode (CMENC low), the input CM of each RGB differential pair (possibly present either in the form of sync-on CM signaling or noise) is removed through the switch, and the output CM is set to a global reference voltage via the VOCM_ CMENCOFF analog input. Therefore, the AD8175 can behave as a differential-in, differential-out switch. If sync-on CM signaling is present at the differential RGB inputs, then the H and V outputs represent decoded syncs. In the second operation mode, input sync-on CM signaling is propagated through the switch. Note that in this mode, as in the previous one, the overall input CM is blocked through the switch. In this mode, the overall output CM is set to a global reference voltage via the VOCM_CMENCON analog input. In either operation mode, input pin VBLK defines the black level of the positive output phase. The combination of VBLK and VOCM_CMENCOFF allows the user to position the positive and negative output phases anywhere in the allowable output voltage range. The switch is organized into nine 16:1 RBG multiplexers, with each being responsible for connecting an RGB input channel to its respective RGB output channel. Decoding logic selects a single input (or none) in each multiplexer and connects it to its respective output. Feedback around each multiplexer realizes a closed-loop differential-in, differential-out gain of +2. A second loop realizes a closed-loop common-mode-in gain of +1. Each differential RGB input channel is buffered by a differential receiver, which is capable of accepting input CM voltages extending all the way to either supply rail. In addition to passing differential information, each receiver processes and routes input CM voltages. Excess closed-loop receiver bandwidth reduces the receiver’s effect on the overall device bandwidth. The output stage is designed for fast slew rate and settling time while driving a series-terminated CAT5 cable. Unlike competing multiplexer designs, the small signal bandwidth closely approaches the large signal bandwidth. The outputs of the AD8175 can be disabled to minimize onchip power dissipation. When disabled, there is a feedback network of approximately 2.7 kΩ between the differential outputs. This high impedance allows multiple ICs to be bussed together without additional buffering. Care must be taken to reduce output capacitance, which can result in overshoot and frequency-domain peaking. A series of internal amplifiers drive internal nodes such that wideband high impedance is presented at the disabled output, even while the output bus experiences fast signal swings. When the outputs are disabled and driven externally, the voltage applied to them should not exceed the valid output swing range for the AD8175 in order to keep these internal amplifiers in their linear range of operation. Applying excessive differential voltages to the disabled outputs can cause damage to the AD8175 and should be avoided (see the Absolute Maximum Ratings section of this data sheet for guidelines). The connectivity of the AD8175 is controlled by a flexible TTLcompatible logic interface. Either parallel or serial loading into a first rank of latches preprograms each output. A global update signal moves the programming data into the second rank of latches, simultaneously updating all outputs. In serial mode, a serial-out pin allows devices to be daisy-chained together for a single-pin programming of multiple ICs. A power-on reset pin is available to avoid bus conflicts by disabling all outputs. This power-on reset clears the second rank of latches, but does not clear the first rank of latches. A broadcast parallel programming feature is available in parallel mode to quickly clear the first rank. In serial mode, preprogramming individual inputs is not possible and the entire shift register needs to be flushed. A global chip-select pin gates the input clock and the global update signal to the second rank of buffers. The AD8175 can operate on a single +5 V supply, powering both the signal path (with the VPOS/VNEG supply pins) and the control logic interface (with the VDD/DGND supply pins). Split supply operation is possible with ±2.5 V supplies in order to easily interface to ground-referenced video signals. In this case, a flexible logic interface allows the control logic supplies (VDD/DGND) to be run off +5 V/0 V to +3.3 V/0 V while the analog core remains on split supplies. Additional flexibility in the analog output common-mode level (VOCM_CMENCOFF) and output black level (VBLK) facilitates operation with unequally split supplies. If +3 V/−2 V supplies to +2 V/−3 V supplies are desired, the output CM can still be set to 0 V for ground-referenced video signals. Rev. B | Page 26 of 40 Data Sheet AD8175 APPLICATIONS OPERATING MODES Depending on the state of the CMENC logic input, the AD8175 can be set in either of two differential-in, differential-out operating modes. An additional application is possible by tapping the outputs single-ended and making use of the decoded H and V outputs. VOCM_CMENCOFF and VBLK both set to 0 V. (Note that both pulses have been slightly shifted off the 0 V line for clarity.) VOCM_CMENCOFF = 0V 0.7V POSITIVE PHASE VBLK = 0V In this application, the AD8175 is placed somewhere in the middle of a CAT5 run. By tying CMENC low, the CM of each RGB differential pair is removed through the device (or turned off), while the overall CM at the output is defined by the reference value VOCM_CMENCOFF. In this mode of operation, CM noise is removed, while the intended differential RGB signals are buffered and passed to the outputs. The AD8175 is placed in this operation mode when used in a sync-on color scheme. Figure 46 shows the voltage levels and CM handling for a single input channel connected to a single output channel in a middleof-CAT5-run application with CM encoding turned off. DIFF. R DIFF. B CMB DIFF. R INPUT OVERALL CM AD8175 DIFF. B DIFF. G CMR CMG –0.7V Figure 47. Output for 0 V to 0.7 V Input Differential Pulse, VBLK = 0 V, VOCM_CMENCOFF = 0 V As a second example, refer to Figure 48. VCOM_CMENCOFF is set to 0.35 V, while VBLK is set to −0.35 V. The input is still a differential pulse with a low level of 0 V and a high level of 0.7 V. Note how the positive phase and the negative phase are now shifted with respect to each other by an amount equal to VBLK – VOCM_CMENCOFF or −0.35 V − 0.35 V = −0.7 V. Since the negative output phase spans the same voltage range as the positive output phase, the usable voltage range for singleended applications is effectively doubled over the previous example. (Note that the output pulses have been slightly shifted with respect to each other for clarity.) CMB VOCM_CMENCOFF = 0.35V OUTPUT OVERALL CM DIFF. G CMG NEGATIVE 0.7V PHASE 06478-019 CMENC VOCM_CMENCOFF VBLK = –0.35V Figure 46. AD8175 in a Middle-of-CAT5-Run Application, CM Encoding Off (Note that in this application, the H and V outputs, though asserted, are not used) Inputs VBLK and VOCM_CMENCOFF allow the user complete flexibility in defining the output CM level and the amount of overlap between the positive and negative phases, thus maximizing output headroom usage. Whenever VBLK differs from VOCM_CMENCOFF by more than approximately ±100 mV, a differential voltage Δdiff is added at the outputs according to the expression Δdiff = VBLK − VOCM_CMENCOFF. Conversely, whenever the difference between VBLK and VOCM_CMENCOFF is less than approximately ±100 mV, no differential voltage is added at the outputs. As a first example, refer to Figure 47. The positive phase of a differential output is shown by the solid line, while the negative phase is shown by the dashed line. The input to the crosspoint is a positive differential pulse with a low level of 0 V and a high level of 0.7 V. The positive and negative outputs are shown with 0V POSITIVE PHASE 06478-021 CMR NEGATIVE PHASE 06478-020 Middle-of-CAT5-Run Application, CM Encoding Turned Off Figure 48. Output for 0 V to 0.7 V Input Differential Pulse, VBLK = −0.35 V, VOCM_CMENCOFF = 0.35 V Middle-of-CAT5-Run Application, CM Encoding Turned On In this application, the AD8175 is also placed somewhere in the middle of a CAT5 run, although the common-mode handling is different. By tying CMENC high, the CM of each RGB input is passed through the part, while at the same time, the overall output CM is stripped and set equal to the voltage applied at the VOCM_CMENCON pin. The AD8175 is placed in this operation mode when used with a sync-on CM scheme. Although asserted, the H and V outputs are not used in this application. Figure 49 shows the voltage levels and CM handling for a single input channel connected to a single output channel in a middle-ofCAT5-run application with CM encoding turned on. Rev. B | Page 27 of 40 AD8175 Data Sheet PROGRAMMING DIFF. R DIFF. B CMR DIFF. R CMB DIFF. B CMR INPUT OVERALL CM CMB AD8175 OUTPUT OVERALL CM DIFF. G CMG DIFF. G 06478-022 CMG CMENC VOCM_CMENCON Figure 49. AD8175 in Middle-of-CAT5-Run Application, CM Encoding On (Note that in this application, the H and V outputs, though asserted, are not used) In this operation mode, the difference Δdiff = VBLK − VOCM_CMENCOFF still adds an output differential voltage, as described in the previous section. End-of-CAT5-Run, CM Encoding Turned Off In this application, each AD8175 output is tapped single-ended at the positive phase and followed by a fast buffer to drive a monitor at the end of a CAT5 run (a suitable choice is the AD8003 set up in a noninverting configuration with gain of +4). The H and V outputs can then be used to drive the monitor’s sync inputs directly. The relationship between the incoming sync-on CM signaling and the H and V syncs is defined according to Table 16. Table 16. H and V Sync Truth Table (VPOS/VNEG = ±2.5 V) CMR 0.5 0 −0.5 0 CMG 0 0.5 0.5 −0.5 CMB 0 −0.5 0 0.5 H Low Low High High V High Low Low High The following two statements are equivalent to the truth table (Table 16) in producing H and V for all allowable CM inputs: 1. H sync is high when the CM of Blue is larger than the CM of Red. 2. V sync is high when the combined CM of Red and Blue is larger then the CM of Green. The AD8175 has two options for changing the programming of the crosspoint matrix. In the first option, a serial word of 45 bits can be provided that updates the entire matrix each time. The second option allows for changing a single output’s programming via a parallel interface. The serial option requires fewer signals, but more time (clock cycles) for changing the programming; the parallel programming technique requires more signals, but allows for changing a single output at a time, therefore requiring fewer clock cycles. Serial Programming Description The serial programming mode uses the device pins CS, CLK, SERIN, UPDATE, and SER/PAR. The first step is to enable the CLK on by pulling CS low. Next, SER/PAR is pulled low to enable the serial programming mode. The parallel clock WE should be held high during the entire serial programming operation. The UPDATE signal should be high during the time that data is shifted into the device’s serial port. Although the data still shifts in when UPDATE is low, the transparent, asynchronous latches allow the shifting data to reach the matrix. This causes the matrix to try to update to every intermediate state as defined by the shifting data. The data at SERIN is clocked in at every falling edge of CLK. A total of 45 bits must be shifted in to complete the programming. A total of five bits must be supplied for each of the nine RGB output channels—an output enable bit (D4) and four bits (D3 to D0), which determine the input channel. If D4 is low (output disabled), the four associated bits (D3 to D0) do not matter, because no input will be switched to that output. The most-significant-output-address data is shifted in first, with the enable bit (D4) shifted in first, followed by the input address (D3 to D0) entered sequentially with D3 first and D0 last. Each remaining output is programmed sequentially, until the leastsignificant-output-address data is shifted in. At this point, UPDATE can be taken low, which causes the programming of the device according to the data that was just shifted in. The UPDATE latches are asynchronous and when UPDATE is low, they are transparent. Rev. B | Page 28 of 40 Data Sheet AD8175 If more than one AD8175 device is to be serially programmed in a system, the SEROUT signal from one device can be connected to the SERIN of the next device to form a serial chain. All of the CLK, UPDATE, and SER/PAR pins should be connected in parallel and operated as described above. The serial data is input to the SERIN pin of the first device of the chain, and it will ripple through to the last. Therefore, the data for the last device in the chain should come at the beginning of the programming sequence. The length of the programming sequence is 45 bits times the number of devices in the chain. CS gates the CLK and UPDATE signals, so that when CS is held high, both CLK and UPDATE are held in their inactive high state, while when CS is held low, both CLK and UPDATE function normally. Parallel Programming Description When using the parallel programming mode, it is not necessary to reprogram the entire device when making changes to the matrix. In fact, parallel programming allows the modification of a single output or more at a time. Since this takes only one WE/UPDATE cycle, significant time savings can be realized by using parallel programming. One important consideration in using parallel programming is that the RST signal does not reset all registers in the AD8175. When taken low, the RST signal only sets each output to the disabled state. This is helpful during power-up to ensure that two parallel outputs are not active at the same time. After initial power-up, the internal registers in the device generally have random data, even though the RST signal has been asserted. If parallel programming is used to program one output, then that output will be properly programmed, but the rest of the device will have a random program state depending on the internal register content at power-up. Therefore, when using parallel programming, it is essential that all outputs be programmed to a desired state after power-up. This ensures that the programming matrix is always in a known state. From then on, parallel programming can be used to modify a single output or more at a time. In similar fashion, if UPDATE is taken low after initial powerup, the random power-up data in the shift register will be programmed into the matrix. Therefore, in order to prevent the crosspoint from being programmed into an unknown state, do not apply a logic level to UPDATE after power is initially applied. Programming the full shift register once to a desired state, by either serial or parallel programming after initial power-up, eliminates the possibility of programming the matrix to an unknown state. The Chip select (CS) feature is not applicable in parallel programming mode; in other words, it is possible to program the AD8175 in parallel mode when the part is deselected. Refer to the logic diagram shown in Figure 7, which shows that the CS feature gates the serial clock and has no bearing on parallel mode programming. Shared WE lines should therefore not be used in parallel programming mode. To change an output’s programming via parallel programming, SER/PAR, UPDATE, and CLK should all be taken high. The parallel clock, WE, should start in the high state. The 4-bit address of the output to be programmed should be put on A3 to A0. Data Bit D3 to Data Bit D0 should contain the information that identifies the input that gets programmed to the output that is addressed. Data Bit D4 determines the enabled state of the output. If D4 is low (output disabled), then the data on D3 to D0 does not matter. After the desired address and data signals have been established, they can be latched into the shift register by a high-to-low transition of the WE signal. The matrix is not programmed, however, until the UPDATE signal is taken low. It is thus possible to latch in new data for several or all of the outputs first via successive negative transitions of WE while UPDATE is held high, and then have all the new data take effect when UPDATE goes low. This is the technique that should be used when programming the device for the first time after power-up when using parallel programming. Reset When powering up the AD8175, it is usually desirable to have the outputs come up in the disabled state. The RST pin, when taken low, causes all outputs to be in the disabled state. However, the RST signal does not reset all registers in the AD8175. This is important when operating in the parallel programming mode. Refer to the Serial Programming Description section for information about programming internal registers after power-up. Serial programming programs the entire matrix each time, so no special considerations apply. Since the data in the shift register is random after power-up, it should not be used to program the matrix, or the matrix can enter unknown states. To prevent this, do not apply a logic low signal to UPDATE initially after power-up. The shift register should first be loaded with the desired data, and only then can the UPDATE be taken low to program the device. The RST pin has a 20 kΩ pull-up resistor to VDD that can be used to create a simple power-up reset circuit. A capacitor from RST to ground holds RST low for some time while the rest of the device stabilizes. The low condition causes all the outputs to be disabled. The capacitor then charges through the pull-up resistor to the high state, thus allowing full programming capability of the device. Broadcast The AD8175 logic interface has a broadcast mode, in which all first rank latches can be simultaneously parallel-programmed to the same data in one write-cycle. This is especially useful in clearing random first rank data after power-up. To access the broadcast mode, the part is parallel-programmed using the device pins WE, A0 to A3, D0 to D4 and UPDATE. The only Rev. B | Page 29 of 40 AD8175 Data Sheet difference is that the SER/PAR pin is held low, as if serial programming were taking place. By holding CLK high, no serial clocking will occur, and instead, the WE can be used to clock all first rank latches in the chip at once. DIFFERENTIAL AND SINGLE-ENDED OPERATION Although the AD8175 has fully differential inputs and outputs, it can also be operated in a single-ended fashion. Single-ended and differential configurations are discussed below, along with implications on gain, impedances, and terminations. Differential Input Each differential input to the AD8175 is applied to a differential receiver. These receivers allow the user to drive the inputs with an uncertain common-mode voltage, such as from a remote source over twisted pair. The receivers respond only to the differences in input voltages and restore an internal commonmode suitable for the internal signal path. Noise or crosstalk, which affect each receiver’s inputs equally, are rejected by the input stage, as specified by its common-mode rejection ratio (CMRR). Furthermore, the overall common-mode voltage of all three differential pairs comprising an RGB channel is processed and rejected by a separate circuit block. For example, a static discharge or a resistive voltage drop in a middle-of-CAT5-run with sync-on CM signaling coupling into all three pairs in an RGB channel are rejected at the output of the AD8175, while the sync-on CM signals are allowed through the switch. The circuit configuration used by the differential input receivers is similar to that of several Analog Devices general-purpose differential amplifiers, such as the AD8131. The topology is that of a voltage-feedback amplifier with internal gain resistors. The input differential impedance for each receiver is 5 kΩ in parallel with 10 kΩ or 3.33 kΩ, as shown in Figure 50. RF RG IN+ OUT– RCM RCVR IN– 06478-023 OUT+ RF 2.525 kΩ 2.5 kΩ + RS where RS is the effective impedance to ground at each input pin. When operating with a differential input, care must be taken to keep the common-mode, or average, of the input voltages within the linear operating range of the AD8175 receiver. For the AD8175 receiver, this common-mode range can extend railto-rail, provided the differential signal swing is small enough to avoid forward biasing the ESD diodes (it is safest to keep the common-mode plus differential signal excursions within the supply voltages of the part). The input voltage of the AD8175 is linear for ±1 V of differential input voltage difference (this limitation is primarily due to ability of the output to swing close to the rails, since the differential gain through the part is +2). Beyond this level, the signal path will saturate and limit the signal swing. This is not a desired operation, as the supply current will increase and the signal path will be slow to recover from clipping. The absolute maximum allowed differential input signal is limited by longterm reliability of the input stage. The limits in the Absolute Maximum Ratings section of the data sheet should be observed in order to avoid degrading device performance permanently. AC Coupling of Inputs It is possible to ac-couple the inputs of the AD8175 receiver, so that bias current does not need to be supplied externally. A capacitor in series with the inputs to the AD8175 creates a highpass filter with the input impedance of the device. This capacitor needs to be sized large enough so that the corner frequency includes all frequencies of interest. Single-Ended Input The AD8175 input receiver can be driven single-endedly (unbalanced). Single-ended inputs apply a component of common-mode signal to the receiver inputs, which is then rejected by the receiver (see the Specifications section for common-mode-to-differential-mode ratio of the part). The single-ended input resistance RIN differs from the differential input impedance, and is equal to TO SWITCH MATRIX RG G dm = R IN = Figure 50. Input Receiver Equivalent Circuit This impedance creates a small differential termination error if the user does not account for the 3.33 kΩ parallel element. However, this error is less than 1% in most cases. Additionally, the source impedance driving the AD8175 appears in parallel with the internal gain-setting resistors, such that there may be a gain error for some values of source resistance. The AD8175 is adjusted such that its gain is correct when driven by a backterminated CAT5 cable (25 Ω effective impedance to ground at each input pin, or 100 Ω differential source impedance across pairs of input pins). If a different source impedance is presented, the differential gain of the AD8175 can be calculated as 1− RG RF 2 × (R G + R F ) with RG and RF as shown in Figure 50. Note that this value is smaller than the differential input resistance, but it is larger than RG. The difference is due to the component of common-mode level applied to the receiver by single-ended inputs. A second, smaller component of input resistance (RCM, also shown in Figure 50) is present across the inputs in both single-ended and differential operation. In single-ended operation, an input is driven, while the undriven input is often tied to midsupply or ground. Since Rev. B | Page 30 of 40 Data Sheet AD8175 signal-frequency current flows at the undriven input, such input should be treated as a signal line in the board design. For example, in order to achieve best dynamic performance, the undriven input should be terminated with an impedance matching that seen by the part at the driven input. Differential Output Benefits of Differential Operation The AD8175 has a fully-differential switch core with differential outputs. The two output voltages move in opposite directions, with a differential feedback loop maintaining a fixed output stage differential gain of +2. This differential output stage provides improved crosstalk cancellation due to parasitic coupling from one output to another being equal and out of phase. Additionally, if the output of the device is utilized in a differential design, then noise, crosstalk, and offset voltages generated on-chip that are coupled equally into both outputs are reduced by the common-mode rejection ratio of the next device in the signal chain. By utilizing the AD8175 outputs in a differential application, the best possible noise and offset specifications can be realized. Common-Mode Gain The common-mode, or average voltage of pairs of output signals, is set by the voltage on the VOCM_CMENCOFF pin when common-mode encoding is off (CMENC is logic low), or by the voltage on the VOCM_CMENCON pin when commonmode encoding is on (CMENC is logic high). Note that in the latter case, VCOM_CMENCON sets the overall common-mode of RGB triplets of differential outputs, while the individual common-mode of each RGB output is free to change. VCOM_ CMENCON and VCOM_CMENCOFF are typically set to midsupply (often ground), but can be moved approximately ±0.5 V in order to accommodate cases where the desired output common-mode voltage may not be midsupply (as in the case of unequal split supplies). Adjusting the output common-mode voltage beyond ±0.5 V can limit differential swing internally below the specifications on the data sheet. The overall commonmode of the output voltages follows the voltage applied to VOCM_CMENCON or VCOM_CMENCOFF, implying a gain of +1. Likewise, sync-on common-mode signaling is carried through the AD8175 (CMENC must be in its high state), implying a gain of +1 for this path as well. The common-mode reference pins are analog signal inputs, common to all output stages on the device. They require only small amounts of bias current, but noise appearing on these pins is buffered to all the output stages. As such, they should be connected to low noise, low impedance voltage references to avoid being sources of noise, offset, and crosstalk in the signal path. Termination The AD8175 is designed to drive 100 Ω terminated to ground on each output (or an effective 200 Ω differential) while meeting data sheet specifications over the specified operating temperature range, if care is taken to observe the maximum power derating curves. Termination at the load end is recommended to shorten settling time and for best signal integrity. In differential signal paths, it is often desirable to series-terminate the outputs, with a resistor in series with each output. A side effect of termination is an attenuation of the output signal by a factor of two. In this case, gain is usually necessary somewhere else in the signal path to restore the signal level. Whenever a differential output is used single-ended, it is desirable to terminate the used single-ended output with a series resistor, as well as to place a resistor on the unused output to match the load seen by the used output. When disabled, the outputs float to midsupply. A small current is required to drive the outputs away from their midsupply state. This current is easily provided by an AD8175 output (in its enabled state) bussed together with the disabled output. Exceeding the allowed output voltage range may saturate internal nodes in the disabled output, and consequently an increase in disabled output current may be observed. Single-Ended Output Usage The AD8175 output pairs can be used single-ended, taking only one output and not using the second. This is often desired to reduce the routing complexity in the design, or because a single-ended load is being driven directly. This mode of operation produces good results, but has some shortcomings when compared to taking the output differentially. When observing the single-ended output, noise that is common to both outputs appears in the output signal. When observing the output single-ended, the distribution of offset voltages will appear greater. In the differential case, the difference between the outputs when the difference between the inputs is zero is a small differential offset. This offset is created from mismatches in devices in the signal path. In the singleended case, this differential offset is still observed, but an additional offset component is also relevant. This additional component is the common-mode offset, which is the difference between the average of the outputs and the output commonmode reference. This offset is created by mismatches that affect the signal path in a common-mode manner. A differential receiver rejects this common-mode offset voltage, but in the single-ended case, this offset is observed with respect to the signal ground. The single-ended output sums half the differential offset voltage and all of the common-mode offset voltage for a net increase in observed offset. Single-Ended Gain The AD8175 operates as a closed-loop differential amplifier. The primary control loop forces the difference between the output terminals to be a ratio of the difference between the Rev. B | Page 31 of 40 AD8175 Data Sheet input terminals. One output increases in voltage, while the other decreases an equal amount to make the total output voltage difference correct. The average of these output voltages is forced to the voltage on the common-mode reference terminal (VOCM_CMENCOFF or VOCM_CMENCON) by a second control loop. If only one output terminal is observed with respect to the common-mode reference terminal, only half of the difference voltage will be observed. This implies that when using only one output of the device, half of the differential gain is observed. An AD8175 taken with single-ended output appears to have a gain of +1. It is important to note that all considerations applying to the used output phase regarding output voltage headroom, apply unchanged to the complement output phase even if this is not actually used. Termination When operating the AD8175 with a single-ended output, the preferred output termination scheme is to refer the load to the output common-mode. A series-termination can be used, at an additional cost of one half the signal gain. In single-ended output operation, the complementary phase of the output is not used, and may or may not be terminated locally. Although the unused output can be floated to reduce power dissipation, there are several reasons for terminating the unused output with a load resistance matched to the load on the signal output. One component of crosstalk is magnetic coupling by mutual inductance between output package traces and bond wires that carry load current. In a differential design, there is coupling from one pair of outputs to other adjacent pairs of outputs. The differential nature of the output signal simultaneously drives the coupling field in one direction for one phase of the output, and in an opposite direction for the other phase of the output. These magnetic fields do not couple equally into adjacent output pairs due to different proximities, but they do destructively cancel the crosstalk to some extent. If the load current in each output is equal, this cancellation will be greater and less adjacent crosstalk will be observed (regardless of whether the second output is actually being used). A second benefit of balancing the output loads in a differential pair is to reduce fluctuations in current requirements from the power supply. In single-ended loads, the load currents alternate from the positive supply to the negative supply. This creates a parasitic signal voltage in the supply pins due to the finite resistance and inductance of the supplies. This supply fluctuation appears as crosstalk in all outputs, attenuated by the power supply rejection ratio (PSRR) of the device. At low frequencies, this is a negligible component of crosstalk, but PSRR falls off as frequency increases. With differential, balanced loads, as one output draws current from the positive supply, the other output draws current from the negative supply. When the phase alternates, the first output draws current from the negative supply and the second from the positive supply. The effect is that a more constant current is drawn from each supply, such that the crosstalk-inducing supply fluctuation is minimized. A third benefit of driving balanced loads can be seen if one considers that the output pulse response changes as load changes. The differential signal control loop in the AD8175 forces the difference of the outputs to be a fixed ratio to the difference of the inputs. If the two output responses are different due to loading, this creates a difference that the control loop sees as signal response error, and it will attempt to correct this error. This distorts the output signal from the ideal response compared to the case when the two outputs are balanced. Decoupling The signal path of the AD8175 is based on high open-loop gain amplifiers with negative feedback. Dominant-pole compensation is used on-chip to stabilize these amplifiers over the range of expected applied swing and load conditions. To guarantee this designed stability, proper supply decoupling is necessary with respect to both the differential control loops and the commonmode control loops of the signal path. Signal-generated currents must return to their sources through low impedance paths at all frequencies in which there is still loop gain (up to 700 MHz at a minimum). The signal path compensation capacitors in the AD8175 are connected to the VNEG supply. At high frequencies, this limits the power supply rejection ratio (PSRR) from the VNEG supply to a lower value than that from the VPOS supply. If given a choice, an application board should be designed such that the VNEG power is supplied from a low inductance plane, subject to a least amount of noise. VOCM_CMENCON and VOCM_CMENCOFF are high speed common-mode control loops of all output drivers. In the singleended output sense, there is no rejection from noise on these inputs to the outputs. For this reason, care must be taken to produce low noise sources over the entire range of frequencies of interest. This is not only important to single-ended operation, but to differential operation, as there is a commonmode-to-differential gain conversion that becomes greater at higher frequencies. VOCM_CMENCON and VOCM_CMENCOFF are internally buffered to prevent transient currents from flowing into or out of these inputs and becoming sources of crosstalk, by acting on their respective source impedances. Rev. B | Page 32 of 40 Data Sheet AD8175 VPOS Power Dissipation Calculation of Power Dissipation IO, QUIESCENT 10 QNPN TJ = 150°C VOUTPUT 9 IOUTPUT IO, QUIESCENT 7 06478-025 MAXIMUM POWER (W) QPNP 8 VNEG 6 Figure 52. Simplified Output Stage 5 Example For the AD8175, with an ambient temperature of 85°C, all nine RGB output channels driving 1 Vrms into 100 Ω loads, and power supplies at ±2.5 V, follow these steps: 3 15 25 35 45 55 65 75 AMBIENT TEMPERATURE (°C) 85 06478-036 4 1. Figure 51. Maximum Die Power Dissipation vs. Ambient Temperature The curve in Figure 51 was calculated from PD , MAX  TJUNCTION , MAX  TAMBIENT  JA PD , QUIESCENT  VPOS  I VPOS   VNEG  I VNEG  (1) As an example, if the AD8175 is enclosed in an environment at 45 C (TA), the total on-chip dissipation under all load and supply conditions must not be allowed to exceed 7.0 W.   (2) 2.   (5) PD , OUTPUT  2.5 V  1 V   1 V / 100 Ω   15 mW There are 27 output pairs, or 54 output currents. nPD, OUTPUT  54  15 mW  0.81 W 3. Subtract quiescent output stage current for number of loads (54 in this example). The output stage is either standing or driving a load, but the current only needs to be counted once (valid for output voltages > 0.5 V). PDQ , OUTPUT  VPOS  VNEG   I OUTPUT , QUIESCENT The user can subtract the quiescent current for the Class AB output stage when calculating the loaded power dissipation. For each output stage driving a load, subtract a quiescent power, according to (6) PDQ , OUTPUT  2.5 V  (2.5 V)  1.65 mA  8.25 mW There are 27 output pairs, or 54 output currents. (3) where IOUTPUT, QUIESCENT = 1.65 mA for each single-ended output pin for the AD8175. Calculate power dissipation from loads. For a differential output and ground-referenced load, the output power is symmetrical in each output phase. PD , OUTPUT  VPOS  VOUTPUT , RMS  I OUTPUT , RMS For nonsinusoidal output, the power dissipation should be calculated by integrating the on-chip voltage drop across the output devices multiplied by the load current over one period. PDQ ,OUTPUT  (VPOS  VNEG )  I OUTPUT ,QUIESCENT (4) PD , QUIESCENT  2.5 V  600 mA   2.5 V  600 mA   3 W When calculating on-chip power dissipation, it is necessary to include the power dissipated in the output devices due to current flowing in the loads. For a sinusoidal output about ground and symmetrical split supplies, the on-chip power dissipation due the load can be approximated by PD , OUTPUT  VPOS  VO UTPUT , RMS  I OUTPUT , RMS Calculate power dissipation of AD8175 using data sheet quiescent currents. Neglecting VDD current, as it is insignificant. nPDQ , OUTPUT  54  8.25 mW  0.45 W 4. For each disabled RGB output channel, the quiescent power supply current in VPOS and VNEG drops by approximately 34 mA. Verify that the power dissipation does not exceed the maximum allowed value. PD , ON  CHIP  PD , QUIESCENT  nPD , OUTPUT  nPDQ , OUTPUT (7) PD ,ON CHIP  3 W  0.81 W  0.45 W  3.36 W From Figure 51 or Equation 1, this power dissipation is below the maximum allowed dissipation for all ambient temperatures up to and including 85°C. Rev. B | Page 33 of 40 AD8175 Data Sheet In a general case, the power delivered by the digital supply and dissipated into the digital output devices has to be taken into account following a similar derivation. However, since the loads driven by the H and V outputs is high and since the voltage at these outputs typically sits close to either rail, the correction to the on-chip power estimate is small. Furthermore, the H and V outputs are active only briefly during sync generation and returned to digital ground thereafter. Short-Circuit Output Conditions Although there is short-circuit current protection on the AD8175 outputs, the output current can reach values of 80 mA into a grounded output. Any sustained operation with too many shorted outputs can exceed the maximum die temperature and can result in device failure (see the Absolute Maximum Ratings section). Crosstalk Many systems (such KVM switches) that handle numerous analog signal channels have strict requirements for keeping the various signals from influencing any of the other signals in the system. Crosstalk is the term used to describe the coupling of the signals of other nearby channels to a given channel. When there are many signals in close proximity in a system, as is undoubtedly the case in a system that uses the AD8175, the crosstalk issues can be quite complex. A good understanding of the nature of crosstalk and some definition of terms is required in order to specify a system that uses one or more crosspoint devices. Types of Crosstalk Crosstalk can be propagated by means of any of three methods. These fall into the categories of electric field, magnetic field, and the sharing of common impedances. This section explains these effects. Every conductor can be both a radiator of electric fields and a receiver of electric fields. The electric field crosstalk mechanism occurs when the electric field created by the transmitter propagates across a stray capacitance (for example, free space) and couples with the receiver and induces a voltage. This voltage is an unwanted crosstalk signal in any channel that receives it. Currents flowing in conductors create magnetic fields that circulate around the currents. These magnetic fields then generate voltages in any other conductors whose paths they link. The undesired induced voltages in these other channels are crosstalk signals. The channels that crosstalk can be said to have a mutual inductance that couples signals from one channel to another. The power supplies, grounds, and other signal return paths of a multichannel system are generally shared by the various channels. When a current from one channel flows in one of these paths, a voltage that is developed across the impedance becomes an input crosstalk signal for other channels that share the common impedance. All these sources of crosstalk are vector quantities, so the magnitudes cannot simply be added together to obtain the total crosstalk. In fact, there are conditions where driving additional circuits in parallel in a given configuration can actually reduce the crosstalk. The fact that the AD8175 is a fully-differential design means that many sources of crosstalk either destructively cancel, or are common-mode to the signal and can be rejected by a differential receiver. Areas of Crosstalk A practical AD8175 circuit must be mounted to an actual circuit board in order to connect it to power supplies and measurement equipment. Great care has been taken to create an evaluation board (available upon request) that adds minimum crosstalk to the intrinsic device. This, however, raises the issue that a system’s crosstalk is a combination of the intrinsic crosstalk of the devices in addition to the circuit board to which they are mounted. It is important to try to separate these two areas when attempting to minimize the effect of crosstalk. In addition, crosstalk can occur among the inputs to a crosspoint and among the outputs. It can also occur from input to output. Techniques are discussed in the following sections for diagnosing which part of a system is contributing to crosstalk. Measuring Crosstalk Crosstalk is measured by applying a signal to one or more channels and measuring the relative strength of that signal on a desired selected channel. The measurement is usually expressed as dB down from the magnitude of the test signal. The crosstalk is expressed by  A (s )   XT = 20 log 10  SEL A   TEST (s)  (8) where: s = jω, the Laplace transform variable ASEL(s) is the amplitude of the crosstalk induced signal in the selected channel. ATEST(s) is the amplitude of the test signal. It can be seen that crosstalk is a function of frequency, but not a function of the magnitude of the test signal (to first order). In addition, the crosstalk signal has a phase relative to the test signal associated with it. A network analyzer is most commonly used to measure crosstalk over a frequency range of interest. It can provide both magnitude and phase information about the crosstalk signal. As a crosspoint system or device grows larger, the number of theoretical crosstalk combinations and permutations can become extremely large. For example, in the case of the triple 16×9 matrix of the AD8175, we can look at the number of crosstalk terms that can be considered for a single channel, for Rev. B | Page 34 of 40 Data Sheet AD8175 example, input channel INPUT0. INPUT0 is programmed to connect to one of the AD8175 outputs where the measurement can be made. First, the crosstalk terms associated with driving a test signal into each of the other 15 input channels can be measured one at a time, while applying no signal to INPUT0. Then, the crosstalk terms associated with driving a parallel test signal into all 15 other inputs can be measured two at a time in all possible combinations, then three at a time, and so on, until, finally, there is only one way to drive a test signal into all 15 other input channels in parallel. Each of these cases is legitimately different from the others and might yield a unique value, depending on the resolution of the measurement system, but it is hardly practical to measure all these terms and then specify them. In addition, this describes the crosstalk matrix for just one input channel. A similar crosstalk matrix can be proposed for every other input. In addition, if the possible combinations and permutations for connecting inputs to the other outputs (not used for measurement) are taken into consideration, the numbers rather quickly grow to astronomical proportions. If a larger crosspoint array of multiple AD8175s is constructed, the numbers grow larger still. Obviously, some subset of all these cases must be selected to be used as a guide for a practical measure of crosstalk. One common method is to measure all hostile crosstalk; this means that the crosstalk to the selected channel is measured while all other system channels are driven in parallel. In general, this yields the worst crosstalk number, but this is not always the case, due to the vector nature of the crosstalk signal. Other useful crosstalk measurements are those created by one nearest neighbor or by the two nearest neighbors on either side. These crosstalk measurements are generally higher than those of more distant channels, so they can serve as a worst-case measure for any other one-channel or two-channel crosstalk measurements. Input and Output Crosstalk Capacitive coupling is voltage-driven (dV/dt), but is generally a constant ratio. Capacitive crosstalk is proportional to input or output voltage, but this ratio is not reduced by simply reducing signal swings. Attenuation factors must be changed by changing impedances (lowering mutual capacitance), or destructive canceling must be utilized by summing equal and out of phase components. For high input impedance devices such as the AD8175, capacitances generally dominate input-generated crosstalk. Inductive coupling is proportional to current (dI/dt), and often scales as a constant ratio with signal voltage, but also shows a dependence on impedances (load current). Inductive coupling can also be reduced by constructive canceling of equal and out of phase fields. In the case of driving low impedance video loads, output inductances contribute highly to output crosstalk. The flexible programming capability of the AD8175 can be used to diagnose whether crosstalk is occurring more on the input side or the output side. Some examples are illustrative. A given input channel (INPUT7 roughly in the middle for this example) can be programmed to drive OUTPUT4 (exactly in the middle). The inputs to INPUT7 are just terminated to ground (via 50 Ω or 75 Ω) and no signal is applied. All the other inputs are driven in parallel with the same test signal (practically provided by a distribution amplifier), with all other outputs except OUTPUT4 disabled. Since grounded INPUT7 is programmed to drive OUTPUT4, no signal should be present. Any signal that is present can be attributed to the other 15 hostile input signals, because no other outputs are driven (they are all disabled). Thus, this method measures the all-hostile input contribution to crosstalk into INPUT7. Of course, the method can be used for other input channels and combinations of hostile inputs. For output crosstalk measurement, a single input channel is driven (INPUT0, for example) and all outputs other than a given output (OUTPUT4 in the middle) are programmed to connect to INPUT0. OUTPUT4 is programmed to connect to INPUT15 (far away from INPUT0), which is terminated to ground. Thus, OUTPUT4 should not have a signal present since it is listening to a quiet input. Any signal measured at the OUTPUT4 can be attributed to the output crosstalk of the other eight hostile outputs. Again, this method can be modified to measure other channels and other crosspoint matrix combinations. Effect of Impedances on Crosstalk The input side crosstalk can be influenced by the output impedance of the sources that drive the inputs. The lower the impedance of the drive source, the lower the magnitude of the crosstalk. The dominant crosstalk mechanism on the input side is capacitive coupling. The high impedance inputs do not have significant current flow to create magnetically induced crosstalk. However, significant current can flow through the input termination resistors and the loops that drive them. Thus, the PC board on the input side can contribute to magnetically coupled crosstalk. From a circuit standpoint, the input crosstalk mechanism looks like a capacitor coupling to a resistive load. For low frequencies, the magnitude of the crosstalk is given by XT = 20 log 10 [(RS C M ) × s ] (9) where: RS is the source resistance. CM is the mutual capacitance between the test signal circuit and the selected circuit. s is the Laplace transform variable. From Equation 9, it can be observed that this crosstalk mechanism has a high-pass nature; it can also be minimized by reducing the coupling capacitance of the input circuits and lowering the output impedance of the drivers. If the input is Rev. B | Page 35 of 40 AD8175 Data Sheet driven from a 75 Ω terminated cable, the input crosstalk can be reduced by buffering this signal with a low output impedance buffer. On the output side, the crosstalk can be reduced by driving a lighter load. Although the AD8175 is specified with excellent settling time when driving a properly terminated CAT5, the crosstalk is higher than the minimum obtainable due to the high output currents. These currents induce crosstalk via the mutual inductance of the output pins and bond wires of the AD8175. From a circuit standpoint, this output crosstalk mechanism looks like a transformer with a mutual inductance between the windings that drives a load resistor. For low frequencies, the magnitude of the crosstalk is given by  s  XT = 20 log 10  M XY ×  R L   (10) where: MXY is the mutual inductance of Output X to Output Y. RL is the load resistance on the measured output. This crosstalk mechanism can be minimized by keeping the mutual inductance low and increasing RL. The mutual inductance can be kept low by increasing the spacing of the conductors and minimizing their parallel length. PCB Layout Extreme care must be exercised to minimize additional crosstalk generated by the system circuit board(s). The areas that must be carefully detailed are grounding, shielding, signal routing, and supply bypassing. The packaging of the AD8175 is designed to help keep the crosstalk to a minimum. On the BGA substrate, each pair is carefully routed to predominately couple to each other, with shielding traces separating adjacent signal pairs. The ball grid array is arranged such that similar board routing can be achieved. Input and output differential pairs are grouped by channel rather than by color to allow for easy, convenient board routing. The input and output signals have minimum crosstalk if they are located between ground planes on layers above and below, and separated by ground in between. Vias should be located as close to the IC as possible to carry the inputs and outputs to the inner layer. The input and output signals surface at the input termination resistors and the output series back-termination resistors. To the extent possible, these signals should also be separated as soon as they emerge from the IC package. PCB Termination Layout As frequencies of operation increase, the importance of proper transmission line signal routing becomes more important. The bandwidth of the AD8175 is large enough that using high impedance routing does not provide a flat in-band frequency response for practical signal trace lengths. It is necessary for the user to choose a characteristic impedance suitable for the application and properly terminate the input and output signals of the AD8175. Traditionally, video applications have used 75 Ω single-ended environments. RF applications are generally 50 Ω single-ended (and board manufacturers have the most experience with this application). CAT-5 cabling is usually driven as differential pairs of 100 Ω differential impedance. For flexibility, the AD8175 does not contain on-chip termination resistors. This flexibility in application comes with some board layout challenges. The distance between the termination of the input transmission line and the AD8175 die is a high impedance stub, and causes reflections of the input signal. With some simplification, it can be shown that these reflections cause peaking of the input at regular intervals in frequency, dependent on the propagation speed (VP) of the signal in the chosen board material and the distance (d) between the termination resistor and the AD8175. If the distance is great enough, these peaks can occur in-band. In fact, practical experience shows that these peaks are not high-Q, and should be pushed out to three or four times the desired bandwidth in order to not have an effect on the signal. For a board designer using FR4 (VP = 144 × 106 m/s), this means the AD8175 should be no more than 1.5 cm after the termination resistors, and preferably should be placed even closer. The BGA substrate routing inside the AD8175 is approximately 1 cm in length and adds to the stub length, so 1.5 cm PCB routing equates to d = 2.5 × 10–2 m in the calculations. f PEAK = (2n + 1)VP 4d (11) where n = {0, 1, 2, 3, ...}. In some cases, it is difficult to place the termination close to the AD8175 due to space constraints, differential routing, and large resistor footprints. A preferable solution in this case is to maintain a controlled transmission line past the AD8175 inputs and terminate the end of the line. This is known as fly-by termination. The input impedance of the AD8175 is large enough and stub length inside the package is small enough that this works well in practice. Implementation of fly-by input termination often includes bringing the signal in on one routing layer, then passing through a filled via under the AD8175 input ball, then back out to termination on another signal layer. In this case, care must be taken to tie the reference ground planes together near the signal via if the signal layers are referenced to different ground planes. Rev. B | Page 36 of 40 Data Sheet AD8175 AD8175 IPn OPn INn 50Ω 06478-026 ONn Figure 53. Fly-By Input Termination (Grounds for the two transmission lines shown must be tied together close to the INn pin) If multiple AD8175s are to be driven in parallel, a fly-by input termination scheme is very useful, but the distance from each AD8175 input to the driven input transmission line is a stub that should be minimized in length and parasitics using the discussed guidelines. When driving the AD8175 single-endedly, the undriven input is often terminated with a resistance in order to balance the input stage. It can be seen that by terminating the undriven input with a resistor of one-half the characteristic impedance, the input stage will be perfectly balanced (25 Ω, for example, to balance the two parallel 50 Ω terminations on the driven input). However, due to the feedback in the input receiver, there is high speed signal current leaving the undriven input. In order to terminate this high speed signal, proper transmission line techniques should be used. One solution is to adjust the trace width to create a transmission line of half the characteristic impedance and terminate the far end with this resistance (25 Ω in a 50 Ω system). This is not often practical as trace widths become large. In most cases, the best practical solution is to place the half-characteristic impedance resistor as close as possible (preferably less than 1.5 cm away) and to reduce the parasitics of the stub (by removing the ground plane under the stub, for example). In either case, the designer must decide if the layout complexity created by a balanced, terminated solution is preferable to simply grounding the undriven input at the ball with no trace. While the examples discussed so far are for input termination, the theory is similar for output back-termination. Taking the AD8175 as an ideal voltage source, any distance of routing between the AD8175 and a back-termination resistor will be an impedance mismatch that potentially creates reflections. For this reason, back-termination resistors should also be placed close to the AD8175. In practice, because back-termination resistors are series elements, they can be placed close to the AD8175 outputs. Finally, the AD8175 pinout allows the user to bring the outputs out as surface traces to the back-termination resistors. The designer can avoid creating stubs and reflections by keeping the AD8175 output signal path on the surface of the board. A stub is created when a top-to-bottom via connection is made on the output signal path that is perpendicular to the signal flow. Rev. B | Page 37 of 40 AD8175 Data Sheet VPOS FOUR 15-PIN HD CONNECTORS VDD FOUR AD8147 (G = +2) AD8003 (G = +4) 15-PIN HD CONNECTOR PC THREE 15-PIN HD CONNECTORS THREE RGB, HV CHANNELS FOUR RGB, HV CHANNELS OUT0 TO OUT2 IN0 TO IN3 FOUR 15-PIN HD CONNECTORS FOUR AD8147 (G = +2) FOUR DIFFERENTIAL RGB WITH SYNC-ON CM CHANNELS THREE 15-PIN HD CONNECTORS THREE RGB, HV CHANNELS THREE RGB CHANNELS OUT3 TO OUT5 RGB MONITOR RGB MONITOR 15-PIN HD CONNECTOR PC FOUR RGB, HV CHANNELS THREE HV PAIRS IN0 TO IN3 IN4 TO IN7 OUT0 TO OUT2 IN4 TO IN7 15-PIN HD CONNECTORS DIFFERENTIAL OFFSET RJ-45 CONNECTOR OUT3 TO OUT5 IN8 TO IN11 OUT6 IN12 TO IN13 OUT7 IN14 TO IN15 OUT8 AD8145 RGB, HV THREE RGB, HV CHANNELS DIFFERENTIAL RGB WITH SYNC-ON CM AD8175 DUT CAT5 PC RJ-45 CONNECTOR (G = +2) CAT-5 OUT6 CHANNEL RGB MONITOR EIGHT SMA CONNECTORS IN8 TO IN11 DIFFERENTIAL RGB, HV FOUR RJ-45 CONNECTORS OUT7 TWO DIFFERENTIAL RGB CHANNELS AD8147 (G = +2) EVALUATION BOARD TWELVE SMA CONNECTORS SIGNAL GENERATOR/ NETWORK ANALYZER HIGH SPEED SCOPE/ NETWORK ANALYZER DIFFERENTIAL RGB, HV CHANNEL IN12 TO IN13 RIBBON CABLE IN14 TO IN15 NATIONAL INSTRUMENTS CONTROLLER BOARD TWO GORE HEADERS GORE HEADER OUT8 USB AD8175 CUSTOMER EVALUATION BOARD GND VNEG TO CONTROLLER PC USB Figure 54. Evaluation Board Block Diagram Rev. B | Page 38 of 40 06478-053 RGB, HV CHANNEL Data Sheet AD8175 OUTLINE DIMENSIONS 27.20 27.00 SQ 26.80 A1 CORNER INDEX AREA 26 25 24 6 22 20 18 16 14 12 10 8 4 2 23 21 19 17 15 13 11 9 3 5 7 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF A1 BALL PAD CORNER 24.20 24.00 SQ 23.80 25.00 BSC SQ TOP VIEW 1.00 BSC 1.00 REF DETAIL A 1.22 1.17 1.12 DETAIL A 0.66 0.61 0.56 0.50 NOM 0.40 MIN 0.70 0.60 0.50 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MS-034-AAL-1 COPLANARITY 0.20 MAX SEATING PLANE 051208-C 2.45 2.28 2.08 Figure 55. 676-Ball Plastic Ball Grid Array [PBGA] (B-676) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD8175ABPZ AD8175-EVALZ 1 Temperature Range −40°C to +85°C Package Description 676-Ball Plastic Ball Grid Array [PBGA] Evaluation Board Z = RoHS Compliant Part. Rev. B | Page 39 of 40 Package Option B-676 AD8175 Data Sheet NOTES ©2007–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06478-0-10/11(B) Rev. B | Page 40 of 40