a
480 MHz Single-Supply (5 V)
Triple 2:1 Multiplexers
AD8186
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Fully Buffered Inputs and Outputs
Fast Channel-to-Channel Switching: 4 ns
Single-Supply Operation (5 V)
High Speed:
480 MHz Bandwidth (–3 dB) 2 V p-p
>1600 V/s (G = +1)
>1500 V/s (G = +2)
Fast Settling Time of 7 ns to 0.1%
Low Current: 19 mA/20 mA
Excellent Video Specifications (RL = 150 )
0.05% Differential Gain Error
0.05 Differential Phase Error
Low Glitch
All Hostile Crosstalk
–84 dB @ 5 MHz
–52 dB @ 100 MHz
High Off Isolation of –95 dB @ 5 MHz
Low Cost
Fast, High Impedance Disable Feature for Connecting
Multiple Outputs
Logic-Shifted Outputs
24 VCC
IN0A 1
LOGIC
DGND 2
IN1A 3
ENABLE 21 VCC
0
IN2A 5
20 OUT 0
19 VEE
VCC 6
VEE 7
1
TE
18 OUT 1
17 VCC
IN2B 8
VEE 9
16 OUT 2
2
IN1B 10
15 VEE
VEE 11
14 DV
CC
IN0B 12
AD8186/AD8187
13 VCC
LE
Table I. Truth Table
SEL A/B
OE
OUT
0
1
1
0
0
0
1
1
High Z
High Z
IN A
IN B
4.0
6.0
3.5
5.5
INPUT VOLTAGE (V)
3.0
5.0
INPUT
2.5
4.5
2.0
4.0
1.5
3.5
1.0
3.0
OUTPUT
0.5
2.5
0
2.0
–0.5
1.5
OUTPUT VOLTAGE (V)
B
SO
GENERAL DESCRIPTION
O
22 SEL A/B
SELECT
VREF 4
APPLICATIONS
Switching RGB in LCD and Plasma Displays
RGB Video Switchers and Routers
The AD8186 (G = +1) and AD8187 (G = +2) are high speed,
single-supply, triple 2-to-1 multiplexers. They offer –3 dB large signal
bandwidth of over 480 MHz along with a slew rate in excess of
1500 V/µs. With better than –80 dB of all hostile crosstalk and
–95 dB OFF isolation, they are suited for many high speed applications. The differential gain and differential phase error of 0.05%
and 0.05°, along with 0.1 dB flatness to 85 MHz, make the
AD8186 and AD8187 ideal for professional and component video
multiplexing. They offer 4 ns switching time, making them an
excellent choice for switching video signals while consuming less
than 20 mA on a single 5 V supply (100 mW). Both devices have a
high speed disable feature that sets the outputs into a high
impedance state. This allows the building of larger input arrays
while minimizing OFF channel output loading. The devices are
offered in a 24-lead TSSOP package.
23 OE
1.0
–1.0
0
5
15
10
20
25
TIME (ns)
Figure 1. AD8187 Video Amplitude Pulse
Response, VOUT = 1.4 V p-p, RL = 150 Ω
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD8186
Conditions
SWITCHING CHARACTERISTICS
Channel-to-Channel Switching Time
ENABLE to Channel ON Time
DISABLE to Channel OFF Time
Channel Switching Transient (Glitch)
Output Enable Transient (Glitch)
Min
50% Logic to 50% Output
Settling, INA = +1 V, INB = –1 V
50% Logic to 50% Output
Settling, INPUT = 1 V
50% Logic to 50% Output
Settling, INPUT = 1 V
All Channels Grounded
All Channels Grounded
SEL A/B, OE Inputs
SEL A/B, OE Inputs
SEL A/B, OE = 2.0 V
SEL A/B, OE = 0.5 V
OPERATING TEMPERATURE RANGE
Temperature Range
JA
JC
Operating (Still Air)
Operating (Still Air)
Operating
B
SO
O
REV. A
–3–
Max
Unit
3.6/4
ns
4/3.8
ns
17/5
21/45
64/118
ns
mV
mV
1.6
0.6
45
2
–40
LE
DIGITAL INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Input Current
Logic 0 Input Current
Specifications subject to change without notice.
AD8186/AD8187
Typ
TE
Parameter
+85
85
20
V
V
nA
A
ºC
ºC/W
ºC/W
AD8186
ABSOLUTE MAXIMUM RATINGS 1, 2, 3, 4
2.5
MAXIMUM POWER DISSIPATION (W)
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
DVCC to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
DVCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0 V
VCC to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0 V
IN0A, IN0B, IN1A, IN1B, IN2A, IN2B, VREF . . . VEE ≤ VIN ≤ VCC
SEL A/B, OE . . . . . . . . . . . . . . . . . . . . . . DGND ≤ VIN ≤ DVCC
Output Short Circuit Operation . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range . . . . . . . . . . . . –65ºC to +150ºC
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300ºC
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the Theory of
Operation section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Specification is for device in free air (T A = 25ºC).
3
24-lead TSSOP; TJA= 85ºC/W. Maximum internal power dissipation (PD) should be
derated for ambient temperature (T A) such that PD < (150ºC TA)/TJA.
4
TJA of 85⬚C/W is on a 4-layer board (2s 2p).
2.0
1.5
1.0
0.5
0
80
90
TE
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70
AMBIENT TEMPERATURE (C)
Figure 2. Maximum Power Dissipation vs. Temperature
PIN CONFIGURATION
MAXIMUM POWER DISSIPATION
IN0A 1
24 VCC
DGND 2
23 OE
LE
The maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of the
plastic, approximately 150ºC. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package. Exceeding a
junction temperature of 175ºC for an extended period can result
in device failure.
IN1A 3
VREF 4
IN2A 5
VCC 6
VEE 7
While the AD8186/AD8187 is internally short circuit protected,
this may not be sufficient to guarantee that the maximum junction
temperature (150ºC) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maximum
power derating curves shown in Figure 2.
21 V
CC
AD8186/
AD8187
20 OUT 0
TOP VIEW
(Not to Scale)
18 OUT 1
IN2B 8
VEE 9
B
SO
22 SEL A/B
IN1B 10
VEE 11
IN0B 12
19 VEE
17 VCC
16 OUT 2
15 VEE
14 DV
CC
13 VCC
ORDERING GUIDE
Model
Package Option
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
O
AD8186ARU
AD8186ARU-REEL
AD8186ARU-REEL 7
AD8187ARU
AD8187ARU-REEL
AD8187ARU-REEL 7
AD8186-EVAL
AD8187-EVAL
Temperature Range Package Description
24-Lead Thin Shrink Small Outline Package (TSSOP)
13" Reel TSSOP
7" Reel TSSOP
24-Lead Thin Shrink Small Outline Package (TSSOP)
13" Reel TSSOP
7" Reel TSSOP
Evaluation Board
Evaluation Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8186/AD8187 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
REV. A
Typical Performance Characteristics– AD8186
3
1
0.6
0.5
976
0.5
52.3
50
1
0.3
–1
0.2
–2
0.1
FLATNESS
–3
0
–4
–0.1
–5
–0.2
–6
1.0
10.0
100.0
FREQUENCY (MHz)
0.2
–3
0.1
0
–4
–0.1
–6
0.1
1.0
10.0
100.0
FREQUENCY (MHz)
1000.0
–0.2
10000.0
TPC 4. AD8187 Frequency Response,
VOUT = 200 mV p-p, RL = 150 Ω
1
1
0
0
NORMALIZED GAIN (dB)
LE
–1
–2
GAIN (dB)
–2
–5
TPC 1. AD8186 Frequency Response,
VOUT = 200 mV p-p, RL = 1 kΩ
–3
–4
–5
–6
976
B
SO
150
DUT
–8
0.1
1.0
10.0
FREQUENCY (MHz)
100.0
–2
–3
–4
150
100.0
1000.0
–40C
+25C
–1
+85C
–2
–3
–4
–5
52.3
50
–6
0.1
10.0
FREQUENCY (MHz)
976
DUT
–5
1.0
0
NORMALIZED GAIN (dB)
O
–40C
–4
1
+25C
–1
–3
TPC 5. AD8187 Frequency Response,
VOUT = 2 V p-p, RL = 150 Ω
+85C
0
–2
–6
0.1
1000.0
TPC 2. AD8186 Frequency Response,
VOUT = 2 V p-p, RL = 1 kΩ
1
–1
–5
52.3
50
–7
1.0
10.0
FREQUENCY (MHz)
100.0
–6
0.1
1000.0
TPC 3. AD8186 Large Signal Bandwidth vs.
Temperature, VOUT = 2 V p-p, RL = 1 kΩ
REV. A
0.3
FLATNESS
–0.3
10000.0
1000.0
–1
TE
0.1
NORMALIZED GAIN (dB)
GAIN (dB)
GAIN
FLATNESS (dB)
GAIN
0
NORMALIZED GAIN (dB)
0.4
0
0.4
1.0
10.0
FREQUENCY (MHz)
100.0
1000.0
TPC 6. AD8187 Large Signal Bandwidth vs.
Temperature, VOUT = 2 V p-p, RL = 150 Ω
–5–
NORMALIZED FLATNESS (dB)
DUT
2
0
0
–10
–10
–20
–20
–30
–30
CROSSTALK (dB)
CROSSTALK (dB)
AD8186
–40
–50
–60
–70
–40
–50
–60
–70
–80
–80
–90
–90
–100
–100
–110
1
10
FREQUENCY (MHz)
100
0.1
1000
TPC 7. AD8186 All Hostile Crosstalk* vs. Frequency
0
100.0
1000.0
0
–10
–20
–20
–30
CROSSTALK (dB)
LE
–30
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–90
–100
–110
0.1
B
SO
–100
1.0
10.0
FREQUENCY (MHz)
100.0
0
–20
–30
0.1
1.0
10.0
FREQUENCY (MHz)
100.0
1000.0
TPC 11. AD8187 Adjacent Channel Crosstalk* vs. Frequency
O
–40
–120
1000.0
TPC 8. AD8186 Adjacent Channel Crosstalk* vs. Frequency
–10
–110
–50
–60
–70
0
–10
–20
–30
OFF ISOLATION (dB)
CROSSTALK (dB)
10.0
FREQUENCY (MHz)
TPC 10. AD8187 All Hostile Crosstalk* vs. Frequency
–10
OFF ISOLATION (dB)
1.0
TE
–110
0.1
–40
–50
–60
–70
–80
–90
–80
–100
–90
–110
–100
0
10
100
FREQUENCY (MHz)
–120
1000
1
TPC 9. AD8186 OFF Isolation* vs. Frequency
10
100
FREQUENCY (MHz)
1000
TPC 12. AD8187 OFF Isolation* vs. Frequency
* All hostile crosstalk—Drive all INA, listen to output with INB selected.
Adjacent channel crosstalk—Drive one INA, listen to an adjacent output with INB selected.
Off isolation—Drive inputs with OE tied low.
–6–
REV. A
0
0
–10
–10
–20
–20
–30
–30
DISTORTION (dBc)
DISTORTION (dBc)
AD8186
–40
–50
–60
THIRD
–70
–40
–50
–60
THIRD
–70
SECOND
–80
–80
–90
–90
SECOND
–100
–100
100
TPC 13. AD8186 Harmonic Distortion vs. Frequency
VOUT = 2 V p-p, RL = 150 Ω
TPC 16. AD8187 Harmonic Distortion vs. Frequency
VOUT = 2 V p-p, RL = 150 Ω
0
0
–10
–10
–20
LE
–20
–40
PSRR (dB)
PSRR (dB)
–30
–PSRR
–50
–60
+PSRR
–90
0.01
B
SO
–80
0.10
1
FREQUENCY (MHz)
10
100
TPC 14. AD8186 PSRR vs. Frequency, RL = 150 Ω
20
18
16
–40
12
10
8
–80
0.01
14
12
10
8
2
0
0.01
10000
100
16
2
1000
10
20
4
10
100
FREQUENCY (MHz)
1
FREQUENCY (MHz)
18
6
1
0.10
TPC 17. AD8187 PSRR vs. Frequency, RL = 150 Ω
4
0.10
+PSRR
–70
6
0
0.01
–PSRR
–50
NOISE (nV/ Hz)
NOISE (nV/ Hz)
O
14
–30
–60
–70
0.1
1
10
100
FREQUENCY (MHz)
1000
10000
TPC 18. AD8187 Input Voltage Noise vs. Frequency
TPC 15. AD8186 Input Voltage Noise vs. Frequency
REV. A
100
10
FREQUENCY (MHz)
1
TE
10
FREQUENCY (MHz)
1
–7–
AD8186
1000
1000
IMPEDANCE (k)
10000
IMPEDANCE (k)
10000
100
10
1
1
10
FREQUENCY (MHz)
100
0.1
1000
0.1
1.0
10.0
FREQUENCY (MHz)
100.0
1000.0
TE
0.1
TPC 19. AD8186 Input Impedance vs. Frequency
TPC 22. AD8187 Input Impedance vs. Frequency
1000
1000
100
IMPEDANCE ()
LE
100
10
1
10
0.1
0.1
B
SO
1
1
10
FREQUENCY (MHz)
100
TPC 20. AD8186 Enabled Output Impedance vs. Frequency
10000
1000
0.1
1.0
10.0
FREQUENCY (MHz)
100.0
1000.0
TPC 23. AD8187 Enabled Output Impedance vs. Frequency
O
100
0.1
1000
10
1
10000
1000
IMPEDANCE ()
IMPEDANCE ()
10
1
0.1
IMPEDANCE (k)
100
100
10
1
0.1
0.1
1.0
10.0
FREQUENCY (MHz)
100.0
0.1
1000.0
0.1
TPC 21. AD8186 Disabled Output Impedance vs. Frequency
1.0
10.0
FREQUENCY (MHz)
100.0
1000.0
TPC 24. AD8187 Disabled Output Impedance vs. Frequency
–8–
REV. A
AD8186
2.80
3.30
2.70
2.8
3.2
2.7
3.1
INPUT
2.6
2.30
2.80
2.20
OUTPUT
2.10
2.00
1.90
0
5
10
15
20
2.9
2.4
2.8
2.3
2.7
2.2
2.6
OUTPUT
2.1
2.5
2.0
2.4
1.9
2.3
1.8
2.30
1.80
3.0
INPUT
2.5
2.2
0
25
5
15
10
20
25
TIME (ns)
TE
TIME (ns)
TPC 25. AD8186 Small Signal Pulse Response,
VOUT = 200 mV p-p, RL = 1 kΩ
3.0
TPC 28. AD8187 Small Signal Pulse Response,
VOUT = 200 mV p-p, RL = 150 kΩ
5.0
2.5
4.5
INPUT
4.0
6.0
3.5
5.5
3.0
LE
1.0
3.0
OUTPUT
0.5
2.5
INPUT
2.5
4.5
2.0
4.0
1.5
3.5
1.0
3.0
OUTPUT
0.5
2.5
OUTPUT VOLTAGE (V)
3.5
INPUT VOLTAGE (V)
1.5
2.0
B
SO
1.5
–0.5
–1.0
5
10
15
20
2.0
–0.5
1.5
1.0
–1.0
1.0
0
0
0
25
5
7.0
4.0
6.0
6.5
3.5
5.5
6.0
3.0
5.5
2.5
4.5
2.0
4.0
1.5
3.5
2.0
5.0
1.5
4.5
1.0
4.0
0.5
3.5
OUTPUT
5.0
INPUT
INPUT VOLTAGE (V)
O
2.5
OUTPUT VOLTAGE (V)
INPUT
3.0
25
TPC 29. AD8187 Video Amplitude Pulse
Response, VOUT = 1.4 V p-p, RL = 150 kΩ
TPC 26. AD8186 Video Signal Pulse Response,
VOUT = 700 mV p-p, RL = 1 kΩ
3.5
20
TIME (ns)
TIME (ns)
4.0
15
10
3.0
1.0
0.5
2.5
OUTPUT
0
2.0
–0.5
1.5
0
3.0
–0.5
2.5
–1.0
2.0
–1.0
1.0
–1.5
1.5
–1.5
0.5
1.0
–2.0
–2.0
0
5
10
15
20
0
0
25
5
10
15
20
25
TIME (ns)
TIME (ns)
TPC 30. AD8187 Large Signal Pulse Response,
VOUT = 2 V p-p, RL = 150 kΩ
TPC 27. AD8186 Large Signal Pulse Response,
VOUT = 2 V p-p, RL = 1 kΩ
–9–
OUTPUT VOLTAGE (V)
0
INPUT VOLTAGE (V)
5.0
4.0
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2.0
REV. A
OUTPUT VOLTAGE (V)
2.40
INPUT VOLTAGE (V)
2.50
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2.60
OUTPUT (1mV/DIV)
tSETTLED
t0
TIME (2ns/DIV)
2.3
SEL A/B
SELECT A/B PULSE AMPLITUDE (V)
5.5
SEL A/B
4.0
0.3
OUTPUT
3.5
–0.8
10
15
20
OUTPUT
–1.5
2.0
1.5
–2.0
1.5
1.0
25
–2.5
0
5
10
2.8
0.5
2.7
0
2.6
OUTPUT
2.5
–0.5
–1.0
0
5
10
15
20
25
30
TIME (ns)
35
40
45
3.00
2.00
SEL A/B
SELECT A/B PULSE AMPLITUDE (V)
1.0
OUTPUT AMPLITUDE (V)
O
SELECT A/B PULSE AMPLITUDE (V)
2.9
1.0
25
20
TPC 35. AD8187 Channel-to-Channel Switching
Time, VOUT = 2 V p-p, INA = 3.0 V, INB = 2.0 V
3.0
SEL A/B
15
TIME (ns)
TPC 32. AD8186 Channel-to-Channel Switching
Time, VOUT = 2 V p-p, INA = 3.5 V, INB = 1.5 V
1.5
3.5
0
TIME (ns)
2.0
4.0
0.5
2.5
B
SO
5
4.5
–1.0
2.0
–1.8
0
1.0
3.0
2.5
–1.3
–2.3
5.0
–0.5
3.0
–2.8
1.5
LE
4.5
0.8
–0.3
OUTPUT AMPLITUDE (V)
5.0
1.3
5.5
2.0
6.0
1.8
SELECT A/B PULSE AMPLITUDE (V)
TPC 34. AD8187 Settling Time (0.1%),
VOUT = 2 V Step, RL = 150 Ω
TE
TPC 31. AD8186 Settling Time (0.1%),
VOUT = 2 V Step, RL = 1 kΩ
TIME (2ns/DIV)
1.50
2.90
1.00
2.80
0.50
2.70
OUTPUT
0
2.60
–0.50
2.50
–1.00
2.4
50
OUTPUT AMPLITUDE (V)
t0
tSETTLED
OUTPUT AMPLITUDE (V)
OUTPUT (1mV/DIV)
AD8186
2.40
0
5
10
15
20
25
30
TIME (ns)
35
40
45
50
TPC 36. AD8187 Channel Switching Transient
(Glitch), INA = INB = VREF = 0 V
TPC 33. AD8186 Channel Switching Transient (Glitch),
INA = INB = 0 V
–10–
REV. A
AD8186
5.5
2.0
1.5
5.0
1.5
1.0
4.5
0.5
4.0
0
3.5
–1.0
2.5
–1.5
0
40
80
120
1.0
5.0
0.5
4.5
4.0
0
OUTPUT
–0.5
3.5
–1.0
3.0
–1.5
2.5
–2.0
2.0
200
160
5.5
0
40
80
TPC 37. AD8186 Enable ON/OFF Time,
VOUT = 0 V to 1 V
1.5
2.6
0.5
OUTPUT
OE PULSE AMPLITUDE (V)
2.7
5
10
15
20
25
30
TIME (ns)
3.00
1.50
2.90
35
40
45
OE
1.00
2.80
0.50
2.70
0
–0.50
2.4
50
–1.00
O
–11–
2.60
OUTPUT
2.5
TPC 38. AD8186 Channel Enable/Disable
Transient (Glitch)
REV. A
2.00
LE
2.8
OUTPUT AMPLITUDE (V)
OE
1.0
B
SO
OE PULSE AMPLITUDE (V)
2.9
0
2.0
200
160
TPC 39. AD8187 Enable ON/OFF Time,
VOUT = 0 V to 1 V
3.0
0
120
TIME – ns
TE
TIME (ns)
OUTPUT AMPLITUDE (V)
–0.5
3.0
OE PULSE AMPLITUDE (V)
OUTPUT
6.0
OE
OUTPUT AMPLITUDE (V)
OE PULSE AMPLITUDE (V)
OE
2.50
2.40
0
5
10
15
20
25
30
TIME (ns)
35
40
TPC 40. AD8187 Channel Enable/Disable
Transient (Glitch)
45
50
OUTPUT AMPLITUDE (V)
2.0
AD8186
The peak slew rate is not the same as the average slew rate. The
average slew rate is typically specified as the ratio
THEORY OF OPERATION
The AD8186 (G = +1) and AD8187 (G = +2) are single-supply,
triple 2:1 multiplexers with TTL compatible global input switching and output-enable control. Optimized for selecting between
two RGB (red, green, blue) video sources, the devices have high
peak slew rates, maintaining their bandwidth for large signals.
Additionally, the multiplexers are compensated for high phase
margin, minimizing overshoot for good pixel resolution. The
multiplexers also have respectable video specifications and are
superior for switching NTSC or PAL composite signals.
∆VOUT
∆t
The multiplexers are organized as three independent channels,
each with two input transconductance stages and one output
transimpedance stage. The appropriate input transconductance
stages are selected via one logic pin (SEL A/B) such that all
three outputs switch input connections simultaneously. The
unused input stages are disabled with a proprietary clamp circuit to provide excellent crosstalk isolation between “on” and
“off ” inputs while protecting the disabled devices from damaging reverse base-emitter voltage stress. No additional input
buffering is necessary, resulting in low input capacitance and
high input impedance without additional signal degradation.
TE
measured between the 20% to 80% output levels of a sufficiently large output pulse. For a natural response, the peak slew
rate may be 2.7 times larger than the average slew rate. Therefore, calculating a full power bandwidth with a specified average
slew rate will give a pessimistic result. In specifying the large
signal performance of these multiplexers, we’ve published the
large-signal bandwidth, the average slew rate, and the measurements of the total harmonic distortion. (Large signal bandwidth
is defined as the –3 dB point measured on a 2 V p-p output
sine wave.) Specifying these three aspects of the signal path’s
large signal dynamics allows the user to predict system behavior
for either pulse or sinusoid waveforms.
Single-Supply Considerations
DC-Coupled Inputs, Integrated Reference Buffers, and
Selecting the VREF Level on the AD8187, (G = +2)
The AD8186 and AD8187 offer superior large signal dynamics.
The trade-off is that the input and output compliance is limited
to ~1.3 V from either rail when driving a 150 ⍀ load. These
sections address some challenges of designing video systems
within a single 5 V supply.
LE
The transconductance stage, a high slew rate, class AB circuit,
sources signal current into a high impedance node. Each output
stage contains a compensation network and is buffered to the
output by a complementary emitter-follower stage. Voltage
feedback sets the gain, with the AD8186 configured as a unity
gain follower and the AD8187 as a gain-of-two amplifier with a
feedback network. This architecture provides drive for a reverseterminated video load (150 ⍀) with low differential gain and
phase errors while consuming relatively little power. Careful
chip layout and biasing result in excellent crosstalk isolation
between channels.
The AD8186
B
SO
The AD8186 is internally wired as a unity-gain follower. Its
inputs and outputs can both swing to within ~1.3 V of either
rail. This affords the user 2.4 V of dynamic range at input and
output, which should be enough for most video signals, whether
the inputs are ac- or dc-coupled. In both cases, the choice of
output termination voltage will determine the quiescent load
current.
High Impedance, Output Disable Feature, and Off Isolation
The output-enable logic pin (OE) controls whether the three
outputs are enabled or disabled to a high impedance state.
The high impedance disable allows larger matrices to be built
by busing the outputs together. In the case of the AD8187
(G = +2), a feedback isolation scheme is used so that the
impedance of the gain-of-two feedback network does not load
the output. When not in use, the outputs can be disabled to
reduce power consumption.
O
The reader may have noticed that the off isolation performance of
the signal path is dependent upon the value of the load resistor,
RL. For calculating off isolation, the signal path may be modeled
as a simple high-pass network with an effective capacitance of
3 fF. Off isolation will improve as the load resistance is decreased. In
the case of the AD8186, off isolation is specified with a 1 kΩ
load. However, a practical application would likely gang the
outputs of multiple muxes. In this case, the proper load resistance
for the off isolation calculation is the output impedance of an
enabled AD8186, typically less than a 10th of an ohm.
For improved supply rejection, the VREF pin should be tied to
an ac ground (the more quiet supply is a good bet). Internally,
the VREF pin connects to one terminal of an on-chip capacitor.
The capacitor’s other terminal connects to an internal node.
The consequence of building this bypass capacitor on-chip is
twofold. First, the VREF pin on the AD8186 draws no input bias
current. (Contrast this to the case of the AD8187, where the
VREF pin typically draws 2 µA of input bias current). Second,
on the AD8186, the VREF pin may be tied to any voltage within
the supply range.
IN0A
OUT0
IN0B
IN1A
OUT1
IN1B
IN2A
OUT2
IN2B
Full Power Bandwidth vs. –3 dB Large Signal Bandwidth
Note that full power bandwidth for an undistorted sinusoidal signal
is often calculated using the peak slew rate from the equation
Full Power Bandwidth =
AD8186
MUX SYSTEM
Peak Slew Rate
2π × Sinusoid Amplitude
“C_BYPASS”
VREF
INTERNAL CAP
BIAS REFERENCE
DIRECT CONNECTION TO ANY “QUIET” AC GROUND
(FOR EXAMPLE, GND, V CC, V EE)
Figure 3. VREF Pin Connection for AD8186 (Differs
from AD8187)
–12–
REV. A
AD8186
The AD8187
The AD8187 uses on-chip feedback resistors to realize the gainof-two function. To provide low crosstalk and a high output
impedance when disabled, each set of 500 Ω feedback resistors is
terminated by a dedicated reference buffer. A reference buffer is
a high speed op amp configured as a unity-gain follower. The
three reference buffers, one for each channel, share a single, high
impedance input, the VREF pin (see Figure 4). VREF input bias
current is typically less than 2 µA.
A0
5V
OUT 0
1
B0
TE
VFO
5V
GBUF 0
For example, consider amplifying a 700 mV video signal with a
sync pulse 300 mV below black level. The user might decide to set
VREF at black level to preferentially run video signals on the faster
NPN transistor path. The AD8186 would, in this case, allow a
reference voltage as low as 1.3 V + 300 mV = 1.6 V. If the AD8187
is used, the sync pulse would be amplified to 600 mV. Therefore,
the lower limit on VREF becomes 1.3 V + 600 mV = 1.9 V. For
routing RGB video, an advantageous configuration would be to
employ +3 V and –2 V supplies, in which case VREF could be
tied to ground.
If system considerations prevent running the multiplexer on split
supplies, a false ground reference should be employed. A low
impedance reference may be synthesized with a second operational amplifier. Alternately, a well bypassed resistor divider
may serve. Refer to the Application section for further explanation and more examples.
5V
500
VREF
3) To maximize the output dynamic range, the reference voltage
should be chosen with some care.
500
VF-1
5V
5V
GBUF 1
OUT1
5V
GBUF 2
100k
VF-2
OUT2
500
10k
500
500
LE
500
0.022F
100
OP21
VREF
1F
1F
Figure 4. Conceptual Diagram of a Single
Multiplexer Channel, G = +2
B
SO
This configuration has a few implications for single-supply
operation:
1) On the AD8187, VREF may not be tied to the most negative
analog supply, VEE.
FROM 1992 ADI AMPLIFIER
APPLICATIONS GUIDE
GND
Figure 6a. Synthesis of a False Ground Reference
5V
Limits on Reference Voltage (AD8187, see Figure 5):
VEE + 1.3 V < VREF < VCC – 1.6 V
1.3 V < VREF < 3.4 V on 0 V / 5 V Supplies
10k
VREF
5V
1.3V
5V
10k
1F
VO_MAX = 3.7V
A0
VOUT
O
OUT 0
VO_MIN = 1.3V
CAP MUST BE LARGE
ENOUGH TO ABSORB
TRANSIENT CURRENTS
WITH MINIMUM BOUNCE.
1.3V
GND
Figure 6b. Alternate Method for Synthesis of a
False Ground Reference
5V
5V
VREF
1.6V
VO_MAX = 3.4V
VREF
VO_MIN = 1.3V
1.3V
GND
Figure 5. Output Compliance of Main Amplifier
Channel and Ground Buffer
High Impedance Disable
Both the AD8186 and the AD8187 may have their outputs
disabled to a high impedance state. In the case of the AD8187,
the reference buffers also disable to a state of high output
impedance. This feature prevents the feedback network of a
disabled channel from loading the output, which is valuable
when busing together the outputs of several muxes.
2) Signal at the VREF pin appears at each output. Therefore,
VREF should be tied to a well bypassed, low impedance source.
Using superposition, it is easily shown that
VOUT = 2 × VIN – VREF
REV. A
–13–
AD8186
AC-Coupled Inputs (DC Restore before Mux Input)
Using ac-coupled inputs presents an interesting challenge for video
systems operating from a single 5 V supply. In NTSC and PAL
video systems, 700 mV is the approximate difference between the
maximum signal voltage and black level. It is assumed that sync
has been stripped. However, given the two pathological cases
shown in Figure 7, a dynamic range of twice the maximum signal
swing is required if the inputs are to be ac-coupled. A possible
solution would be to use a dc restore circuit before the mux.
WHITE LINE WITH BLACK PIXEL
IN0A
1
24
VCC
DGND
2
23
OE
IN1A
3
22
SEL A/B
VREF
4
21
VCC
IN2A
5
20
OUT 0
VCC
6
19
VEE
VEE
7
18
OUT 1
IN2B
8
17
VCC
VREF
+700mV
MUX0
0.1F
VAVG
1F
VAVG
–700mV
VREF
TE
BLACK LINE WITH WHITE PIXEL
VEE
+5 V
VREF ~ V AVG
VREF IS A DC VOLTAGE
SET BY THE RESISTORS
Tolerance to Capacitive Load
OUT 2
15
VEE
VEE 11
14
DVCC
IN0B 12
13
VCC
MUX2
LE
GND
Figure 7. Pathological Case for
Input Dynamic Range
16
9
IN1B 10
VINPUT = V REF + V SIGNAL
VSIGNAL
MUX1
Figure 8. Detail of Primary and Secondary Supplies
Split-Supply Operation
Operating from split supplies (e.g., +3 V/–2 V or ± 2.5 V) simplifies the selection of the VREF voltage and load resistor termination
voltage. In this case, it is convenient to tie VREF to ground.
The logic inputs are level shifted internally to allow the digital
supplies and logic inputs to operate from 0 V and 5 V when
powering the analog circuits from split supplies. The maximum
voltage difference between DVCC and VEE must not exceed 8 V
(see Figure 9).
B
SO
Op amps are sensitive to reactive loads. A capacitive load at the
output appears in parallel with an effective resistance of REFF =
(RL储rO), where RL is the discrete resistive load, and rO is the openloop output impedance, approximately 15 Ω for these muxes.
The load pole, at fLOAD = 1/(2 REFF CL), can seriously degrade
phase margin and therefore stability. The old workaround is to
place a small series resistance directly at the output to isolate the
load pole. While effective, this ruse also affects the dc and termination characteristics of a 75 Ω system. The AD8186 and AD8187
are built with a variable compensation scheme that senses the
output reactance and trades bandwidth for phase margin, ensuring
faster settling and lower overshoot at higher capacitive loads.
SPLIT-SUPPLY OPERATION
(+5)
DVCC
(+2.5)
VCC
(–2.5)
VEE
8V MAX
Secondary Supplies and Supply Bypassing
(0V)
DGND
Figure 9. Split-Supply Operation
O
The high current output transistors are given their own supply
pins (Pins 15, 17, 19, and 21) to reduce supply noise on-chip
and to improve output isolation. Since these secondary, high
current supply pins are not connected on-chip to the primary
analog supplies (VCC/VEE, Pins 6, 7, 9, 11, 13, and 24), some
care should be taken to ensure that the supply bypass capacitors
are connected to the correct pins. At a minimum, the primary
supplies should be bypassed. Pin 6 and Pin 7 may be a convenient
place to accomplish this. Stacked power and ground planes could
be a convenient way to bypass the high current supply pins.
ANALOG SUPPLIES
DIGITAL SUPPLIES
–14–
REV. A
AD8186
APPLICATION
Single-Supply Operation
there is still enough dynamic range to handle an ac-coupled,
standard video signal with 700 mV p-p amplitude.
The AD8186/AD8187 are targeted mainly for use in singlesupply 5 V systems. For operating on these supplies, both VEE
and DGND should be tied to ground. The control logic pins will
be referenced to ground. Normally, the DVCC supply should be
set to the same positive supply as the driving logic.
If the input is biased at 2.5 V dc, the input signal can potentially go
700 mV both above and below this point. The resulting 1.8 V and
2.2 V are within the input signal range for single 5 V operation.
Since the part is unity-gain, the outputs will follow the inputs,
and there will be adequate range at the output as well.
For dc-coupled single-supply operation, it is necessary to set an
appropriate input dc level that is within the specified range of the
amplifier. For the unity-gain AD8186, the output dc level will
be the same as the input, while for the gain-of-two AD8187, the
VREF input can be biased to obtain an appropriate output dc level.
When using the gain-of-two AD8187 in a simple ac-coupled
application, there will be a dynamic range limitation at the output
caused by its higher gain. At the output, the gain-of-two will
produce a signal swing of 1.4 V, but the ac coupling will double
this required amount to 2.8 V. The AD8187 outputs can only
swing from 1.4 V to 3.6 V on a 5 V supply, so there are only
2.2 V of dynamic signal swing available at the output.
Figure 10 shows a circuit that provides a gain-of-two and is
dc-coupled. The video input signals must have a dc bias
from their source of approximately 1.5 V. This same voltage is applied to VREF of the AD8187. The result is that when
the video signal is at 1.5 V, the output will also be at the
same voltage. This is close to the lower dynamic range of
both the input and the output.
TE
A standard means for reducing the dynamic range requirements
of an ac-coupled video signal is to use a dc restore. This circuit
works to limit the dynamic range requirements by clamping the
black level of the video signal to a fixed level at the input to the
amplifier. This prevents the video content of the signal from
varying the black level as happens in a simple ac-coupled circuit.
When the input goes most positive, which is 700 mV above the
black level for a standard video signal, it reaches a value of 2.2 V
and there is enough headroom for the signal. On the output
side, the magnitude of the signal will change by 1.4 V, which
will make the maximum output voltage 2.2 V + 1.4 V = 3.6 V.
This is just within the dynamic range of the output of the part.
LE
After ac coupling a video signal, it is always necessary to use a
dc restore to establish where the black level is. Usually, this
appears at the end of a video signal chain. This dc restore circuit
needs to have the required accuracy for the system. It compensates for all the offsets of the preceding stages. Therefore, if a
dc restore circuit is to be used only for dynamic-range limiting,
it does not require great dc accuracy.
AC Coupling
B
SO
When a video signal is ac-coupled, the amount of dynamic range
required to handle the signal can potentially be double that
required for dc-coupled operation. For the unity-gain AD8186,
IN0A
REDA
2.2V
DVCC
VCC
1.5V
VREF
O
AD8187
2
OUT0
RED
IN2A
BLUA
5V
3.48k
1.5V
BLACK
LEVEL
5V
IN1A
GRNA
0.7V MAX
3V TO 5V
3.0V
1.4V MAX
2
OUT1
1.5V
GRN
BLACK
LEVEL
TYPICAL OUTPUT LEVELS
(ALL 3 OUTPUTS)
1.5k
TYPICAL INPUT LEVELS
(ALL 6 OUTPUTS)
REDB
GRNB
BLUB
IN0B
2
OUT2
BLU
IN1B
IN2B
DGND
VEE
SEL A/B
OE
Figure 10. DC-Coupled (Bypassing and Logic Not Shown)
REV. A
–15–
AD8186
A dc restore circuit using the AD8187 is shown in Figure 11.
Two separate sources of RGB video are ac-coupled to the
0.1 µF input capacitors of the AD8187. The input points of
the AD8187 are switched to a 1.5 V reference by the ADG786,
which works in the following manner:
The change in voltage is IBIAS times the line time divided by
the capacitance. With an IBIAS of 2.5 µA, a line time of 30 µs,
and a 0.1 µF coupling capacitor, the amount of droop is
0.75 mV. This is roughly 0.1% of the full video amplitude and
will not be observable in the video display.
The SEL A/B signal selects the A or B inputs to the AD8187. It
also selects the switch positions in the ADG786 such that the
same selected inputs will be connected to VREF when EN is low.
High Speed Design Considerations
During the horizontal interval, all of the RGB input signals are at
a flat black level. A logic signal that is low during HSYNC is
applied to the EN of the ADG786. This closes the switches
and clamps the black level to 1.5 V. At all other times, the switches
are off and the node at the inputs to the AD8187 floats.
First, the board should have at least one layer of a solid ground
plane. Long signal paths should be referenced to a ground plane
as controlled-impedance traces. All bypass capacitors should be
very close to the pins of the part with absolutely minimum extra
circuit length in the path. It is also helpful to have a large VCC
plane on a circuit board layer that is closely spaced to the ground
plane. This creates a low inductance interplane capacitance,
which is very helpful in supplying the fast transient currents that
the part demands during high resolution signal transitions.
TE
There are two considerations for sizing the input coupling capacitors. One is the time constant during the H-pulse clamping. The
other is the droop associated with the capacitor discharge due to the
input bias current of the AD8187. For the former, it is better to
have a small capacitor; but for the latter, a larger capacitor is better.
The AD8186/AD8187 are extremely high speed switching amplifiers for routing the highest resolution graphic signals. Extra care
is required in the circuit design and layout to ensure that the full
resolution of the video is realized.
The ON resistance of the ADG786 and the coupling capacitor
forms the time constant of the input clamp. The ADG786 ON
resistance is 5 Ω max. With a 0.1 µF capacitor, a time constant
of 0.5 µs is created. Thus, a sync pulse of greater than 2.5 µs will
cause less than 1% error. This is not critical because the black
level from successive lines is very close and the voltage changes
little from line to line.
Evaluation Board
LE
An evaluation board has been designed and is offered for running the AD8186/AD8187 on a single supply. The inputs and
outputs are ac-coupled and terminated with 75 Ω resistors.
For the AD8187, a potentiometer is provided to allow setting
VREF at any value between VCC and ground.
The logic control signals can be statically set by adding or
removing a jumper. If it is required to drive the logic pins
with a fast signal, an SMA connector can be used to deliver the
signal, and a place for a termination resistor is provided.
B
SO
A rough approximation for the horizontal line time for a graphics
system is 30 µs. This will vary depending on the resolution and
the vertical rate. The coupling capacitor needs to hold the voltage
relatively constant during this time while the input bias current
of the AD8187 is discharging it.
5V
0.1F
VDD
REDA
ADG786
0.1F
S1A
D1
S1B
GRNA
BLUA
5V
1.5V
5V
DVCC
VCC
AD8187
IN1A
2
OUT0
RED
IN2A
0.1F
VREF
O
3.48k
IN0A
3V TO 5V
S2A
D2
VREF
S2B
+
2
VREF
OUT1
GRN
1.5k
0.1F
10F 0.1F
S3A
D3
REDB
0.1F
S3B
GRNB
GND
2.4V MIN
HSYNC
VSS
2
OUT2
BLU
IN1B
IN2B
BLUB
0.1F
LOGIC
IN0B
DGND
VEE
SEL A/B
OE
EN A0 A1 A2
0.8V MIN
SEL A/B
Figure 11. AD8187 AC-Coupled with DC Restore
–16–
REV. A
AD8186
LE
TE
EVALUATION BOARD
O
B
SO
Figure 12. Component Side Board Layout
Figure 13. Circuit Side Board Layout
REV. A
–17–
LE
TE
AD8186
O
B
SO
Figure 14. Component Side Silkscreen
Figure 15. Circuit Side Silkscreen
–18–
REV. A
REV. A
AGND
AGND
Figure 16. Single-Supply Evaluation Board
–19–
IN2A
AGND
AGND
VREF
C5
0.1F
AGND
R8
75
AGND
R3
75
C9
0.1F
C8
0.1F
C6
0.1F
AGND
C3
0.1F
VCC
R21
4.99k
VREF
R18
4.99k
VREF
R17
4.99k
VREF
C14
0.01F
R22
4.99k
VREF
R22
4.99k
VREF
AGND
12
11
10
9
8
7
6
5
4
3
2
1
VCC 24
OE 23
AGND
C12
0.1F
VCC
VCC
VCC 13
DVCC
14
VEE 15
OUT 2 16
VCC 17
OUT 1 18
VEE 19
VCC
OUT 0 20
21
SEL A/B 22
AD8186/
AD8187
IN0B
VEE
IN1B
VEE
IN2B
VEE
VCC
IN2A
VREF
IN1A
DGND
C17
0.1F
AGND
C16
10F
R13
75
TE
VCC
R11
75
R9
75
VCC
VCC
AGND
W2
AGND
W1
AGND
R14*
TBD
AGND
R12*
TBD
AGND
R10*
TBD
AGND
R20*
TBD
AGND
R15*
TBD
AGND
C15
10F
AGND
C7
0.1F
AGND
C10
0.1F
AGND
LE
IN0A
DUT
AGND
GND1 GND2 GND3 GND4
B
SO
C4
0.1F
C1
0.1F
AGND
C24
0.1F
AGND
R5
75
VREF
R16
4.99k
AGND
R7
75
AGND
R6
75
AGND
C13
10F
CW
VCC
AGND
IN0B
IN1B
IN2B
AGND
AGND
R1
AGND
O
R4
75
*R10, R12, R14, R15, AND R20 NOT INSTALLED ON EVALUATION BOARD FOR TEST PURPOSES.
R1 IS NOT USED FOR AD8186.
VREF
IN1A
IN0A
R24
1k
C20
0.1F
C19
0.1F
C18
0.1F
VCC
R23
1k
VCC
OUT 0
SEL A/B
AGND
OUT 2
AGND
OUT 1
AGND
AGND
AGND
OE
VCC
AD8186
AD8186
OUTLINE DIMENSIONS
24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
24
C02985–0–6/03(A)
7.90
7.80
7.70
13
4.50
4.40
4.30
6.40 BSC
1
12
0.65
BSC
0.15
0.05
0.30
0.19
0.10 COPLANARITY
1.20
MAX
SEATING
PLANE
TE
PIN 1
0.20
0.09
8
0
0.75
0.60
0.45
Revision History
Page
B
SO
Location
LE
COMPLIANT TO JEDEC STANDARDS MO-153AD
6/03—Data Sheet changed from REV. 0 to REV. A.
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to TPCs 32, 35, and 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
O
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
REV. A
–20–
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