2:1 HDMI/DVI Switch with Equalization and DDC/CEC Buffers AD8192
FEATURES
2 inputs, 1 output HDMI/DVI links HDMI 1.3a receive and transmit compliant ±7 kV HBM ESD on HDMI input pins 4 TMDS channels per link Supports 250 Mbps to 2.25 Gbps data rates and beyond Supports 25 MHz to 225 MHz pixel clocks and beyond Fully buffered unidirectional inputs/outputs Switchable 50 Ω on-chip input terminations with programmable or automatic control on channel switch Equalized inputs and pre-emphasized outputs Low added jitter Output disable feature for reduced power dissipation Switched output termination for building of larger arrays Bidirectional and cascadable DDC buffers (SDA/SCL) DDC bus logic level translation (3.3 V, 5 V) Bidirectional and cascadable CEC buffer with integrated pull-up resistors (27 kΩ) Hot plug detect pulse low on channel switch Standards compatible: DVI, HDMI 1.3a, HDCP, I2C Serial (I2C slave) control interface 56-lead, 8 mm × 8 mm LFCSP, RoHS-compliant package
I2C_SDA I2C_SCL I2C_ADDR
FUNCTIONAL BLOCK DIAGRAM
RESET SERIAL INTERFACE CONFIG INTERFACE CONTROL LOGIC
AD8192
AVCC DVCC AMUXVCC AVEE DVEE VREF_AB VREF_COM
VTTI + – + – 2 2 SWITCH CORE 2 DDC_COM[1:0] DVEE 4 4 4 4 HIGH SPEED BUFFERED EQ SWITCH CORE 4 PE 4 + – VTTO
IP_A[3:0] IN_A[3:0]
OP[3:0] ON[3:0]
IP_B[3:0] IN_B[3:0]
VTTI DDC_A[1:0] DDC_B[1:0]
CEC_I/O HPD_A HPD_B LOW SPEED BUFFERED
CEC_O/I
Figure 1.
TYPICAL APPLICATION APPLICATIONS
Front panel buffer for advanced television (HDTV) sets Standalone HDMI switcher Multiple input displays Projectors A/V receivers Set-top boxes
SET-TOP BOX HDTV SET HDMI RECEIVER DVD PLAYER
07050-002
AD8192
Figure 2. Typical Application for HDTV Sets
GENERAL DESCRIPTION
The AD8192 is a complete HDMI™/DVI link switch featuring equalized TMDS inputs and pre-emphasized TMDS outputs ideal for systems with long cable runs. The TMDS outputs can be set to a high impedance state to reduce the power dissipation and/or allow the construction of larger arrays using the wireOR technique. The AD8192 includes bidirectional buffering for the DDC bus and CEC line, with integrated pull-up resistors for the CEC line. The AD8192 is available in a space-saving, 56-lead LFCSP surface-mount, lead-free plastic package specified to operate over the −40°C to +85°C temperature range.
PRODUCT HIGHLIGHTS
1. 2. Fully HDMI 1.3a transmit and receive compliant. Supports data rates up to 2.25 Gbps, enabling greater than 1080p HDMI formats with deep color (12-bit) and UXGA (1600 × 1200) DVI resolutions. Input cable equalizer enables use of long cables; more than 20 m (24 AWG) at data rates up to 2.25 Gbps. Auxiliary switch isolates and buffers the DDC bus and the CEC line, improving total system capacitance limit. Hot plug detect (HPD) signal is pulsed low on link switch. Manually or automatically switched input terminations.
3. 4. 5. 6.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
07050–001
BIDIRECTIONAL
AD8192 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Typical Application........................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 12 Input Channels............................................................................ 12 Output Channels ........................................................................ 12 Switching Mode .......................................................................... 13 Pre-Emphasis .............................................................................. 13 Auxiliary Multiplexer ................................................................. 14 DDC Logic Levels....................................................................... 14 Input/Output Mapping Control ............................................... 14 Serial Control Interface.................................................................. 15 Reset ............................................................................................. 15 Write Procedure.......................................................................... 15 Read Procedure........................................................................... 16 Configuration Registers ................................................................. 17 High Speed Device Modes Register ......................................... 18 Auxiliary Device Modes Register ............................................. 18 Receiver Settings Register ......................................................... 18 Input Termination Control Register ........................................ 18 Receive Equalizer Register ........................................................ 18 Transmitter Settings Register .................................................... 19 Source Sign Control Register .................................................... 19 Source A Input/Output Mapping Register.............................. 19 Source B Input/Output Mapping Register .............................. 19 Applications Information .............................................................. 20 Pinout ........................................................................................... 20 Cable Lengths and Equalization ............................................... 21 TMDS Output Rise/Fall Times ................................................. 21 Front Panel Buffer for Advanced TV....................................... 21 HDMI Switcher .......................................................................... 21 Cascading Multiple Devices...................................................... 21 PCB Layout Guidelines.............................................................. 22 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 25
REVISION HISTORY
5/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD8192 SPECIFICATIONS
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, VREF_AB = 5 V, VREF_COM = 5 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted. Table 1. TMDS Performance Specifications
Parameter TMDS DYNAMIC PERFORMANCE Maximum Data Rate (DR) per Channel Bit Error Rate (BER) Added Data Jitter Added Clock Jitter Differential Intrapair Skew Differential Interpair Skew TMDS EQUALIZATION PERFORMANCE Receiver (Highest Setting) 1 Transmitter (Highest Setting) 2 TMDS INPUT CHARACTERISTICS Input Voltage Swing Input Common-Mode Voltage (VICM) TMDS OUTPUT CHARACTERISTICS High Voltage Level Low Voltage Level Rise/Fall Time (20% to 80%) 3 TMDS TERMINATION Input Termination Resistance Output Termination Resistance
1 2
Conditions/Comments NRZ PRBS 223 − 1 DR ≤ 2.25 Gbps, PRBS 27 − 1, no equalization At output At output Boost frequency = 1.125 GHz Boost frequency = 1.125 GHz Differential
Min 2.25
Typ
Max
Unit Gbps
10−9 23 1 1 30 12 6 150 AVCC − 800 AVCC − 200 AVCC − 600 50 1200 AVCC AVCC + 10 AVCC − 400 150 ps (p-p) ps (rms) ps ps dB dB mV mV mV mV ps Ω Ω
Single-ended high speed channel Single-ended high speed channel DR = 2.25 Gbps Single-ended Single-ended
90 50 50
Output meets transmitter eye diagram as defined in the DVI Standard Revision 1.0 and HDMI Standard Revision 1.3a. Cable output meets receiver eye diagram mask as defined in the DVI Standard Revision 1.0 and HDMI Standard Revision 1.3a. 3 Output rise/fall time measurement excludes external components such as HDMI connector or external ESD protection diodes. See Applications Information section for more information.
Table 2. Auxiliary Channel Performance Specifications
Parameter DDC CHANNELS Input Capacitance Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Rise Time Fall Time Leakage CEC CHANNEL Input Capacitance Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage, VOH Symbol CAUX VIL VIH VOL VOH Conditions/Comments DC bias = 2.5 V, ac voltage = 3.5 V p-p, f = 100 kHz 0.7 × VREF 1 IOL = 5 mA 10% to 90%, no capacitive load 90% to 10%, CLOAD = 400 pF VREF1 140 100 0.4 Min Typ 10 Max 15 0.5 Unit pF V V V V ns ns μA pF V V V V
200 10 25 0.8 0.6
CAUX VIL VIH VOL
DC bias = 1.65 V, ac voltage = 2.5 V p-p, f = 100 kHz 2.0 RPULLUP = 3 kΩ to +3.3 V 2.5
5
AVCC
Rev. 0 | Page 3 of 28
AD8192
Parameter Rise Time Fall Time Leakage HOT PLUG DETECT Output Low Voltage
1
Symbol
Conditions/Comments 10% to 90%, CLOAD = 1500 pF, RPULLUP = 27 kΩ; or CLOAD = 7200 pF, RPULLUP = 3 kΩ 90% to 10%, CLOAD = 1500 pF, RPULLUP = 27 kΩ; or CLOAD = 7200 pF, RPULLUP = 3 kΩ Off-leakage test conditions from HDMI Compliance Test Specification Test ID: 8-14 RPULLUP = 800 Ω to +5 V
Min
Typ 50 5
Max 100 10 1.8
Unit μs μs μA
VOL
0.4
V
VREF refers to the voltage at the VREF_AB or VREF_COM pins. VREF should be at the same supply voltage as that to which the external pull-up resistors are connected.
Table 3. Power Supply and Control Logic Specifications
Parameter POWER SUPPLY AVCC AMUXVCC VREF_AB VREF_COM QUIESCENT CURRENT AVCC AVCC AVCC V TTI V TTO DVCC VREF_AB VREF_COM AMUXVCC POWER DISSIPATION Outputs disabled Outputs enabled, no pre-emphasis Outputs enabled, maximum pre-emphasis I2C® AND LOGIC INPUTS 2 Input High Voltage, VIH Input Low Voltage, VIL I2C AND LOGIC OUTPUTS Output Low Voltage, VOL
1 2
Conditions/Comments Operating range (3.3 V ± 5%) Operating range (5 V ± 10%)
Min 3.135 4.5 3 3
Typ 3.3 5 5 5 40 60 100 40 40 80 10 1 1 10 215 545 881
Max 3.465 5.5 5.5 5.5 45 70 120 54 50 100 15 10 10 20 318 765 1200
Unit V V V V mA mA mA mA mA mA mA μA μA mA mW mW mW V V V
Outputs disabled Outputs enabled, no pre-emphasis Outputs enabled, maximum pre-emphasis Input termination on 1 Outputs enabled, output termination on Output termination on, maximum pre-emphasis
Serial interface Serial interface Serial interface, IOL = +3 mA
2.4 0.8 0.4
Assumes that the unselected HDMI/DVI link is deactivated through the hot plug detect line, as required by the DVI Standard Revision 1.0 and HDMI Standard Revision 1.3a. The AD8192 is an I2C slave and its control interface is based on the 3.3 V I2C bus specification.
Rev. 0 | Page 4 of 28
AD8192 ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter AVCC to AVEE DVCC to DVEE DVEE to AVEE V TTI V TTO AMUXVCC VREF_AB VREF_COM Internal Power Dissipation High Speed Input Voltage High Speed Differential Input Voltage Low Speed Input Voltage I2C Logic Input Voltage Storage Temperature Range Operating Temperature Range Junction Temperature ESD HBM Input Pins Only ESD HBM All Other Pins Rating 3.7 V 3.7 V ±0.3 V AVCC + 0.6 V AVCC + 0.6 V 5.5 V 5.5 V 5.5 V 2.41 W AVCC − 1.4 V < VIN < AVCC + 0.6 V 2.0 V DVEE − 0.3 V < VIN < AMUXVCC + 0.6 V DVEE − 0.3 V < VIN < DVCC + 0.6 V −65°C to +125°C −40°C to +85°C 150°C ±7 kV ±1.5 kV
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device soldered in a four-layer JEDEC circuit board for surface-mount packages. θJC is specified for the exposed pad soldered to the circuit board with no airflow. Table 5. Thermal Resistance
Model 56-Lead LFCSP θJA 27 θJC 2.1 Unit °C/W
ESD CAUTION
Rev. 0 | Page 5 of 28
AD8192 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
56 55 54 53 52 51 50 49 48 47 46 45 44 43
AVCC IN_A0 IP_A0 AVEE IN_A1 IP_A1 VTTI IN_A2 IP_A2 AVCC IN_A3 IP_A3 AVEE I2C_ADDR
DDC_A0 DDC_A1 HPD_A CEC_I/O DVEE VREF_AB DDC_COM0 DDC_COM1 VREF_COM AMUXVCC CEC_O/I DDC_B0 DDC_B1 HPD_B
PIN 1 INDICATOR
1 2 3 4 5 6 7 8 9 10 11 12 13 14
AD8192
TOP VIEW (Not to Scale)
42 41 40 39 38 37 36 35 34 33 32 31 30 29
AVCC IP_B3 IN_B3 AVEE IP_B2 IN_B2 VTTI IP_B1 IN_B1 AVCC IP_B0 IN_B0 AVEE I2C_SDA
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. 1, 10, 33, 42 2 3 4, 13, 30, 39, ePAD 5 6 7, 36 8 9 11 12 14 15, 21 16 17 18, 24 19 20 22 23 25 26 27 28 29 31 32 34 35 Mnemonic AVCC IN_A0 IP_A0 AVEE IN_A1 IP_A1 VTTI IN_A2 IP_A2 IN_A3 IP_A3 I2C_ADDR DVCC ON0 OP0 VTTO ON1 OP1 ON2 OP2 ON3 OP3 RESET I2C_SCL I2C_SDA IN_B0 IP_B0 IN_B1 IP_B1 Type 1 Power HS I/O HS I/O Power HS I/O HS I/O Power HS I/O HS I/O HS I/O HS I/O Control Power HS I/O HS I/O Power HS I/O HS I/O HS I/O HS I/O HS I/O HS I/O Control Control Control HS I/O HS I/O HS I/O HS I/O Description Positive Analog Supply. 3.3 V nominal. High Speed Input Complement. High Speed Input. Negative Analog Supply. 0 V nominal. High Speed Input Complement. High Speed Input. Input Termination Supply. Nominally connected to AVCC. High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input. I2C Address LSB. Positive Digital Power Supply. 3.3 V nominal. High Speed Output Complement. High Speed Output. Output Termination Supply. Nominally connected to AVCC. High Speed Output Complement. High Speed Output. High Speed Output Complement. High Speed Output. High Speed Output Complement. High Speed Output. Configuration Registers Reset. Normally pulled to AVCC. I2C Clock. I2C Data. High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input.
Rev. 0 | Page 6 of 28
07050-003
NOTES 1. THE AD8192 LFCSP HAS AN EXPOSED PADDLE (ePAD) ON THE UNDERSIDE OF THE PACKAGE WHICH AIDS IN HEAT DISSIPATION. THE ePAD MUST BE ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE IN ORDER TO MEET THERMAL SPECIFICATIONS.
DVCC ON0 OP0 VTTO ON1 OP1 DVCC ON2 OP2 VTTO ON3 OP3 RESET I2C_SCL
15 16 17 18 19 20 21 22 23 24 25 26 27 28
AD8192
Pin No. 37 38 40 41 43 44 45 46 47 48 49 50 51 52 53 54 55 56
1
Mnemonic IN_B2 IP_B2 IN_B3 IP_B3 HPD_B DDC_B1 DDC_B0 CEC_O/I AMUXVCC VREF_COM DDC_COM1 DDC_COM0 VREF_AB DVEE CEC_I/O HPD_A DDC_A1 DDC_A0
Type 1 HS I/O HS I/O HS I/O HS I/O LS O LS I/O LS I/O LS I/O Power Reference LS I/O LS I/O Reference Power LS I/O LS O LS I/O LS I/O
Description High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input. Hot Plug Detect Output. Display Data Channel Input/Output. Display Data Channel Input/Output. Consumer Electronics Control Output/Input. Positive Auxiliary Switch Supply. 5 V typical. Positive Auxiliary Switch Supply Common Side. Display Data Channel Common Input/Output. Display Data Channel Common Input/Output. Positive Auxiliary Switch Supply Source Side. Negative Digital and Auxiliary Switch Power Supply. 0 V nominal. Consumer Electronics Control Input/Output. Hot Plug Detect Output. Display Data Channel Input/Output. Display Data Channel Input/Output.
HS = high speed, LS = low speed, I = input, O = output.
Rev. 0 | Page 7 of 28
AD8192 TYPICAL PERFORMANCE CHARACTERISTICS
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
HDMI CABLE DIGITAL PATTERN GENERATOR
EVALUATION BOARD
AD8192
SERIAL DATA ANALYZER
SMA COAX CABLE
07050-004
REFERENCE EYE DIAGRAM AT TP1
TP1
TP2
TP3
Figure 4. Test Circuit Diagram for Rx Eye Diagrams
250mV/DIV
07050-005
250mV/DIV
0.125UI/DIV AT 2.25Gbps
0.125UI/DIV AT 2.25Gbps
Figure 5. Rx Eye Diagram at TP2 (Cable = 2 m, 30 AWG)
Figure 7. Rx Eye Diagram at TP3, EQ = 12 dB (Cable = 2 m, 30 AWG)
250mV/DIV
250mV/DIV
07050-006
0.125UI/DIV AT 2.25Gbps
0.125UI/DIV AT 2.25Gbps
Figure 6. Rx Eye Diagram at TP2 (Cable = 20 m, 24 AWG)
Figure 8. Rx Eye Diagram at TP3, EQ = 12 dB (Cable = 20 m, 24 AWG)
Rev. 0 | Page 8 of 28
07050-008
07050-007
AD8192
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
HDMI CABLE DIGITAL PATTERN GENERATOR
EVALUATION BOARD
AD8192
SERIAL DATA ANALYZER
SMA COAX CABLE
07050-009
REFERENCE EYE DIAGRAM AT TP1
TP1
TP2
TP3
Figure 9. Test Circuit Diagram for Tx Eye Diagrams
250mV/DIV
07050-010
250mV/DIV
0.125UI/DIV AT 2.25Gbps
0.125UI/DIV AT 2.25Gbps
Figure 10. Tx Eye Diagram at TP2, PE = 0 dB
Figure 12. Tx Eye Diagram at TP3, PE = 0 dB (Cable = 2 m, 24 AWG)
250mV/DIV
250mV/DIV
07050-011
0.125UI/DIV AT 2.25Gbps
0.125UI/DIV AT 2.25Gbps
Figure 11. Tx Eye Diagram at TP2, PE = 6 dB
Figure 13. Tx Eye Diagram at TP3, PE = 6 dB (Cable = 10 m, 24 AWG)
Rev. 0 | Page 9 of 28
07050-013
07050-012
AD8192
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
0.6 0.6 ALL CABLES = 24 AWG, EQ = 12dB 0.5 0.5
DETERMINISTIC JITTER (UI)
0.4
DETERMINISTIC JITTER (UI)
0.4 2.25Gbps, PE OFF 0.3 1.5Gbps, PE OFF 0.2 0.75Gbps, MAX PE 0.1
07050-017
0.3 2.25Gbps, EQ = 12dB 0.2
0.75Gbps, PE OFF 2.25Gbps, MAX PE 1.5Gbps, MAX PE
1.5Gbps, EQ = 12dB 0.75Gbps, EQ = 12dB
0.1 ALL CABLES = 24 AWG 0 0 5 10 15 20 25 30 35
07050-014
0
0
10
20
30
CABLE LENGTH (m)
HDMI CABLE LENGTH (m)
Figure 14. Jitter vs. Input Cable Length (See Figure 4 for Test Setup)
Figure 17. Jitter vs. Output Cable Length (See Figure 9 for Test Setup)
50 45 40 35 JITTER (ps) 30 25 20 15 10
07050-015
1.2 DJ, EQ = 12dB RJ, EQ = 12dB 1.0
EYE HEIGHT (V)
0.8
0.6
0.4
0.2
07050-018
5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
2.4
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0 2.2
2.4
DATA RATE (Gbps)
DATA RATE (Gbps)
Figure 15. Jitter vs. Data Rate
Figure 18. Eye Height vs. Data Rate
50 DJ, EQ = 12dB RJ, EQ = 12dB 40
1.2
1.0
JITTER (ps)
30
EYE HEIGHT (V)
07050-016
0.8
0.6
20
0.4
10
0.2
07050-019
0 3.135
3.185
3.235
3.285
3.335
3.385
3.435
0 3.135
3.185
3.235
3.285
3.335
3.385
3.435
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 16. Jitter vs. Supply Voltage
Figure 19. Eye Height vs. Supply Voltage
Rev. 0 | Page 10 of 28
AD8192
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
50 DJ, EQ = 12dB RJ, EQ = 12dB 40
50 45 40 35 DJ, EQ = 12dB RJ, EQ = 12dB
JITTER (ps)
JITTER (ps)
30
30 25 20 15
20
10
07050-020
10 5 0 2.5 2.7 2.9 3.1 3.3 3.5
07050-023
0
0
0.5
1.0 DIFFERENTIAL SWING (V)
1.5
2.0
3.7
INPUT COMMON-MODE VOLTAGE (V)
Figure 20. Jitter vs. Differential Input Swing
50 DJ, EQ = 12dB RJ, EQ = 12dB 40
100 90 80 70
Figure 23. Jitter vs. Input Common-Mode Voltage
JITTER (ps)
30
RESISTANCE (Ω)
60 OUTPUT 50 40 30 INPUT
20
10
07050-021
20 10 0 –40 –20 0 20 40 60 80
07050-024
0 –40
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. Jitter vs. Temperature
120
Figure 24. Single-Ended Termination Resistance vs. Temperature
RISE/FALL TIME 20% TO 80% (ps)
100
80 RISE FALL
60
40
20
07050-022
0 –40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 22. Rise and Fall Time vs. Temperature
Rev. 0 | Page 11 of 28
AD8192 THEORY OF OPERATION
The primary function of the AD8192 is to switch one of two (HDMI or DVI) single link sources to one output. Each HDMI/DVI link consists of four differential, high speed channels and four auxiliary single-ended, low speed control signals. The high speed channels include a data-word clock and three transition minimized differential signaling (TMDS) data channels running at 10× the data-word clock frequency for data rates up to 2.25 Gbps. The low speed control signals include the display data channel (DDC) bus (SDA and SCL), the consumer electronics control (CEC) line, and the hot plug detect (HPD) signal. All four high speed TMDS channels are identical; that is, the pixel clock can be run on any of the four TMDS channels. Transmit and receive channel compensation is provided for the high speed channels where the user can (manually) select among a number of fixed settings. The AD8192 isolates and buffers the DDC bus. It additionally isolates and buffers the CEC line and includes integrated pullups for the CEC line. The AD8192 also pulses the HPD signal low upon channel switching. The AD8192 has I2C serial programming with two user programmable I2C slave addresses. The I2C slave address of the AD8192 is 0b100100X. The least significant bit, represented by X in the address, is set by tying the I2C_ADDR pin to either 3.3 V (for the value X = 1) or to 0 V (for X = 0).
OP
VTTI 50Ω 50Ω
IP IN
CABLE EQ
AVEE
Figure 25. High Speed Input Simplified Schematic
OUTPUT CHANNELS
Each high speed output differential pair is terminated to the +3.3 V VTTO power supply through a pair of 50 Ω on-chip resistors, as shown in Figure 26. This termination is userselectable; it can be turned on or off by programming the TX_PTO bit of the transmitter settings register.
VTTO
50Ω
50Ω
ON
ESD PROT.
AVEE
INPUT CHANNELS
Each high speed input differential pair terminates to the 3.3 V VTTI power supply through a pair of single-ended 50 Ω onchip resistors, as shown in Figure 25. The state of the input terminations can be configured automatically or programmed manually through the serial control interface. The termination state is placed in the automatic mode by programming 0 in the RX_TO bit of the receiver settings register. In the automatic mode, the selected input has all terminations enabled, and the deselected input has all input terminations disabled. This state is automatically updated upon channel switching. In the manual mode, 1 is programmed into the RX_TO bit of the receiver settings register, and the state of each individual input termination is set by programming the associated RX_PT bits in the input termination control register. The input equalizer can be manually configured to provide two different levels of high frequency boost: 6 dB or 12 dB. The equalizer level defaults to 12 dB after reset. The user can individually program the equalization level of the eight high speed input channels by selectively setting the associated RX_EQ bits in the receive equalizer register. No specific cable length is suggested for a particular equalization setting because cable performance varies widely among manufacturers; however, in general, the equalization of the AD8192 can be set to 12 dB without degrading the signal integrity, even for short input cables.
Figure 26. High Speed Output Simplified Schematic
The output termination resistors of the AD8192 back terminate the output TMDS transmission lines. These back terminations, as recommended in the HDMI 1.3a specification, act to absorb reflections from impedance discontinuities on the output traces, improving the signal integrity of the output traces and adding flexibility to how the output traces can be routed. For example, interlayer vias can be used to route the AD8192 TMDS outputs on multiple layers of the PCB without severely degrading the quality of the output signal. The output has a disable feature that places the outputs in tristate mode (HS_EN bit of the high speed device modes register). Bigger wire-OR’ed arrays can be constructed using the AD8192 in this mode. The AD8192 requires output termination resistors when the high speed outputs are enabled. Termination can be internal and/or external. The internal terminations of the AD8192 are enabled by programming the TX_PTO bit of the transmitter settings register (the default upon reset). External terminations can be provided either by on-board resistors or by the input termination resistors of an HDMI/DVI receiver. If both the internal terminations are enabled and external terminations are present, set the output current level to 20 mA by programming the TX_OCL bit of the transmitter settings register (the default upon reset). If only external terminations are provided (if the internal terminations are disabled), set the output current level
Rev. 0 | Page 12 of 28
07050-026
DISABLE
IOUT
07050-025
AD8192
to 10 mA by programming the TX_OCL bit of the transmitter settings register. The high speed outputs must be disabled if there are no output termination resistors present in the system. The output equalizer (pre-emphasis) can be manually configured to provide one of four different levels of high frequency boost. The specific boost level is selected by programming the TX_PE bits of the transmitter settings register. No specific cable length is suggested for a particular pre-emphasis setting because cable performance varies widely among manufacturers. frequency response than that of the channel, thereby leading to improved high frequency energy, improved transition times, and improved eye opening on the far end of the channel. Using a pre-emphasis filter for compensating channel losses allows for longer cable runs with or without a receive equalizer on the far end of the channel. When there is no receive equalizer on the far end of the channel, the pre-emphasis filter should allow longer cable runs than is acceptable with no pre-emphasis. In the case of both a pre-emphasis filter on the near end and a receive equalizer on the far end of the channel, the allowable cable run should be longer than either compensation could achieve alone. The pulse response of a pre-emphasized waveform is shown in Figure 27. The output voltage levels and symbol descriptions are listed in Table 7 and Table 8, respectively.
PRE-EMPHASIS OFF VTTO VOCM VOSE-DC VL VH
SWITCHING MODE
The AD8192 is a 2:1 HDMI/DVI source switch. The user can select which high speed TMDS input is routed to the output by programming the HS_CH bit of the high speed modes register and which low speed DDC input/output is routed to the DDC common input/output by programming the AUX_CH bit of the auxiliary device register.
PRE-EMPHASIS
The pre-emphasized TMDS outputs precompensate the transmitted signal to account for losses in systems with long cable runs. These long cable runs selectively attenuate the high frequency energy of the signal, leading to degraded transition times and eye closure. Similar to a receive equalizer, the goal of the preemphasis filter is to boost the high frequency energy in the signal. However, unlike the receive equalizer, the pre-emphasis filter is applied before the channel, thus predistorting the transmitted signal to account for the loss of the channel. The series connection of the pre-emphasis filter and the channel results in a flatter Table 7. Output Voltage Levels
PE Setting 0 1 2 3 0 1 2 3 OCL Setting 0 0 0 0 1 1 1 1 Boost (dB) 0 2 4 6 0 2 4 6 IT (mA) 10 12.5 15 20 20 25 30 40 VOSE-DC (mV p-p) 250 250 250 250 500 500 500 500 VOSE-BOOST (mV p-p) 250 312.5 375 500 500 625 750 1000 VOCM (V) 3.175 3.144 3.133 3.050 3.050 2.988 2.925 2.8 DC-Coupled VH (V) VL (V) 3.3 3.050 3.3 2.988 3.3 2.925 3.3 2.8 3.3 2.8 3.3 2.675 3.3 2.550 3.3 2.3
PRE-EMPHASIS ON VTTO
VH VOSE-DC VOSE-BOOST VL
