4:1 HDMI/DVI Switch with Equalization AD8197A
FEATURES
4 inputs, 1 output HDMI/DVI link Enables HDMI 1.3-compliant receiver Pin-to-pin compatible with the AD8191A 4 TMDS channels per link Supports 250 Mbps to 2.25 Gbps data rates Supports 25 MHz to 225 MHz pixel clocks Equalized inputs for operation with long HDMI cables (20 meters at 2.25 Gbps) Fully buffered unidirectional inputs/outputs Globally switchable, 50 Ω on-chip terminations Pre-emphasized outputs Low added jitter Single-supply operation (3.3 V) 4 auxiliary channels per link Bidirectional unbuffered inputs/outputs Flexible supply operation (3.3 V to 5 V) HDCP standard compatible Allows switching of DDC bus and 2 additional signals Output disable feature Reduced power dissipation Removable output termination Allows building of larger arrays 2 AD8197A devices support HDMI/DVI dual-link Standards compatible: HDMI receiver, HDCP, DVI Serial (I2C slave) and parallel control interface 100-lead, 14 mm × 14 mm LQFP, Pb-free package
FUNCTIONAL BLOCK DIAGRAM
PP_CH[1:0] PP_OTO PP_OCL PP_EQ PP_EN PP_PRE[1:0]
RESET
PARALLEL SERIAL I2C_SDA I2C_SCL I2C_ADDR[2:0] VTTI
2
2
AD8197A
CONTROL LOGIC AVCC DVCC AMUXVCC AVEE DVEE VTTO
3
CONFIG INTERFACE
+ IP_A[3:0] IN_A[3:0] – + IP_B[3:0]
4 4 4 4 4 4 4 4 4 4
IN_B[3:0] – + IP_C[3:0] IN_C[3:0] – + IP_D[3:0] IN_D[3:0] –
SWITCH CORE EQ
PE
+ OP[3:0] – ON[3:0]
HIGH SPEED VTTI AUX_A[3:0] AUX_B[3:0] AUX_C[3:0] AUX_D[3:0]
BUFFERED
4 4 4 4
SWITCH CORE LOW SPEED UNBUFFERED
4
AUX_COM[3:0]
BIDIRECTIONAL
Figure 1.
TYPICAL APPLICATION
MEDIA CENTER HDTV SET HDMI RECEIVER SET-TOP BOX DVD PLAYER
04:20
GAME CONSOLE
APPLICATIONS
Multiple input displays Projectors A/V receivers Set-top boxes Advanced television (HDTV) sets
Figure 2. Typical HDTV Application
GENERAL DESCRIPTION
The AD8197A is an HDMI™/DVI switch featuring equalized TMDS® inputs and pre-emphasized TMDS outputs, ideal for systems with long cable runs. Outputs can be set to a high impedance state to reduce the power dissipation and/or to allow the construction of larger arrays using the wire-OR technique. The AD8197A is provided in a 100-lead LQFP, Pb-free, surfacemount package, specified to operate over the −40°C to +85°C temperature range.
PRODUCT HIGHLIGHTS
1. Supports data rates up to 2.25 Gbps, enabling 1080p deep color (12-bit color) HDMI formats, and greater than UXGA (1600 × 1200) DVI resolutions. Input cable equalizer enables use of long cables at the input (more than 20 meters of 24 AWG cable at 2.25 Gbps). Auxiliary switch routes a DDC bus and two additional signals for a single-chip, HDMI 1.3 receive-compliant solution.
2. 3.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
07014-002
AD8197A
07014-001
AD8197A TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Typical Application........................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 Maximum Power Dissipation ..................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 9 Eye Diagrams ................................................................................ 9 Performance Graphs .................................................................. 11 Theory of Operation ...................................................................... 13 Introduction ................................................................................ 13 Input Channels............................................................................ 13 Output Channels ........................................................................ 13 Auxiliary Switch.......................................................................... 14 Serial Control Interface.................................................................. 15 Reset ............................................................................................. 15 Write Procedure.......................................................................... 15 Read Procedure........................................................................... 16 Switching/Update Delay............................................................ 16 Parallel Control Interface .............................................................. 17 Serial Interface Configuration Registers ..................................... 18 High Speed Device Modes Register......................................... 19 Auxiliary Device Modes Register............................................. 19 Receiver Settings Register ......................................................... 19 Input Termination Pulse Register 1 and Register 2 ............... 19 Receive Equalizer Register 1 and Register 2 ........................... 20 Transmitter Settings Register.................................................... 20 Parallel Interface Configuration Registers .................................. 21 High Speed Device Modes Register......................................... 22 Auxiliary Device Modes Register............................................. 22 Receiver Settings Register ......................................................... 22 Input Termination Pulse Register 1 and Register 2 ............... 22 Receive Equalizer Register 1 and Register 2 ........................... 22 Transmitter Settings Register.................................................... 22 Application Information................................................................ 23 Pinout........................................................................................... 23 Cable Lengths and Equalization............................................... 23 PCB Layout Guidelines.............................................................. 24 Outline Dimensions ....................................................................... 28 Ordering Guide .......................................................................... 28
REVISION HISTORY
11/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD8197A SPECIFICATIONS
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE Maximum Data Rate (DR) per Channel Bit Error Rate (BER) Added Deterministic Jitter Added Random Jitter Differential Intrapair Skew Differential Interpair Skew 1 EQUALIZATION PERFORMANCE Receiver (Highest Setting) 2 Transmitter (Highest Setting) 3 INPUT CHARACTERISTICS Input Voltage Swing Input Common-Mode Voltage (VICM) OUTPUT CHARACTERISTICS High Voltage Level Low Voltage Level Rise/Fall Time (20% to 80%) INPUT TERMINATION Resistance AUXILIARY CHANNELS On Resistance, RAUX On Capacitance, CAUX Input/Output Voltage Range POWER SUPPLY AVCC QUIESCENT CURRENT AVCC Conditions/Comments NRZ PRBS 223 − 1 DR ≤ 2.25 Gbps, PRBS 27 − 1, EQ = 12 dB At output At output Boost frequency = 825 MHz Boost frequency = 825 MHz Differential 150 AVCC − 800 AVCC − 10 AVCC − 600 75 Min 2.25 10−9 25 1 1 40 12 6 1200 AVCC AVCC + 10 AVCC − 400 200 ps (p-p) ps (rms) ps ps dB dB mV mV mV mV ps Ω Ω pF V V mA mA mA mA mA mA mA mA mW mW mW ms ms ns Typ Max Unit Gbps
Single-ended high speed channel Single-ended high speed channel
135 50 100 8
Single-ended
DC bias = 2.5 V, ac voltage = 3.5 V, f = 100 kHz DVEE Operating range Outputs disabled Outputs enabled, no pre-emphasis Outputs enabled, maximum pre-emphasis Input termination on 4 Output termination on, no pre-emphasis Output termination on, maximum pre-emphasis 3 30 52 95 5 35 72 3.2
AMUXVCC 3.3 40 60 110 40 40 80 7 0.01 271 574 910 3.6 44 66 122 54 46 90 8 0.1 361 671 1050 200 1.5
V TTI V TTO DVCC AMUXVCC POWER DISSIPATION
Outputs disabled Outputs enabled, no pre-emphasis Outputs enabled, maximum pre-emphasis TIMING CHARACTERISTICS Switching/Update Delay RESET Pulse Width High speed switching register: HS_CH All other configuration registers
115 384 704
50
Rev. 0 | Page 3 of 28
AD8197A
Parameter SERIAL CONTROL INTERFACE 5 Input High Voltage, VIH Input Low Voltage, VIL Output High Voltage, VOH Output Low Voltage, VOL PARALLEL CONTROL INTERFACE Input High Voltage, VIH Input Low Voltage, VIL
1 2
Conditions/Comments
Min 2
Typ
Max
Unit V V V V V V
0.8 2.4 0.4 2 0.8
Differential interpair skew is measured between the TMDS pairs of a single link. AD8197A output meets the transmitter eye diagram as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3. 3 Cable output meets the receiver eye diagram mask as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3. 4 Typical value assumes only the selected HDMI/DVI link is active with nominal signal swings and that the unselected HDMI/DVI links are deactivated. Minimum and maximum limits are measured at the respective extremes of input termination resistance and input voltage swing. 5 The AD8197A is an I2C slave and its serial control interface is based on the 3.3 V I2C bus specification.
Rev. 0 | Page 4 of 28
AD8197A ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter AVCC to AVEE DVCC to DVEE DVEE to AVEE V TTI V TTO AMUXVCC Internal Power Dissipation High Speed Input Voltage High Speed Differential Input Voltage Low Speed Input Voltage I2C and Parallel Logic Input Voltage Storage Temperature Range Operating Temperature Range Junction Temperature Rating 3.7 V 3.7 V ±0.3 V AVCC + 0.6 V AVCC + 0.6 V 5.5 V 2.2 W AVCC − 1.4 V < VIN < AVCC + 0.6 V 2.0 V DVEE − 0.3 V < VIN < AMUXVCC + 0.6 V DVEE − 0.3 V < VIN < DVCC + 0.6 V −65°C to +125°C −40°C to +85°C 150°C
THERMAL RESISTANCE
θJA is specified for the worst-case conditions: a device soldered in a 4-layer JEDEC circuit board for surface-mount packages. θJC is specified for no airflow. Table 3. Thermal Resistance
Package Type 100-Lead LQFP θJA 56 θJC 19 Unit °C/W
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8197A is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure. To ensure proper operation, it is necessary to observe the maximum power rating as determined by the coefficients in Table 3.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. 0 | Page 5 of 28
AD8197A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AUX_COM0 AUX_COM1 AUX_COM2 AUX_COM3 AMUXVCC PP_OTO AUX_A0 AUX_A1 AUX_A2 AUX_A3 AUX_B0 AUX_B1 AUX_B2 AUX_B3 AUX_C0 AUX_C1 AUX_C2 AUX_C3 AUX_D0 AUX_D1 AUX_D2 AUX_D3
78
PP_EQ
77
100
99
95
89
88
87
84
93
92
82
97
96
91
90
86
85
81
80
98
94
83
79
76
PP_EN
DVEE
AVCC IN_B0 IP_B0 AVEE IN_B1 IP_B1 VTTI IN_B2 IP_B2 AVEE IN_B3 IP_B3 AVCC IN_A0 IP_A0 AVEE IN_A1 IP_A1 VTTI IN_A2 IP_A2 AVCC IN_A3 IP_A3 AVEE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIN 1 INDICATOR
75 74 73 72 71 70 69 68 67 66
AVCC IP_C3 IN_C3 AVEE IP_C2 IN_C2 VTTI IP_C1 IN_C1 AVEE IP_C0 IN_C0 AVCC IP_D3 IN_D3 AVEE IP_D2 IN_D2 VTTI IP_D1 IN_D1 AVCC IP_D0 IN_D0 AVEE
AD8197A
TOP VIEW (Not to Scale)
65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
27
31
37
38
39
42
48
49
26
33
34
44
29
30
35
36
40
41
45
46
28
32
VTTO
VTTO
OP0
OP1
OP2
DVEE
ON0
OP3
43
47
PP_PRE0
PP_PRE1
PP_OCL
PP_CH0
RESET
DVCC
DVCC
ON3
ON1
ON2
DVCC
I2C_SCL
PP_CH1
I2C_ADDR0
I2C_ADDR1
I2C_ADDR2
I2C_SDA
50
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1, 13, 22, 54, 63, 75 2 3 4, 10, 16, 25, 51, 60, 66, 72 5 6 7, 19, 57, 69 8 9 11 12 14 15 17 18 20 21 23 Mnemonic AVCC IN_B0 IP_B0 AVEE IN_B1 IP_B1 V TTI IN_B2 IP_B2 IN_B3 IP_B3 IN_A0 IP_A0 IN_A1 IP_A1 IN_A2 IP_A2 IN_A3 Type 1 Power HS I HS I Power HS I HS I Power HS I HS I HS I HS I HS I HS I HS I HS I HS I HS I HS I Description Positive Analog Supply. 3.3 V nominal. High Speed Input Complement. High Speed Input. Negative Analog Supply. 0 V nominal. High Speed Input Complement. High Speed Input. Input Termination Supply. Nominally connected to AVCC. High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input. High Speed Input Complement.
Rev. 0 | Page 6 of 28
07014-003
AD8197A
Pin No. 24 26 27 28 29, 95 30 31 32, 38, 47 33 34 35, 41 36 37 39 40 42 43 44 45 46 48 49 50 52 53 55 56 58 59 61 62 64 65 67 68 70 71 73 74 76 77 78 79 80 81 82 83 84 85 86 87 88 89 Mnemonic IP_A3 I2C_ADDR0 I2C_ADDR1 I2C_ADDR2 DVEE PP_CH0 PP_CH1 DVCC ON0 OP0 V TTO ON1 OP1 ON2 OP2 ON3 OP3 RESET PP_PRE0 PP_PRE1 PP_OCL I2C_SCL I2C_SDA IN_D0 IP_D0 IN_D1 IP_D1 IN_D2 IP_D2 IN_D3 IP_D3 IN_C0 IP_C0 IN_C1 IP_C1 IN_C2 IP_C2 IN_C3 IP_C3 PP_EN PP_EQ AUX_D3 AUX_D2 AUX_D1 AUX_D0 AMUXVCC AUX_C3 AUX_C2 AUX_C1 AUX_C0 AUX_COM3 AUX_COM2 AUX_COM1 Type 1 HS I Control Control Control Power Control Control Power HS O HS O Power HS O HS O HS O HS O HS O HS O Control Control Control Control Control Control HS I HS I HS I HS I HS I HS I HS I HS I HS I HS I HS I HS I HS I HS I HS I HS I Control Control LS I/O LS I/O LS I/O LS I/O Power LS I/O LS I/O LS I/O LS I/O LS I/O LS I/O LS I/O Description High Speed Input. I2C Address 1st LSB. I2C Address 2nd LSB. I2C Address 3rd LSB. Negative Digital and Auxiliary Multiplexer Power Supply. 0 V nominal. High Speed Source Selection Parallel Interface LSB. High Speed Source Selection Parallel Interface MSB. Positive Digital Power Supply. 3.3 V nominal. High Speed Output Complement. High Speed Output. Output Termination Supply. Nominally connected to AVCC. High Speed Output Complement. High Speed Output. High Speed Output Complement. High Speed Output. High Speed Output Complement. High Speed Output. Configuration Registers Reset. Normally pulled up to AVCC. High Speed Pre-Emphasis Selection Parallel Interface LSB. High Speed Pre-Emphasis Selection Parallel Interface MSB. High Speed Output Current Level Parallel Interface. I2C Clock. I2C Data. High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input. High Speed Output Enable Parallel Interface. High Speed Equalization Selection Parallel Interface. Low Speed Input/Output. Low Speed Input/Output. Low Speed Input/Output. Low Speed Input/Output. Positive Auxiliary Multiplexer Supply. 5 V typical. Low Speed Input/Output. Low Speed Input/Output. Low Speed Input/Output. Low Speed Input/Output. Low Speed Common Input/Output. Low Speed Common Input/Output. Low Speed Common Input/Output.
Rev. 0 | Page 7 of 28
AD8197A
Pin No. 90 91 92 93 94 96 97 98 99 100
1
Mnemonic AUX_COM0 AUX_B3 AUX_B2 AUX_B1 AUX_B0 AUX_A3 AUX_A2 AUX_A1 AUX_A0 PP_OTO
Type 1 LS I/O LS I/O LS I/O LS I/O LS I/O LS I/O LS I/O LS I/O LS I/O Control
Description Low Speed Common Input/Output. Low Speed Input/Output. Low Speed Input/Output. Low Speed Input/Output. Low Speed Input/Output. Low Speed Input/Output. Low Speed Input/Output. Low Speed Input/Output. Low Speed Input/Output. High Speed Output Termination Selection Parallel Interface.
HS = high speed, LS = low speed, I = input, O = output.
Rev. 0 | Page 8 of 28
AD8197A TYPICAL PERFORMANCE CHARACTERISTICS
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, unless otherwise noted.
EYE DIAGRAMS
HDMI CABLE DIGITAL PATTERN GENERATOR
EVALUATION BOARD
AD8197A
SERIAL DATA ANALYZER
SMA COAX CABLE
07014-004
REFERENCE EYE DIAGRAM AT TP1
TP1
TP2
TP3
Figure 4. Test Circuit Diagram for Rx Eye Diagram
250mV/DIV
07014-005
250mV/DIV
0.125UI/DIV AT 2.25Gbps
0.125UI/DIV AT 2.25Gbps
Figure 5. Rx Eye Diagram at TP2 (Cable = 2 meters, 30 AWG)
Figure 7. Rx Eye Diagram at TP3, EQ = 6 dB (Cable = 2 meters, 30 AWG)
250mV/DIV
07014-006
250mV/DIV
0.125UI/DIV AT 2.25Gbps
0.125UI/DIV AT 2.25Gbps
Figure 6. Rx Eye Diagram at TP2 (Cable = 20 meters, 24 AWG)
Figure 8. Rx Eye Diagram at TP3, EQ = 12 dB (Cable = 20 meters, 24 AWG)
Rev. 0 | Page 9 of 28
07014-008
07014-007
AD8197A
HDMI CABLE DIGITAL PATTERN GENERATOR
EVALUATION BOARD
AD8197A
SERIAL DATA ANALYZER
SMA COAX CABLE
07014-009
REFERENCE EYE DIAGRAM AT TP1
TP1
TP2
TP3
Figure 9. Test Circuit Diagram for Tx Eye Diagrams
250mV/DIV
07014-010
250mV/DIV
0.125UI/DIV AT 2.25Gbps
0.125UI/DIV AT 2.25Gbps
Figure 10. Tx Eye Diagram at TP2, PE = 2 dB
Figure 12. Tx Eye Diagram at TP3, PE = 2 dB (Cable = 2 meters, 30 AWG)
250mV/DIV
07014-011
250mV/DIV
0.125UI/DIV AT 2.25Gbps
0.125UI/DIV AT 2.25Gbps
Figure 11. Tx Eye Diagram at TP2, PE = 6 dB
Figure 13. Tx Diagram at TP3, PE = 6 dB (Cable = 10 meters, 28 AWG)
Rev. 0 | Page 10 of 28
07014-013
07014-012
AD8197A
PERFORMANCE GRAPHS
0.6 2m CABLE = 30AWG 5m TO 20m CABLES = 24AWG 0.5 0.5 0.6 2m CABLE = 30AWG 5m TO 20m CABLES = 24AWG
DETERMINISTIC JITTER (UI)
0.4
DETERMINISTIC JITTER (UI)
2.25Gbps EQ = 12dB 1.65Gbps EQ = 6dB 2.25Gbps EQ = 6dB 1.65Gbps EQ = 12dB
0.4 1.65Gbps, PE OFF 0.3 2.25Gbps, PE OFF 0.2 2.25Gbps, PE MAX
0.3
0.2
0.1
07014-014
0.1
07014-017
1.65Gbps, PE MAX 0
0
0
5
10
15
20
25
0
5
10 HDMI CABLE LENGTH (m)
15
20
HDMI CABLE LENGTH (m)
Figure 14. Jitter vs. Input Cable Length (See Figure 4 for Test Setup)
Figure 17. Jitter vs. Output Cable Length (See Figure 9 for Test Setup)
50 45 40
1200
1000
JITTER (ps)
30 25 20 15 10 480p 480i 1080i/720p
1080p 12-BIT
1.65Gbps
EYE HEIGHT (mV)
07014-015
35
1080p 8-BIT
800
600
DJ (p-p)
400
200 RJ (rms) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
07014-018
5 0
2.4
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
DATA RATE (Gbps)
DATA RATE (Gbps)
Figure 15. Jitter vs. Data Rate
Figure 18. Eye Height vs. Data Rate
50 45 40
800 700 600
EYE HEIGHT (mV)
07014-016
35
JITTER (ps)
30 25 DJ (p-p) 20 15 10 5 0 3.0 3.1 3.2 RJ (rms) 3.3 3.4 3.5
500 400 300 200
07014-019
100 0 2.5
3.6
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 16. Jitter vs. Supply Voltage
Figure 19. Eye Height vs. Supply Voltage
Rev. 0 | Page 11 of 28
AD8197A
50 50
40
40
JITTER (ps)
JITTER (ps)
30 DJ (p-p) 20
30 DJ (p-p) 20
10
07014-020
10 RJ (rms) RJ (rms) 0 2.5 2.7 2.9 3.1 3.3 3.5
07014-023
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
3.7
DIFFERENTIAL INPUT SWING (V)
INPUT COMMON-MODE VOLTAGE (V)
Figure 20. Jitter vs. Differential Input Swing
Figure 23. Jitter vs. Input Common-Mode Voltage
50 45
120 115
DIFFERENTIAL INPUT TERMINATION RESISTANCE (Ω)
07014-021
40 35
110 105 100 95 90
07014-024
JITTER (ps)
30 25 20 15 10 5 0 –40 –20 0 RJ (rms) 20 40 60 80 DJ (p-p)
85 80 –40
100
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. Jitter vs. Temperature
Figure 24. Differential Input Termination Resistance vs. Temperature
160 140
RISE/FALL TIME 20% TO 80% (ps)
FALL TIME 120 RISE TIME 100 80 60 40
07014-022
20 0 –40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 22. Rise and Fall Time vs. Temperature
Rev. 0 | Page 12 of 28
AD8197A THEORY OF OPERATION
INTRODUCTION
The AD8197A is a pin-to-pin HDMI 1.3 receive-compliant replacement for the AD8191A. The primary function of the AD8197A is to switch one of four (HDMI or DVI) single-link sources to one output. Each HDMI/DVI link consists of four differential, high speed channels and four auxiliary singleended, low speed control signals. The high speed channels include a data-word clock and three transition minimized differential signaling (TMDS) data channels running at 10× the data-word clock frequency for data rates up to 2.25 Gbps. The four low speed control signals are 5 V tolerant bidirectional lines that can carry configuration signals, HDCP encryption, and other information, depending upon the specific application. All four high speed TMDS channels in a given link are identical; that is, the pixel clock can be run on any of the four TMDS channels. Transmit and receive channel compensation is provided for the high speed channels where the user can (manually) select among a number of fixed settings. The AD8197A has two control interfaces. Users have the option of controlling the part through either the parallel control interface or the I2C® serial control interface. The AD8197A has eight user-programmable I2C slave addresses to allow multiple AD8197A devices to be controlled by a single I2C bus. A RESET pin is provided to restore the control registers of the AD8197A to default values. In all cases, serial programming values override any prior parallel programming values and any use of the serial control interface disables the parallel control interface until the AD8197A is reset.
VTTI 50Ω 50Ω
IP_xx IN_xx
CABLE EQ
AVEE
Figure 25. High Speed Input Simplified Schematic
The input equalizer can be manually configured to provide two different levels of high frequency boost: 6 dB or 12 dB. The user can individually control the equalization level of the eight high speed input channels by selectively programming the associated RX_EQ bits in the receive equalizer register through the serial control interface. Alternately, the user can globally control the equalization level of all eight high speed input channels by setting the PP_EQ pin of the parallel control interface. No specific cable length is suggested for a particular equalization setting because cable performance varies widely between manufacturers; however, in general, the equalization of the AD8197A can be set to 12 dB without degrading the signal integrity, even for short input cables. At the 12 dB setting, the AD8197A can equalize more than 20 meters of 24 AWG cable at 2.25 Gbps.
OUTPUT CHANNELS
Each high speed output differential pair is terminated to the 3.3 V VTTO power supply through two 50 Ω on-chip resistors (see Figure 26). This termination is user-selectable; it can be turned on or off by programming the TX_PTO bit of the transmitter settings register through the serial control interface, or by setting the PP_OTO pin of the parallel control interface. The output termination resistors of the AD8197A back-terminate the output TMDS transmission lines. These back-terminations, as recommended in the HDMI 1.3 specification, act to absorb reflections from impedance discontinuities on the output traces, improving the signal integrity of the output traces and adding flexibility to how the output traces can be routed. For example, interlayer vias can be used to route the AD8197A TMDS outputs on multiple layers of the PCB without severely degrading the quality of the output signal. The AD8197A output has a disable feature that places the outputs in a tristate mode. This mode is enabled by programming the HS_EN bit of the high speed device modes register through the serial control interface or by setting the PP_EN pin of the parallel control interface. Larger wire-OR’ed arrays can be constructed using the AD8197A in this mode.
INPUT CHANNELS
Each high speed input differential pair terminates to the 3.3 V VTTI power supply through a pair of single-ended 50 Ω onchip resistors, as shown in Figure 25. The input terminations can be optionally disconnected for approximately 100 ms following a source switch. The user can program which of the 16 high speed input channels employs this feature by selectively programming the associated RX_PT bits in the input termination pulse registers through the serial control interface. Additionally, all the input terminations can be disconnected by programming the RX_TO bit in the receiver settings register. By default, the input termination is enabled. The input terminations are enabled and cannot be switched when programming the AD8197A through the parallel control interface.
Rev. 0 | Page 13 of 28
07014-025
AD8197A
VTTO 50Ω 50Ω
OPx
ONx
DISABLE
AVEE
Figure 26. High Speed Output Simplified Schematic
The AD8197A requires output termination resistors when the high speed outputs are enabled. Termination can be internal and/or external. The internal terminations of the AD8197A are enabled by programming the TX_PTO bit of the transmitter settings register or by setting the PP_OTO pin of the parallel control interface. The internal terminations of the AD8197A default to the setting indicated by PP_OTO upon reset. External terminations can be provided either by on-board resistors or by the input termination resistors of an HDMI/DVI receiver. If both the internal terminations are enabled and external terminations are present, set the output current level to 20 mA by programming the TX_OCL bit of the transmitter settings register through the serial control interface or by setting the PP_OCL pin of the parallel control interface. The output current level defaults to the level indicated by PP_OCL upon reset. If only external terminations are provided (if the internal terminations are disabled), set the output current level to 10 mA by programming the TX_OCL bit of the transmitter settings register or by setting the PP_OCL pin of the parallel control interface. The high speed outputs must be disabled if there are no output termination resistors present in the system. The output pre-emphasis can be manually configured to provide one of four different levels of high frequency boost. The specific boost level is selected by programming the TX_PE bits of the transmitter settings register through the serial control interface, or by setting the PP_PE bus of the parallel control interface. No specific cable length is suggested for a particular pre-emphasis setting because cable performance varies widely between manufacturers.
07014-026
IOUT
When turning off the AD8197A, care needs to be taken with the AMUXVCC supply to ensure that the auxiliary multiplexer pins remain in a high impedance state. A scenario that illustrates this requirement is one where the auxiliary multiplexer is used to switch the display data channel (DDC) bus. In some applications, additional devices can be connected to the DDC bus (such as an EEPROM with EDID information) upstream of the AD8197A. Extended display identification data (EDID) is a VESA standard-defined data format for conveying display configuration information to sources to optimize display use. EDID devices may need to be available via the DDC bus, regardless of the state of the AD8197A and any downstream circuit. For this configuration, the auxiliary inputs of the powered down AD8197A need to be in a high impedance state to avoid pulling down on the DDC lines and preventing these other devices from using the bus. The AD8197A requires 5 V on its supply pin, AMUXVCC, in order for the AUXMUX channels to be high impedance. When a TV is turned off, it cannot provide such a supply; however, it can be provided from any HDMI source that is plugged into it. A Schottky diode network, as shown in Figure 28, uses the 5 V supply (Pin 18) from any HDMI/DVI source to power AMUXVCC and guarantee high impedance of the auxiliary multiplexer pins. The AMUXVCC supply does not draw any significant static current. The use of diodes ensures that connected HDMI sources do not load this circuit if their 5 V pin is low impedance when turned off. The 100 kΩ resistor ensures that a minimum of current flows through the diodes to keep them forward biased. This precaution does not need to be taken if the DDC peripheral circuitry is connected to the bus downstream of the AD8197A.
PIN 18 HDMI CONNECTOR PIN 14 DVI CONNECTOR SOURCE A +5V +5V INTERNAL (IF ANY) PIN 18 HDMI CONNECTOR PIN 14 DVI CONNECTOR BAT54L BAT54L BAT54L +5V SOURCE C I
