AD8203YRZ-RL

High Common-Mode Voltage, Single-Supply Difference Amplifier AD8203 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAMS NC A1 A2 +VS 6 3 4 7 AD8203 100kΩ G = ×7 G = ×2 +IN A1 –IN +IN 8 –IN 1 +IN A2 –IN 5 10kΩ 200kΩ 200kΩ 10kΩ APPLICATIONS 2 Transmission control Diesel injection control Engine management Adaptive suspension control Vehicle dynamics control OUT 05013-001 High common-mode voltage range −6 V to +30 V at a 5 V supply voltage Operating temperature range: −40°C to +125°C Supply voltage range: 3.5 V to 12 V Low-pass filter (1-pole or 2-pole) Excellent ac and dc performance ±1 mV voltage offset (8-lead SOIC) ±1 ppm/°C typical gain drift 80 dB CMRR minimum dc to 10 kHz NC = NO CONNECT GND Figure 1. Functional Block Diagram INDUCTIVE 5V LOAD CLAMP DIODE GENERAL DESCRIPTION OUTPUT +IN BATTERY 4-TERM SHUNT AD8203 –IN GND A1 A2 NC = NO CONNECT COMMON 05013-002 POWER DEVICE Figure 2. High Line Current Sensor POWER DEVICE 5V OUTPUT +IN BATTERY +VS NC OUT 14V 4-TERM SHUNT AD8203 –IN The AD8203 features an externally accessible 100 kΩ resistor at the output of the Preamp A1, which can be used for low-pass filter applications and for establishing gains other than 14. OUT 14V The AD8203 is available in packaged form. The MSOP and SOIC packages are specified over a wide temperature range, from −40°C to +125°C, making the AD8203 well-suited for use in many automotive platforms. Automotive platforms demand precision components for better system control. The AD8203 provides excellent ac and dc performance keeping errors to a minimum in the user’s system. Typical offset and gain drift in the SOIC package are 0.3 µV/°C and 1 ppm/°C, respectively. Typical offset and gain drift in the MSOP package are 2 μV/°C and 1 ppm/°C, respectively. The device also delivers a minimum CMRR of 80 dB from dc to 10 kHz. NC CLAMP DIODE COMMON GND A1 A2 INDUCTIVE LOAD NC = NO CONNECT 05013-003 The AD8203 is a single-supply difference amplifier for amplifying and low-pass filtering small differential voltages in the presence of a large common-mode voltage (CMV). The input CMV range extends from −6 V to +30 V at a typical supply voltage of 5 V. +VS Figure 3. Low Line Current Sensor Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8203 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 12 Applications ....................................................................................... 1 Applications..................................................................................... 14 Functional Block Diagrams ............................................................. 1 Current Sensing .......................................................................... 14 Revision History ............................................................................... 2 Gain Adjustment ........................................................................ 14 Specifications..................................................................................... 3 Gain Trim .................................................................................... 15 Single Supply ................................................................................. 3 Low-Pass Filtering ...................................................................... 15 Absolute Maximum Ratings ............................................................ 4 High Line Current Sensing with LPF and Gain Adjustment 16 ESD Caution .................................................................................. 4 Driving Charge Redistribution ADCs ..................................... 16 Pin Configuration and Function Descriptions ............................. 5 Outline Dimensions ....................................................................... 17 Typical Performance Characteristics ............................................. 6 Ordering Guide .......................................................................... 17 REVISION HISTORY 4/13—Rev. C to Rev. D Changes to Initial System Gain Parameter.................................... 3 Changes to Ordering Guide .......................................................... 17 2/13—Rev. B to Rev. C Changes to Features Section and General Description Section........ 1 Changes to Table 1 ............................................................................ 3 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 17 2/05—Rev. 0 to Rev. A Changes to Specifications Table ......................................................3 Changes to Caption on Figure 6 and Figure 8 ...............................6 Changes to Figure 12.........................................................................7 Added Figure 14 to Figure 23 ..........................................................7 Changes to Figure 26 and Figure 27 ............................................ 10 Changes to Figure 29...................................................................... 11 Changes to Figure 32 and Figure 33 ............................................ 12 Changes to Ordering Guide .......................................................... 13 10/05—Rev. A to Rev. B Added SOIC Package ......................................................... Universal Replaced Figure 23 ........................................................................... 8 Added Figure 24 to Figure 29.......................................................... 9 Changes to Theory of Operation Section ................................... 12 Added Figure 41.............................................................................. 12 Updated Outline Dimensions ....................................................... 17 10/04—Revision 0: Initial Version Rev. D | Page 2 of 20 Data Sheet AD8203 SPECIFICATIONS SINGLE SUPPLY TOPR = operating temperature range, VS = 5 V, unless otherwise noted, RTI = referred to input, VCM = common-mode voltage. Table 1. Parameter SYSTEM GAIN Initial Error vs. Temperature Gain Drift VOLTAGE OFFSET Initial Input Offset (RTI), TOPR Offset vs. Temperature INPUT Input Impedance Differential Common Mode CMV CMRR 1 PREAMPLIFIER Gain Gain Error Output Voltage Range Output Resistance OUTPUT BUFFER Gain Gain Error Output Voltage Range 3 Input Bias Current Output Resistance DYNAMIC RESPONSE System Bandwidth Slew Rate NOISE 0.1 Hz to 10 Hz Spectral Density, 1 kHz (RTI) POWER SUPPLY Operating Range Quiescent Current vs. Temperature PSRR TEMPERATURE RANGE For Specified Performance Conditions Min AD8203 SOIC Typ Max Min 14 AD8203 MSOP Typ Max 0.04 ≤ VOUT ≤ 4.8 V dc, TOPR TOPR ±0.3 ±20 ±0.3 ±20 V/V % ppm/°C VCM = 0V, TOPR ±2 ±10 ±2 ±15 µV/°C 380 190 +30 kΩ kΩ V 260 130 −6 Continuous VCM = −6 V to +30 V f = dc to 1 kHz f = 10 kHz 2 320 160 14 Unit 380 190 +30 82 80 260 130 −6 82 80 7 0.02 97 100 0.04 ≤ VOUT ≤ 4.8 V dc, TOPR 0.02 97 60 0.33 40 10 300 3.5 VO = 0.1 V dc VS = 3.5 V to 12 V 0.25 75 −40 12 1.0 83 +125 40 2 60 0.33 kHz V/µs 10 300 µV p-p nV/√Hz ±0.3 4.8 3.5 0.25 75 −40 V/V % V kΩ V/V % V nA Ω 0.04 40 2 40 100 ±0.3 4.8 103 2 ±0.3 4.8 0.04 dB dB 7 ±0.3 4.8 103 2 VIN = 0.01 V p-p, VOUT = 0.14 V p-p VIN = 0.28 V, VOUT = 4 V step 320 160 12 1.0 83 V mA dB +125 °C Source imbalance 14 05013-017 10Ω 1% 05013-016 REXT Data Sheet AD8203 GAIN TRIM Figure 45 shows a method for incremental gain trimming by using a trim potentiometer and external resistor REXT. The following approximation is useful for small gain ranges: ΔG ≈ (10 MΩ/REXT)% Thus, the adjustment range is ±2% for REXT = 5 MΩ; ±10% for REXT = 1 MΩ, and so on. Low-pass filters can be implemented in several ways by using the features provided by the AD8203. In the simplest case, a single-pole filter (20 dB/decade) is formed when the output of A1 is connected to the input of A2 via the internal 100 kΩ resistor by strapping Pin 3, Pin 4, and a capacitor added from this node to ground, as shown in Figure 46. If a resistor is added across the capacitor to lower the gain, the corner frequency increases; it should be calculated using the parallel sum of the resistor and 100 kΩ. 5V 5V OUTPUT OUT +IN +VS NC +IN OUT VDIFF 2 VCM GND A1 fC = AD8203 AD8203 –IN OUT NC VDIFF 2 VDIFF 2 VCM +VS VDIFF 2 REXT C IN FARADS –IN A2 1 2πC105 GND A2 A1 GAIN TRIM 20kΩ MIN 05013-019 NC = NO CONNECT 05013-018 C NC = NO CONNECT Figure 45. Incremental Gain Trim Figure 46. Single-Pole, Low-Pass Filter Using the Internal 100 kΩ Resistor Internal Signal Overload Considerations If the gain is raised using a resistor, as shown in Figure 44, the corner frequency is lowered by the same factor as the gain is raised. Thus, using a resistor of 200 kΩ (for which the gain would be doubled), the corner frequency is now 0.796 Hz µF (0.039 µF for a 20 Hz corner frequency). When configuring gain for values other than 14, the maximum input voltage with respect to the supply voltage and ground must be considered, since either the preamplifier or the output buffer reaches its full-scale output (approximately VS − 0.2 V) with large differential input voltages. The input of the AD8203 is limited to (VS − 0.2)/7 for overall gains ≤ 7, since the preamplifier, with its fixed gain of ×7, reaches its full-scale output before the output buffer. For gains greater than 7, the swing at the buffer output reaches its full scale first and limits the AD8203 input to (VS − 0.2)/G, where G is the overall gain. 5V OUT +IN +VS OUT NC VDIFF 2 AD8203 VCM C VDIFF 2 –IN GND A1 A2 LOW-PASS FILTERING When implementing a filter, the PAR should be considered so that the output of the AD8203 preamplifier (A1) does not clip before A2, since this nonlinearity would be averaged and appear as an error at the output. To avoid this error, both amplifiers should be made to clip at the same time. This condition is achieved when the PAR is no greater than the gain of the second amplifier (2 for the default configuration). For example, if a PAR of 5 is expected, the gain of A2 should be increased to 5. 255kΩ C fC(Hz) = 1/C(µF) NC = NO CONNECT 005013-020 In many transducer applications, it is necessary to filter the signal to remove spurious high frequency components, including noise, or to extract the mean value of a fluctuating signal with a peak-to-average ratio (PAR) greater than unity. For example, a full-wave rectified sinusoid has a PAR of 1.57, a raised cosine has a PAR of 2, and a half-wave sinusoid has a PAR of 3.14. Signals having large spikes can have PARs of 10 or more. Figure 47. 2-Pole, Low-Pass Filter A 2-pole filter (with a roll-off of 40 dB/decade) can be implemented using the connections shown in Figure 47. This is a Sallen-Key form based on a ×2 amplifier. It is useful to remember that a 2-pole filter with a corner frequency f2 and a 1-pole filter with a corner at f1 have the same attenuation at the frequency (f22/f1). The attenuation at that frequency is 40 log (f2/f1), which is illustrated in Figure 48. Using the standard resistor value shown and equal capacitors (see Figure 47), the corner frequency is conveniently scaled at 1 Hz µF (0.05 µF for a 20 Hz corner). A maximally flat response occurs when the resistor is lowered to 196 kΩ and the scaling is then 1.145 Hz µF. The output offset is raised by approximately 5 mV (equivalent to 250 µV at the input pins). Rev. D | Page 15 of 20 AD8203 Data Sheet FREQUENCY by a 1-pole low-pass filter, shown in Figure 49, set with a corner frequency of 3.6 Hz, which provides about 30 dB of attenuation at 100 Hz. A higher rate of attenuation can be obtained using a 2-pole filter with fC = 20 Hz, as shown in Figure 50. Although this circuit uses two separate capacitors, the total capacitance is less than half that needed for the 1-pole filter. 20dB/DECADE 40log (f2/f1) INDUCTIVE 5V LOAD CLAMP DIODE OUTPUT +VS +IN f1 BATTERY 05013-021 4-TERM SHUNT BATTERY 93kΩ C NC = NO CONNECT NC OUT 133kΩ AD8203 20kΩ GND A1 A2 POWER DEVICE VOS/IB NULL COMMON 5% CALIBRATION RANGE fC(Hz) = 0.767Hz/C(µF) (0.22µF FOR fC = 3.6Hz) 05013-022 C NC = NO CONNECT COMMON fC(Hz) = 1/C(µF) (0.05µF FOR fC = 20Hz) Figure 50. 2-Pole Low-Pass Filter OUT 4V/AMP 14V –IN A2 A1 DRIVING CHARGE REDISTRIBUTION ADCS INDUCTIVE 5V LOAD 4-TERM SHUNT GND POWER DEVICE Figure 49 is another refinement of Figure 2, including gain adjustment and low-pass filtering. +VS C 50kΩ HIGH LINE CURRENT SENSING WITH LPF AND GAIN ADJUSTMENT +IN AD8203 –IN Figure 48. Comparative Responses of 1-Pole and 2-Pole Low-Pass Filters CLAMP DIODE 301kΩ 14V f22/f1 f2 OUT 05013-023 A 1-POLE FILTER, CORNER f1, AND A 2-POLE FILTER, CORNER f2, HAVE THE SAME ATTENUATION –40log (f2/f1) AT FREQUENCY f22/f1 NC Figure 49. High Line Current Sensor Interface; Gain = ×40, Single-Pole Low-Pass Filter A power device that is either on or off controls the current in the load. The average current is proportional to the duty cycle of the input pulse and is sensed by a small value resistor. The average differential voltage across the shunt is typically 100 mV, although its peak value is higher by an amount that depends on the inductance of the load and the control frequency. The common-mode voltage, conversely, extends from roughly 1 V above ground for the on condition to about 1.5 V above the battery voltage for the off condition. The conduction of the clamping diode regulates the common-mode potential applied to the device. For example, a battery spike of 20 V may result in an applied common-mode potential of 21.5 V to the input of the devices. When driving CMOS ADCs, such as those embedded in popular microcontrollers, the charge injection (ΔQ) can cause a significant deflection in the output voltage of the AD8203. Though generally of short duration, this deflection may persist until after the sample period of the ADC has expired due to the relatively high open-loop output impedance (21 kΩ) of the AD8203. Including an R-C network in the output can significantly reduce the effect. The capacitor helps to absorb the transient charge, effectively lowering the high frequency output impedance of the AD8203. For these applications, the output signal should be taken from the midpoint of the RLAG to CLAG combination, as shown in Figure 51. Since the perturbations from the analog-to-digital converter are small, the output impedance of the AD8203 appears to be low. The transient response, therefore, has a time constant governed by the product of the two LAG components, CLAG × RLAG. For the values shown in Figure 51, this time constant is programmed at approximately 10 µs. Therefore, if samples are taken at several tens of microseconds or more, there is negligible charge stack-up. To produce a full-scale output of 4 V, a gain ×40 is used, adjustable by ±5% to absorb the tolerance in the shunt. There is sufficient headroom to allow 10% overrange (to 4.4 V). The roughly triangular voltage across the sense resistor is averaged Rev. D | Page 16 of 20 5V 4 7 +IN AD8203 RLAG 1kΩ A2 5 –IN 10kΩ CLAG 0.01µF MICROPROCESSOR A/D 10kΩ 2 Figure 51. Recommended Circuit for Driving CMOS A/D 05013-024 ATTENUATION 40dB/DECADE Data Sheet AD8203 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 8 3.20 3.00 2.80 1 4.00 (0.1574) 3.80 (0.1497) 5.15 4.90 4.65 5 4 1 5 4 1.27 (0.0500) BSC PIN 1 IDENTIFIER 0.25 (0.0098) 0.10 (0.0040) 0.65 BSC 0.95 0.85 0.75 COPLANARITY 0.10 SEATING PLANE 15° MAX 1.10 MAX 0.40 0.25 6° 0° 0.80 0.55 0.40 0.23 0.09 COMPLIANT TO JEDEC STANDARDS MO-187-AA 10-07-2009-B 0.15 0.05 COPLANARITY 0.10 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 53. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Figure 52. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD8203YRMZ AD8203YRMZ-RL AD8203YRMZ-R7 AD8203YRZ AD8203YRZ-RL AD8203YRZ-R7 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] Z = RoHS Compliant part. Rev. D | Page 17 of 20 Package Outline RM-8 RM-8 RM-8 R-8 R-8 R-8 Branding JXA JXA JXA 012407-A 3.20 3.00 2.80 AD8203 Data Sheet NOTES Rev. D | Page 18 of 20 Data Sheet AD8203 NOTES Rev. D | Page 19 of 20 AD8203 Data Sheet NOTES © 2004–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05013-0-4/13(D) Rev. D | Page 20 of 20