FEATURES
PIN CONFIGURATION
AD8220
–IN
1
8
+VS
RG
2
7
VOUT
RG
3
6
REF
+IN
4
5
–VS
TOP VIEW
(Not to Scale)
Figure 1.
10n
INPUT BIAS CURRENT (A)
1n
IBIAS
100p
10p
IOS
1p
0.1p
03579-059
Low input currents
10 pA maximum input bias current (B grade)
0.6 pA maximum input offset current (B grade)
High CMRR
100 dB CMRR (minimum), G = 10 (B grade)
80 dB CMRR (minimum) to 5 kHz, G = 1 (B grade)
Excellent ac specifications and low power
1.5 MHz bandwidth (G = 1)
14 nV/√Hz input noise (1 kHz)
Slew rate: 2 V/μs
750 μA quiescent supply current (maximum)
Versatile
MSOP package
Rail-to-rail output
Input voltage range to below negative supply rail
4 kV ESD protection
4.5 V to 36 V single supply
±2.25 V to ±18 V dual supply
Gain set with single resistor (G = 1 to 1000)
Qualified for automotive applications
03579-005
Data Sheet
JFET Input Instrumentation Amplifier with
Rail-to-Rail Output in MSOP Package
AD8220
APPLICATIONS
–50
Medical instrumentation
Precision data acquisition
Transducer interfaces
–25
0
25
50
75
100
125
150
TEMPERATURE (°C)
Figure 2. Input Bias Current and Offset Current vs. Temperature
GENERAL DESCRIPTION
The AD8220 is the first single-supply, JFET input instrumentation
amplifier available in an MSOP package. Designed to meet the
needs of high performance, portable instrumentation, the AD8220
has a minimum common-mode rejection ratio (CMRR) of 86 dB
at dc and a minimum CMRR of 80 dB at 5 kHz for G = 1. Maximum input bias current is 10 pA and typically remains below
300 pA over the entire industrial temperature range. Despite
the JFET inputs, the AD8220 typically has a noise corner of only
10 Hz.
With the proliferation of mixed-signal processing, the number
of power supplies required in each system has grown. The AD8220
is designed to alleviate this problem. The AD8220 can operate on a
±18 V dual supply, as well as on a single +5 V supply. Its railto-rail output stage maximizes dynamic range on the low
voltage supplies common in portable applications. Its ability to
run on a single 5 V supply eliminates the need to use higher
voltage, dual supplies. The AD8220 draws a maximum of 750 μA
of quiescent current, making it ideal for battery powered devices.
Rev. C
Gain is set from 1 to 1000 with a single resistor. Increasing the
gain increases the common-mode rejection. Measurements that
need higher CMRR when reading small signals benefit when
the AD8220 is set for large gains.
A reference pin allows the user to offset the output voltage. This
feature is useful when interfacing with analog-to-digital converters.
The AD8220 is available in an MSOP that takes roughly half the
board area of an SOIC. Performance for the A and B grade is
specified over the industrial temperature range of −40°C to +85°C,
and the W grade is specified over the automotive temperature
range of −40°C to +125°C.
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Tel: 781.329.4700 ©2006–2019 Analog Devices, Inc. All rights reserved.
Technical Support
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AD8220
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Power Supply Regulation and Bypassing ................................ 21
Applications ....................................................................................... 1
Input Bias Current Return Path ............................................... 21
Pin Configuration ............................................................................. 1
Input Protection ......................................................................... 21
General Description ......................................................................... 1
RF Interference ........................................................................... 22
Revision History ............................................................................... 2
Common-Mode Input Voltage Range ..................................... 22
Specifications..................................................................................... 3
Driving an ADC ......................................................................... 22
Absolute Maximum Ratings ............................................................ 8
Applications Information .............................................................. 23
ESD Caution .................................................................................. 8
AC-Coupled Instrumentation Amplifier ................................ 23
Pin Configuration and Function Descriptions ............................. 9
Differential Output .................................................................... 23
Typical Performance Characteristics ........................................... 10
Electrocardiogram Signal Conditioning ................................. 25
Theory of Operation ...................................................................... 19
Outline Dimensions ....................................................................... 26
Gain Selection ............................................................................. 20
Ordering Guide .......................................................................... 26
Layout........................................................................................... 20
Automotive Products ................................................................. 26
Reference Terminal .................................................................... 21
REVISION HISTORY
9/2019—Rev. B to Rev. C
Changes to Power Supply Parameter, Table 1 ............................... 5
Changes to Ordering Guide .......................................................... 26
5/2010—Rev. A to Rev. B
Added W Grade .................................................................. Universal
Changes to Features Section and General Description Section . 1
Changes to Specifications Section and Table 1 ............................. 3
Changes to Table 2 ............................................................................ 5
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 26
Added Automotive Products Section........................................... 26
5/2007—Rev. 0 to Rev. A
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................5
Changes to Table 3.............................................................................8
Changes to Figure 6 and Figure 7 ................................................. 10
Changes to Figure 23 and Figure 24 ............................................ 13
Changes to Theory of Operation.................................................. 19
Changes to Layout .......................................................................... 20
Changes to Ordering Guide .......................................................... 26
4/2006—Revision 0: Initial Version
Rev. C | Page 2 of 28
Data Sheet
AD8220
SPECIFICATIONS
VS+ = 15 V, VS− = −15 V, VREF = 0 V, TA = 25°C, TOPR = −40°C to +85°C for A and B grades. TOPR = −40°C to +125°C for W grade,
G = 1, RL = 2 kΩ 1, unless otherwise noted.
Table 1.
Parameter
COMMON-MODE
REJECTION RATIO (CMRR)
CMRR DC to 60 Hz with
1 kΩ Source Imbalance
G=1
G = 10
G = 100
G = 1000
CMRR at 5 kHz
G=1
G = 10
G = 100
G = 1000
NOISE
Voltage Noise, 1 kHz
Input Voltage Noise, eni
Output Voltage Noise, eno
RTI, 0.1 Hz to 10 Hz
G=1
G = 1000
Current Noise
VOLTAGE OFFSET
Input Offset, VOSI
Average TC
Output Offset, VOSO
Average TC
Offset RTI vs. Supply
(PSR)
G=1
G = 10
G = 100
G = 1000
INPUT CURRENT
Input Bias Current
Over Temperature
Input Offset Current
Over Temperature
DYNAMIC RESPONSE
Small Signal Bandwidth,
−3 dB
G=1
G = 10
G = 100
G = 1000
Test Conditions
TA for A, B grades,
TOPR for W grade
VCM = ±10 V
Min
A Grade
Typ
Max
Min
B Grade
Typ
Max
Min
W Grade
Typ
Max
Unit
78
94
94
94
86
100
100
100
77
92
92
92
dB
dB
dB
dB
74
84
84
84
80
90
90
90
72
80
80
80
dB
dB
dB
dB
VCM = ±10 V
RTI noise =
√(eni2 + (eno/G)2), TA
VIN+, VIN− = 0 V
VIN+, VIN− = 0 V
f = 1 kHz
VOS = VOSI + VOSO/G
TA
TOPR
TA
TOPR
VS = ±5 V to ±15 V,
TA for A, B grades,
TOPR for W grade
14
90
14
90
5
0.8
1
5
0.8
1
−250
−10
−750
−10
+250
+10
+750
+10
86
96
96
96
TA
TOPR
TA
TOPR
−125
−5
−500
−5
17
100
+125
+5
+500
+5
86
100
100
100
nV/√Hz
nV/√Hz
5
0.8
1
µV p-p
µV p-p
fA/√Hz
−250
−10
−750
−10
+250
+10
+750
+10
80
92
92
92
25
0.3
14
90
dB
dB
dB
dB
10
25
100
2
10
0.3
2
0.6
0.005
0.005
1500
800
120
14
1500
800
120
14
µV
µV/°C
µV
µV/°C
pA
nA
pA
nA
TA
Rev. C | Page 3 of 28
1500
800
120
14
kHz
kHz
kHz
kHz
AD8220
Parameter
Settling Time 0.01%
G=1
G = 10
G = 100
G = 1000
Settling Time 0.001%
G=1
G = 10
G = 100
G = 1000
Slew Rate
G = 1 to 100
GAIN
Gain Range
Gain Error
G=1
G = 10
G = 100
G = 1000
Gain Nonlinearity
G=1
G = 10
G = 100
G = 1000
G=1
G = 10
G = 100
Gain vs. Temperature
G=1
G > 10
INPUT
Impedance (Pin to
Ground) 2
Input Operating Voltage
Range 3
Over Temperature
OUTPUT
Output Swing
Over Temperature
Short-Circuit Current
REFERENCE INPUT
RIN
IIN
Voltage Range
Gain to Output
Data Sheet
Test Conditions
10 V step, TA
Min
A Grade
Typ
Max
Min
B Grade
Typ
Max
Min
W Grade
Typ
Max
Unit
5
4.3
8.1
58
5
4.3
8.1
58
5
4.3
8.1
58
µs
µs
µs
µs
6
4.6
9.6
74
6
4.6
9.6
74
6
4.6
9.6
74
µs
µs
µs
µs
10 V step, TA
TA
G = 1 + (49.4 kΩ/RG),
TA for A, B grades,
TOPR for W grade
2
2
2
V/µs
1
1000
1
1000
1
1000
V/V
−0.06
−0.3
−0.3
−0.3
+0.06
+0.3
+0.3
+0.3
−0.04
−0.2
−0.2
−0.2
+0.04
+0.2
+0.2
+0.2
−0.1
−0.8
−0.8
−0.8
+0.1
+0.8
+0.8
+0.8
%
%
%
%
VOUT = ±10 V
VOUT =
−10 V to +10 V, TA
RL = 10 kΩ
RL = 10 kΩ
RL = 10 kΩ
RL = 10 kΩ
RL = 2 kΩ
RL = 2 kΩ
RL = 2 kΩ
TA
10
5
30
400
10
10
50
15
10
60
500
15
15
75
10
5
30
400
10
10
50
15
10
60
500
15
15
75
10
5
30
400
10
10
50
15
10
60
500
15
15
75
ppm
ppm
ppm
ppm
ppm
ppm
ppm
3
10
−50
2
5
−50
3
10
−50
ppm/°C
ppm/°C
104||5
104||5
104||5
GΩ||pF
VS = ±2.25 V to ±18 V
for dual supplies
TOPR
−VS −
0.1
−VS −
0.1
+VS −
2
+VS −
2.1
−VS −
0.1
−VS −
0.1
+VS −
2
+VS −
2.1
−VS −
0.1
−VS −
0.1
+VS − 2
V
+VS −
2.2
V
RL = 10 kΩ, TA
TOPR
TA
TA
−14.7
−14.6
+14.7
+14.6
−14.7
−14.6
+14.7
+14.6
−14.7
−14.3
+14.7
+14.3
V
V
mA
kΩ
µA
V
V/V
V/V
15
15
40
VIN+, VIN− = 0 V
TA
40
70
+VS
−VS
15
−VS
1±
0.0001
Rev. C | Page 4 of 28
40
70
+VS
1±
0.0001
70
+VS
1±
0.0001
Data Sheet
Parameter
POWER SUPPLY
Operating Range
Quiescent Current
Over Temperature
TEMPERATURE RANGE
For Specified
Performance
AD8220
Test Conditions
Min
A Grade
Typ
Max
B Grade
Typ
Max
Min
W Grade
Typ
Max
Unit
±2.25 4
±18
750
850
±2.254
±18
750
850
±2.254
±18
750
1000
V
µA
µA
−40
+85
−40
+85
−40
+125
°C
TA
TOPR
TOPR
Min
When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ.
Differential and common-mode input impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2.
3
The AD8220 can operate up to a diode drop below the negative supply but the bias current increases sharply. The input voltage range reflects the maximum
allowable voltage where the input bias current is within the specification.
4
At this supply voltage, ensure that the input common-mode voltage is within the input voltage range specification.
1
2
VS + = 5 V, VS− = 0 V, VREF = 2.5 V, TA = 25°C, TOPR = −40°C to +85°C for A and B grades. TOPR = −40°C to +125°C for W grade, G = 1,
RL = 2 kΩ 1, unless otherwise noted.
Table 2.
Parameter
COMMON-MODE REJECTION
RATIO (CMRR)
CMRR DC to 60 Hz with
1 kΩ Source Imbalance
G=1
G = 10
G = 100
G = 1000
CMRR at 5 kHz
G=1
G = 10
G = 100
G = 1000
NOISE
Voltage Noise, 1 kHz
Input Voltage Noise, eni
Output Voltage Noise, eno
RTI, 0.1 Hz to 10 Hz
G=1
G = 1000
Current Noise
VOLTAGE OFFSET
Input Offset, VOSI
Average TC
Output Offset, VOSO
Average TC
Offset RTI vs. Supply (PSR)
G=1
G = 10
G = 100
G = 1000
Test Conditions
TA for A, B grades,
TOPR for W grade
VCM = 0 to 2.5 V
Min
A Grade
Typ
Max
Min
B Grade
Typ
Max
Min
W Grade
Typ
Max
Unit
78
94
94
94
86
100
100
100
77
92
92
92
dB
dB
dB
dB
74
84
84
84
80
90
90
90
72
80
80
80
dB
dB
dB
dB
VCM = 0 to 2.5 V
RTI noise = √(eni2 +
(eno/G)2), TA
VS = ±2.5 V
VIN+, VIN− = 0 V, VREF =
0V
VIN+, VIN− = 0 V, VREF =
0V
f = 1 kHz
VOS = VOSI + VOSO/G
TA
TOPR
TA
TOPR
TA for A, B grades,
TOPR for W grade
−300
−10
−800
−10
14
14
17
14
nV/√Hz
90
90
100
90
nV/√Hz
5
0.8
1
5
0.8
1
5
0.8
1
µV p-p
µV p-p
fA/√Hz
+300
+10
+800
+10
86
96
96
96
−200
−5
−600
−5
86
100
100
100
Rev. C | Page 5 of 28
+200
+5
+600
+5
−300
−10
−800
−10
80
92
92
92
+300
10
+800
+10
µV
µV/°C
µV
µV/°C
dB
dB
dB
dB
AD8220
Parameter
INPUT CURRENT
Input Bias Current
Over Temperature
Input Offset Current
Over Temperature
DYNAMIC RESPONSE
Small Signal Bandwidth,
−3 dB
G=1
G = 10
G = 100
G = 1000
Settling Time 0.01%
G=1
G = 10
G = 100
G = 1000
Settling Time 0.001%
G=1
G = 10
G = 100
G = 1000
Slew Rate
G = 1 to 100
GAIN
Gain Range
Gain Error
G=1
G = 10
G = 100
G = 1000
Nonlinearity
G=1
G = 10
G = 100
G = 1000
G=1
G = 10
G = 100
Gain vs. Temperature
G=1
G > 10
INPUT
Impedance (Pin to
Ground) 2
Input Voltage Range 3
Over Temperature
Data Sheet
Test Conditions
Min
TA
TOPR
TA
TOPR
TA
Min
B Grade
Typ
Max
25
Min
W Grade
Typ
Max
10
0.3
25
100
2
10
0.3
2
TA
3 V step
4 V step
4 V step
4 V step
TA
3 V step
4 V step
4 V step
4 V step
TA
A Grade
Typ
Max
0.6
Unit
pA
nA
pA
nA
0.005
0.005
1500
800
120
14
1500
800
120
14
1500
800
120
14
kHz
kHz
kHz
kHz
2.5
2.5
7.5
30
2.5
2.5
7.5
30
2.5
2.5
7.5
30
µs
µs
µs
µs
3.5
3.5
8.5
37
3.5
3.5
8.5
37
3.5
3.5
8.5
37
µs
µs
µs
µs
2
2
2
V/µs
G = 1 + (49.4 kΩ/RG),
TA for A, B grades,
TOPR for W grade
1
1000
1
1000
1
1000
V/V
−0.06
−0.3
−0.3
−0.3
+0.06
+0.3
+0.3
+0.3
−0.04
−0.2
−0.2
−0.2
+0.04
+0.2
+0.2
+0.2
−0.1
−0.8
−0.8
−0.8
+0.1
+0.8
+0.8
+0.8
%
%
%
%
50
50
75
750
50
50
75
ppm
ppm
ppm
ppm
ppm
ppm
ppm
10
−50
ppm/°C
ppm/°C
VOUT = 0.3 V to 2.9 V for
G = 1, VOUT = 0.3 V to
3.8 V for G > 1
VOUT = 0.3 V to 2.9 V for
G = 1, VOUT = 0.3 V to
3.8 V for G > 1, TA
RL = 10 kΩ
RL = 10 kΩ
RL = 10 kΩ
RL = 10 kΩ
RL = 2 kΩ
RL = 2 kΩ
RL = 2 kΩ
TA
35
35
50
650
35
35
50
50
50
75
750
50
50
75
35
35
50
650
35
35
50
50
50
75
750
50
50
75
3
10
−50
2
5
−50
104||6
TA
−0.1
TOPR
−0.1
3
104||6
+VS −
2
+VS −
2.1
Rev. C | Page 6 of 28
−0.1
−0.1
104||6
+VS −
2
+VS −
2.1
GΩ||pF
V
−0.1
+VS −
2.2
V
Data Sheet
Parameter
OUTPUT
Output Swing
Over Temperature
Short-Circuit Current
REFERENCE INPUT
RIN
IIN
Voltage Range
Gain to Output
POWER SUPPLY
Operating Range
Quiescent Current
Over Temperature
TEMPERATURE RANGE
TOPR, For Specified
Performance
AD8220
Test Conditions
Min
A Grade
Typ
Max
Min
B Grade
Typ
Max
Min
W Grade
Typ
Max
RL = 10 kΩ
TOPR
0.15
0.2
4.85
4.80
0.15
0.2
4.85
4.80
0.15
0.3
4.85
4.70
15
15
15
Unit
V
V
mA
TA
40
VIN+, VIN− = 0 V
−VS
TA
40
70
+VS
−VS
1±
0.0001
−VS
1±
0.0001
70
+VS
kΩ
µA
V
V/V
1±
0.0001
4.5
36
750
850
4.5
36
750
850
4.5
36
750
1000
V
µA
µA
−40
+85
−40
+85
−40
+125
°C
TA
TOPR
TOPR
40
70
+VS
When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ.
Differential and common-mode impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2.
3
The AD8220 can operate up to a diode drop below the negative supply but the bias current increases sharply. The input voltage range reflects the maximum
allowable voltage where the input bias current is within the specification.
1
2
Rev. C | Page 7 of 28
AD8220
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Rating
±18 V
See Figure 3
Indefinite 1
±Vs
±Vs
−65°C to +125°C
−40°C to +125°C
300°C
140°C
135°C/W
140°C
4 kV
1 kV
0.4 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the MSOP on a 4-layer
JEDEC standard board. θJA values are approximations.
2.00
Assumes the load is referenced to midsupply.
2
Temperature for specified performance is −40°C to +85°C. For performance
to 125°C, see the Typical Performance Characteristics section.
1
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
–40
03579-045
Parameter
Supply Voltage
Power Dissipation
Output Short-Circuit Current
Input Voltage (Common Mode)
Differential Input Voltage
Storage Temperature Range
Operating Temperature Range 2
Lead Temperature (Soldering 10 sec)
Junction Temperature
θJA (4-Layer JEDEC Standard Board)
Package Glass Transition Temperature
ESD (Human Body Model)
ESD (Charge Device Model)
ESD (Machine Model)
MAXIMUM POWER DISSIPATION (W)
Table 3.
–20
0
20
40
60
80
100
120
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
Rev. C | Page 8 of 28
Data Sheet
AD8220
–IN
1
RG
RG
+IN
AD8220
8
+VS
2
7
VOUT
3
6
REF
4
5
–VS
TOP VIEW
(Not to Scale)
03579-005
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2, 3
4
5
6
7
8
Mnemonic
−IN
RG
+IN
−VS
REF
VOUT
+VS
Description
Negative Input Terminal (True Differential Input)
Gain Setting Terminals (Place Resistor Across the RG Pins)
Positive Input Terminal (True Differential Input)
Negative Power Supply Terminal
Reference Voltage Terminal (Drive This Terminal with a Low Impedance Voltage Source to Level-Shift the Output)
Output Terminal
Positive Power Supply Terminal
Rev. C | Page 9 of 28
AD8220
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1600
1200
1400
1000
NUMBER OF UNITS
NUMBER OF UNITS
1200
800
600
400
1000
800
600
400
03579-060
200
–40
–20
0
20
200
03579-063
0
0
40
0
1
2
CMRR (µV/V)
3
4
5
IBIAS (pA)
Figure 5. Typical Distribution of CMRR (G = 1)
Figure 8. Typical Distribution of Input Bias Current
1200
1000
800
NUMBER OF UNITS
600
400
200
600
400
200
03579-061
0
800
–200
–100
0
100
0
200
03579-064
NUMBER OF UNITS
1000
–0.2
–0.1
0
0.1
0.2
IOS (pA)
VOSI (µV)
Figure 9. Typical Distribution of Input Offset Current
Figure 6. Typical Distribution of Input Offset Voltage
1000
600
400
200
0
–1000
–500
0
500
1000
VOSO (µV)
GAIN = 100 BANDWIDTH ROLL-OFF
100
GAIN = 1
GAIN = 10
GAIN = 100/GAIN = 1000
10
GAIN = 1000 BANDWIDTH ROLL-OFF
1
03579-042
VOLTAGE NOISE RTI (nV/ Hz)
800
03579-062
NUMBER OF UNITS
1000
1
10
100
1k
10k
FREQUENCY (Hz)
Figure 10. Voltage Spectral Density vs. Frequency
Figure 7. Typical Distribution of Output Offset Voltage
Rev. C | Page 10 of 28
100k
Data Sheet
AD8220
XX
150
GAIN = 1000
130
PSRR (dB)
XXX (X)
BANDWIDTH
LIMITED
GAIN = 100
110
GAIN = 10
90
GAIN = 1
70
50
XX
XX
30
10
XX
03579-035
1s/DIV
03579-024
5µV/DIV
1
10
100
XXX (X)
1k
10k
1M
100k
FREQUENCY (Hz)
Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1)
Figure 14. Positive PSRR vs. Frequency, RTI
XX
150
130
XXX (X)
PSRR (dB)
110
GAIN = 1000
90
GAIN = 1
70
GAIN = 10
50
GAIN = 100
10
XX
03579-040
1s/DIV
03579-025
1µV/DIV
XX
XX
30
1
10
100
XXX (X)
1k
10k
1M
100k
FREQUENCY (Hz)
Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000)
Figure 15. Negative PSRR vs. Frequency, RTI
0.3
8
5
4
3
2
0.1
7
0
5
–15.1V
1
0
0.1
1
10
100
1k
–0.1
–0.2
3
–5.1V
INPUT BIAS
CURRENT ±15
INPUT BIAS
CURRENT ±5
1
03579-009
Δ VOSI (µV)
6
0.2
INPUT OFFSET
CURRENT ±5
–0.3
–0.4
–1
–16
–12
–8
–4
0
4
8
12
16
COMMON-MODE VOLTAGE (V)
TIME (s)
Figure 13. Change in Input Offset Voltage vs. Warmup Time
Figure 16. Input Bias Current and Input Offset Current vs.
Common-Mode Voltage
Rev. C | Page 11 of 28
–0.5
03579-050
INPUT BIAS CURRENT (pA)
7
INPUT OFFSET CURRENT (pA)
INPUT OFFSET
CURRENT ±15
9
AD8220
Data Sheet
160
140
IBIAS
120
100p
10p
IOS
1p
0
25
50
75
100
125
BANDWIDTH
LIMITED
GAIN = 1
GAIN = 10
60
03579-059
–25
GAIN = 100
100
80
0.1p
–50
GAIN = 1000
40
150
03579-051
1n
CMRR (dB)
INPUT BIAS CURRENT (A)
10n
1
10
100
TEMPERATURE (°C)
1k
100k
10k
FREQUENCY (Hz)
Figure 17. Input Bias Current and Offset Current vs. Temperature,
VS = ±15 V, VREF = 0 V
Figure 20. CMRR vs. Frequency, 1 kΩ Source Imbalance
10
8
10n
6
4
IBIAS
Δ CMRR (μV/V)
100p
10p
IOS
1p
2
0
–2
–4
03579-065
–50
–25
0
25
50
75
100
125
–8
–10
–50
150
TEMPERATURE (°C)
10
30
50
70
90
110
130
70
60
GAIN = 1000
GAIN = 1000
50
40
GAIN = 100
GAIN = 100
GAIN = 10
GAIN (dB)
30
BANDWIDTH
LIMITED
100
GAIN = 1
20
GAIN = 10
10
0
80
GAIN = 1
–10
60
40
10
–20
03579-023
CMRR (dB)
–10
Figure 21. Change in CMRR vs. Temperature, G = 1
160
120
–30
TEMPERATURE (°C)
Figure 18. Input Bias Current and Offset Current vs. Temperature,
VS = +5 V, VREF = 2.5 V
140
03579-034
–6
0.1p
100
1k
10k
100k
FREQUENCY (Hz)
03579-022
CURRENT (A)
1n
–30
–40
100
1k
10k
100k
FREQUENCY (Hz)
Figure 19. CMRR vs. Frequency
Figure 22. Gain vs. Frequency
Rev. C | Page 12 of 28
1M
10M
VS = ±15V
–10
–6
–8
RLOAD = 10kΩ
–4
–2
0
2
4
6
8
03579-029
XXX
RLOAD = 10kΩ
NONLINEARITY (500ppm/DIV)
RLOAD = 2kΩ
RLOAD = 2kΩ
03579-026
XXX
AD8220
NONLINEARITY (5ppm/DIV)
Data Sheet
VS = ±15V
–10
10
–8
–6
–4
–2
0
2
4
6
8
10
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 23. Gain Nonlinearity, G = 1
Figure 26. Gain Nonlinearity, G = 1000
RLOAD = 10kΩ
VS = ±15V
–10
–6
–8
–4
–2
0
2
4
6
8
+13V
12
±15V SUPPLIES
6
–14.8V, +5.5V
0
+14.9V, +5.5V
+3V
+4.95V, +0.6V
–4.8V, +0.6V
±5V SUPPLIES
+4.95V, –3.3V
–4.8V, –3.3V
–6
–14.8V, –8.3V
+14.9V, –8.3V
–5.3V
–12
03579-037
INPUT COMMON-MODE VOLTAGE (V)
RLOAD = 2kΩ
03579-027
XXX
NONLINEARITY (5ppm/DIV)
18
–15.3V
–18
–16
10
–12
–8
–4
0
4
8
12
16
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 24. Gain Nonlinearity, G = 10
Figure 27. Input Common-Mode Voltage Range vs. Output Voltage,
G = 1, VREF = 0 V
RLOAD = 10kΩ
VS = ±15V
–10
–8
–6
–4
–2
0
2
4
6
8
2
+4.9V, +1.7V
+0.1V, +1.7V
+5V SINGLE SUPPLY,
VREF = +2.5V
1
+4.9V, +0.5V
+0.1V, +0.5V
0
–0.3V
–1
–1
10
+3V
3
0
1
2
03579-036
INPUT COMMON-MODE VOLTAGE (V)
RLOAD = 2kΩ
03579-028
XXX
NONLINEARITY (50ppm/DIV)
4
3
4
5
6
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 28. Input Common-Mode Voltage Range vs. Output Voltage,
G = 1, VS = +5 V, VREF = 2.5 V
Figure 25. Gain Nonlinearity, G = 100
Rev. C | Page 13 of 28
AD8220
Data Sheet
VS+
–1
+3V
–14.9V, +5.4V
+14.9V, +5.4V
–4.9V, +0.4V
0
+4.9V, +0.5V
±5V SUPPLIES
–4.9V, –4.1V
+4.9V, –4.1V
–6
–5.3V
–14.8V, –9V
+14.9V, –9V
–12
–15.3V
–18
–16
–12
–8
–4
0
4
8
12
–40°C
–2
–3
+125°C
–4
+4
+3
+2
+125°C
+1
VS–
16
2
4
6
12
14
–40°C
16
18
VS+
4
–0.2
2
+0.1V, +1.7V
+4.9V, +1.7V
+5V SINGLE SUPPLY,
VREF = +2.5V
1
0
+0.1V, –0.5V
–1
–1
0
1
+4.9V, –0.5V
–0.3V
2
3
4
5
+125°C
–0.4
+0.4
+125°C
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
03579-054
3
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGE
+3V
03579-038
+0.2
VS –
6
2
4
6
8
10
12
14
16
18
DUAL SUPPLY VOLTAGE (±V)
OUTPUT VOLTAGE (V)
Figure 33. Output Voltage Swing vs. Supply Voltage, RLOAD = 10 kΩ, G = 10,
VREF = 0 V
Figure 30. Input Common-Mode Voltage Range vs. Output Voltage,
G = 100, VS = +5 V, VREF = 2.5 V
15
VS+
–40°C
10
+125°C
OUTPUT VOLTAGE SWING (V)
–1
–2
+25°C
+85°C
NOTES
1. THE AD8220 CAN OPERATE UP TO A VBE BELOW
THE NEGATIVE SUPPLY, BUT THE BIAS CURRENT
WILL INCREASE SHARPLY.
+1
–40°C
+25°C
+85°C
+125°C
03579-052
2
4
6
8
10
12
14
16
+125°C
0
+85°C
+25°C
–40°C
1k
10k
RLOAD (Ω)
SUPPLY VOLTAGE (V)
Figure 31. Input Voltage Limit vs. Supply Voltage, G = 1, VREF =0 V
+125°C
–5
–15
100
18
+85°C
5
–10
VS–
–40°C
+25°C
03579-055
INPUT COMMON-MODE VOLTAGE (V)
10
+25°C
Figure 32. Output Voltage Swing vs. Supply Voltage, RLOAD = 2 kΩ, G = 10,
VREF = 0 V
Figure 29. Input Common-Mode Voltage Range vs. Output Voltage,
G = 100, VREF = 0 V
INPUT VOLTAGE LIMIT (V)
8
+85°C
DUAL SUPPLY VOLTAGE (±V)
OUTPUT VOLTAGE (V)
–1
+85°C
+25°C
03579-053
6
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGE
+13V
±15V SUPPLIES
12
03579-039
INPUT COMMON-MODE VOLTAGE (V)
18
Figure 34. Output Voltage Swing vs. Load Resistance VS = ±15 V, VREF = 0 V
Rev. C | Page 14 of 28
Data Sheet
AD8220
XX
5
+25°C
4
47pF
NO LOAD
+85°C
100pF
+125°C
XXX (X)
3
+125°C
1
+25°C
+85°C
–40°C
0
100
20mV/DIV
XX
XX
10k
1k
03579-018
2
03579-056
OUTPUT VOLTAGE SWING (V)
–40°C
5µs/DIV
XX
XXX (X)
RLOAD (Ω)
Figure 35. Output Voltage Swing vs. Load Resistance VS = +5 V, VREF = 2.5 V
Figure 38. Small Signal Pulse Response for Various Capacitive Loads,
VS = ±15 V, VREF = 0 V
VS+
XX
–40°C
+125°C
–2
47pF
100pF
NO LOAD
+85°C
+25°C
–3
XXX (X)
–4
+4
+3
+125°C
+85°C
+25°C
+1
VS–
–40°C
0
2
4
6
8
10
12
14
20mV/DIV
XX
XX
16
03579-019
+2
03579-057
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
–1
5µs/DIV
XX
IOUT (mA)
XXX (X)
Figure 36. Output Voltage Swing vs. Output Current, VS = ±15 V, VREF = 0 V
Figure 39. Small Signal Pulse Response for Various Capacitive Loads,
VS = 5 V, VREF = 2.5 V
+85°C
+25°C
+125°C
–2
+2
+125°C
+1
+85°C
+25°C
–40°C
VS–
0
2
4
6
8
10
12
14
30
25
GAIN = 10, 100, 1000
GAIN = 1
20
15
10
5
0
100
16
IOUT (mA)
03579-021
–1
OUTPUT VOLTAGE SWING (V p-p)
35
03579-058
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
VS+
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 37. Output Voltage Swing vs. Output Current, VS = 5 V, VREF = 2.5 V
Figure 40. Output Voltage Swing vs. Large Signal Frequency Response
Rev. C | Page 15 of 28
AD8220
Data Sheet
XX
XX
5V/DIV
XXX (X)
5µs TO 0.01%
6µs TO 0.001%
0.002%/DIV
03579-046
0.002%/DIV
20µs/DIV
XX
XX
58μs TO 0.01%
74μs TO 0.001%
03579-049
XXX (X)
5V/DIV
200µs/DIV
XX
XX
XX
XX
XXX (X)
XXX (X)
Figure 41. Large Signal Pulse Response and Settle Time, G = 1,
RLOAD = 10 kΩ, VS = ±15 V, VREF = 0 V
Figure 44. Large Signal Pulse Response and Settle Time, G = 1000,
RLOAD = 10 kΩ, VS = ±15 V, VREF = 0 V
XX
XXX
XXX (X)
5V/DIV
4.3μs TO 0.01%
4.6μs TO 0.001%
20mV/DIV
20µs/DIV
XX
XX
03579-016
03579-047
0.002%/DIV
XX
4µs/DIV
XXX (X)
XXX
Figure 42. Large Signal Pulse Response and Settle Time, G = 10,
RLOAD = 10 kΩ, VS = ±15 V, VREF = 0 V
Figure 45. Small Signal Pulse Response, G = 1, RLOAD = 2 kΩ, CLOAD = 100 pF,
VS = ±15 V, VREF = 0 V
XX
XXX
XXX (X)
5V/DIV
8.1μs TO 0.01%
9.6μs TO 0.001%
20mV/DIV
20µs/DIV
XX
XX
03579-014
03579-048
0.002%/DIV
XX
4µs/DIV
XXX (X)
Figure 43. Large Signal Pulse Response and Settle Time, G = 100,
RLOAD = 10 kΩ, VS = ±15 V, VREF = 0 V
XXX
Figure 46. Small Signal Pulse Response, G = 10, RLOAD = 2 kΩ, CLOAD = 100 pF,
VS = ±15 V, VREF = 0 V
Rev. C | Page 16 of 28
XXX
AD8220
XXX
Data Sheet
20mV/DIV
03579-015
03579-012
20mV/DIV
4µs/DIV
4µs/DIV
XXX
XXX
Figure 50. Small Signal Pulse Response, G = 10, RLOAD = 2 kΩ, CLOAD = 100 pF,
VS = 5 V, VREF = 2.5 V
XXX
XXX
Figure 47. Small Signal Pulse Response, G = 100, RLOAD = 2 kΩ, CLOAD = 100 pF,
VS = ±15 V, VREF =0 V
20mV/DIV
03579-010
03579-013
20mV/DIV
4µs/DIV
40µs/DIV
XXX
XXX
Figure 51. Small Signal Pulse Response, G = 100, RLOAD = 2 kΩ, CLOAD = 100 pF,
VS = 5 V, VREF = 2.5 V
XXX
XXX
Figure 48. Small Signal Pulse Response, G = 1000, RLOAD = 2 kΩ,
CLOAD = 100 pF, VS = ±15 V, VREF = 0 V
03579-017
03579-011
20mV/DIV
20mV/DIV
40µs/DIV
4µs/DIV
XXX
XXX
Figure 49. Small Signal Pulse Response, G = 1, RLOAD = 2 kΩ, CLOAD = 100 pF,
VS = 5 V, VREF = 2.5 V
Rev. C | Page 17 of 28
Figure 52. Small Signal Pulse Response, G = 1000, RLOAD = 2 kΩ,
CLOAD = 100 pF, VS = 5 V, VREF = 2.5 V
AD8220
Data Sheet
10
SETTLED TO 0.001%
SETTLED TO 0.01%
5
0
0
5
10
15
SETTLED TO 0.001%
10
SETTLED TO 0.01%
1
20
OUTPUT VOLTAGE STEP SIZE (V)
03579-041
SETTLING TIME (µs)
100
03579-043
SETTLING TIME (µs)
15
1
10
100
1000
GAIN (V/V)
Figure 53. Settling Time vs. Output Voltage Step Size (G = 1) ±15 V, VREF = 0 V
Figure 54. Settling Time vs. Gain for a 10 V Step, VS = ±15 V, VREF = 0 V
Rev. C | Page 18 of 28
Data Sheet
AD8220
THEORY OF OPERATION
+VS
+VS
RG
NODE A
R1
24.7kΩ
+VS
+VS
NODE B
–VS
20kΩ
R2
24.7kΩ
–VS
NODE F
+VS
20kΩ
OUTPUT
20kΩ
+VS
+VS
NODE C
J1 Q1
+IN
–VS
A3
VPINCH
NODE E
NODE D
C1
C2
A1
A2
Q2
–IN
J2
VPINCH
+VS
–VS
REF
20kΩ
–VS
–VS
VB
I
03579-006
I
–VS
Figure 55. Simplified Schematic
Using JFET transistors, the AD8220 offers an extremely high
input impedance, extremely low bias currents of 10 pA
maximum, a low offset current of 0.6 pA maximum, and no
input bias current noise. In addition, input offset is less than
125 μV and drift is less than 5 μV/°C. Ease of use and robustness
were considered. A common problem for instrumentation
amplifiers is that at high gains, when the input is overdriven,1
an excessive milliampere input bias current can result and the
output can undergo phase reversal. The AD8220 has none of
these problems; its input bias current is limited to less than
10 μA, and the output does not phase reverse under overdrive
fault conditions.
The AD8220 has extremely low load-induced nonlinearity. All
amplifiers that comprise the AD8220 have rail-to-rail output
capability for enhanced dynamic range. The input of the AD8220
can amplify signals with wide common-mode voltages even
slightly lower than the negative supply rail. The AD8220 operates
over a wide supply voltage range. It can operate from either a
single +4.5 V to +36 V supply or a dual ±2.25 V to ±18 V. The
transfer function of the AD8220 is
G 1
49.4 kΩ
RG
Users can easily and accurately set the gain using a single,
standard resistor. Because the input amplifiers employ a current
feedback architecture, the AD8220 gain-bandwidth product
increases with gain, resulting in a system that does not suffer as
much bandwidth loss as voltage feedback architectures at higher
gains. A unique pinout enables the AD8220 to meet a CMRR
specification of 80 dB through 5 kHz (G = 1). The balanced
pinout, shown in Figure 56, reduces parasitics that adversely
affect CMRR performance. In addition, the new pinout
simplifies board layout because associated traces are grouped
together. For example, the gain setting resistor pins are adjacent
to the inputs, and the reference pin is next to the output.
1
Overdriving the input at high gains refers to when the input signal is within
the supply voltages but the amplifier cannot output the gained signal. For
example, at a gain of 100, driving the amplifier with 10 V on ±15 V constitutes
overdriving the inputs since the amplifier cannot output 100 V.
Rev. C | Page 19 of 28
AD8220
–IN
1
8
+VS
RG
2
7
VOUT
RG
3
6
REF
+IN
4
5
–VS
TOP VIEW
(Not to Scale)
Figure 56. Pin Configuration
03579-005
The AD8220 is a JFET input, monolithic instrumentation amplifier
based on the classic 3-op amp topology (see Figure 55). Input
Transistor J1 and Input Transistor J2 are biased at a fixed current so
that any input signal forces the output voltages of A1 and A2 to
change accordingly; the input signal creates a current through RG
that flows in R1 and R2 such that the outputs of A1 and A2 provide
the correct, gained signal. Topologically, J1, A1, and R1 and J2, A2,
and R2 can be viewed as precision current feedback amplifiers that
have a gain bandwidth of 1.5 MHz. The common-mode voltage
and amplified differential signal from A1 and A2 are applied to a
difference amplifier that rejects the common-mode voltage but
amplifies the differential signal. The difference amplifier employs
20 kΩ laser-trimmed resistors that result in an in-amp with gain
error less than 0.04%. New trim techniques were developed to
ensure that CMRR exceeds 86 dB (G = 1).
AD8220
Data Sheet
GAIN SELECTION
Placing a resistor across the RG terminals sets the AD8220 gain,
which can be calculated by referring to Table 5 or by using the
gain equation
49.4 kΩ
G 1
Common-Mode Rejection Ratio (CMRR)
Table 5. Gains Achieved Using 1% Resistors
1% Standard Table Value of RG (Ω)
49.9 k
12.4 k
5.49 k
2.61 k
1.00 k
499
249
100
49.9
The AD8220 has high CMRR over frequency giving it greater
immunity to disturbances, such as line noise and its associated
harmonics, in contrast to typical in-amps whose CMRR falls off
around 200 Hz. These in-amps often need common-mode
filters at the inputs to compensate for this shortcoming. The
AD8220 is able to reject CMRR over a greater frequency range,
reducing the need for input common-mode filtering.
Calculated Gain
1.990
4.984
9.998
19.93
50.40
100.0
199.4
495.0
991.0
A well-implemented layout helps to maintain the high CMRR
over frequency of the AD8220. Input source impedance and
capacitance should be closely matched. In addition, source
resistance and capacitance should be placed as close to the
inputs as possible.
The AD8220 defaults to G = 1 when no gain resistor is used.
Gain accuracy is determined by the absolute tolerance of RG.
The TC of the external gain resistor increases the gain drift of
the instrumentation amplifier. Gain error and gain drift are kept
to a minimum when the gain resistor is not used.
LAYOUT
The output voltage of the AD8220 is developed with respect to
the potential on the reference terminal. Care should be taken to
tie REF to the appropriate local ground (see Figure 59).
In mixed-signal environments, low level analog signals need to
be isolated from the noisy digital environment. Many ADCs
have separate analog and digital ground pins. Although it is
convenient to tie both grounds to a single ground plane, the
current traveling through the ground wires and PC board can
cause a large error. Therefore, separate analog and digital
ground returns should be used to minimize the current flow
from sensitive points to the system ground.
03579-101
Careful board layout maximizes system performance. In
applications that need to take advantage of the low input bias
current of the AD8220, avoid placing metal under the input path
to minimize leakage current. To maintain high CMRR over
frequency, lay out the input traces symmetrically and lay out the
traces of the RG resistor symmetrically. Ensure that the traces
maintain resistive and capacitive balance; this holds for additional
PCB metal layers under the input and RG pins. Traces from the
Grounding
03579-102
RG
gain setting resistor to the RG pins should be kept as short as
possible to minimize parasitic inductance. An example layout is
shown in Figure 57 and Figure 58. To ensure the most accurate
output, the trace from the REF pin should either be connected to
the AD8220 local ground (see Figure 59) or connected to a
voltage that is referenced to the AD8220 local ground.
Figure 57. Example Layout—Top Layer of the AD8220 Evaluation Board
Figure 58. Example Layout—Bottom Layer of the AD8220 Evaluation Board
Rev. C | Page 20 of 28
Data Sheet
AD8220
REFERENCE TERMINAL
INPUT BIAS CURRENT RETURN PATH
The reference terminal, REF, is at one end of a 20 kΩ resistor
(see Figure 55). The output of the instrumentation amplifier is
referenced to the voltage on the REF terminal; this is useful
when the output signal needs to be offset to voltages other than
common. For example, a voltage source can be tied to the REF
pin to level-shift the output so that the AD8220 can interface
with an ADC. The allowable reference voltage range is a function of
the gain, common-mode input, and supply voltages. The REF
pin should not exceed either +VS or −VS by more than 0.5 V.
The AD8220 input bias current is extremely small at less than
10 pA. Nonetheless, the input bias current must have a return
path to common. When the source, such as a transformer,
cannot provide a return current path, one should be created
(see Figure 60).
+VS
AD8220
For best performance, especially in cases where the output is
not measured with respect to the REF terminal, source impedance
to the REF terminal should be kept low, because parasitic
resistance can adversely affect CMRR and gain accuracy.
REF
POWER SUPPLY REGULATION AND BYPASSING
–VS
TRANSFORMER
The AD8220 has high PSRR. However, for optimal
performance, a stable dc voltage should be used to power
the instrumentation amplifier. Noise on the supply pins can
adversely affect performance. As in all linear circuits, bypass
capacitors must be used to decouple the amplifier.
+VS
C
A 0.1 μF capacitor should be placed close to each supply pin.
A 10 μF tantalum capacitor can be used further away from the
part (see Figure 59). In most cases, it can be shared by other
precision integrated circuits.
R
1
fHIGH-PASS = 2πRC
AD8220
C
+VS
REF
0.1µF
–VS
10µF
AC-COUPLED
03579-002
R
Figure 60. Creating an IBIAS Path
+IN
INPUT PROTECTION
VOUT
AD8220
LOAD
0.1µF
–VS
10µF
03579-001
REF
–IN
Figure 59. Supply Decoupling, REF and Output Referred to Ground
All terminals of the AD8220 are protected against ESD.
(ESD protection is guaranteed to 4 kV, human body model.) In
addition, the input structure allows for dc overload conditions
a diode drop above the positive supply and a diode drop below
the negative supply. Voltages beyond a diode drop of the supplies
cause the ESD diodes to conduct and enable current to flow
through the diode. Therefore, an external resistor should be
used in series with each of the inputs to limit current for
voltages above +Vs. In either scenario, the AD8220 safely
handles a continuous 6 mA current at room temperature.
For applications where the AD8220 encounters extreme
overload voltages, as in cardiac defibrillators, external series
resistors and low leakage diode clamps, such as BAV199Ls,
FJH1100s, or SP720s, should be used.
Rev. C | Page 21 of 28
AD8220
Data Sheet
+15V
RF INTERFERENCE
FilterFreq DIFF
+IN
4.02kΩ
CD
R
REF
10µF
–15V
Figure 62. RFI Suppression
COMMON-MODE INPUT VOLTAGE RANGE
The common-mode input voltage range is a function of the
input range and the outputs of Internal Amplifier A1, Internal
Amplifier A2, and Internal Amplifier A3, the reference voltage,
and the gain. Figure 27 to Figure 30 show common-mode
voltage ranges for various supply voltages and gains.
10µF
DRIVING AN ADC
CG
AD8220
–VS
CG
–VS
VOUT
An instrumentation amplifier is often used in front of an ADC
to provide CMRR and additional conditioning, such as a voltage
level shift and gain (see Figure 63). In this example, a 2.7 nF
capacitor and a 1 kΩ resistor create an antialiasing filter for the
AD7685. The 2.7 nF capacitor also serves to store and deliver
the necessary charge to the switched capacitor input of the
ADC. The 1 kΩ series resistor reduces the burden of the 2.7 nF
load from the amplifier. However, large source impedance in
front of the ADC can degrade THD.
REF
10µF
–15V
03579-030
0.1µF
Figure 61. RFI Filtering Without External Capacitors
To eliminate high frequency common-mode signals while using
smaller source resistors, a low-pass RC network can be placed at
the input of the instrumentation amplifier (see Figure 62). The
filter limits the input signal bandwidth according to the following
relationship:
FilterFreq DIFF
1nF
0.1µF
+IN
–IN
–IN
CC
0.1µF
R
VOUT
AD8220
10nF
4.02kΩ
1
2πRCG
R
1nF
R
1
2πRCG
+15V
FilterFreqCM
CC
10µF
The example shown in Figure 63 is for sub-60 kHz applications.
For higher bandwidth applications where THD is important,
the series resistor needs to be small. At worst, a small series
resistor can load the AD8220, potentially causing the output to
overshoot or ring. In such cases, a buffer amplifier, such as the
AD8615, should be used after the AD8220 to drive the ADC.
+5V
1
2πR(2 CD CC CG )
10µF
0.1µF
ADR435
+5V
1
2πR(CC CG )
4.7µF
+IN
±50mV
Mismatched CC capacitors result in mismatched low-pass filters.
The imbalance causes the AD8220 to treat what would have
been a common-mode signal as a differential signal. To reduce
the effect of mismatched external CC capacitors, select a value of
CD greater than 10 times CC. This sets the differential filter
frequency lower than the common-mode frequency.
Rev. C | Page 22 of 28
1kΩ
AD8220
1.07kΩ
REF
2.7nF
AD7685
–IN
+2.5V
03579-033
FilterFreqCM
0.1µF
03579-003
RF rectification is often a problem in applications where there are
large RF signals. The problem appears as a small dc offset voltage.
The AD8220 by its nature has a 5 pF gate capacitance, CG, at its
inputs. Matched series resistors form a natural low-pass filter that
reduces rectification at high frequency (see Figure 61). The
relationship between external, matched series resistors and the
internal gate capacitance is expressed as follows:
Figure 63. Driving an ADC in a Low Frequency Application
Data Sheet
AD8220
APPLICATIONS INFORMATION
AC-COUPLED INSTRUMENTATION AMPLIFIER
DIFFERENTIAL OUTPUT
Measuring small signals that are in the noise or offset of the
amplifier can be a challenge. Figure 64 shows a circuit that
can improve the resolution of small ac signals. The large gain
reduces the referred input noise of the amplifier to 14 nV/√Hz.
Therefore, smaller signals can be measured because the noise
floor is lower. DC offsets that would have been gained by 100
are eliminated from the AD8220 output by the integrator
feedback network.
In certain applications, it is necessary to create a differential
signal. New high resolution ADCs often require a differential
input. In other cases, transmission over a long distance can
require differential processing for better immunity to
interference.
At low frequencies, the OP1177 forces the AD8220 output to
0 V. Once a signal exceeds fHIGH-PASS, the AD8220 outputs the
amplified input signal.
+VS
When using this circuit to drive a differential ADC, VREF can be
set using a resistor divider from the reference of the ADC to
make the output ratiometric with the ADC as shown in Figure 66.
0.1µF
+IN
R
499Ω
Figure 65 shows how to configure the AD8220 to output a
differential signal. An OP1177 op amp is used to create a
differential voltage. Errors from the op amp are common to
both outputs and are thus common mode. Likewise, errors from
using mismatched resistors cause a common-mode dc offset
error. Such errors are rejected in differential signal processing
by differential input ADCs or instrumentation amplifiers.
fHIGH-PASS =
1
2πRC
AD8220
R
15.8kΩ
REF
C
–IN
1µF
0.1µF
+VS
0.1µF
–VS
OP1177
–VS
10µF
0.1µF
–VS
VREF
03579-004
+VS
10µF
Figure 64. AC-Coupled Circuit
Rev. C | Page 23 of 28
AD8220
Data Sheet
+15V
AMPLITUDE
0.1µF
+5V
TIME
–5V
+IN
VOUTA = +VIN + VREF
2
AD8220
±5V
AMPLITUDE
+5.0V
+2.5V
+0V
REF
4.99kΩ
–IN
TIME
0.1µF
–15V
–15V
OP1177
+15V
4.99kΩ
0.1µF
0.1µF
10µF
AMPLITUDE
+5.0V
+2.5V
+0V
VREF
2.5V
TIME
03579-008
+5V
VOUTB = –VIN + VREF
2
Figure 65. Differential Output with Level Shift
+15V
0.1µF
+IN
VOUTA = +VIN + VREF
2
AD8220
±5V
TO 0V TO +5V ADC
REF
4.99kΩ
–IN
VREF
2.5V
0.1µF
+5V
10µF
–15V
–15V
+5V FROM REFERENCE
+5V FROM REFERENCE
4.99kΩ
0.1µF
OP1177
4.99kΩ
+15V
+AIN
10nF
4.99kΩ
REF
–AIN
0.1µF
TO 0V TO +5V ADC
VOUTB = –VIN + VREF
2
Figure 66. Configuring the AD8220 to Output A Ratiometric, Differential Signal
Rev. C | Page 24 of 28
03579-031
TIME
Data Sheet
AD8220
ELECTROCARDIOGRAM SIGNAL CONDITIONING
In addition, the AD8220 JFET inputs have ultralow input
bias current and no current noise, making it useful for ECG
applications where there are often large impedances. The MSOP
and the optimal pinout of the AD8220 allow smaller footprints
and more efficient layout, paving the way for next-generation
portable ECGs.
The AD8220 makes an excellent input amplifier for next
generation ECGs. Its small size, high CMRR over frequency,
rail-to-rail output, and JFET inputs are well suited for this
application. Potentials measured on the skin range from 0.2 mV
to 2 mV. The AD8220 solves many of the typical challenges of
measuring these body surface potentials. The high CMRR of
the AD8220 helps reject common-mode signals that come in
the form of line noise or high frequency EMI from equipment
in the operating room. Its rail-to-rail output offers a wide
dynamic range allowing for higher gains than would be possible
using other instrumentation amplifiers. JFET inputs offer a
large input capacitance of 5 pF. A natural RC filter is formed
reducing high frequency noise when series input resistors are
used in front of the AD8220 (see the RF Interference section).
INSTRUMENTATION
AMPLIFIER
G = +14
+5V
2.2pF
A
B
15kΩ
AD8220
Figure 67 shows an example ECG schematic. Following the
AD8220 is a 0.033 Hz high-pass filter, formed by the 4.7 µF
capacitor and the 1 MΩ resistor, which removes the dc offset
that develops between the electrodes. An additional gain of 50,
provided by the AD8618, makes use of the 0 V to 5 V input
range of the ADC. An active, fifth-order, low-pass Bessel filter
removes signals greater than approximately 160 Hz. An OP2177
buffers, inverts, and gains the common-mode voltage taken at
the midpoint of the AD8220 gain setting resistors. This rightleg drive circuit helps cancel common-mode signals by
inverting the common-mode signal and driving it back into the
body. A 499 kΩ series resistor at the output of the OP2177
limits the current driven into the body.
G = +50
2.5V
1.18kΩ
57.6kΩ
LOW-PASS FIFTH ORDER FILTER AT 157Hz
14kΩ
–5V +5V
+5V
4.12kΩ
+5V
4.7µF
10kΩ
2.2pF
2.5V
4.99kΩ
22nF
4.7µF
REFERENCE
ADR435
2.5V
–5V
OP AMPS
68pF
12.7kΩ
866kΩ
+5V
499kΩ
OP2177
03579-032
C
2.5V
ADC
REF
+5V
1.15kΩ
33nF
2.5V
OP2177
AD7685
500Ω
2.7nF
1MΩ
+5V
–5V
+5V
14.5kΩ
AD8618
220pF
–5V
AD8618
+5V
19.3kΩ
AD8618
24.9kΩ
68nF
AD8618
+5V
24.9kΩ
10pF
14.5kΩ
47nF
HIGH-PASS FILTER 0.033Hz
10kΩ
33nF
19.3kΩ
14kΩ
–5V
Figure 67. Example ECG Schematic
Rev. C | Page 25 of 28
AD8220
Data Sheet
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
3.20
3.00
2.80
1
5.15
4.90
4.65
5
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.40
0.25
6°
0°
0.23
0.09
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.55
0.40
100709-B
0.15
0.05
COPLANARITY
0.10
Figure 68. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
AD8220ARMZ
AD8220ARMZ-R7
AD8220BRMZ
AD8220BRMZ-RL
AD8220BRMZ-R7
AD8220WARMZ
AD8220WARMZ-RL
AD8220WARMZ-R7
1
2
3
Temperature Range 3
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead MSOP
8-Lead MSOP, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
Package Option
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
Marking Code
H01
H01
H0P
H0P
H0P
Y2D
Y2D
Y2D
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
See the Typical Performance Characteristics section for expected operation from 85°C to 125°C.
AUTOMOTIVE PRODUCTS
The AD8220W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
Rev. C | Page 26 of 28
Data Sheet
AD8220
NOTES
Rev. C | Page 27 of 28
AD8220
Data Sheet
NOTES
©2006–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03579-0-9/19(C)
Rev. C | Page 28 of 28
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