AD8220ARMZ-RL

JFET Input Instrumentation Amplifier with Rail-to-Rail Output in MSOP Package AD8220 FEATURES Low input currents 10 pA maximum input bias current (B grade) 0.6 pA maximum input offset current (B grade) High CMRR 100 dB CMRR (minimum), G = 10 (B grade) 80 dB CMRR (minimum) to 5 kHz, G = 1 (B grade) Excellent ac specifications and low power 1.5 MHz bandwidth (G = 1) 14 nV/√Hz input noise (1 kHz) Slew rate: 2 V/μs 750 μA quiescent supply current (maximum) Versatile MSOP package Rail-to-rail output Input voltage range to below negative supply rail 4 kV ESD protection 4.5 V to 36 V single supply ±2.25 V to ±18 V dual supply Gain set with single resistor (G = 1 to 1000) Qualified for automotive applications PIN CONFIGURATION –IN RG RG +IN 1 2 3 4 AD8220 8 7 6 5 +VS VOUT REF –VS 03579-005 TOP VIEW (Not to Scale) Figure 1. 10n INPUT BIAS CURRENT (A) 1n 100p 10p 1p 0.1p IBIAS IOS APPLICATIONS Medical instrumentation Precision data acquisition Transducer interfaces –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) 150 Figure 2. Input Bias Current and Offset Current vs. Temperature GENERAL DESCRIPTION The AD8220 is the first single-supply, JFET input instrumentation amplifier available in an MSOP package. Designed to meet the needs of high performance, portable instrumentation, the AD8220 has a minimum common-mode rejection ratio (CMRR) of 86 dB at dc and a minimum CMRR of 80 dB at 5 kHz for G = 1. Maximum input bias current is 10 pA and typically remains below 300 pA over the entire industrial temperature range. Despite the JFET inputs, the AD8220 typically has a noise corner of only 10 Hz. With the proliferation of mixed-signal processing, the number of power supplies required in each system has grown. The AD8220 is designed to alleviate this problem. The AD8220 can operate on a ±18 V dual supply, as well as on a single +5 V supply. Its rail-to-rail output stage maximizes dynamic range on the low voltage supplies common in portable applications. Its ability to run on a single 5 V supply eliminates the need to use higher voltage, dual supplies. The AD8220 draws a maximum of 750 μA of quiescent current, making it ideal for battery powered devices. Gain is set from 1 to 1000 with a single resistor. Increasing the gain increases the common-mode rejection. Measurements that need higher CMRR when reading small signals benefit when the AD8220 is set for large gains. A reference pin allows the user to offset the output voltage. This feature is useful when interfacing with analog-to-digital converters. The AD8220 is available in an MSOP that takes roughly half the board area of an SOIC. Performance for the A and B grade is specified over the industrial temperature range of −40°C to +85°C, and the W grade is specified over the automotive temperature range of −40°C to +125°C. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2010 Analog Devices, Inc. All rights reserved. 03579-059 AD8220 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  Pin Configuration ............................................................................. 1  General Description ......................................................................... 1  Revision History ............................................................................... 2  Specifications..................................................................................... 3  Absolute Maximum Ratings............................................................ 8  ESD Caution .................................................................................. 8  Pin Configuration and Function Descriptions ............................. 9  Typical Performance Characteristics ........................................... 10  Theory of Operation ...................................................................... 19  Gain Selection ............................................................................. 20  Layout........................................................................................... 20  Reference Terminal .................................................................... 21  Power Supply Regulation and Bypassing ................................ 21  Input Bias Current Return Path ............................................... 21  Input Protection ......................................................................... 21  RF Interference ........................................................................... 22  Common-Mode Input Voltage Range ..................................... 22  Driving an ADC ......................................................................... 22  Applications Information .............................................................. 23  AC-Coupled Instrumentation Amplifier ................................ 23  Differential Output .................................................................... 23  Electrocardiogram Signal Conditioning ................................. 25  Outline Dimensions ....................................................................... 26  Ordering Guide .......................................................................... 26  Automotive Products ................................................................. 26  REVISION HISTORY 5/10—Rev. A to Rev. B Added W Grade .................................................................. Universal Changes to Features Section and General Description Section . 1 Changes to Specifications Section and Table 1 ............................. 3 Changes to Table 2 ............................................................................ 5 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 26 Added Automotive Products Section .......................................... 26 5/07—Rev. 0 to Rev. A Changes to Table 1.............................................................................3 Changes to Table 2.............................................................................5 Changes to Table 3.............................................................................8 Changes to Figure 6 and Figure 7 ................................................. 10 Changes to Figure 23 and Figure 24............................................. 13 Changes to Theory of Operation.................................................. 19 Changes to Layout .......................................................................... 20 Changes to Ordering Guide .......................................................... 26 4/06—Revision 0: Initial Version Rev. B | Page 2 of 28 AD8220 SPECIFICATIONS VS+ = 15 V, VS− = −15 V, VREF = 0 V, TA = 25°C, TOPR = −40°C to +85°C for A and B grades. TOPR = −40°C to +125°C for W grade, G = 1, RL = 2 kΩ1, unless otherwise noted. Table 1. Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz with 1 kΩ Source Imbalance G=1 G = 10 G = 100 G = 1000 CMRR at 5 kHz G=1 G = 10 G = 100 G = 1000 NOISE Voltage Noise, 1 kHz Input Voltage Noise, eni Output Voltage Noise, eno RTI, 0.1 Hz to 10 Hz G=1 G = 1000 Current Noise VOLTAGE OFFSET Input Offset, VOSI Average TC Output Offset, VOSO Average TC Offset RTI vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Over Temperature Input Offset Current Over Temperature DYNAMIC RESPONSE Small Signal Bandwidth, −3 dB G=1 G = 10 G = 100 G = 1000 Test Conditions TA for A, B grades, TOPR for W grade VCM = ±10 V Min A Grade Typ Max Min B Grade Typ Max Min W Grade Typ Max Unit 78 94 94 94 VCM = ±10 V 74 84 84 84 RTI noise = √(eni2 + (eno/G)2), TA VIN+, VIN− = 0 V VIN+, VIN− = 0 V 14 90 5 0.8 1 −250 −10 −750 −10 +250 +10 +750 +10 86 100 100 100 80 90 90 90 77 92 92 92 72 80 80 80 dB dB dB dB dB dB dB dB 14 90 5 0.8 1 −125 −5 −500 −5 17 100 14 90 5 0.8 1 nV/√Hz nV/√Hz μV p-p μV p-p fA/√Hz +250 +10 +750 +10 μV μV/°C μV μV/°C f = 1 kHz VOS = VOSI + VOSO/G TA TOPR TA TOPR VS = ±5 V to ±15 V, TA for A, B grades, TOPR for W grade +125 +5 +500 +5 −250 −10 −750 −10 86 96 96 96 TA TOPR TA TOPR TA 1500 800 120 14 25 0.3 2 0.005 86 100 100 100 10 0.3 0.6 0.005 80 92 92 92 25 100 2 10 dB dB dB dB pA nA pA nA 1500 800 120 14 1500 800 120 14 kHz kHz kHz kHz Rev. B | Page 3 of 28 AD8220 Parameter Settling Time 0.01% G=1 G = 10 G = 100 G = 1000 Settling Time 0.001% G=1 G = 10 G = 100 G = 1000 Slew Rate G = 1 to 100 GAIN Test Conditions 10 V step, TA Min A Grade Typ Max 5 4.3 8.1 58 10 V step, TA 6 4.6 9.6 74 TA G = 1 + (49.4 kΩ/RG), TA for A, B grades, TOPR for W grade VOUT = ±10 V −0.06 −0.3 −0.3 −0.3 VOUT = −10 V to +10 V, TA RL = 10 kΩ RL = 10 kΩ RL = 10 kΩ RL = 10 kΩ RL = 2 kΩ RL = 2 kΩ RL = 2 kΩ +0.06 +0.3 +0.3 +0.3 −0.04 −0.2 −0.2 −0.2 +0.04 +0.2 +0.2 +0.2 −0.1 −0.8 −0.8 −0.8 +0.1 +0.8 +0.8 +0.8 % % % % 2 2 6 4.6 9.6 74 2 6 4.6 9.6 74 μs μs μs μs V/μs Min B Grade Typ Max 5 4.3 8.1 58 Min W Grade Typ Max 5 4.3 8.1 58 Unit μs μs μs μs Gain Range Gain Error G=1 G = 10 G = 100 G = 1000 Gain Nonlinearity G=1 G = 10 G = 100 G = 1000 G=1 G = 10 G = 100 Gain vs. Temperature G=1 G > 10 INPUT Impedance (Pin to Ground)2 Input Operating Voltage Range3 Over Temperature OUTPUT Output Swing Over Temperature Short-Circuit Current REFERENCE INPUT RIN IIN Voltage Range Gain to Output 1 1000 1 1000 1 1000 V/V 10 5 30 400 10 10 50 3 15 10 60 500 15 15 75 10 −50 10 5 30 400 10 10 50 2 15 10 60 500 15 15 75 5 −50 10 5 30 400 10 10 50 3 15 10 60 500 15 15 75 10 −50 ppm ppm ppm ppm ppm ppm ppm ppm/°C ppm/°C GΩ||pF TA VS = ±2.25 V to ±18 V for dual supplies TOPR −VS − 0.1 −VS − 0.1 −14.7 −14.6 104||5 +VS − 2 +VS − 2.1 +14.7 +14.6 15 40 −VS − 0.1 −VS − 0.1 −14.7 −14.6 104||5 +VS − 2 +VS − 2.1 +14.7 +14.6 15 40 70 +VS −VS 1± 0.0001 70 +VS −VS − 0.1 −VS − 0.1 −14.7 −14.3 104||5 +VS − 2 +VS − 2.2 +14.7 +14.3 15 40 70 +VS 1± 0.0001 V V RL = 10 kΩ, TA TOPR TA TA VIN+, VIN− = 0 V −VS TA 1± 0.0001 V V mA kΩ μA V V/V V/V Rev. B | Page 4 of 28 AD8220 Parameter POWER SUPPLY Operating Range Quiescent Current Over Temperature TEMPERATURE RANGE For Specified Performance 1 2 Test Conditions Min ±2.254 A Grade Typ Max ±18 750 850 +85 Min ±2.254 B Grade Typ Max ±18 750 850 +85 Min ±2.254 W Grade Typ Max ±18 750 1000 +125 TA TOPR TOPR −40 Unit V μA μA μA °C −40 −40 When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ. Differential and common-mode input impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2. 3 The AD8220 can operate up to a diode drop below the negative supply but the bias current increases sharply. The input voltage range reflects the maximum allowable voltage where the input bias current is within the specification. 4 At this supply voltage, ensure that the input common-mode voltage is within the input voltage range specification. VS + = 5 V, VS− = 0 V, VREF = 2.5 V, TA = 25°C, TOPR = −40°C to +85°C for A and B grades. TOPR = −40°C to +125°C for W grade, G = 1, RL = 2 kΩ1, unless otherwise noted. Table 2. Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz with 1 kΩ Source Imbalance G=1 G = 10 G = 100 G = 1000 CMRR at 5 kHz G=1 G = 10 G = 100 G = 1000 NOISE Voltage Noise, 1 kHz Input Voltage Noise, eni Output Voltage Noise, eno RTI, 0.1 Hz to 10 Hz G=1 G = 1000 Current Noise VOLTAGE OFFSET Input Offset, VOSI Average TC Output Offset, VOSO Average TC Offset RTI vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 Test Conditions TA for A, B grades, TOPR for W grade VCM = 0 to 2.5 V Min A Grade Typ Max Min B Grade Typ Max Min W Grade Typ Max Unit 78 94 94 94 VCM = 0 to 2.5 V 74 84 84 84 RTI noise = √(eni2 + (eno/G)2), TA VS = ±2.5 V VIN+, VIN− = 0 V, VREF = 0V VIN+, VIN− = 0 V, VREF = 0V 86 100 100 100 80 90 90 90 77 92 92 92 72 80 80 80 dB dB dB dB dB dB dB dB 14 90 14 90 17 100 14 90 nV/√Hz nV/√Hz f = 1 kHz VOS = VOSI + VOSO/G TA TOPR TA TOPR TA for A, B grades, TOPR for W grade 5 0.8 1 −300 −10 −800 −10 +300 +10 +800 +10 −200 −5 −600 −5 5 0.8 1 +200 +5 +600 +5 −300 −10 −800 −10 5 0.8 1 +300 10 +800 +10 μV p-p μV p-p fA/√Hz μV μV/°C μV μV/°C 86 96 96 96 86 100 100 100 80 92 92 92 dB dB dB dB Rev. B | Page 5 of 28 AD8220 Parameter INPUT CURRENT Input Bias Current Over Temperature Input Offset Current Over Temperature DYNAMIC RESPONSE Small Signal Bandwidth, −3 dB G=1 G = 10 G = 100 G = 1000 Settling Time 0.01% G=1 G = 10 G = 100 G = 1000 Settling Time 0.001% G=1 G = 10 G = 100 G = 1000 Slew Rate G = 1 to 100 GAIN Test Conditions TA TOPR TA TOPR TA Min A Grade Typ Max 25 0.3 2 0.005 0.005 0.3 0.6 Min B Grade Typ Max 10 Min W Grade Typ Max 25 100 2 10 Unit pA nA pA nA 1500 800 120 14 TA 3 V step 4 V step 4 V step 4 V step TA 3 V step 4 V step 4 V step 4 V step TA G = 1 + (49.4 kΩ/RG), TA for A, B grades, TOPR for W grade 1 VOUT = 0.3 V to 2.9 V for G = 1, VOUT = 0.3 V to 3.8 V for G > 1 −0.06 −0.3 −0.3 −0.3 VOUT = 0.3 V to 2.9 V for G = 1, VOUT = 0.3 V to 3.8 V for G > 1, TA RL = 10 kΩ RL = 10 kΩ RL = 10 kΩ RL = 10 kΩ RL = 2 kΩ RL = 2 kΩ RL = 2 kΩ +0.06 +0.3 +0.3 +0.3 −0.04 −0.2 −0.2 −0.2 1000 1 2 2.5 2.5 7.5 30 3.5 3.5 8.5 37 2 1500 800 120 14 2.5 2.5 7.5 30 3.5 3.5 8.5 37 2 1500 800 120 14 2.5 2.5 7.5 30 3.5 3.5 8.5 37 kHz kHz kHz kHz μs μs μs μs μs μs μs μs V/μs Gain Range Gain Error 1000 1 1000 V/V G=1 G = 10 G = 100 G = 1000 Nonlinearity +0.04 +0.2 +0.2 +0.2 −0.1 −0.8 −0.8 −0.8 +0.1 +0.8 +0.8 +0.8 % % % % G=1 G = 10 G = 100 G = 1000 G=1 G = 10 G = 100 Gain vs. Temperature G=1 G > 10 INPUT Impedance (Pin to Ground)2 Input Voltage Range3 Over Temperature 35 35 50 650 35 35 50 3 50 50 75 750 50 50 75 10 −50 35 35 50 650 35 35 50 2 50 50 75 750 50 50 75 5 −50 3 50 50 75 750 50 50 75 10 −50 ppm ppm ppm ppm ppm ppm ppm ppm/°C ppm/°C GΩ||pF V TA TA TOPR −0.1 −0.1 104||6 +VS − 2 +VS − 2.1 −0.1 −0.1 104||6 +VS − 2 +VS − 2.1 104||6 −0.1 +VS − 2.2 V Rev. B | Page 6 of 28 AD8220 Parameter OUTPUT Output Swing Over Temperature Short-Circuit Current REFERENCE INPUT RIN IIN Voltage Range Gain to Output POWER SUPPLY Operating Range Quiescent Current Over Temperature TEMPERATURE RANGE TOPR, For Specified Performance 1 2 Test Conditions RL = 10 kΩ TOPR TA Min 0.15 0.2 A Grade Typ Max 4.85 4.80 15 40 Min 0.15 0.2 B Grade Typ Max 4.85 4.80 15 40 Min 0.15 0.3 W Grade Typ Max 4.85 4.70 15 40 Unit V V mA kΩ μA V V/V VIN+, VIN− = 0 V −VS TA 1± 0.0001 4.5 TA TOPR TOPR −40 70 +VS −VS 1± 0.0001 70 +VS −VS 1± 0.0001 70 +VS 36 750 850 +85 4.5 36 750 850 +85 4.5 36 750 1000 +125 V μA μA °C −40 −40 When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ. Differential and common-mode impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2. 3 The AD8220 can operate up to a diode drop below the negative supply but the bias current increases sharply. The input voltage range reflects the maximum allowable voltage where the input bias current is within the specification. Rev. B | Page 7 of 28 AD8220 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage Power Dissipation Output Short-Circuit Current Input Voltage (Common Mode) Differential Input Voltage Storage Temperature Range Operating Temperature Range2 Lead Temperature (Soldering 10 sec) Junction Temperature θJA (4-Layer JEDEC Standard Board) Package Glass Transition Temperature ESD (Human Body Model) ESD (Charge Device Model) ESD (Machine Model) 1 MAXIMUM POWER DISSIPATION (W) Rating ±18 V See Figure 3 Indefinite1 ±Vs ±Vs −65°C to +125°C −40°C to +125°C 300°C 140°C 135°C/W 140°C 4 kV 1 kV 0.4 kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the MSOP on a 4-layer JEDEC standard board. θJA values are approximations. 2.00 1.75 1.50 1.25 1.00 0.75 0.50 03579-045 Assumes the load is referenced to midsupply. 2 Temperature for specified performance is −40°C to +85°C. For performance to 125°C, see the Typical Performance Characteristics section. 0.25 0 –40 –20 0 20 40 60 80 100 120 AMBIENT TEMPERATURE (°C) Figure 3. Maximum Power Dissipation vs. Ambient Temperature ESD CAUTION Rev. B | Page 8 of 28 AD8220 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS –IN RG RG +IN 1 2 3 4 AD8220 8 7 6 5 +VS VOUT REF –VS 03579-005 TOP VIEW (Not to Scale) Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2, 3 4 5 6 7 8 Mnemonic −IN RG +IN −VS REF VOUT +VS Description Negative Input Terminal (True Differential Input) Gain Setting Terminals (Place Resistor Across the RG Pins) Positive Input Terminal (True Differential Input) Negative Power Supply Terminal Reference Voltage Terminal (Drive This Terminal with a Low Impedance Voltage Source to Level-Shift the Output) Output Terminal Positive Power Supply Terminal Rev. B | Page 9 of 28 AD8220 TYPICAL PERFORMANCE CHARACTERISTICS 1200 1600 1400 1200 1000 NUMBER OF UNITS 800 NUMBER OF UNITS 03579-060 1000 800 600 400 600 400 200 03579-063 200 0 0 –40 –20 0 CMRR (µV/V) 20 40 0 1 2 3 IBIAS (pA) 4 5 Figure 5. Typical Distribution of CMRR (G = 1) Figure 8. Typical Distribution of Input Bias Current 1200 1000 1000 NUMBER OF UNITS NUMBER OF UNITS 03579-061 800 800 600 600 400 400 200 200 03579-064 0 –200 –100 0 VOSI (µV) 100 200 0 –0.2 –0.1 0 IOS (pA) 0.1 0.2 Figure 6. Typical Distribution of Input Offset Voltage Figure 9. Typical Distribution of Input Offset Current 1000 1000 VOLTAGE NOISE RTI (nV/ Hz) GAIN = 100 BANDWIDTH ROLL-OFF 100 GAIN = 1 GAIN = 10 10 GAIN = 100/GAIN = 1000 NUMBER OF UNITS 800 600 400 200 03579-062 GAIN = 1000 BANDWIDTH ROLL-OFF 03579-042 0 1 –1000 –500 0 VOSO (µV) 500 1000 1 10 100 1k 10k 100k FREQUENCY (Hz) Figure 7. Typical Distribution of Output Offset Voltage Figure 10. Voltage Spectral Density vs. Frequency Rev. B | Page 10 of 28 AD8220 XX 150 130 110 GAIN = 100 GAIN = 10 GAIN = 1000 BANDWIDTH LIMITED PSRR (dB) XXX (X) 90 70 50 30 10 GAIN = 1 03579-024 5µV/DIV XX XX XXX (X) 1s/DIV XX 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1) Figure 14. Positive PSRR vs. Frequency, RTI XX 150 130 110 GAIN = 1000 PSRR (dB) XXX (X) 90 GAIN = 1 70 GAIN = 10 50 GAIN = 100 30 10 03579-025 1µV/DIV XX XX XXX (X) 1s/DIV XX 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000) Figure 15. Negative PSRR vs. Frequency, RTI 8 7 9 INPUT OFFSET CURRENT ±15 INPUT OFFSET CURRENT ±5 0.3 0.2 0.1 0 5 –15.1V –0.1 –0.2 –5.1V 1 03579-009 03579-040 03579-035 INPUT BIAS CURRENT (pA) 6 5 4 3 2 1 0 0.1 7 3 INPUT BIAS CURRENT ±5 INPUT BIAS CURRENT ±15 –0.3 –0.4 1 10 TIME (s) 100 1k –12 –8 –4 0 4 8 12 16 COMMON-MODE VOLTAGE (V) Figure 13. Change in Input Offset Voltage vs. Warmup Time Figure 16. Input Bias Current and Input Offset Current vs. Common-Mode Voltage Rev. B | Page 11 of 28 03579-050 –1 –16 –0.5 INPUT OFFSET CURRENT (pA) Δ VOSI (µV) AD8220 160 10n 140 IBIAS INPUT BIAS CURRENT (A) GAIN = 1000 1n 100p 10p 1p 0.1p 120 CMRR (dB) 100 GAIN = 100 GAIN = 1 BANDWIDTH LIMITED IOS 80 GAIN = 10 03579-059 60 03579-051 –50 –25 0 25 50 75 100 125 150 40 1 10 100 1k 10k 100k TEMPERATURE (°C) FREQUENCY (Hz) Figure 17. Input Bias Current and Offset Current vs. Temperature, VS = ±15 V, VREF = 0 V Figure 20. CMRR vs. Frequency, 1 kΩ Source Imbalance 10 10n 1n 8 6 IBIAS 100p 10p 1p 0.1p IOS 4 CURRENT (A) Δ CMRR (μV/V) 2 0 –2 –4 –6 03579-065 –8 –10 –50 –30 –10 10 30 50 70 90 110 –50 –25 0 25 50 75 100 125 150 130 TEMPERATURE (°C) TEMPERATURE (°C) Figure 18. Input Bias Current and Offset Current vs. Temperature, VS = +5 V, VREF = 2.5 V 160 GAIN = 1000 70 60 140 50 40 30 GAIN = 10 100 GAIN = 1 80 Figure 21. Change in CMRR vs. Temperature, G = 1 GAIN = 1000 120 GAIN = 100 GAIN = 100 CMRR (dB) GAIN (dB) BANDWIDTH LIMITED 20 10 0 –10 GAIN = 10 GAIN = 1 60 03579-023 –20 –30 –40 100 1k 10k 100k 1M 03579-022 40 10 100 1k FREQUENCY (Hz) 10k 100k 10M FREQUENCY (Hz) Figure 19. CMRR vs. Frequency Figure 22. Gain vs. Frequency Rev. B | Page 12 of 28 03579-034 AD8220 NONLINEARITY (500ppm/DIV) NONLINEARITY (5ppm/DIV) RLOAD = 2kΩ XXX XXX RLOAD = 2kΩ RLOAD = 10kΩ RLOAD = 10kΩ 03579-026 VS = ±15V –10 –8 –6 –4 –2 0 2 4 6 8 VS = ±15V –10 –8 –6 –4 –2 0 2 4 6 8 10 10 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 23. Gain Nonlinearity, G = 1 Figure 26. Gain Nonlinearity, G = 1000 18 INPUT COMMON-MODE VOLTAGE (V) +13V 12 ±15V SUPPLIES NONLINEARITY (5ppm/DIV) RLOAD = 2kΩ 6 –14.8V, +5.5V –4.8V, +0.6V +3V +14.9V, +5.5V +4.95V, +0.6V XXX 0 ±5V SUPPLIES –4.8V, –3.3V +4.95V, –3.3V –5.3V +14.9V, –8.3V RLOAD = 10kΩ –6 –14.8V, –8.3V –12 –15.3V –12 –8 –4 0 4 8 12 16 03579-037 VS = ±15V –10 –8 –6 –4 –2 0 2 4 6 8 03579-027 10 –18 –16 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 24. Gain Nonlinearity, G = 10 Figure 27. Input Common-Mode Voltage Range vs. Output Voltage, G = 1, VREF = 0 V 4 INPUT COMMON-MODE VOLTAGE (V) 3 +3V NONLINEARITY (50ppm/DIV) RLOAD = 2kΩ RLOAD = 10kΩ 2 +0.1V, +1.7V 1 +4.9V, +1.7V +5V SINGLE SUPPLY, VREF = +2.5V +0.1V, +0.5V 0 03579-036 XXX +4.9V, +0.5V VS = ±15V –10 –8 –6 –4 –2 0 2 4 6 8 03579-028 –0.3V –1 –1 10 0 1 2 3 4 5 6 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 25. Gain Nonlinearity, G = 100 Figure 28. Input Common-Mode Voltage Range vs. Output Voltage, G = 1, VS = +5 V, VREF = 2.5 V Rev. B | Page 13 of 28 03579-029 AD8220 18 INPUT COMMON-MODE VOLTAGE (V) VS+ +13V OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGE –1 –2 –3 –4 12 ±15V SUPPLIES –40°C +25°C +85°C 6 –14.9V, +5.4V –4.9V, +0.4V +3V +14.9V, +5.4V +4.9V, +0.5V +125°C 0 ±5V SUPPLIES –4.9V, –4.1V –6 –14.8V, –9V –12 03579-039 +4.9V, –4.1V –5.3V +14.9V, –9V +4 +3 +2 +1 VS– 2 4 6 8 10 03579-053 –15.3V –18 –16 +125°C +85°C +25°C –40°C –12 –8 –4 0 4 8 12 16 12 14 16 18 OUTPUT VOLTAGE (V) DUAL SUPPLY VOLTAGE (±V) Figure 29. Input Common-Mode Voltage Range vs. Output Voltage, G = 100, VREF = 0 V 4 INPUT COMMON-MODE VOLTAGE (V) Figure 32. Output Voltage Swing vs. Supply Voltage, RLOAD = 2 kΩ, G = 10, VREF = 0 V VS+ 3 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGE +3V –0.2 –0.4 +125°C +85°C +25°C –40°C 2 +0.1V, +1.7V 1 +4.9V, +1.7V +5V SINGLE SUPPLY, VREF = +2.5V 0 –0.3V 2 3 03579-038 +0.4 +0.2 VS – 2 +125°C +85°C –1 –1 0 1 4 5 6 4 6 8 10 12 14 16 18 OUTPUT VOLTAGE (V) DUAL SUPPLY VOLTAGE (±V) Figure 30. Input Common-Mode Voltage Range vs. Output Voltage, G = 100, VS = +5 V, VREF = 2.5 V VS+ –1 INPUT VOLTAGE LIMIT (V) Figure 33. Output Voltage Swing vs. Supply Voltage, RLOAD = 10 kΩ, G = 10, VREF = 0 V 15 OUTPUT VOLTAGE SWING (V) –40°C +125°C 10 –40°C +25°C –2 +25°C +85°C NOTES 1. THE AD8220 CAN OPERATE UP TO A VBE BELOW THE NEGATIVE SUPPLY, BUT THE BIAS CURRENT WILL INCREASE SHARPLY. +1 –40°C VS– –1 +25°C +85°C +125°C 03579-052 5 +125°C 0 +85°C –5 +125°C +85°C –10 2 4 6 8 10 12 14 16 18 –15 100 1k RLOAD (Ω) 10k SUPPLY VOLTAGE (V) Figure 31. Input Voltage Limit vs. Supply Voltage, G = 1, VREF =0 V Figure 34. Output Voltage Swing vs. Load Resistance VS = ±15 V, VREF = 0 V Rev. B | Page 14 of 28 03579-055 +25°C –40°C 03579-054 +0.1V, –0.5V +4.9V, –0.5V +25°C –40°C AD8220 5 –40°C OUTPUT VOLTAGE SWING (V) 4 +125°C 3 XXX (X) XX NO LOAD 47pF 100pF +25°C +85°C 2 1 +125°C –40°C +25°C 0 100 1k RLOAD (Ω) 10k 20mV/DIV XX XX 5µs/DIV XX XXX (X) Figure 35. Output Voltage Swing vs. Load Resistance VS = +5 V, VREF = 2.5 V Figure 38. Small Signal Pulse Response for Various Capacitive Loads, VS = ±15 V, VREF = 0 V VS+ –1 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES XX –40°C +125°C +85°C +25°C NO LOAD 47pF 100pF –2 –3 –4 +4 +3 +2 +1 VS– –40°C 0 2 4 6 8 IOUT (mA) 10 12 14 16 +125°C +85°C +25°C 03579-057 XXX (X) 20mV/DIV XX XX 5µs/DIV XX XXX (X) Figure 36. Output Voltage Swing vs. Output Current, VS = ±15 V, VREF = 0 V VS+ Figure 39. Small Signal Pulse Response for Various Capacitive Loads, VS = 5 V, VREF = 2.5 V 35 30 25 20 15 10 5 0 100 GAIN = 10, 100, 1000 GAIN = 1 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES –1 +85°C +125°C –2 +25°C +2 +25°C +1 +125°C +85°C 03579-058 VS– 0 2 4 6 8 IOUT (mA) 10 12 14 16 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 37. Output Voltage Swing vs. Output Current, VS = 5 V, VREF = 2.5 V Figure 40. Output Voltage Swing vs. Large Signal Frequency Response Rev. B | Page 15 of 28 03579-021 –40°C OUTPUT VOLTAGE SWING (V p-p) 03579-019 03579-018 03579-056 +85°C AD8220 XX XX 5V/DIV XXX (X) XXX (X) 5V/DIV 0.002%/DIV 5µs TO 0.01% 6µs TO 0.001% 0.002%/DIV 58μs TO 0.01% 74μs TO 0.001% 03579-046 20µs/DIV XX XX XXX (X) XX 200µs/DIV XX XX XXX (X) XX Figure 41. Large Signal Pulse Response and Settle Time, G = 1, RLOAD = 10 kΩ, VS = ±15 V, VREF = 0 V XX Figure 44. Large Signal Pulse Response and Settle Time, G = 1000, RLOAD = 10 kΩ, VS = ±15 V, VREF = 0 V 5V/DIV XXX (X) 0.002%/DIV 4.3μs TO 0.01% 4.6μs TO 0.001% XXX 20mV/DIV 20µs/DIV XX XX XXX (X) XX 03579-047 4µs/DIV XXX Figure 42. Large Signal Pulse Response and Settle Time, G = 10, RLOAD = 10 kΩ, VS = ±15 V, VREF = 0 V XX Figure 45. Small Signal Pulse Response, G = 1, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = ±15 V, VREF = 0 V 5V/DIV XXX (X) 0.002%/DIV 8.1μs TO 0.01% 9.6μs TO 0.001% XXX 20mV/DIV 20µs/DIV XX XX XXX (X) XX 03579-048 4µs/DIV XXX Figure 43. Large Signal Pulse Response and Settle Time, G = 100, RLOAD = 10 kΩ, VS = ±15 V, VREF = 0 V Figure 46. Small Signal Pulse Response, G = 10, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = ±15 V, VREF = 0 V Rev. B | Page 16 of 28 03579-014 03579-016 03579-049 AD8220 XXX 20mV/DIV XXX 20mV/DIV 03579-012 4µs/DIV XXX XXX 4µs/DIV Figure 47 Small Signal Pulse Response, G = 100, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = ±15 V, VREF =0 V Figure 50. Small Signal Pulse Response, G = 10, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = 5 V, VREF = 2.5 V XXX XXX 20mV/DIV 20mV/DIV 03579-010 40µs/DIV XXX XXX 4µs/DIV Figure 48. Small Signal Pulse Response, G = 1000, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = ±15 V, VREF = 0 V Figure 51. Small Signal Pulse Response, G = 100, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = 5 V, VREF = 2.5 V XXX XXX 20mV/DIV 20mV/DIV 03579-017 4µs/DIV XXX XXX 40µs/DIV Figure 49. Small Signal Pulse Response, G = 1, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = 5 V, VREF = 2.5 V Figure 52. Small Signal Pulse Response, G = 1000, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = 5 V, VREF = 2.5 V Rev. B | Page 17 of 28 03579-011 03579-013 03579-015 AD8220 15 100 SETTLING TIME (µs) 10 SETTLED TO 0.001% SETTLING TIME (µs) SETTLED TO 0.001% 10 SETTLED TO 0.01% 5 SETTLED TO 0.01% 03579-043 0 0 5 10 15 20 1 1 10 GAIN (V/V) 100 1000 OUTPUT VOLTAGE STEP SIZE (V) Figure 53. Settling Time vs. Output Voltage Step Size (G = 1) ±15 V, VREF = 0 V Figure 54. Settling Time vs. Gain for a 10 V Step, VS = ±15 V, VREF = 0 V Rev. B | Page 18 of 28 03579-041 AD8220 THEORY OF OPERATION +VS NODE A +VS RG +VS NODE B R2 24.7kΩ +VS 20kΩ NODE F 20kΩ A3 +VS OUTPUT 20kΩ +VS NODE C +IN J1 Q1 VPINCH C1 A1 A2 NODE D C2 Q2 J2 –IN +VS NODE E 20kΩ +VS R1 24.7kΩ –VS –VS –VS REF –VS VPINCH –VS –VS I VB –VS I 03579-006 Figure 55. Simplified Schematic The AD8220 is a JFET input, monolithic instrumentation amplifier based on the classic 3-op amp topology (see Figure 55). Input Transistor J1 and Input Transistor J2 are biased at a fixed current so that any input signal forces the output voltages of A1 and A2 to change accordingly; the input signal creates a current through RG that flows in R1 and R2 such that the outputs of A1 and A2 provide the correct, gained signal. Topologically, J1, A1, and R1 and J2, A2, and R2 can be viewed as precision current feedback amplifiers that have a gain bandwidth of 1.5 MHz. The common-mode voltage and amplified differential signal from A1 and A2 are applied to a difference amplifier that rejects the common-mode voltage but amplifies the differential signal. The difference amplifier employs 20 kΩ laser-trimmed resistors that result in an in-amp with gain error less than 0.04%. New trim techniques were developed to ensure that CMRR exceeds 86 dB (G = 1). Using JFET transistors, the AD8220 offers an extremely high input impedance, extremely low bias currents of 10 pA maximum, a low offset current of 0.6 pA maximum, and no input bias current noise. In addition, input offset is less than 125 μV and drift is less than 5 μV/°C. Ease of use and robustness were considered. A common problem for instrumentation amplifiers is that at high gains, when the input is overdriven,1 an excessive milliampere input bias current can result and the output can undergo phase reversal. The AD8220 has none of these problems; its input bias current is limited to less than 10 μA, and the output does not phase reverse under overdrive fault conditions. 1 The AD8220 has extremely low load-induced nonlinearity. All amplifiers that comprise the AD8220 have rail-to-rail output capability for enhanced dynamic range. The input of the AD8220 can amplify signals with wide common-mode voltages even slightly lower than the negative supply rail. The AD8220 operates over a wide supply voltage range. It can operate from either a single +4.5 V to +36 V supply or a dual ±2.25 V to ±18 V. The transfer function of the AD8220 is G 1 49.4 kΩ RG Users can easily and accurately set the gain using a single, standard resistor. Because the input amplifiers employ a current feedback architecture, the AD8220 gain-bandwidth product increases with gain, resulting in a system that does not suffer as much bandwidth loss as voltage feedback architectures at higher gains. A unique pinout enables the AD8220 to meet a CMRR specification of 80 dB through 5 kHz (G = 1). The balanced pinout, shown in Figure 56, reduces parasitics that adversely affect CMRR performance. In addition, the new pinout simplifies board layout because associated traces are grouped together. For example, the gain setting resistor pins are adjacent to the inputs, and the reference pin is next to the output. –IN RG RG +IN 1 2 3 4 AD8220 8 7 6 5 +VS VOUT REF –VS 03579-005 Overdriving the input at high gains refers to when the input signal is within the supply voltages but the amplifier cannot output the gained signal. For example, at a gain of 100, driving the amplifier with 10 V on ±15 V constitutes overdriving the inputs since the amplifier cannot output 100 V. TOP VIEW (Not to Scale) Figure 56. Pin Configuration Rev. B | Page 19 of 28 AD8220 GAIN SELECTION Placing a resistor across the RG terminals sets the AD8220 gain, which can be calculated by referring to Table 5 or by using the gain equation RG  49.4 kΩ G 1 Calculated Gain 1.990 4.984 9.998 19.93 50.40 100.0 199.4 495.0 991.0 gain setting resistor to the RG pins should be kept as short as possible to minimize parasitic inductance. An example layout is shown in Figure 57 and Figure 58. To ensure the most accurate output, the trace from the REF pin should either be connected to the AD8220 local ground (see Figure 59) or connected to a voltage that is referenced to the AD8220 local ground. Common-Mode Rejection Ratio (CMRR) The AD8220 has high CMRR over frequency giving it greater immunity to disturbances, such as line noise and its associated harmonics, in contrast to typical in-amps whose CMRR falls off around 200 Hz. These in-amps often need common-mode filters at the inputs to compensate for this shortcoming. The AD8220 is able to reject CMRR over a greater frequency range, reducing the need for input common-mode filtering. A well-implemented layout helps to maintain the high CMRR over frequency of the AD8220. Input source impedance and capacitance should be closely matched. In addition, source resistance and capacitance should be placed as close to the inputs as possible. Table 5. Gains Achieved Using 1% Resistors 1% Standard Table Value of RG (Ω) 49.9 k 12.4 k 5.49 k 2.61 k 1.00 k 499 249 100 49.9 The AD8220 defaults to G = 1 when no gain resistor is used. Gain accuracy is determined by the absolute tolerance of RG. The TC of the external gain resistor increases the gain drift of the instrumentation amplifier. Gain error and gain drift are kept to a minimum when the gain resistor is not used. Grounding The output voltage of the AD8220 is developed with respect to the potential on the reference terminal. Care should be taken to tie REF to the appropriate local ground (see Figure 59). In mixed-signal environments, low level analog signals need to be isolated from the noisy digital environment. Many ADCs have separate analog and digital ground pins. Although it is convenient to tie both grounds to a single ground plane, the current traveling through the ground wires and PC board can cause a large error. Therefore, separate analog and digital ground returns should be used to minimize the current flow from sensitive points to the system ground. LAYOUT Careful board layout maximizes system performance. In applications that need to take advantage of the low input bias current of the AD8220, avoid placing metal under the input path to minimize leakage current. To maintain high CMRR over frequency, lay out the input traces symmetrically and lay out the traces of the RG resistor symmetrically. Ensure that the traces maintain resistive and capacitive balance; this holds for additional PCB metal layers under the input and RG pins. Traces from the Figure 57. Example Layout—Top Layer of the AD8220 Evaluation Board 03579-101 Figure 58. Example Layout—Bottom Layer of the AD8220 Evaluation Board Rev. B | Page 20 of 28 03579-102 AD8220 REFERENCE TERMINAL The reference terminal, REF, is at one end of a 20 kΩ resistor (see Figure 55). The output of the instrumentation amplifier is referenced to the voltage on the REF terminal; this is useful when the output signal needs to be offset to voltages other than common. For example, a voltage source can be tied to the REF pin to level-shift the output so that the AD8220 can interface with an ADC. The allowable reference voltage range is a function of the gain, common-mode input, and supply voltages. The REF pin should not exceed either +VS or −VS by more than 0.5 V. For best performance, especially in cases where the output is not measured with respect to the REF terminal, source impedance to the REF terminal should be kept low, because parasitic resistance can adversely affect CMRR and gain accuracy. INPUT BIAS CURRENT RETURN PATH The AD8220 input bias current is extremely small at less than 10 pA. Nonetheless, the input bias current must have a return path to common. When the source, such as a transformer, cannot provide a return current path, one should be created (see Figure 60). +V S AD8220 REF POWER SUPPLY REGULATION AND BYPASSING The AD8220 has high PSRR. However, for optimal performance, a stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. As in all linear circuits, bypass capacitors must be used to decouple the amplifier. A 0.1 μF capacitor should be placed close to each supply pin. A 10 μF tantalum capacitor can be used further away from the part (see Figure 59). In most cases, it can be shared by other precision integrated circuits. +VS –VS TRANSFORMER +VS C fHIGH-PASS = 2π1 RC C R AD8220 REF R 0.1µF 10µF 03579-002 –VS AC-COUPLED +IN Figure 60. Creating an IBIAS Path AD8220 –IN REF VOUT LOAD INPUT PROTECTION All terminals of the AD8220 are protected against ESD. (ESD protection is guaranteed to 4 kV, human body model.) In addition, the input structure allows for dc overload conditions a diode drop above the positive supply and a diode drop below the negative supply. Voltages beyond a diode drop of the supplies cause the ESD diodes to conduct and enable current to flow through the diode. Therefore, an external resistor should be used in series with each of the inputs to limit current for voltages above +Vs. In either scenario, the AD8220 safely handles a continuous 6 mA current at room temperature. For applications where the AD8220 encounters extreme overload voltages, as in cardiac defibrillators, external series resistors and low leakage diode clamps, such as BAV199Ls, FJH1100s, or SP720s, should be used. –VS Figure 59. Supply Decoupling, REF and Output Referred to Ground 03579-001 0.1µF 10µF Rev. B | Page 21 of 28 AD8220 RF INTERFERENCE RF rectification is often a problem in applications where there are large RF signals. The problem appears as a small dc offset voltage. The AD8220 by its nature has a 5 pF gate capacitance, CG, at its inputs. Matched series resistors form a natural low-pass filter that reduces rectification at high frequency (see Figure 61). The relationship between external, matched series resistors and the internal gate capacitance is expressed as follows: 0.1µF CC R 4.02kΩ CD R 4.02kΩ CC 1nF 0.1µF –15V 10µF 03579-003 +15V 10µF 1nF +IN 10nF AD8220 REF –IN VOUT FilterFreq DIFF  FilterFreqCM 1 2πRCG 1  2πRCG +15V Figure 62. RFI Suppression COMMON-MODE INPUT VOLTAGE RANGE 10µF 0.1µF R +IN CG –VS VOUT The common-mode input voltage range is a function of the input range and the outputs of Internal Amplifier A1, Internal Amplifier A2, and Internal Amplifier A3, the reference voltage, and the gain. Figure 27 to Figure 30 show common-mode voltage ranges for various supply voltages and gains. DRIVING AN ADC An instrumentation amplifier is often used in front of an ADC to provide CMRR and additional conditioning, such as a voltage level shift and gain (see Figure 63). In this example, a 2.7 nF capacitor and a 1 kΩ resistor create an antialiasing filter for the AD7685. The 2.7 nF capacitor also serves to store and deliver the necessary charge to the switched capacitor input of the ADC. The 1 kΩ series resistor reduces the burden of the 2.7 nF load from the amplifier. However, large source impedance in front of the ADC can degrade THD. The example shown in Figure 63 is for sub-60 kHz applications. For higher bandwidth applications where THD is important, the series resistor needs to be small. At worst, a small series resistor can load the AD8220, potentially causing the output to overshoot or ring. In such cases, a buffer amplifier, such as the AD8615, should be used after the AD8220 to drive the ADC. +5V AD8220 CG –VS REF R –IN 0.1µF 10µF 03579-030 –15V Figure 61. RFI Filtering Without External Capacitors To eliminate high frequency common-mode signals while using smaller source resistors, a low-pass RC network can be placed at the input of the instrumentation amplifier (see Figure 62). The filter limits the input signal bandwidth according to the following relationship: FilterFreq DIFF  FilterFreqCM 1 2πR(2 CD  CC  CG ) 10µF 0.1µF ADR435 +5V +IN 4.7µF 1  2πR(CC  CG ) ±50mV 1.07kΩ Mismatched CC capacitors result in mismatched low-pass filters. The imbalance causes the AD8220 to treat what would have been a common-mode signal as a differential signal. To reduce the effect of mismatched external CC capacitors, select a value of CD greater than 10 times CC. This sets the differential filter frequency lower than the common-mode frequency. AD8220 REF –IN +2.5V 1kΩ 2.7nF AD7685 Figure 63. Driving an ADC in a Low Frequency Application Rev. B | Page 22 of 28 03579-033 AD8220 APPLICATIONS INFORMATION AC-COUPLED INSTRUMENTATION AMPLIFIER Measuring small signals that are in the noise or offset of the amplifier can be a challenge. Figure 64 shows a circuit that can improve the resolution of small ac signals. The large gain reduces the referred input noise of the amplifier to 14 nV/√Hz. Therefore, smaller signals can be measured because the noise floor is lower. DC offsets that would have been gained by 100 are eliminated from the AD8220 output by the integrator feedback network. At low frequencies, the OP1177 forces the AD8220 output to 0 V. Once a signal exceeds fHIGH-PASS, the AD8220 outputs the amplified input signal. +VS 0.1µF DIFFERENTIAL OUTPUT In certain applications, it is necessary to create a differential signal. New high resolution ADCs often require a differential input. In other cases, transmission over a long distance can require differential processing for better immunity to interference. Figure 65 shows how to configure the AD8220 to output a differential signal. An OP1177 op amp is used to create a differential voltage. Errors from the op amp are common to both outputs and are thus common mode. Likewise, errors from using mismatched resistors cause a common-mode dc offset error. Such errors are rejected in differential signal processing by differential input ADCs or instrumentation amplifiers. When using this circuit to drive a differential ADC, VREF can be set using a resistor divider from the reference of the ADC to make the output ratiometric with the ADC as shown in Figure 66. +IN R 499Ω –IN fHIGH-PASS = 1 2πRC AD8220 REF C 1µF +VS R 15.8kΩ 0.1µF –VS 0.1µF OP1177 +VS 10µF –VS 03579-004 10µF 0.1µF –VS VREF Figure 64. AC-Coupled Circuit Rev. B | Page 23 of 28 AD8220 +15V AMPLITUDE +5V TIME +IN 0.1µF –5V VOUTA = +VIN + VREF ±5V –IN AD8220 REF 4.99kΩ 2 AMPLITUDE +5.0V +2.5V +0V TIME 0.1µF –15V 4.99kΩ 0.1µF 0.1µF +15V AMPLITUDE +5.0V +2.5V +0V TIME 03579-008 +5V 10µF –15V OP1177 VREF 2.5V VOUTB = –VIN + VREF 2 Figure 65. Differential Output with Level Shift +15V 0.1µF TIME +IN VOUTA = +VIN + VREF ±5V –IN AD8220 REF 4.99kΩ VREF 2.5V 2 TO 0V TO +5V ADC +5V FROM REFERENCE 4.99kΩ +AIN –AIN REF +5V FROM REFERENCE 0.1µF –15V 4.99kΩ 0.1µF +5V 10µF –15V OP1177 +15V 0.1µF 4.99kΩ 10nF TO 0V TO +5V ADC VOUTB = –VIN + VREF 2 03579-031 Figure 66. Configuring the AD8220 to Output A Ratiometric, Differential Signal Rev. B | Page 24 of 28 AD8220 ELECTROCARDIOGRAM SIGNAL CONDITIONING The AD8220 makes an excellent input amplifier for next generation ECGs. Its small size, high CMRR over frequency, rail-to-rail output, and JFET inputs are well suited for this application. Potentials measured on the skin range from 0.2 mV to 2 mV. The AD8220 solves many of the typical challenges of measuring these body surface potentials. The high CMRR of the AD8220 helps reject common-mode signals that come in the form of line noise or high frequency EMI from equipment in the operating room. Its rail-to-rail output offers a wide dynamic range allowing for higher gains than would be possible using other instrumentation amplifiers. JFET inputs offer a large input capacitance of 5 pF. A natural RC filter is formed reducing high frequency noise when series input resistors are used in front of the AD8220 (see the RF Interference section). In addition, the AD8220 JFET inputs have ultralow input bias current and no current noise, making it useful for ECG applications where there are often large impedances. The MSOP and the optimal pinout of the AD8220 allow smaller footprints and more efficient layout, paving the way for next-generation portable ECGs. Figure 67 shows an example ECG schematic. Following the AD8220 is a 0.033 Hz high-pass filter, formed by the 4.7 μF capacitor and the 1 MΩ resistor, which removes the dc offset that develops between the electrodes. An additional gain of 50, provided by the AD8618, makes use of the 0 V to 5 V input range of the ADC. An active, fifth-order, low-pass Bessel filter removes signals greater than approximately 160 Hz. An OP2177 buffers, inverts, and gains the common-mode voltage taken at the midpoint of the AD8220 gain setting resistors. This rightleg drive circuit helps cancel common-mode signals by inverting the common-mode signal and driving it back into the body. A 499 kΩ series resistor at the output of the OP2177 limits the current driven into the body. +5V 2.2pF A B 15kΩ 10kΩ 10pF 10kΩ 2.2pF –5V C –5V +5V INSTRUMENTATION AMPLIFIER G = +14 G = +50 2.5V 1.18kΩ 57.6kΩ 14kΩ LOW-PASS FIFTH ORDER FILTER AT 157Hz 14kΩ 47nF 19.3kΩ 33nF 14.5kΩ 68nF AD8220 24.9kΩ 4.12kΩ 24.9kΩ HIGH-PASS FILTER 0.033Hz +5V +5V AD8618 +5V 19.3kΩ 14.5kΩ 1.15kΩ 33nF 4.99kΩ AD8618 +5V 500Ω 2.7nF +5V AD7685 ADC REF +5V 4.7µF 4.7µF –5V +5V 220pF 1MΩ AD8618 AD8618 22nF 2.5V REFERENCE ADR435 OP2177 –5V OP AMPS 68pF 866kΩ +5V 499kΩ –5V 12.7kΩ 2.5V 2.5V 2.5V OP2177 03579-032 Figure 67. Example ECG Schematic Rev. B | Page 25 of 28 AD8220 OUTLINE DIMENSIONS 3.20 3.00 2.80 3.20 3.00 2.80 PIN 1 IDENTIFIER 8 5 1 5.15 4.90 4.65 4 0.65 BSC 0.95 0.85 0.75 0.15 0.05 COPLANARITY 0.10 0.40 0.25 15° MAX 1.10 MAX 0.23 0.09 0.80 0.55 0.40 100709-B 6° 0° COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 68. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model1, 2 AD8220ARMZ AD8220ARMZ-RL AD8220ARMZ-R7 AD8220BRMZ AD8220BRMZ-RL AD8220BRMZ-R7 AD8220WARMZ AD8220WARMZ-RL AD8220WARMZ-R7 1 2 3 Temperature Range3 −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 8-Lead MSOP 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel 8-Lead MSOP 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel 8-Lead MSOP 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel Package Option RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 Branding H01 H01 H01 H0P H0P H0P Y2D Y2D Y2D Z = RoHS Compliant Part. W = Qualified for Automotive Applications. See the Typical Performance Characteristics section for expected operation from 85°C to 125°C. AUTOMOTIVE PRODUCTS The AD8220W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. B | Page 26 of 28 AD8220 NOTES Rev. B | Page 27 of 28 AD8220 NOTES ©2006–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03579-0-5/10(B) Rev. B | Page 28 of 28