AD8226

Wide Supply Range, Rail-to-Rail Output Instrumentation Amplifier AD8226 FEATURES Gain set with 1 external resistor Gain range: 1 to 1000 Input voltage goes below ground Inputs protected beyond supplies Very wide power supply range Single supply: 2.2 V to 36 V Dual supplies: ±1.35 V to ±18 V Bandwidth (G = 1): 1.5 MHz CMRR (G = 1): 90 dB minimum for BR models Input noise: 22 nV/√Hz Typical supply current: 350 μA Specified temperature: −40°C to +125°C 8-lead SOIC and MSOP packages PIN CONFIGURATION –IN RG RG +IN 1 2 3 4 AD8226 8 7 6 5 +VS VOUT REF –VS 07036-001 TOP VIEW (Not to Scale) Figure 1. Table 1. Instrumentation Amplifiers by Category1 General Purpose AD8220 AD8221 AD8222 AD8224 AD8228 AD8295 1 APPLICATIONS Industrial process controls Bridge amplifiers Medical instrumentation Portable data acquisition Multichannel systems Zero Drift AD8231 AD8290 AD8293 AD8553 AD8556 AD8557 Military Grade AD620 AD621 AD524 AD526 AD624 Low Power AD627 AD623 AD8223 AD8226 AD8227 High Speed PGA AD8250 AD8251 AD8253 Visit www.analog.com for the latest instrumentation amplifiers. GENERAL DESCRIPTION The AD8226 is a low cost, wide supply range instrumentation amplifier that requires only one external resistor to set any gain between 1 and 1000. The AD8226 is designed to work with a variety of signal voltages. A wide input range and rail-to-rail output allow the signal to make full use of the supply rails. Because the input range also includes the ability to go below the negative supply, small signals near ground can be amplified without requiring dual supplies. The AD8226 operates on supplies ranging from ±1.35 V to ±18 V for dual supplies and 2.2 V to 36 V for single supply. The robust AD8226 inputs are designed to connect to realworld sensors. In addition to its wide operating range, the AD8226 can handle voltages beyond the rails. For example, with a ±5 V supply, the part is guaranteed to withstand ±35 V at the input with no damage. Minimum as well as maximum input bias currents are specified to facilitate open wire detection. The AD8226 is perfect for multichannel, space-constrained industrial applications. Unlike other low cost, low power instrumentation amplifiers, the AD8226 is designed with a minimum gain of 1 and can easily handle ±10 V signals. With its MSOP package and 125°C temperature rating, the AD8226 thrives in tightly packed, zero airflow designs. The AD8226 is available in 8-lead MSOP and SOIC packages, and is fully specified for −40°C to +125°C operation. For a device with a similar package and performance as the AD8226 but with gain settable from 5 to 1000, consider using the AD8227. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. AD8226 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  Pin Configuration ............................................................................. 1  General Description ......................................................................... 1  Revision History ............................................................................... 2  Specifications..................................................................................... 3  Absolute Maximum Ratings............................................................ 7  Thermal Resistance ...................................................................... 7  ESD Caution .................................................................................. 7  Pin Configuration and Function Descriptions ............................. 8  Typical Performance Characteristics ............................................. 9  Theory of Operation ...................................................................... 19  Architecture................................................................................. 19  Gain Selection ............................................................................. 19  Reference Terminal .................................................................... 20  Input Voltage Range ................................................................... 20  Layout .......................................................................................... 20  Input Bias Current Return Path ............................................... 21  Input Protection ......................................................................... 22  Radio Frequency Interference (RFI) ........................................ 22  Applications Information .............................................................. 23  Differential Drive ....................................................................... 23  Precision Strain Gage ................................................................. 24  Driving an ADC ......................................................................... 24  Outline Dimensions ....................................................................... 25  Ordering Guide .......................................................................... 25  REVISION HISTORY 7/09—Rev. 0 to Rev. A Added BRZ and BRM Models .......................................... Universal Changes to Features Section............................................................ 1 Changes to Table 1 ............................................................................ 1 Changes to General Description Section ...................................... 1 Changes to Gain vs. Temperature Parameter, Output Parameter, and Operating Range Parameter, Table 2 ......................................... 4 Changes to Common-Mode Rejection Ratio (CMRR) Parameter and to Input Offset, VOSO, Average Temperature Coefficient Parameter, Table 3 ........................................................................ 5 Changes to Gain vs. Temperature Parameter, Table 3 ................. 6 Changes to Gain Selection Section............................................... 19 Changes to Reference Terminal Section and Input Voltage Range Section .............................................................................. 20 Changes to Ordering Guide .......................................................... 25 1/09—Revision 0: Initial Version Rev. A | Page 2 of 28 AD8226 SPECIFICATIONS +VS = +15 V, −VS = −15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, specifications referred to input, unless otherwise noted. Table 2. Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR with DC to 60 Hz G=1 G = 10 G = 100 G = 1000 CMRR with DC at 5 kHz G=1 G = 10 G = 100 G = 1000 NOISE Voltage Noise Input Voltage Noise, eNI Output Voltage Noise, eNO RTI G=1 G = 10 G = 100 to 1000 Current Noise VOLTAGE OFFSET Input Offset, VOSI Average Temperature Coefficient Output Offset, VOSO Average Temperature Coefficient Offset RTI vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current 1 Conditions VCM = −10 V to +10 V Min ARZ, ARMZ Typ Max Min BRZ, BRMZ Typ Max Unit 80 100 105 105 80 90 90 100 Total noise: eN = √(eNI2 + (eNO/G)2) 1 kHz 22 120 f = 0.1 Hz to 10 Hz 2 0.5 0.4 100 3 24 125 90 105 110 110 80 90 90 100 dB dB dB dB dB dB dB dB 22 120 2 0.5 0.4 100 3 24 125 nV/√Hz nV/√Hz μV p-p μV p-p μV p-p fA/√Hz pA p-p f = 1 kHz f = 0.1 Hz to 10 Hz Total offset voltage: VOS = VOSI + (VOSO/G) VS = ±5 V to ±15 V TA = −40°C to +125°C VS = ±5 V to ±15 V TA = −40°C to +125°C VS = ±5 V to ±15 V 80 100 105 105 TA = +25°C TA = +125°C TA = −40°C TA = −40°C to +125°C TA = +25°C TA = +125°C TA = −40°C TA = −40°C to +125°C 5 5 5 0.5 2 200 2 1000 10 90 105 110 110 0.5 1 100 1 500 5 μV μV/°C μV μV/°C dB dB dB dB Average Temperature Coefficient Input Offset Current 20 15 30 70 27 25 35 1.5 1.5 2 5 5 5 20 15 30 70 27 25 35 0.5 0.5 0.5 Average Temperature Coefficient REFERENCE INPUT RIN IIN Voltage Range Reference Gain to Output Reference Gain Error DYNAMIC RESPONSE Small-Signal −3 dB Bandwidth G=1 G = 10 G = 100 G = 1000 5 100 7 −VS 1 0.01 +VS −VS 5 100 7 +VS 1 0.01 nA nA nA pA/°C nA nA nA pA/°C kΩ μA V V/V % 1500 160 20 2 Rev. A | Page 3 of 28 1500 160 20 2 kHz kHz kHz kHz AD8226 Parameter Settling Time 0.01% G=1 G = 10 G = 100 G = 1000 Slew Rate GAIN Gain Range Gain Error G=1 G = 5 to 1000 Gain Nonlinearity G = 1 to 10 G = 100 G = 1000 Gain vs. Temperature 2 G=1 G>1 INPUT Input Impedance Differential Common Mode Input Operating Voltage Range 3 Conditions 10 V step Min ARZ, ARMZ Typ Max 25 15 40 350 0.4 0.6 1 VOUT ±10 V 0.04 0.3 VOUT = −10 V to +10 V RL ≥ 2 kΩ RL ≥ 2 kΩ RL ≥ 2 kΩ TA = −40°C to +85°C TA = 85°C to 125°C TA = −40°C to +125°C VS = ±1.35 V to +36 V 0.8||2 0.4||2 TA = +25°C TA = +125°C TA = −40°C TA = −40°C to +125°C −VS − 0.1 −VS − 0.05 −VS − 0.15 +VS − 40 +VS − 0.8 +VS − 0.6 +VS − 0.9 −VS + 40 −VS − 0.1 −VS − 0.05 −VS − 0.15 +VS − 40 10 75 750 5 5 −100 0.01 0.1 10 75 750 1 2 −100 % % ppm ppm ppm ppm/°C ppm/°C ppm/°C 1000 1 Min BRZ, BRMZ Typ Max 25 15 40 350 0.4 0.6 1000 Unit μs μs μs μs V/μs V/μs V/V G=1 G = 5 to 100 G = 1 + (49.4 kΩ/RG) 0.8||2 0.4||2 +VS − 0.8 +VS − 0.6 +VS − 0.9 −VS + 40 Input Overvoltage Range OUTPUT Output Swing RL = 2 kΩ to Ground GΩ||pF GΩ||pF V V V V TA = +25°C TA = +125°C TA = −40°C RL = 10 kΩ to Ground TA = +25°C TA = +125°C TA = −40°C RL = 100 kΩ to Ground TA = −40°C to +125°C Short-Circuit Current POWER SUPPLY Operating Range Quiescent Current −VS + 0.4 −VS + 0.4 −VS + 1.2 −VS + 0.2 −VS + 0.3 −VS + 0.2 −VS + 0.1 13 +VS − 0.7 +VS – 1.0 +VS – 1.1 +VS − 0.2 +VS − 0.3 +VS − 0.2 +VS − 0.1 −VS + 0.4 −VS + 0.4 −VS + 1.2 −VS + 0.2 −VS + 0.3 −VS + 0.2 −VS + 0.1 13 +VS − 0.7 +VS – 1.0 +VS – 1.1 +VS − 0.2 +VS − 0.3 +VS − 0.2 +VS − 0.1 V V V V V V V mA V μA μA μA μA °C Dual-supply operation TA = +25°C TA = −40°C TA = +85°C TA = +125°C ±1.35 350 250 450 525 −40 TEMPERATURE RANGE 1 2 ±18 425 325 525 600 +125 ±1.35 350 250 450 525 −40 ±18 425 325 525 600 +125 The input stage uses pnp transistors; therefore, input bias current always flows into the part. The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG. 3 Input voltage range of the AD8226 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage. See the Input Voltage Range section for more information. Rev. A | Page 4 of 28 AD8226 +VS = 2.7 V, −VS = 0 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, specifications referred to input, unless otherwise noted. Table 3. Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR with DC to 60 Hz G=1 G = 10 G = 100 G = 1000 CMRR with DC at 5 kHz G=1 G = 10 G = 100 G = 1000 NOISE Voltage Noise Input Voltage Noise, eNI Output Voltage Noise, eNO RTI G=1 G = 10 G = 100 to 1000 Current Noise VOLTAGE OFFSET Input Offset, VOSI Average Temperature Coefficient Output Offset, VOSO Average Temperature Coefficient Offset RTI vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current 1 Conditions VCM = 0 V to 1.7 V Min ARZ, ARMZ Typ Max Min BRZ, BRMZ Typ Max Unit 80 100 105 105 80 90 90 100 Total noise: eN = √(eNI2 + (eNO/G2)) 1 kHz 22 120 f = 0.1 Hz to 10 Hz 2.0 0.5 0.4 100 3 200 2 1000 10 24 125 90 105 110 110 80 90 90 100 dB dB dB dB dB dB dB dB 22 120 2.0 0.5 0.4 100 3 24 125 nV/√Hz nV/√Hz μV p-p μV p-p μV p-p fA/√Hz pA p-p f = 1 kHz f = 0.1 Hz to 10 Hz Total offset voltage: VOS = VOSI + (VOSO/G) TA = −40°C to +125°C TA = −40°C to +125°C VS = 0 V to 1.7 V 80 100 105 105 TA = +25°C TA = +125°C TA = −40°C TA = −40°C to +125°C TA = +25°C TA = +125°C TA = −40°C TA =−40°C to +125°C 5 5 5 0.5 2 0.5 1 90 105 110 110 100 1 500 5 μV μV/°C μV μV/°C dB dB dB dB Average Temperature Coefficient Input Offset Current 20 15 30 70 27 25 35 1.5 1.5 1 5 5 5 20 15 30 70 27 25 35 0.5 0.5 0.1 Average Temperature Coefficient REFERENCE INPUT RIN IIN Voltage Range Reference Gain to Output Reference Gain Error DYNAMIC RESPONSE Small-Signal −3 dB Bandwidth G=1 G = 10 G = 100 G = 1000 5 100 7 −VS 1 0.01 +VS −VS 5 100 7 +VS 1 0.01 nA nA nA pA/°C nA nA nA pA/°C kΩ μA V V/V % 1500 160 20 2 1500 160 20 2 kHz kHz kHz kHz Rev. A | Page 5 of 28 AD8226 Parameter Settling Time 0.01% G=1 G = 10 G = 100 G = 1000 Slew Rate GAIN Gain Range Gain Error G=1 G = 5 to 1000 Gain vs. Temperature 2 G=1 G>1 INPUT Input Impedance Differential Common Mode Input Operating Voltage Range 3 Conditions 2 V step Min ARZ, ARMZ Typ Max 6 6 35 350 0.4 0.6 1 VOUT = 0.8 V to 1.8 V VOUT = 0.2 V to 2.5 V TA = −40°C to +85°C TA = +85°C to +125°C TA = −40°C to +125°C −VS = 0 V, +VS = 2.7 V to 36 V 0.8||2 0.4||2 TA = +25°C TA = −40°C TA = +125°C TA = −40°C to +125°C RL = 10 kΩ to 1.35 V, TA = −40°C to +125°C −0.1 −0.15 −0.05 +VS − 40 0.1 13 Single-supply operation TA = +25°C, −VS = 0 V, +VS = 2.7 V TA = −40°C, −VS = 0 V, +VS = 2.7 V TA = +85°C, −VS = 0 V, +VS = 2.7 V TA = +125°C, −VS = 0 V, +VS = 2.7 V 2.2 325 250 425 475 −40 36 400 325 500 550 +125 2.2 325 250 425 475 −40 +VS − 0.7 +VS − 0.9 +VS − 0.6 −VS + 40 +VS − 0.1 −0.1 −0.15 −0.05 +VS − 40 0.1 13 36 400 325 500 550 +125 1000 0.04 0.3 5 5 −100 1 Min BRZ, BRMZ Typ Max 6 6 35 350 0.4 0.6 1000 0.01% 0.1% 1 2 Unit μs μs μs μs V/μs V/μs V/V % % ppm/°C ppm/°C ppm/°C G=1 G = 5 to 100 G = 1 + (49.4 kΩ/RG) 0.8||2 0.4||2 +VS − 0.7 +VS − 0.9 +VS − 0.6 −VS + 40 +VS − 0.1 GΩ||pF GΩ||pF V V V Input Overvoltage Range OUTPUT Output Swing Short-Circuit Current POWER SUPPLY Operating Range Quiescent Current V mA V μA μA μA μA °C TEMPERATURE RANGE 1 2 Input stage uses pnp transistors; therefore, input bias current always flows into the part. The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG. 3 Input voltage range of the AD8226 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage. See the Input Voltage Range section for more information. Rev. A | Page 6 of 28 AD8226 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Supply Voltage Output Short-Circuit Current Maximum Voltage at −IN or +IN Minimum Voltage at −IN or +IN REF Voltage Storage Temperature Range Specified Temperature Range Maximum Junction Temperature ESD Human Body Model Charge Device Model Machine Model Rating ±18 V Indefinite −VS + 40 V +VS − 40 V ±VS −65°C to +150°C −40°C to +125°C 140°C 1.5 kV 1.5 kV 100 V THERMAL RESISTANCE θJA is specified for a device in free air. Table 5. Thermal Resistance Package 8-Lead MSOP, 4-Layer JEDEC Board 8-Lead SOIC, 4-Layer JEDEC Board θJA 135 121 Unit °C/W °C/W ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 7 of 28 AD8226 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS –IN RG RG +IN 1 2 3 4 AD8226 8 7 6 5 +VS VOUT REF –VS 07036-002 TOP VIEW (Not to Scale) Figure 2. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2, 3 4 5 6 7 8 Mnemonic −IN RG +IN −VS REF VOUT +VS Description Negative Input. Gain-Setting Pins. Place a gain resistor between these two pins. Positive Input. Negative Supply. Reference. This pin must be driven by low impedance. Output. Positive Supply. Rev. A | Page 8 of 28 AD8226 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, VS = ±15 V, RL = 10 kΩ, unless otherwise noted. 160 140 200 120 HITS N: 2203 MEAN: 35.7649 SD: 229.378 250 MEAN: 0.041 SD: 0.224 80 60 40 20 07036-031 HITS 100 150 100 50 –900 –600 –300 0 300 VOSO @ ±15V (µV) 600 900 –0.9 –0.6 0 0.3 –0.3 VOSI DRIFT (µV) 0.6 0.9 1.2 Figure 3. Typical Distribution of Output Offset Voltage Figure 6. Typical Distribution of Input Offset Voltage Drift, G = 100 240 210 180 MEAN: –0.57 SD: 1.5762 180 MEAN: 21.5589 SD: 0.624 150 120 150 HITS HITS 120 90 90 60 60 30 30 07036-032 07036-035 07036-036 0 –9 –6 –3 0 3 VOSO DRIFT (µV) 6 9 0 18 20 22 24 POSITIVE IBIAS CURRENT @ ±15V (nA) 26 Figure 4. Typical Distribution of Output Offset Voltage Drift Figure 7. Typical Distribution of Input Bias Current 350 300 MEAN: –3.67283 SD: 51.1 300 MEAN: 0.003 SD: 0.075 250 250 200 200 150 100 50 0 –400 0 200 –200 VOSI @ RG PINS @ ±15V (µV) 400 100 HITS HITS 150 50 07036-033 0 –0.9 –0.6 –0.3 0 0.3 VOSI @ ±15V (nA) 0.6 0.9 Figure 5. Typical Distribution of Input Offset Voltage Figure 8. Typical Distribution of Input Offset Current Rev. A | Page 9 of 28 07036-034 0 0 –1.2 AD8226 2.5 +0.02V, +2.0V 2.5 +1.35V, +1.9V VREF = +1.35V COMMON-MODE VOLTAGE (V) 2.0 +0.02V, +2.0V COMMON-MODE VOLTAGE (V) 2.0 +1.35V, +1.9V VREF = +1.35V 1.5 +0.02V, +1.3V +2.68V, +1.2V 1.5 +0.02V, +1.3V +2.67V, +1.3V +2.4V, +0.8V 1.0 VREF = 0V 0.5 +0.02V, +0.3V +2.68V, +0.3V +2.4V, +0.8V 1.0 VREF = 0V 0.5 +0.02V, +0.4V +2.67V, +0.4V 0 07036-037 +0.02V, –0.4V –1.0 –0.5 0 0.5 2.0 1.0 1.5 OUTPUT VOLTAGE (V) 2.5 3.0 –0.5 –0.5 +0.02V, –0.3V +1.35, –0.3V 0 0.5 2.0 1.0 1.5 OUTPUT VOLTAGE (V) 2.5 3.0 Figure 9. Input Common-Mode Voltage vs. Output Voltage, Single Supply, VS = +2.7 V, G = 1 Figure 12. Input Common-Mode Voltage vs. Output Voltage, Single Supply, VS = +2.7 V, G = 100 5 +0.02V, +4.3V +2.5V, +4.3V 5 VREF = +1.35V COMMON-MODE VOLTAGE (V) +0.02V, +4.3V +2.5V, +4.2V VREF = +2.5V COMMON-MODE VOLTAGE (V) 4 4 3 +0.02V, +3.0V +4.98V, +3.0V 3 +0.02V, +3.0V +4.96V, +3.0V 2 VREF = 0V +4.7V, +1.9V 2 VREF = 0V +4.7V, +1.9V 1 +0.02V, +0.8V +4.98V, +0.8V 1 +0.02V, +0.7V +4.96V, +0.7V 0 07036-038 0 +0.02V, –0.4V +2.5V, –0.4V +0.02V, –0.3V +2.5V, –0.3.V 07036-041 –1 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT VOLTAGE (V) 4.0 4.5 5.0 5.5 –1 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT VOLTAGE (V) 4.0 4.5 5.0 5.5 Figure 10. Input Common-Mode Voltage vs. Output Voltage, Single Supply, VS = +5 V, G = 1 Figure 13. Input Common-Mode Voltage vs. Output Voltage, Single Supply, VS = +5 V, G = 100 6 0V, +4.3V 6 0V, +4.2V COMMON-MODE VOLTAGE (V) COMMON-MODE VOLTAGE (V) 4 4 2 –4.97V, +1.8V +4.96V, +1.8V 2 –4.96V, +1.7V +4.96V, +1.7V 0 0 –2 –4.97V, –3.0V +4.96V, –0.3V –2 –4.96V, –3.1V +4.96V, –3.1V –4 07036-039 –4 0V, –5.4V 0V, –5.3V 07036-042 –6 –6 –4 –2 0 2 OUTPUT VOLTAGE (V) 4 6 –6 –6 –4 –2 0 2 OUTPUT VOLTAGE (V) 4 6 Figure 11. Input Common-Mode Voltage vs. Output Voltage, Dual Supplies, VS = ±5 V, G = 1 Figure 14. Input Common-Mode Voltage vs. Output Voltage, Dual Supplies, VS = ±5 V, G = 100 Rev. A | Page 10 of 28 07036-040 –0.5 0 +1.35V, –0.4V AD8226 20 15 COMMON-MODE VOLTAGE (V) 0V, +14.3V 20 VS = ±15V COMMON-MODE VOLTAGE (V) +14.94V, +6.8V 15 10 5 0 –5 –10 –15 –14.95V, –8.0V +14.95V, +6.7V 0V, +14.2V VS = ±15V +14.95V, +6.7V 10 5 0 –5 –10 –15 +14.96V, +6.8V 0V, +11.3V +11.95V, +5.3V 0V, +11.2V +11.95V, +5.2V –11.95V, +5.3V –11.95V, +5.2V VS = ±12V –11.95V, –6.4V 0V, –12.4V +11.95V, –6.4V VS = ±12V –11.95V, –6.5V 0V, –12.3V +11.95V, –6.5V –14.96V, –7.9V +14.94V, –7.9V +14.95V, –8.0V 07036-043 0V, –15.4V 0V, –15.4V –20 –20 –15 –10 5 –5 0 OUTPUT VOLTAGE (V) 10 15 20 –20 –20 –15 –10 5 –5 0 OUTPUT VOLTAGE (V) 10 15 20 Figure 15. Input Common-Mode Voltage vs. Output Voltage, Dual Supplies, VS = ±15 V, G = 1 Figure 18. Input Common-Mode Voltage vs. Output Voltage, Dual Supplies, VS = ±15 V, G = 100 2.25 2.00 1.75 OUTPUT VOLTAGE (V) 0.6 VS = 2.7V G=1 –VIN = 0V VOUT 0.5 0.4 0.3 2.75 2.50 2.25 VS = 2.7V G = 100 –VIN = 0V 0.6 0.5 0.4 VOUT 0.3 0.2 0.1 0 OUTPUT VOLTAGE (V) INPUT CURRENT (mA) 1.50 1.25 1.00 IIN 0.75 0.50 0.25 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 1.75 1.50 1.25 –0.1 1.00 0.75 0.50 0.25 IIN –0.2 –0.3 –0.4 –0.5 07036-044 Figure 16. Input Overvoltage Performance, G = 1, VS = 2.7 V Figure 19. Input Overvoltage Performance, G = 100, VS = 2.7 V 16 14 12 10 OUTPUT VOLTAGE (V) 0.5 VS = ±15V G=1 –VIN = 0V VOUT 0.4 0.3 INPUT CURRENT (mA) 16 14 12 10 OUTPUT VOLTAGE (V) 0.6 VS = ±15V G = 100 –VIN = 0V VOUT 0.5 0.4 0.3 0.2 0.1 IIN 0 –0.1 –0.2 –0.3 –0.4 –0.5 07036-048 2 0 –2 –4 –6 –8 –10 –12 –14 IIN 0.1 0 –0.1 –0.2 –0.3 –0.4 2 0 –2 –4 –6 –8 –10 –12 –14 Figure 17. Input Overvoltage Performance, G = 1, VS = ±15 V 07036-045 –0.5 –16 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40 INPUT VOLTAGE (V) –0.6 –16 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40 INPUT VOLTAGE (V) Figure 20. Input Overvoltage Performance, G = 100, VS = ±15 V Rev. A | Page 11 of 28 INPUT CURRENT (mA) 8 6 4 0.2 8 6 4 07036-047 0 –0.6 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40 INPUT VOLTAGE (V) 0 –0.6 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40 INPUT VOLTAGE (V) INPUT CURRENT (mA) 2.00 07036-046 AD8226 30 29 28 INPUT BIAS CURRENT (nA) 160 140 –0.15V NEGATIVE PSRR (dB) GAIN = 1000 120 GAIN = 100 GAIN = 10 100 GAIN = 1 80 60 40 20 07036-049 27 26 25 24 23 22 21 20 19 18 17 0 16 –0.5 +4.22V 0.5 1.0 1.5 2.0 2.5 3.0 3.5 COMMON-MODE VOLTAGE (V) 4.0 4.5 1 10 100 1k FREQUENCY (Hz) 10k 100k 1M Figure 21. Input Bias Current vs. Common-Mode Voltage, VS = +5 V Figure 24. Negative PSRR vs. Frequency 50 45 40 INPUT BIAS CURRENT (nA) 70 –15.13V 60 50 40 GAIN = 1000 VS = ±15V 35 30 25 20 15 10 5 0 07036-050 GAIN = 100 GAIN (dB) 30 20 10 0 –10 –20 GAIN = 1 GAIN = 10 +14.18V –12 –8 –4 0 4 8 COMMON-MODE VOLTAGE (V) 12 16 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 22. Input Bias Current vs. Common-Mode Voltage, VS = ±15 V Figure 25. Gain vs. Frequency, VS = ±15 V 160 140 GAIN = 1000 GAIN = 100 120 GAIN = 10 POSITIVE PSRR (dB) 100 80 60 40 GAIN = 1 GAIN (dB) 70 60 50 40 30 20 10 0 –10 GAIN = 1 GAIN = 10 GAIN = 100 GAIN = 1000 VS = 2.7V 20 07036-013 –20 1 10 100 1k FREQUENCY (Hz) 10k 100k 1M 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 23. Positive PSRR vs. Frequency, RTI Figure 26. Gain vs. Frequency, 2.7 V Single Supply Rev. A | Page 12 of 28 07036-016 0 0.1 –30 100 07036-015 –5 –16 –30 100 07036-014 0 0.1 AD8226 160 GAIN = 1000 140 GAIN = 100 35 –IN BIAS CURRENT +IN BIAS CURRENT OFFSET CURRENT VS = ±15V VREF = 0V 150 30 125 INPUT BIAS CURRENT (nA) 120 GAIN = 10 100 GAIN = 1 BANDWIDTH LIMITED 25 100 80 60 40 20 07036-017 20 75 15 50 10 25 1 10 100 1k FREQUENCY (Hz) 10k 100k 0 15 30 45 60 75 TEMPERATURE (°C) 90 Figure 27. CMRR vs. Frequency, RTI Figure 30. Input Bias Current and Input Offset Current vs. Temperature 120 GAIN = 1000 100 GAIN = 1 GAIN = 10 GAIN = 100 BANDWIDTH LIMITED 20 10 0 GAIN ERROR (µV/V) 80 –10 –20 –0.3ppm/°C –30 –0.4ppm/°C –40 –50 –0.6 ppm/°C CMRR (dB) 60 40 20 –60 07036-018 07036-051 07036-052 0 0.1 1 10 100 1k FREQUENCY (Hz) 10k 100k NORMALIZED AT 25°C –70 –60 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 140 Figure 28. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance Figure 31. Gain Error vs. Temperature, G = 1 3.0 CHANGE IN INPUT OFFSET VOLTAGE (µV) 2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 07036-011 20 10 –0.35ppm/°C 0 CMRR (µV/V) –10 0.2ppm/°C –20 –30 REPRESENTATIVE DATA NORMALIZED AT 25°C 0 10 20 30 40 50 60 70 80 90 WARM-UP TIME (Seconds) 100 110 120 –3.0 –40 –50 –30 –10 10 30 50 70 TEMPERATURE (°C) 90 110 130 Figure 29. Change in Input Offset Voltage vs. Warm-Up Time Figure 32. CMRR vs. Temperature, G = 1 Rev. A | Page 13 of 28 07036-012 0 0.1 5 –45 –30 –15 0 105 120 135 INPUT OFFSET CURRENT (pA) CMRR (dB) AD8226 +VS –40°C –0.2 +25°C +85°C +105°C +125°C 15 INPUT VOLTAGE (V) REFERRED TO SUPPLY VOLTAGES OUTPUT VOLTAGE SWING (V) –0.4 –0.6 –0.8 10 –40°C +25°C +85°C +105°C +125°C 5 0 –VS –0.2 –0.4 –0.6 07036-053 –5 –10 2 4 6 8 10 12 SUPPLY VOLTAGE (±VS) 14 16 18 1k 10k LOAD RESISTANCE (Ω) 100k Figure 33. Input Voltage Limit vs. Supply Voltage Figure 36. Output Voltage Swing vs. Load Resistance +VS –0.1 +VS –0.2 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES –0.2 –0.3 –0.4 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES –40°C +25°C +85°C +105°C +125°C –0.4 –0.6 –0.8 –40°C +25°C +85°C +105°C +125°C +0.4 +0.3 +0.2 +0.1 07036-054 +0.8 +0.6 +0.4 +0.2 2 4 6 8 10 12 SUPPLY VOLTAGE (±VS) 14 16 18 100µ 1M OUTPUT CURRENT (A) 10M Figure 34. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ Figure 37. Output Voltage Swing vs. Output Current, G = 1 +VS –0.2 –0.4 8 G=1 6 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES NONLINEARITY (2ppm/DIV) –0.6 –0.8 –1.0 –1.2 +1.2 +1.0 +0.8 +0.6 +0.4 +0.2 –VS 2 –40°C +25°C +85°C +105°C +125°C 4 2 0 –2 –4 –6 07036-055 4 6 8 10 12 SUPPLY VOLTAGE (±VS) 14 16 18 –8 –6 –4 –2 0 2 4 OUTPUT VOLTAGE (V) 6 8 10 Figure 35. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ Figure 38. Gain Nonlinearity, G = 1, RL ≥ 2 kΩ Rev. A | Page 14 of 28 07036-019 –8 –10 07036-057 –VS –VS 10µ 07036-056 –0.8 –15 100 AD8226 8 G = 10 6 1k NONLINEARITY (2ppm/DIV) 4 2 0 –2 –4 –6 07036-020 NOISE (nV/ Hz) GAIN = 1 100 GAIN = 10 GAIN = 100 GAIN = 1000 10 1 10 –8 –6 –4 –2 0 2 4 OUTPUT VOLTAGE (V) 6 8 10 100 1k FREQUENCY (Hz) 10k 100k Figure 39. Gain Nonlinearity, G = 10, RL ≥ 2 kΩ Figure 42. Voltage Noise Spectral Density vs. Frequency 80 G = 100 60 NONLINEARITY (20ppm/DIV) GAIN = 1000, 200nV/DIV 40 20 0 –20 –40 –60 1s/DIV 07036-021 07036-024 GAIN = 1, 1µV/DIV –80 –10 –8 –6 –4 –2 0 2 4 OUTPUT VOLTAGE (V) 6 8 10 Figure 40. Gain Nonlinearity, G = 100, RL ≥ 2 kΩ Figure 43. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1, G = 1000 800 G = 1000 600 NONLINEARITY (100ppm/DIV) 1k 400 200 0 –200 –400 –600 07036-022 07036-058 NOISE (fA/ Hz) 100 –800 –10 10 1 10 100 FREQUENCY (Hz) 1k 10k –8 –6 –4 –2 0 2 4 OUTPUT VOLTAGE (V) 6 8 10 Figure 41. Gain Nonlinearity, G = 1000, RL ≥ 2 kΩ Figure 44. Current Noise Spectral Density vs. Frequency Rev. A | Page 15 of 28 07036-023 –8 –10 BANDWIDTH LIMITED AD8226 5V/DIV 15.46μs TO 0.01% 17.68µs TO 0.001% 0.002%/DIV 07036-025 1.5pA/DIV 1s/DIV 40µs/DIV Figure 45. 0.1 Hz to 10 Hz Current Noise Figure 48. Large-Signal Pulse Response and Settling Time, G = 10, 10 V Step, VS = ±15 V 30 27 24 OUTPUT VOLTAGE (V p-p) VS = ±15V 21 18 15 12 9 6 3 0 100 VS = +5V 07036-059 5V/DIV 39.64μs TO 0.01% 58.04µs TO 0.001% 0.002%/DIV 100µs/DIV 1k 10k FREQUENCY (Hz) 100k 1M Figure 46. Large-Signal Frequency Response Figure 49. Large-Signal Pulse Response and Settling Time, G = 100, 10 V Step, VS = ±15 V 5V/DIV 25.38μs TO 0.01% 26.02µs TO 0.001% 5V/DIV 349.6μs TO 0.01% 529.6µs TO 0.001% 0.002%/DIV 0.002%/DIV 07036-060 40µs/DIV 400µs/DIV Figure 47. Large-Signal Pulse Response and Settling Time, G = 1, 10 V Step, VS = ±15 V Figure 50. Large-Signal Pulse Response and Settling Time, G = 1000, 10 V Step, VS = ±15 V Rev. A | Page 16 of 28 07036-063 07036-062 07036-061 AD8226 07036-026 20mV/DIV 4µs/DIV 20mV/DIV 20µs/DIV Figure 51. Small-Signal Response, G = 1, RL = 10 kΩ, CL = 100 pF Figure 53. Small-Signal Response, G = 100, RL = 10 kΩ, CL = 100 pF 07036-027 20mV/DIV 4µs/DIV 20mV/DIV 100µs/DIV Figure 52. Small-Signal Response, G = 10, RL = 10 kΩ, CL = 100 pF Figure 54. Small-Signal Response, G = 1000, RL = 10 kΩ, CL = 100 pF Rev. A | Page 17 of 28 07036-029 07036-028 AD8226 340 330 SUPPLY CURRENT (µA) NO LOAD RL = 47pF RL = 100pF RL = 147pF 07036-030 320 310 300 20mV/DIV 4µs/DIV 0 2 4 6 8 10 12 SUPPLY VOLTAGE (±VS) 14 16 18 Figure 55. Small-Signal Response with Various Capacitive Loads, G = 1, RL = ∞ Figure 57. Supply Current vs. Supply Voltage 60 50 SETTLING TIME (µs) 40 30 SETTLED TO 0.001% 20 SETTLED TO 0.01% 10 07036-064 0 2 4 6 8 10 12 STEP SIZE (V) 14 16 18 20 Figure 56. Settling Time vs. Step Size, VS = ±15 V Dual Supplies Rev. A | Page 18 of 28 07036-066 290 AD8226 THEORY OF OPERATION +VS NODE 3 RG +VS NODE 4 R3 50kΩ R2 24.7kΩ NODE 2 NODE 1 ESD AND OVERVOLTAGE PROTECTION ESD AND OVERVOLTAGE PROTECTION R5 50kΩ A2 Q2 –IN –VS RB VBIAS –VS GAIN STAGE RB DIFFERENCE AMPLIFIER STAGE 07036-003 R1 24.7kΩ –VS –VS R4 50kΩ A3 +VS R6 50kΩ +VS VOUT –VS REF +IN Q1 A1 Figure 58. Simplified Schematic ARCHITECTURE The AD8226 is based on the classic 3-op-amp topology. This topology has two stages: a preamplifier to provide differential amplification, followed by a difference amplifier to remove the common-mode voltage. Figure 58 shows a simplified schematic of the AD8226. The first stage works as follows: in order to maintain a constant voltage across the bias resistor RB, A1 must keep Node 3 a constant diode drop above the positive input voltage. Similarly, A2 keeps Node 4 at a constant diode drop above the negative input voltage. Therefore, a replica of the differential input voltage is placed across the gain-setting resistor, RG. The current that flows across this resistance must also flow through the R1 and R2 resistors, creating a gained differential signal between the A2 and A1 outputs. Note that, in addition to a gained differential signal, the original common-mode signal, shifted a diode drop up, is also still present. The second stage is a difference amplifier, composed of A3 and four 50 kΩ resistors. The purpose of this stage is to remove the common-mode signal from the amplified differential signal. The transfer function of the AD8226 is VOUT = G(VIN+ − VIN−) + VREF where: GAIN SELECTION Placing a resistor across the RG terminals sets the gain of the AD8226, which can be calculated by referring to Table 7 or by using the following gain equation: RG = 49.4 kΩ G −1 Table 7. Gains Achieved Using 1% Resistors 1% Standard Table Value of RG (Ω) 49.9 k 12.4 k 5.49 k 2.61 k 1.00 k 499 249 100 49.9 Calculated Gain 1.990 4.984 9.998 19.93 50.40 100.0 199.4 495.0 991.0 The AD8226 defaults to G = 1 when no gain resistor is used. The tolerance and gain drift of the RG resistor should be added to the AD8226 specifications to determine the total gain accuracy of the system. When the gain resistor is not used, gain error and gain drift are minimal. If a gain of 5 is required and minimal gain drift is important, consider using the AD8227. The AD8227 has a default gain of 5 that is set with internal resistors. Because all resistors are internal, the gain drift is extremely low ( −V S + V−LIMIT 2 (VDIFF )(G) < +VS − V+ LIMIT 2 (1) (2) (VDIFF )(G) + VCM + VREF 2 < +VS − VREF _ LIMIT 2 Table 8. Input Voltage Range Constants for Various Temperatures Temperature −40°C +25°C +85°C +125°C V−LIMIT −0.55 V −0.35 V −0.15 V −0.05 V V+LIMIT 0.8 V 0.7 V 0.65 V 0.6 V VREF_LIMIT 1.3 V 1.15 V 1.05 V 0.9 V (3) Performance Across Temperature The common-mode input range shifts upward with temperature. At cold temperatures, the part requires extra headroom from the positive supply, and operation near the negative supply has more margin. Conversely, hot temperatures require less headroom from the positive supply, but are the worst-case conditions for input voltages near the negative supply. AD8226 REF V + V AD8226 REF OP1177 – 07036-004 Recommendation for Best Performance A typical part functions up to the boundaries described in this section. However, for best performance, designing with a few hundred millivolts extra margin is recommended. As signals approach the boundary, internal transistors begin to saturate, which can affect frequency and linearity performance. If the application requirements exceed the boundaries, one solution is to apply less gain with the AD8226, and then apply additional gain later in the signal chain. Another option is to use the pin-compatible AD8227. Figure 59. Driving the Reference Pin INPUT VOLTAGE RANGE Figure 9 through Figure 15 and Figure 18 show the allowable common-mode input voltage ranges for various output voltages and supply voltages. The 3-op-amp architecture of the AD8226 applies gain in the first stage before removing common-mode voltage with the difference amplifier stage. Internal nodes between the first and second stages (Node 1 and Node 2 in Figure 58) experience a combination of a gained signal, a common-mode signal, and a diode drop. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not limited. For most applications, Figure 9 through Figure 15 and Figure 18 provide sufficient information to achieve a good design. For applications where a more detailed understanding is needed, Equation 1 to Equation 3 can be used to understand how the gain (G), common-mode input voltage (VCM), differential input voltage (VDIFF), and reference voltage (VREF) interact. The values for the constants, V−LIMIT, V+LIMIT, and VREF_LIMIT, are shown in Table 8. These three formulas, along with the input and output range specifications in Table 2 and Table 3, set the operating boundaries of the part. LAYOUT To ensure optimum performance of the AD8226 at the PCB level, care must be taken in the design of the board layout. The AD8226 pins are arranged in a logical manner to aid in this task. –IN 1 RG 2 RG 3 +IN 4 8 +VS 7 VOUT 6 REF TOP VIEW (Not to Scale) Figure 60. Pinout Diagram Rev. A | Page 20 of 28 07036-005 AD8226 5 –VS AD8226 Common-Mode Rejection Ratio Over Frequency Poor layout can cause some of the common-mode signals to be converted to differential signals before reaching the in-amp. Such conversions occur when one input path has a frequency response that is different from the other. To keep CMRR across frequency high, the input source impedance and capacitance of each path should be closely matched. Additional source resistance in the input path (for example, for input protection) should be placed close to the in-amp inputs, which minimizes their interaction with parasitic capacitance from the PCB traces. Parasitic capacitance at the gain-setting pins can also affect CMRR over frequency. If the board design has a component at the gain-setting pins (for example, a switch or jumper), the part should be chosen so that the parasitic capacitance is as small as possible. INPUT BIAS CURRENT RETURN PATH The input bias current of the AD8226 must have a return path to ground. When the source, such as a thermocouple, cannot provide a return current path, one should be created, as shown in Figure 62. INCORRECT +VS CORRECT +VS AD8226 REF AD8226 REF –VS TRANSFORMER +VS –VS TRANSFORMER +VS Power Supplies A stable dc voltage should be used to power the instrumentation amplifier. Note that noise on the supply pins can adversely affect performance. For more information, see the PSRR performance curves in Figure 23 and Figure 24. A 0.1 μF capacitor should be placed as close as possible to each supply pin. As shown in Figure 61, a 10 μF tantalum capacitor can be used farther away from the part. In most cases, it can be shared by other precision integrated circuits. +VS C AD8226 REF 10MΩ –VS THERMOCOUPLE AD8226 REF –VS THERMOCOUPLE +VS C +VS 0.1µF +IN 10µF AD8226 C fHIGH-PASS = 2π1 RC REF C R AD8226 REF AD8226 –IN REF VOUT LOAD –VS R –VS CAPACITIVELY COUPLED 07036-007 CAPACITIVELY COUPLED Figure 62. Creating an IBIAS Path –VS 07036-006 0.1µF 10µF Figure 61. Supply Decoupling, REF, and Output Referred to Local Ground References The output voltage of the AD8226 is developed with respect to the potential on the reference terminal. Care should be taken to tie REF to the appropriate local ground. Rev. A | Page 21 of 28 AD8226 INPUT PROTECTION The AD8226 has very robust inputs and typically does not need additional input protection. Input voltages can be up to 40 V from the opposite supply rail. For example, with a +5 V positive supply and a −8 V negative supply, the part can safely withstand voltages from −35 V to 32 V. Unlike some other instrumentation amplifiers, the part can handle large differential input voltages even when the part is in high gain. Figure 16, Figure 17, Figure 19, and Figure 20 show the behavior of the part under overvoltage conditions. The rest of the AD8226 terminals should be kept within the supplies. All terminals of the AD8226 are protected against ESD. For applications where the AD8226 encounters voltages beyond the allowed limits, external current-limiting resistors and lowleakage diode clamps such as the BAV199L, the FJH1100s, or the SP720 should be used. 0.1µF CC 1nF R 4.02kΩ CD 10nF R 4.02kΩ CC 1nF 0.1µF –VS 10µF 07036-008 +VS 10µF +IN VOUT REF –IN RG AD8226 Figure 63. RFI Suppression RADIO FREQUENCY INTERFERENCE (RFI) RF rectification is often a problem when amplifiers are used in applications having strong RF signals. The disturbance can appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass RC network placed at the input of the instrumentation amplifier, as shown in Figure 63. The filter limits the input signal bandwidth according to the following relationship: CD affects the difference signal and CC affects the common-mode signal. Values of R and CC should be chosen to minimize RFI. Mismatch between the R × CC at the positive input and the R × CC at the negative input degrades the CMRR of the AD8226. By using a value of CD that is one magnitude larger than CC, the effect of the mismatch is reduced and performance is improved. FilterFrequency DIFF = FilterFrequency CM = where CD ≥ 10 CC. 1 2πR(2C D + C C ) 1 2πRC C Rev. A | Page 22 of 28 AD8226 APPLICATIONS INFORMATION DIFFERENTIAL DRIVE +IN Tips for Best Differential Output Performance For best ac performance, an op amp with at least a 2 MHz gain bandwidth and a 1 V/μs slew rate is recommended. Good choices for op amps are the AD8641, AD8515, and AD820. Keep trace lengths from the resistors to the inverting terminal of the op amp as short as possible. Excessive capacitance at this node can cause the circuit to be unstable. If capacitance cannot be avoided, use lower value resistors. For best linearity and ac performance, a minimum positive supply voltage (+VS) is required. Table 9 shows the minimum supply voltage required for optimum performance. In this mode, VCM_MAX indicates the maximum common-mode voltage expected at the input of the AD8226. Table 9. Minimum Positive Supply Voltage Temperature Less than −10°C −10°C to 25°C More than 25°C Equation +VS > ( VCM_MAX + VBIAS)/2 + 1.4 V +VS > ( VCM_MAX + VBIAS)/2 + 1.25 V +VS > ( VCM_MAX + VBIAS)/2 + 1.1 V AD8226 –IN REF R VBIAS +OUT R + – OP AMP RECOMMENDED OP AMPS: AD8515, AD8641, AD820. RECOMMENDED R VALUES: 5kΩ to 20kΩ. Figure 64. Differential Output Using an Op Amp Figure 64 shows how to configure the AD8226 for differential output. The differential output is set by the following equation: VDIFF_OUT = VOUT+ − VOUT− = Gain × (VIN+ − VIN−) The common-mode output is set by the following equation: VCM_OUT = (VOUT+ − VOUT−)/2= VBIAS The advantage of this circuit is that the dc differential accuracy depends on the AD8226, not on the op amp or the resistors. In addition, this circuit takes advantage of the precise control that the AD8226 has of its output voltage relative to the reference voltage. Although the dc performance and resistor matching of the op amp affect the dc common-mode output accuracy, such errors are likely to be rejected by the next device in the signal chain and therefore typically have little effect on overall system accuracy. 07036-009 –OUT Rev. A | Page 23 of 28 AD8226 PRECISION STRAIN GAGE The low offset and high CMRR over frequency of the AD8226 make it an excellent candidate for performing bridge measurements. The bridge can be connected directly to the inputs of the amplifier (see Figure 65). 5V 10µF 350Ω 350Ω +IN 350Ω 350Ω RG –IN + 0.1µF Option 1 shows the minimum configuration required to drive a charge-sampling ADC. The capacitor provides charge to the ADC sampling capacitor while the resistor shields the AD8226 from the capacitance. To keep the AD8226 stable, the RC time constant of the resistor and capacitor needs to stay above 5 μs. This circuit is mainly useful for lower frequency signals. Option 2 shows a circuit for driving higher speed signals. It uses a precision op amp (AD8616) with relatively high bandwidth and output drive. This amplifier can drive a resistor and capacitor with a much higher time constant and is therefore suited for higher frequency applications. AD8226 – 07036-010 2.5V Figure 65. Precision Strain Gage DRIVING AN ADC Figure 66 shows several methods for driving an ADC. The ADuC7026 microcontroller was chosen for this example because it contains ADCs with an unbuffered, charge-sampling architecture that is typical of most modern ADCs. This type of architecture typically requires an RC buffer stage between the ADC and amplifier to work correctly. Option 3 is useful for applications where the AD8226 needs to run off a large voltage supply but drive a single-supply ADC. In normal operation, the AD8226 output stays within the ADC range, and the AD8616 simply buffers it. However, in a fault condition, the output of the AD8226 may go outside the supply range of both the AD8616 and the ADC. This is not an issue in the circuit, however, because the 10 kΩ resistor between the two amplifiers limits the current into the AD8616 to a safe level. OPTION 1: DRIVING LOW FREQUENCY SIGNALS 3.3V 3.3V AD8226 REF 100Ω 100nF AVDD ADC0 ADuC7026 OPTION 2: DRIVING HIGH FREQUENCY SIGNALS 3.3V 3.3V AD8226 REF 10Ω AD8616 10nF ADC1 OPTION 3: PROTECTING ADC FROM LARGE VOLTAGES +15V 3.3V AD8226 REF 10kΩ 10Ω AD8616 10nF ADC2 07036-065 AGND –15V Figure 66. Driving an ADC Rev. A | Page 24 of 28 AD8226 OUTLINE DIMENSIONS 3.20 3.00 2.80 3.20 3.00 2.80 8 5 1 5.15 4.90 4.65 4 PIN 1 0.65 BSC 0.95 0.85 0.75 0.15 0.00 0.38 0.22 SEATING PLANE 1.10 MAX 8° 0° 0.80 0.60 0.40 0.23 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 67. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 8 5 4 4.00 (0.1574) 3.80 (0.1497) 1 6.20 (0.2441) 5.80 (0.2284) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.50 (0.0196) 0.25 (0.0099) 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 45° 0.51 (0.0201) 0.31 (0.0122) COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 68. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model AD8226ARMZ 1 AD8226ARMZ-RL1 AD8226ARMZ-R71 AD8226ARZ1 AD8226ARZ-RL1 AD8226ARZ-R71 AD8226BRMZ1 AD8226BRMZ-RL1 AD8226BRMZ-R71 AD8226BRZ1 AD8226BRZ-RL1 AD8226BRZ-R71 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 8-Lead MSOP 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N, 13" Tape and Reel 8-Lead SOIC_N, 7" Tape and Reel 8-Lead MSOP 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N, 13" Tape and Reel 8-Lead SOIC_N, 7" Tape and Reel Package Option RM-8 RM-8 RM-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 R-8 R-8 R-8 012407-A Branding Y18 Y18 Y18 Y19 Y19 Y19 Z = RoHS Compliant Part. Rev. A | Page 25 of 28 AD8226 NOTES Rev. A | Page 26 of 28 AD8226 NOTES Rev. A | Page 27 of 28 AD8226 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07036-0-7/09(A) Rev. A | Page 28 of 28