AD8229HDZ

1nV/√Hz Low Noise 210°C Instrumentation Amplifier AD8229 FEATURES Designed for 210°C operation Low noise 1 nV/√Hz input noise 45 nV/√Hz output noise High CMRR 126 dB CMRR (minimum), G = 100 80 dB CMRR (minimum) to 5 kHz, G = 1 Excellent ac specifications 15 MHz bandwidth (G = 1) 1.2 MHz bandwidth (G = 100) 22 V/μs slew rate THD: 130 dB (1 kHz, G = 1) Versatile ±4 V to ±17 V dual supply Gain set with single resistor (G = 1 to 1000) Temperature range: −40°C to +210°C FUNCTIONAL BLOCK DIAGRAM –IN RG RG +IN 1 2 3 4 AD8229 8 7 6 5 +VS VOUT REF –VS 09412-001 TOP VIEW (Not to Scale) Figure 1. 100 80 60 40 VOSI (µV) 20 0 –20 –40 APPLICATIONS Down-hole instrumentation Harsh environment data acquisition Exhaust gas measurements Vibration analysis –60 –80 5 25 45 65 85 105 125 145 165 185 205 225 09412-016 –100 –55 –35 –15 TEMPERATURE (°C) GENERAL DESCRIPTION The AD8229 is an ultralow noise instrumentation amplifier designed for measuring small signals in the presence of large common-mode voltages and high temperatures. The AD8229 has been designed for high temperature operation. The process is dielectrically isolated to avoid leakage currents at high temperatures. The design architecture was chosen to compensate for the low VBE voltages at high temperatures. To enhance long term reliability, the wire bonding in the packaging is designed to avoid intermetallic absorption at high temperatures. The AD8229 excels at distinguishing tiny signals. It delivers industry leading 1 nV/√Hz input noise performance. The AD8229’s high CMRR prevents unwanted signals from corrupting the acquisition. The CMRR increases as the gain increases, offering high rejection when it is most needed. Figure 2. Typical Input Offset vs. Temperature (G = 100) The AD8229 is one of the fastest instrumentation amplifiers available. Its current feedback architecture provides bandwidth that is quite high, even at high gains, for example, 1.2 MHz at G = 100. With the high bandwidth comes excellent distortion performance, allowing use in demanding applications such as vibration analysis. Gain is set from 1 to 1000 with a single resistor. A reference pin allows the user to offset the output voltage. This feature is useful when interfacing with analog-to-digital converters. The AD8229 is available in an 8-pin ceramic DIP package. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. AD8229 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  General Description ......................................................................... 1  Functional Block Diagram .............................................................. 1  Revision History ............................................................................... 2  Specifications..................................................................................... 3  Absolute Maximum Ratings............................................................ 6  Thermal Resistance ...................................................................... 6  ESD Caution .................................................................................. 6  Pin Configuration and Function Descriptions ............................. 7  Typical Performance Characteristics ............................................. 8  Theory of Operation ...................................................................... 17  Architecture ................................................................................ 17  Gain Selection ............................................................................. 17  Reference Terminal .................................................................... 17  Input Voltage Range ................................................................... 18  Layout .......................................................................................... 18  Input Bias Current Return Path ............................................... 19  Input Protection ......................................................................... 19  Radio Frequency Interference (RFI) ........................................ 19  Calculating the Noise of the Input Stage ................................. 20  Outline Dimensions ....................................................................... 21  Ordering Guide .......................................................................... 21  REVISION HISTORY 1/11—Revision 0: Initial Version Rev. 0 | Page 2 of 24 AD8229 SPECIFICATIONS +VS = 15 V, −VS = −15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, unless otherwise noted. Table 1. Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz with 1 kΩ Source Imbalance G=1 Temperature Drift G = 10 Temperature Drift G = 100 Temperature Drift G = 1000 CMRR at 5 kHz G=1 G = 10 G = 100 G = 1000 VOLTAGE NOISE Spectral Density 1: 1 kHz Input Voltage Noise, eni Output Voltage Noise, eno Peak to Peak: 0.1 Hz to 10 Hz G=1 G = 1000 CURRENT NOISE Spectral Density: 1 kHz Peak to Peak: 0.1 Hz to 10 Hz VOLTAGE OFFSET Input Offset, VOSI Average TC Output Offset, VOSO Average TC Offset RTI vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current High Temperature Input Offset Current High Temperature −40°C to +210°C −40°C to +210°C VS = ±5 V to ±15 V −40°C to +210°C −40°C to +210°C −40°C to +210°C −40°C to +210°C 0.1 3 86 106 126 130 70 200 35 50 VOS = VOSI + VOSO/G 100 1 1000 10 µV µV/°C µV µV/°C dB dB dB dB nA nA nA nA 1.5 100 pA/√Hz pA p-p Test Conditions VCM = ±10 V 86 TA = −40°C to +210°C 106 TA = −40°C to +210°C 126 TA = −40°C to +210°C TA = −40°C to +210°C VCM = ±10 V 3 134 80 90 90 90 VIN+, VIN− = 0 V 1 45 2 100 1.1 50 nV/√Hz nV/√Hz µV p-p nV p-p 30 300 dB nV/V/°C dB nV/V/°C dB nV/V/°C dB dB dB dB dB Min DIP package Typ Max Unit TA = 210°C TA = 210°C Rev. 0 | Page 3 of 24 AD8229 Parameter DYNAMIC RESPONSE Small Signal Bandwidth – 3 dB G=1 G = 10 G = 100 G = 1000 Settling Time 0.01% G=1 G = 10 G = 100 G = 1000 Settling Time 0.001% G=1 G = 10 G = 100 G = 1000 Slew Rate G = 1 to 100 GAIN2 Gain Range Gain Error G=1 G = 10 G = 100 G = 1000 Gain Nonlinearity G = 1 to 1000 Gain vs. Temperature G=1 G > 10 INPUT Impedance (Pin to Ground)3 Input Operating Voltage Range4 Over Temperature OUTPUT Output Swing High Temperature Output Swing High Temperature Short-Circuit Current REFERENCE INPUT RIN IIN Voltage Range Reference Gain to Output Reference Gain Error Test Conditions Min DIP package Typ Max Unit 15 4 1.2 0.15 10 V step 0.75 0.65 0.85 5 10 V step 0.9 0.9 1.2 7 22 G = 1 + (6 kΩ/RG) 1 VOUT = ±10 V 0.01 0.05 0.05 0.1 VOUT = −10 V to +10 V RL = 10 kΩ −40°C to +210°C −40°C to +210°C 2 2 5 −100 0.03 0.3 0.3 0.3 1000 MHz MHz MHz MHz µs µs µs µs µs µs µs µs V/µs V/V % % % % ppm ppm/°C ppm/°C GΩ||pF V V V V V V mA kΩ µA V V/V % 1.5||3 VS = ±5 V to ±18 V for dual supplies −40°C to +210°C RL = 2 kΩ TA = 210°C RL = 10 kΩ TA = 210°C −VS + 2.8 −VS + 2.8 −VS + 1.9 −VS + 1.1 −VS + 1.8 −VS + 1.1 35 10 70 −VS 1 0.01 + VS +VS − 2.5 +VS − 2.5 +Vs − 1.5 +Vs − 1.1 +Vs − 1.2 +Vs − 1.1 VIN+, VIN− = 0 V Rev. 0 | Page 4 of 24 AD8229 Parameter POWER SUPPLY Operating Range Quiescent Current High Temperature TEMPERATURE RANGE For Specified Performance5 1 2 Test Conditions Min ±4 DIP package Typ Max ±17 7 12 +210 Unit V mA mA °C 6.7 T = 210°C −40 Total Voltage Noise = √(eni2 + (eno/G)2)+ eRG2). See the Theory of Operation section for more information. These specifications do not include the tolerance of the external gain setting resistor, RG. For G>1, RG errors should be added to the specifications given in this table. 3 Differential and common-mode input impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2. 4 Input voltage range of the AD8229 input stage only. The input range can depend on the common-mode voltage, differential voltage, gain, and reference voltage. See the Input Voltage Range section for more details. 5 Performance at 210°C is guaranteed for 1000 hours. Rev. 0 | Page 5 of 24 AD8229 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage Output Short-Circuit Current Duration Maximum Voltage at –IN, +IN1 Differential Input Voltage1 Gain ≤ 4 4 > Gain > 50 Gain ≥ 50 Maximum Voltage at REF Storage Temperature Range CERDIP Specified Temperature Range CERDIP Maximum Junction Temperature CERDIP 1 THERMAL RESISTANCE Rating ±17 V Indefinite ± VS ±VS ±50 V/Gain ±1 V ±VS −65°C to +150°C −40°C to +210°C 245°C θJA is specified for a device in free air. Table 3. Package 8-Lead, Size Brazed, CERDIP, 4-Layer JEDEC Board θJA 100 Unit °C/W ESD CAUTION For voltages beyond these limits, use input protection resistors. See the Applications section for more information. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 6 of 24 AD8229 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS –IN RG RG +IN 1 2 3 4 AD8229 8 7 6 5 +VS VOUT REF –VS 09412-003 TOP VIEW (Not to Scale) Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2, 3 4 5 6 7 8 Mnemonic −IN RG +IN − VS REF VOUT + VS Description Negative Input Terminal. Gain Setting Terminals. Place resistor across the RG pins to set the gain. G = 1 + (6 kΩ/RG). Positive Input Terminal. Negative Power Supply Terminal. Reference Voltage Terminal. Drive this terminal with a low impedance voltage source to level-shift the output. Output Terminal. Positive Power Supply Terminal. Rev. 0 | Page 7 of 24 AD8229 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, VS = ±15, VREF = 0, RL = 2 kΩ, unless otherwise noted. 60 N: 200 MEAN: 12.2 σ: 8.2 60 N: 201 MEAN: 4.0 σ: 0.7 50 50 40 40 HITS HITS 09412-004 30 30 20 20 10 10 –40 –20 0 VOSI ±15V (µV) 20 40 60 0 2 4 6 IBIAS OFFSET (nA) 8 Figure 4. Typical Distribution of Input Offset Voltage N: 200 MEAN: 0.9 σ: 161.2 Figure 7. Typical Distribution of Input Offset Current N: 200 MEAN: 10.9 σ: 3.7 35 30 25 120 100 80 HITS 20 15 HITS 60 40 10 5 0 –600 20 09412-005 –400 –200 200 VOSO ±15V (µV) 0 400 600 800 –40 –20 0 20 40 60 CMRR G1 (µV/V) Figure 5. Typical Distribution of Output Offset Voltage 40 35 30 25 INVERTING NONINVERTING N: 200 MEAN: –6.1 σ: 6.7 N: 200 MEAN: –10.1 σ: 6.9 Figure 8. Typical Distribution of Common Mode Rejection, G = 1 35 30 25 N: 198 MEAN: –9.1 σ: 9.9 HITS HITS 20 15 20 15 10 5 0 –50 10 5 0 –60 –40 –30 –20 –10 IBIAS (nA) 0 10 20 30 09412-006 –40 –20 0 20 NINV G ERROR G1 10K ±15V (µV/V) Figure 6. Typical Distribution of Input Bias Current Figure 9. Typical Distribution of Gain Error, G = 1 Rev. 0 | Page 8 of 24 09412-015 09412-008 0 –60 09412-007 0 –60 0 AD8229 3 G = 1, VS = ±5V 25°C 210°C 3 2 2 COMMON-MODE VOLTAGE (V) 1 COMMON-MODE VOLTAGE (V) 1 0 0 –1 –1 –2 –2 G = 100, VS = ±5V –4 –3 –2 –1 0 1 2 3 4 5 09412-009 25°C 210°C –1 0 1 2 3 4 5 09412-012 –3 –5 –3 –5 –4 –3 –2 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 10. Input Common-Mode Voltage vs. Output Voltage, Dual Supply, VS = ±5 V; G = 1 10 8 G = 1, VS = ±12V 25°C 210°C Figure 13. Input Common-Mode Voltage vs. Output Voltage, Dual Supply, VS = ±5 V; G = 100 10 8 COMMON-MODE VOLTAGE (V) 4 2 0 –2 –4 –6 –8 09412-010 COMMON-MODE VOLTAGE (V) 6 6 4 2 0 –2 –4 –6 –8 G = 100, VS = ±12V 25°C 210°C –2 0 2 4 6 8 10 12 09412-013 09412-014 –10 –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 –10 –12 –10 –8 –6 –4 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 11. Input Common-Mode Voltage vs. Output Voltage, Dual Supply, VS = ±12 V; G = 1 14 12 10 G = 1, VS = ±15V 25°C 210°C Figure 14. Input Common-Mode Voltage vs. Output Voltage, Dual Supply, VS = ±12 V; G = 100 14 12 10 COMMON-MODE VOLTAGE (V) 8 6 4 2 0 –2 –4 –6 –8 –10 –12 09412-011 COMMON-MODE VOLTAGE (V) 8 6 4 2 0 –2 –4 –6 –8 –10 –12 G = 100, VS = ±15V –10 –5 0 5 25°C 210°C 10 15 –14 –15 –10 –5 0 5 10 15 –14 –15 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 12. Input Common-Mode Voltage vs. Output Voltage, Dual Supply, VS = ±15 V; G = 1 Figure 15. Input Common-Mode Voltage vs. Output Voltage, Dual Supply, VS = ±15 V; G = 100 Rev. 0 | Page 9 of 24 AD8229 0 –5 –10 70 60 50 –12.28V GAIN = 1000 VS = ±15V INPUT BIAS CURRENT (nA) –15 –20 –25 –30 –35 –40 –45 40 GAIN = 100 GAIN (dB) 30 20 10 0 –10 –20 GAIN = 1 GAIN = 10 12.60V 09412-068 –6 –4 –2 0 2 4 6 8 10 12 14 1k 10k 100k 1M 10M 100M COMMON-MODE VOLTAGE (V) FREQUENCY (Hz) Figure 16. Input Bias Current vs. Common-Mode Voltage 160 140 120 160 Figure 19. Gain vs. Frequency GAIN = 1000 GAIN = 100 GAIN = 10 GAIN = 1 GAIN = 1000 GAIN = 100 GAIN = 10 GAIN = 1 140 120 100 80 60 40 20 0 NEGATIVE PSRR 80 60 40 20 0 CMRR (dB) 100 BANDWIDTH LIMITED 09412-069 1 10 100 1k 10k 100k 1M 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 17. Positive PSRR vs. Frequency 160 140 120 Figure 20. CMRR vs. Frequency 160 GAIN = 1000 GAIN = 100 GAIN = 10 GAIN = 1 140 120 100 80 60 40 20 0 GAIN = 1000 GAIN = 100 GAIN = 10 GAIN = 1 BANDWIDTH LIMITED NEGATIVE PSRR 80 60 40 20 0 CMRR (dB) 100 09412-070 1 10 100 1k 10k 100k 1M 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 18. Negative PSRR vs. Frequency Figure 21. CMRR vs. Frequency, 1 kΩ Source Imbalance Rev. 0 | Page 10 of 24 09412-019 09412-018 09412-017 –50 –14 –12 –10 –8 –30 100 AD8229 12 20 CHANGE IN INPUT OFFSET VOLTAGE (µV) 10 15 8 10 CMRR (µV/V) 0 100 200 300 400 500 600 700 09412-071 6 5 4 0 2 –5 0 –10 –5 20 35 50 65 80 –55 –40 –25 –10 95 110 125 140 155 170 185 200 215 230 WARM-UP TIME (s) TEMPERATURE (°C) Figure 22. Change in Input Offset Voltage (VOSI) vs. Warm-Up Time 200 150 10 8 Figure 25. CMRR vs. Temperature, G = 1, Normalized at 25°C 12 4 SUPPLY CURRENT (mA) 100 50 0 –50 –100 INPUT OFFSET CURRENT (nA) INPUT BIAS CURRENT (nA) INPUT OFFSET CURRENT 6 10 8 2 INPUT BIAS CURRENT 0 –2 –4 –6 6 4 2 –150 –8 09412-074 Figure 23. Input Bias Current and Input Offset Current vs. Temperature 150 100 50 40 09412-072 –10 –200 –55 –25 35 65 95 125 155 185 215 5 230 –40 –10 20 50 80 110 140 170 200 TEMPERATURE (°C) 0 –55 –25 5 35 65 95 125 155 185 215 –40 –10 20 50 80 110 140 170 200 230 TEMPERATURE (°C) Figure 26. Supply Current vs. Temperature, G = 1 ISHORT+ SHORT CIRCUIT CURRENT (mA) 30 20 10 0 –10 –20 –30 –40 ISHORT– 09412-075 50 GAIN ERROR (µV/V) 0 –50 –100 –150 –200 –250 –55 –25 35 65 95 125 155 185 215 5 –40 –10 20 50 80 110 140 170 200 230 TEMPERATURE (°C) 09412-073 –50 –55 –25 35 65 95 125 155 185 215 5 –40 –10 20 50 80 110 140 170 200 230 TEMPERATURE (°C) Figure 24. Gain Error vs. Temperature, G = 1, Normalized at 25°C Figure 27. Short-Circuit Current vs. Temperature, G = 1 Rev. 0 | Page 11 of 24 09412-023 AD8229 30 +VS OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES 25 +SR –SR –0.4 –0.8 –1.2 –55°C +125°C +2.0 +1.6 +1.2 +0.8 +0.4 09412-076 SLEW RATE (V/μs) 20 –40°C +150°C +25°C +210°C +85°C +225°C 15 10 5 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE (±VS) Figure 28. Slew Rate vs. Temperature, VS = ±15 V, G = 1 25 +SR –SR Figure 31. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ +VS –0.4 20 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES –0.8 –1.2 –55°C +125°C +2.0 +1.6 +1.2 +0.8 +0.4 –40°C +150°C +25°C +210°C +85°C +225°C SLEW RATE (V/μs) 15 10 5 09412-077 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE (±VS) Figure 29. Slew Rate vs. Temperature, VS = ±5 V, G = 1 +VS –0.5 –55°C +125°C –40°C +150°C +25°C +210°C +85°C +225°C Figure 32. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ 15 VS = ±15V INPUT VOLTAGE (V) REFERRED TO SUPPLY VOLTAGES –1.0 –1.5 –2.0 –2.5 10 OUTPUT VOLTAGE SWING (V) 5 –55°C –40°C +25°C +85°C +125°C +150°C +210°C +225°C 0 +2.5 +2.0 +1.5 +1.0 +1.5 09412-028 –5 –10 4 6 8 10 12 14 16 18 1k 10k 100k SUPPLY VOLTAGE (±VS) LOAD (Ω) Figure 30. Input Voltage Limit vs. Supply Voltage Figure 33. Output Voltage Swing vs. Load Resistance Rev. 0 | Page 12 of 24 09412-031 –VS –15 100 09412-030 0 –55 –25 5 35 65 95 125 155 185 215 –40 –10 20 50 80 110 140 170 200 230 TEMPERATURE (°C) –VS 09412-029 0 –55 –25 65 95 125 155 185 215 5 35 –40 –10 20 50 80 110 140 170 200 230 TEMPERATURE (°C) –VS AD8229 +VS –0.4 1000 VS = ±15V OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES –0.8 –1.2 –1.6 –55°C +125°C +1.8 +1.6 +1.2 +0.8 +0.4 100μ OUTPUT CURRENT (A) 09412-032 100 GAIN = 1 –40°C +150°C +25°C +210°C +85°C +225°C NOISE (nV/√Hz) 10 GAIN = 10 GAIN = 100 1 GAIN = 1000 1m 5m 1 10 100 1k 10k 100k FREQUENCY (Hz) Figure 34. Output Voltage Swing vs. Output Current 10 GAIN = 1 Figure 37. Voltage Noise Spectral Density vs. Frequency 8 GAIN = 1000, 100nV/DIV 6 NONLINEARITY (ppm/DIV) 4 2 0 –2 –4 –6 –8 –8 –6 –4 –2 0 2 4 6 8 10 09412-083 GAIN = 1, 2μV/DIV 1s/DIV –10 –10 OUTPUT VOLTAGE (V) Figure 35. Gain Nonlinearity, G = 1, RL = 10 kΩ 10 GAIN = 1000 Figure 38. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1, G = 1000 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 09412-084 8 6 NONLINEARITY (ppm/DIV) 4 2 0 –2 –4 –6 –8 –10 –10 –8 –6 –4 –2 0 2 4 6 8 10 NOISE (pA/√Hz) 1 10 100 1k 10k 100k OUTPUT VOLTAGE (V) FREQUENCY (Hz) Figure 36. Gain Nonlinearity, G = 1000, RL = 10 kΩ Figure 39. Current Noise Spectral Density vs. Frequency Rev. 0 | Page 13 of 24 09412-087 1 09412-086 09412-037 –VS 10μ 0.1 AD8229 5V/DIV 640ns TO 0.01% 896ns TO 0.001% 0.002%/DIV TIME (µs) Figure 40. 1 Hz to 10 Hz Current Noise 30 VS = ±15V Figure 43. Large Signal Pulse Response and Settling Time (G = 10), 10 V Step, VS = ±15 V G=1 25°C 210°C G=1 175°C 225°C 25 OUTPUT VOLTAGE (V p-p) 20 15 10 VS = ±5V 09412-048 5 1k 10k 100k 1M 10M FREQUENCY (Hz) 09412-089 0 100 50mV/DIV 50mV/DIV 1μs/DIV Figure 41. Large Signal Frequency Response Figure 44. Small Signal Response, G = 1, RL = 10 kΩ, CL = 100 pF G = 10 5V/DIV 750ns TO 0.01% 872ns TO 0.001% 0.002%/DIV 20mV/DIV 20mV/DIV 25°C 210°C 175°C 225°C 09412-049 09412-090 2µs/DIV TIME (µs) 1μs/DIV Figure 42. Large Signal Pulse Response and Settling Time (G = 1), 10 V Step, VS = ±15 V Figure 45. Small Signal Response, G = 10, RL = 10 kΩ, CL = 100 pF Rev. 0 | Page 14 of 24 09412-091 50pA/DIV 09412-088 1s/DIV 2µs/DIV AD8229 25°C 175°C 210°C 225°C G = 100 1400 1200 SETTLING TIME (ns) 1000 SETTLED TO 0.001% 800 SETTLED TO 0.01% 600 400 200 20mV/DIV 2µs/DIV 09412-094 2 4 6 8 10 12 14 16 18 20 STEP SIZE (V) Figure 46. Small Signal Response, G = 100, RL = 10 kΩ, CL = 100 pF 25°C 175°C 210°C 225°C G = 1000 Figure 49. Settling Time vs. Step Size, G = 1 1 NO LOAD 2kΩ LOAD 600Ω LOAD G = 1, SECOND HARMONIC VOUT = 10V p-p AMPLITUDE (Percentage of Fundamental) 0.1 0.01 0.001 0.0001 20mV/DIV 10µs/DIV 09412-095 100 1k 10k 100k FREQUENCY (Hz) Figure 47. Small Signal Response, G = 1000, RL = 10 kΩ, CL = 100 pF G = 10 Figure 50. Second Harmonic Distortion vs. Frequency, G = 1 1 NO LOAD 2kΩ LOAD 600Ω LOAD G = 1, THIRD HARMONIC VOUT = 10V p-p AMPLITUDE (Percentage of Fundamental) 0.1 0.01 0.001 50mV/DIV 1µs/DIV 09412-093 NO LOAD CL = 100pF CL = 147pF 0.0001 100 1k 10k 100k FREQUENCY (Hz) Figure 48. Small Signal Response with Various Capacitive Loads, G = 1, RL = Infinity Figure 51. Third Harmonic Distortion vs. Frequency, G = 1 Rev. 0 | Page 15 of 24 09412-097 0.00001 10 09412-096 0.00001 10 09412-092 0 AD8229 1 AMPLITUDE (Percentage of Fundamental) NO LOAD 2kΩ LOAD 600Ω LOAD 1 G = 1000, SECOND HARMONIC VOUT = 10V p-p VOUT = 10V p-p RL ≥ 2kΩ 0.1 0.1 0.01 THD (%) 0.01 GAIN = 100 0.001 GAIN = 1000 0.001 0.0001 GAIN = 10 GAIN = 1 0.0001 10 09412-098 100 1k 10k 100k 100 1k 10k 100k FREQUENCY(Hz) FREQUENCY (Hz) Figure 52. Second Harmonic Distortion vs. Frequency, G = 1000 1 NO LOAD 2kΩ LOAD 600Ω LOAD G = 1000, THIRD HARMONIC VOUT = 10V p-p Figure 54. THD vs. Frequency AMPLITUDE (Percentage of Fundamental) 0.1 0.01 0.001 100 1k 10k 100k FREQUENCY (Hz) Figure 53. Third Harmonic Distortion vs. Frequency, G = 1000 Rev. 0 | Page 16 of 24 09412-099 0.0001 10 09412-100 0.00001 10 AD8229 THEORY OF OPERATION I IB COMPENSATION A1 C1 NODE 1 NODE 2 +VS Q1 R1 3kΩ +VS RG 09412-058 VB I IB COMPENSATION C2 A2 R3 5kΩ +VS R4 5kΩ A3 +VS Q2 R5 5kΩ +IN –VS +VS R6 5kΩ OUTPUT R2 3kΩ +VS –VS REF –IN –VS RG– –VS –VS RG+ –VS Figure 55. Simplified Schematic ARCHITECTURE The AD8229 is based on the classic 3-op-amp topology. This topology has two stages: a preamplifier to provide differential amplification followed by a difference amplifier that removes the common-mode voltage and provides additional amplification. Figure 55 shows a simplified schematic of the AD8229. The first stage works as follows. To keep its two inputs matched, Amplifier A1 must keep the collector of Q1 at a constant voltage. It does this by forcing RG− to be a precise diode drop from –IN. Similarly, A2 forces RG+ to be a constant diode drop from +IN. Therefore, a replica of the differential input voltage is placed across the gain setting resistor, RG. The current that flows through this resistance must also flow through the R1 and R2 resistors, creating a gained differential signal between the A2 and A1 outputs. The second stage is a G = 1 difference amplifier, composed of Amplifier A3 and the R3 through R6 resistors. This stage removes the common-mode signal from the amplified differential signal. The transfer function of the AD8229 is VOUT = G × (VIN+ − VIN−) + VREF where: G =1+ 6 kΩ RG Table 5. Gains Achieved Using 1% Resistors 1% Standard Table Value of RG (Ω) 6.04 k 1.5 k 665 316 121 60.4 30.1 12.1 6.04 3.01 Calculated Gain 1.993 5.000 10.02 19.99 50.59 100.34 200.34 496.9 994.4 1994.355 The AD8229 defaults to G = 1 when no gain resistor is used. The tolerance and gain drift of the RG resistor should be added to the AD8229’s specifications to determine the total gain accuracy of the system. When the gain resistor is not used, gain error and gain drift are minimal. RG Power Dissipation The AD8229 duplicates the differential voltage across its inputs onto the RG resistor. The RG resistor size should be chosen to handle the expected power dissipation. REFERENCE TERMINAL The output voltage of the AD8229 is developed with respect to the potential on the reference terminal. This is useful when the output signal must be offset to a precise midsupply level. For example, a voltage source can be tied to the REF pin to levelshift the output so that the AD8229 can drive a single-supply ADC. The REF pin is protected with ESD diodes and should not exceed either +VS or −VS by more than 0.3 V. GAIN SELECTION Placing a resistor across the RG terminals sets the gain of the AD8229, which can be calculated by referring to Table 5 or by using the following gain equation: RG = 6 kΩ G −1 Rev. 0 | Page 17 of 24 AD8229 For best performance, source impedance to the REF terminal should be kept well below 1 Ω. As shown in Figure 55, the reference terminal, REF, is at one end of a 5 kΩ resistor. Additional impedance at the REF terminal adds to this 5 kΩ resistor and results in amplification of the signal connected to the positive input. The amplification from the additional RREF can be calculated as follows: 2(5 kΩ + RREF)/(10 kΩ + RREF) Only the positive signal path is amplified; the negative path is unaffected. This uneven amplification degrades CMRR. INCORRECT CORRECT Common-Mode Rejection Ratio over Frequency Poor layout can cause some of the common-mode signals to be converted to differential signals before reaching the in-amp. Such conversions occur when one input path has a frequency response that is different from the other. To keep CMRR over frequency high, the input source impedance and capacitance of each path should be closely matched. Additional source resistance in the input path (for example, for input protection) should be placed close to the in-amp inputs, which minimizes their interaction with parasitic capacitance from the PCB traces. Parasitic capacitance at the gain setting pins can also affect CMRR over frequency. If the board design has a component at the gain setting pins (for example, a switch or jumper), the component should be chosen so that the parasitic capacitance is as small as possible. AD8229 REF V + V AD8229 REF Power Supplies OP1177 – 09412-059 Figure 56. Driving the Reference Pin A stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. See the PSRR performance curves in Figure 19 and Figure 20 for more information. A 0.1 µF capacitor should be placed as close as possible to each supply pin. As shown in Figure 58, a 10 µF tantalum capacitor can be used farther away from the part. In most cases, it can be shared by other precision integrated circuits. +VS INPUT VOLTAGE RANGE Figure 10 through Figure 15 show the allowable common-mode input voltage ranges for various output voltages and supply voltages. The 3-op-amp architecture of the AD8229 applies gain in the first stage before removing common-mode voltage with the difference amplifier stage. Internal nodes between the first and second stages (Node 1 and Node 2 in Figure 55) experience a combination of a gained signal, a common-mode signal, and a diode drop. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not limited. 0.1µF +IN RG 10µF AD8229 –IN REF VOUT LOAD LAYOUT To ensure optimum performance of the AD8229 at the PCB level, care must be taken in the design of the board layout. The pins of the AD8229 are arranged in a logical manner to aid in this task. –IN 1 RG 2 RG 3 +IN 4 8 7 6 –VS Figure 58. Supply Decoupling, REF, and Output Referred to Local Ground Reference Pin +VS VOUT REF –VS 09412-060 AD8229 TOP VIEW (Not to Scale) 5 The output voltage of the AD8229 is developed with respect to the potential on the reference terminal. Care should be taken to tie REF to the appropriate local ground. Figure 57. Pinout Diagram Rev. 0 | Page 18 of 24 09412-061 0.1µF 10µF AD8229 INPUT BIAS CURRENT RETURN PATH The input bias current of the AD8229 must have a return path to ground. When using a floating source without a current return path, such as a thermocouple, a current return path should be created, as shown in Figure 59. INCORRECT +VS and therefore allow smaller protection resistor values. To ensure current flows primarily through the external protection diodes, place a small value resistor, such as a 33 Ω, between the diodes and the AD8229. RPROTECT + VIN+ – I +VS +VS RPROTECT + VIN+ – I –VS +VS RPROTECT –VS + VIN– – 33Ω –VS –VS LOW NOISE METHOD 09412-066 09412-067 33Ω +VS CORRECT +VS AD8229 RPROTECT AD8229 AD8229 REF AD8229 REF VIN– – + SIMPLE METHOD Figure 60. Protection for Voltages Beyond the Rails –VS TRANSFORMER +VS –VS TRANSFORMER +VS Large Differential Input Voltage at High Gain If large differential voltages at high gain are expected, an external resistor should be used in series with each input to limit current during overload conditions. The limiting resistor at each input can be computed from REF AD8229 REF 10M Ω –VS THERMOCOUPLE +VS C C AD8229  1 |V | −1V RPROTECT ≥  DIFF − RG   2 I MAX   Noise-sensitive applications may require a lower protection resistance. Low leakage diode clamps, such as the BAV199, can be used across the inputs to shunt current away from the AD8229 inputs and therefore allow smaller protection resistor values. RPROTECT + VDIFF I RPROTECT +I VDIFF – RPROTECT LOW NOISE METHOD –VS THERMOCOUPLE +VS AD8229 C REF 1 fHIGH-PASS = 2πRC C R AD8229 AD8229 AD8229 REF – RPROTECT SIMPLE METHOD R –VS CAPACITIVELY COUPLED –VS CAPACITIVELY COUPLED 09412-062 Figure 61. Protection for Large Differential Voltages IMAX The maximum current into the AD8229 inputs, IMAX, depends both on time and temperature. At room temperature, the part can withstand a current of 10 mA for at least a day. This time is cumulative over the life of the part. At 210°C, current should be limited to 2 mA for the same period of time. The part can withstand 5 mA at 210°C for an hour, cumulative over the life of the part. Figure 59. Creating an Input Bias Current Return Path INPUT PROTECTION The inputs to the AD8229 should be kept within the ratings stated in the Absolute Maximum Ratings section of this data sheet. If this cannot be done, protection circuitry can be added in front of the AD8229 to limit the current into the inputs to a maximum current, IMAX. Input Voltages Beyond the Rails If voltages beyond the rails are expected, an external resistor should be used in series with each input to limit current during overload conditions. The limiting resistor at the input can be computed from RADIO FREQUENCY INTERFERENCE (RFI) RF rectification is often a problem when amplifiers are used in applications that have strong RF signals. The disturbance can appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass RC network placed at the input of the instrumentation amplifier, as shown in Figure 62. The filter limits the input signal bandwidth, according to the following relationship: FilterFrequency DIFF = RPROTECT ≥ | VIN − VSUPPLY | I MAX Noise-sensitive applications may require a lower protection resistance. Low leakage diode clamps, such as the BAV199, can be used at the inputs to shunt current away from the AD8229 inputs Rev. 0 | Page 19 of 24 1 2πR(2C D + C C ) AD8229 FilterFrequency CM = 1 2πRC C Source Resistance Noise Any sensor connected to the AD8229 has some output resistance. There may also be resistance placed in series with inputs for protection from either overvoltage or radio frequency interference. This combined resistance is labeled R1 and R2 in Figure 63. Any resistor, no matter how well made, has a minimum level of noise. This noise is proportional to the square root of the resistor value. At room temperature, the value is approximately equal to 4 nV/√Hz × √(resistor value in kΩ). For example, assuming that the combined sensor and protection resistance on the positive input is 4 kΩ and on the negative input is 1 kΩ, the total noise from the resistance is ( 4 × 4 ) 2 + ( 4 × 1) 2 = where CD ≥ 10 CC. +VS 0.1µF CC 1nF R 4.02kΩ CD 10nF R 4.02kΩ CC 1nF 0.1µF –VS 10µF 09412-063 10µF +IN VOUT REF –IN RG AD8229 64 + 16 = 8.9 nV/ Hz Voltage Noise of the Instrumentation Amplifier The voltage noise of the instrumentation amplifier is calculated using three parameters: the part input noise, output noise, and the Rg resistor noise. It is calculated as follows: Total Voltage Noise = (Output Noise / G ) 2 + ( Input Noise) 2 + ( Noise of Rg Resistor ) 2 Figure 62. RFI Suppression CD affects the difference signal, and CC affects the common-mode signal. Values of R and CC should be chosen to minimize RFI. A mismatch between R × CC at the positive input and R × CC at the negative input degrades the CMRR of the AD8229. By using a value of CD one magnitude larger than CC, the effect of the mismatch is reduced, and performance is improved. Resistors add noise; therefore, the resistor and capacitor values chosen depend on the desired tradeoff between noise, input impedance at high frequencies, and RFI immunity. The resistors used for the RFI filter can be the same as those used for input protection. For example, for a gain of 100, the gain resistor is 60.4 Ω. Therefore, the voltage noise of the in-amp is (43 / 100) 2 + 12 + (4 × 0.0604 ) 2 = 1.5 nV/ Hz Current Noise of the Instrumentation Amplifier Current noise is calculated by multiplying the source resistance by the current noise. For example, if the R1 source resistance in Figure 63 is 4 kΩ, and the R2 source resistance is 1 k Ω, the total effect from the current noise is calculated as follows: CALCULATING THE NOISE OF THE INPUT STAGE SENSOR R1 RG AD8229 09412-064 ((4 × 1.5) 2 + (1 × 1.5) 2 ) = 6.2 nV/ Hz R2 Figure 63. AD8229 with Source Resistance from Sensor and Protection Resistors Total Noise calculation To determine the total noise of the in-amp, referred to input, combine the source resistance noise, voltage noise, and current noise contribution by the sum of squares method. For example, if the R1 source resistance in Figure 63 is 4 kΩ, the R2 source resistance is 1 k Ω, and the gain of the in-amps is 100, the total noise, referred to input, is 8.9 2 + 1.52 + 6.2 2 ) = 11.0 nV/ Hz The total noise of the amplifier front end depends on much more than the 1 nV/√Hz headline specification of this data sheet. The total noise is dependent on three main factors: the source resistance, the voltage noise of the instrumentation amplifier, and the current noise of the instrumentation amplifier. In the following calculations, noise is referred to the input (RTI). In other words, everything is calculated as if it appeared at the amplifier input. To calculate the noise referred to the amplifier output (RTO), simply multiple the RTI noise by the gain of the instrumentation amplifier. Rev. 0 | Page 20 of 24 AD8229 OUTLINE DIMENSIONS 0.528 0.520 0.512 8 5 0.298 0.290 0.282 1 4 0.320 0.310 0.300 INDEX MARK 0.305 0.300 0.295 0.011 0.010 0.009 0.125 0.110 0.095 0.105 0.095 0.085 0.130 NOM 0.045 0.035 0.025 0.310 0.300 0.290 SEATING PLANE 0.175 NOM 0.105 0.100 0.095 0.032 NOM Figure 64. 8-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] (D-8-1)) Dimensions shown in inches ORDERING GUIDE Model1 AD8229HDZ 1 Temperature Range −40°C to +210°C Package Description Ceramic Dual In-Line Package [SBDIP] Package Option D-8-1 Z = RoHS Compliant Part. Rev. 0 | Page 21 of 24 07-08-2010-B 0.054 NOM 0.020 0.018 0.016 0.011 0.010 0.009 AD8229 NOTES Rev. 0 | Page 22 of 24 AD8229 NOTES Rev. 0 | Page 23 of 24 AD8229 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09412-0-1/11(0) Rev. 0 | Page 24 of 24