a
FEATURES TRUE SINGLE SUPPLY OPERATION Output Swings Rail to Rail Input Voltage Range Extends Below Ground Single Supply Capability from +3 V to +36 V Dual Supply Capability from 1.5 V to 18 V HIGH LOAD DRIVE Capacitive Load Drive of 350 pF, G = 1 Minimum Output Current of 15 mA EXCELLENT AC PERFORMANCE FOR LOW POWER 800 A Max Quiescent Current per Amplifier Unity Gain Bandwidth: 1.8 MHz Slew Rate of 3.0 V/ s GOOD DC PERFORMANCE 800 V Max Input Offset Voltage 2 V/ C Typ Offset Voltage Drift 25 pA Max Input Bias Current LOW NOISE 13 nV/√Hz @ 10 kHz NO PHASE INVERSION APPLICATIONS Battery Powered Precision Instrumentation Photodiode Preamps Active Filters 12- to 14-Bit Data Acquisition Systems Medical Instrumentation Low Power References and Regulators PRODUCT DESCRIPTION
Single Supply, Rail-to-Rail Low Power FET-Input Op Amp AD822
CONNECTION DIAGRAM 8-Pin Plastic DIP, Cerdip and SOIC
OUT1 –IN1 +IN1 V– 1 2 3 4 8 7 6 V+ OUT2 –IN2 +IN2
AD822
5
capability with an input voltage range extending below the negative rail, allowing the AD822 to accommodate input signals below ground in the single supply mode. Output voltage swing extends to within 10 mV of each rail providing the maximum output dynamic range. Offset voltage of 800 µV max, offset voltage drift of 2 µV/°C, input bias currents below 25 pA and low input voltage noise provide dc precision with source impedances up to a Gigaohm. 1.8 MHz unity gain bandwidth, –93 dB THD at 10 kHz and 3 V/µs slew rate are provided with a low supply current of 800 µA per amplifier. The AD822 drives up to 350 pF of direct capacitive load as a follower, and provides a minimum output current of 15 mA. This allows the amplifier to handle a wide range of load conditions. This combination of ac and dc performance, plus the outstanding load drive capability, results in an exceptionally versatile amplifier for the single supply user. The AD822 is available in four performance grades. The A and B grades are rated over the industrial temperature range of –40°C to +85°C. There is also a 3 volt grade—the AD822A-3V, rated over the industrial temperature range. The mil grade is rated over the military temperature range of –55°C to +125°C and is available processed on standard military drawing. The AD822 is offered in three varieties of 8-pin package: plastic DIP, hermetic cerdip and surface mount (SOIC) as well as die form.
1V
100
The AD822 is a dual precision, low power FET input op amp that can operate from a single supply of +3.0 V to 36 V, or dual supplies of ± 1.5 V to ± 18 V. It has true single supply
100
INPUT VOLTAGE NOISE – nV/√Hz
1V
20µ s
10
5V
90
VOUT
10 0%
1 10 100 1k FREQUENCY – Hz 10k
0V (GND)
1V
Input Voltage Noise vs. Frequency
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Gain of +2 Amplifier; VS = +5, 0, VIN = 2.5 V Sine Centered at 1.25 Volts, RL = 100 kΩ
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD822–SPECIFICATIONS (V = 0, 5 volts @ T = +25 C, V
S A
CM
= 0 V, VOUT = 0.2 V unless otherwise noted)
Min AD822B Typ Max 0.1 0.5 2 2 0.5 2 0.5 500 400 80 80 15 10 1000 150 30 0.4 0.9 10 2.5 10 500 80 15 Min AD822S1 Typ Max 0.1 0.5 2 2 0.5 2 1.5 1000 150 30 0.8 25 20 Units mV mV µV/°C pA nA pA nA V/mV V/mV V/mV V/mV V/mV V/mV
Parameter DC PERFORMANCE Initial Offset Max Offset over Temperature Offset Drift Input Bias Current at TMAX Input Offset Current at TMAX Open-Loop Gain TMIN to TMAX
Conditions
Min
AD822A Typ Max 0.1 0.5 2 2 0.5 2 0.5 0.8 1.2 25 5 20
VCM = 0 V to 4 V
VO = 0.2 V to 4 V RL = 100 k RL = 1 0 k
TMIN to TMAX RL = 1 k TMIN to TMAX NOISE/HARMONIC PERFORMANCE Input Voltage Noise 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz Input Current Noise 0.1 Hz to 10 Hz f = 1 kHz Harmonic Distortion f = 10 kHz DYNAMIC PERFORMANCE Unity Gain Frequency Full Power Response Slew Rate Settling Time to 0.1% to 0.01% MATCHING CHARACTERISTICS Initial Offset Max Offset Over Temperature Offset Drift Input Bias Current Crosstalk @ f = 1 kHz f = 100 kHz INPUT CHARACTERISTICS Common-Mode Voltage Range2 TMIN to TMAX CMRR TMIN to TMAX Input Impedance Differential Common Mode OUTPUT CHARACTERISTICS Output Saturation Voltage3 VOL–VEE TMIN to TMAX VCC–VOH TMIN to TMAX VOL–VEE TMIN to TMAX VCC–VOH TMIN to TMAX VOL–VEE TMIN to TMAX VCC–VOH TMIN to TMAX Operating Output Current TMIN to TMAX Capacitive Load Drive POWER SUPPLY Quiescent Current TMIN to TMAX Power Supply Rejection TMIN to TMAX
500 400 80 80 15 10
1000 150 30
2 25 21 16 13 18 0.8 RL = 10 k to 2.5 V VO = 0.25 V to 4.75 V –93 1.8 210 3 1.4 1.8 1.0 1.6 3 RL = 5 k Ω 20 –130 –93 –0.2 –0.2 66 66 4 4 80 1013||0.5 1013||2.8 –0.2 –0.2 69 66
2 25 21 16 13 18 0.8 –93 1.8 210 3 1.4 1.8 0.5 1.3 3 10 –130 –93 4 4 80 1013||0.5 1013||2.8 –0.2 66
2 25 21 16 13 18 0.8 –93 1.8 210 3 1.4 1.8 1.6 20 –130 –93 4 80 1013||0.5 1013||2.8
µV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz fA p-p fA/√Hz dB MHz kHz V/µs µs µs mV mV µV/°C pA dB dB V V dB dB Ω||pF Ω||pF
VO p-p = 4.5 V VO = 0.2 V to 4.5 V
VCM = 0 V to +2 V
ISINK = 20 µA ISOURCE = 20 µA ISINK = 2 mA ISOURCE = 2 mA ISINK = 15 mA ISOURCE = 15 mA 15 12
5 10 40 80 300 800
7 10 14 20 55 80 110 160 500 1000 1500 1900 15 12
5 10 40 80 300 800
7 10 14 20 55 80 110 160 500 1000 1500 1900 15
5 10 40 80 300 800
7 14 55 110 500 1500
350 1.24 80 1.6 66 66
350 1.24 80 1.6 70
350 1.24 80
mV mV mV mV mV mV mV mV mV mV mV mV mA mA pF mA dB dB
VS+ = 5 V to 15 V
70 70
–2–
REV. A
(VS =
5 volts @ TA = +25 C, VCM = 0 V, VOUT = 0 V unless otherwise noted)
Conditions Min AD822A Typ Max 0.1 0.5 2 2 0.5 2 0.5 400 400 80 80 20 10 1000 150 30 0.8 1.5 25 5 20 400 400 80 80 20 10 Min AD822B Typ Max 0.1 0.5 2 2 0.5 2 0.5 1000 150 30 0.4 1 10 2.5 10 400 80 20 Min AD822S1 Typ Max 0.1 0.5 2 2 0.5 2 1.5 1000 150 30
AD822
Units mV mV µV/°C pA nA pA nA V/mV V/mV V/mV V/mV V/mV V/mV
Parameter DC PERFORMANCE Initial Offset Max Offset over Temperature Offset Drift Input Bias Current at TMAX Input Offset Current at TMAX Open-Loop Gain TMIN to TMAX
VCM = –5 V to 4 V
25
VO = –4 V to 4 V RL = 100 k RL = 1 0 k
TMIN to TMAX RL = 1 k TMIN to TMAX NOISE/HARMONIC PERFORMANCE Input Voltage Noise 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz Input Current Noise 0.1 Hz to 10 Hz f = 1 kHz Harmonic Distortion f = 10 kHz DYNAMIC PERFORMANCE Unity Gain Frequency Full Power Response Slew Rate Settling Time to 0.1% to 0.01% MATCHING CHARACTERISTICS Initial Offset Max Offset Over Temperature Offset Drift Input Bias Current Crosstalk @ f = 1 kHz f = 100 kHz INPUT CHARACTERISTICS Common-Mode Voltage Range2 TMIN to TMAX CMRR TMIN to TMAX Input Impedance Differential Common Mode OUTPUT CHARACTERISTICS Output Saturation Voltage3 VOL–VEE TMIN to TMAX VCC–VOH TMIN to TMAX VOL–VEE TMIN to TMAX VCC–VOH TMIN to TMAX VOL–VEE TMIN to TMAX VCC–VOH TMIN to TMAX Operating Output Current TMIN to TMAX Capacitive Load Drive POWER SUPPLY Quiescent Current TMIN to TMAX Power Supply Rejection TMIN to TMAX
2 25 21 16 13 18 0.8 RL = 1 0 k VO = ± 4.5 V –93 1.9 105 3 1.4 1.8 1.0 3 3 RL = 5 k Ω 25 –130 –93 –5.2 –5.2 66 66 4 4 80 1013||0.5 1013||2.8 –5.2 –5.2 69 66
2 25 21 16 13 18 0.8 –93 1.9 105 3 1.4 1.8 0.5 2 3 10 –130 –93 4 4 80 1013||0.5 1013||2.8 –5.2 66
2 25 21 16 13 18 0.8 –93 1.9 105 3 1.4 1.8 1.6 2 25 –130 –93 4 80 1013||0.5 1013||2.8
µV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz fA p-p fA/√Hz dB MHz kHz V/µs µs µs mV mV µV/°C pA dB dB V V dB dB Ω||pF Ω||pF
VO p-p = 9 V VO = 0 V to ± 4.5 V
VCM = –5 V to +2 V
ISINK = 20 µA ISOURCE = 20 µA ISINK = 2 mA ISOURCE = 2 mA ISINK = 15 mA ISOURCE = 15 mA 15 12
5 10 40 80 300 800
7 10 14 20 55 80 110 160 500 1000 1500 1900 15 12
5 10 40 80 300 800
7 10 14 20 55 80 110 160 500 1000 1500 1900 15
5 10 40 80 300 800
7 14 55 110 500 1500
350 1.3 80 1.6 66 66
350 1.3 80 1.6 70
350 1.3 80
mV mV mV mV mV mV mV mV mV mV mV mV mA mA pF mA dB dB
VS+ = 5 V to 15 V
70 70
REV. A
–3–
AD822–SPECIFICATIONS (V =
S
15 volts @ TA = +25 C, VCM = 0 V, VOUT = 0 V unless otherwise noted)
Min AD822A Typ Max 0.4 0.5 2 2 40 0.5 2 0.5 500 500 100 100 30 20 2000 500 45 2 3 25 5 20 500 500 100 100 30 20 Min AD822B Typ Max 0.3 0.5 2 2 40 0.5 2 0.5 2000 500 45 1.5 2.5 12 2.5 12 500 150 30 Min AD822S1 Typ Max 0.4 0.5 2 2 40 0.5 2 1.5 2000 400 45 2.0 25 20 Units mV mV µV/°C pA pA nA pA nA V/mV V/mV V/mV V/mV V/mV V/mV
Parameter DC PERFORMANCE Initial Offset Max Offset over Temperature Offset Drift Input Bias Current at TMAX Input Offset Current at TMAX Open-Loop Gain TMIN to TMAX
Conditions
VCM = 0 V VCM = –10 V VCM = 0 V VO = +10 V to –10 V RL = 100 k RL = 1 0 k
TMIN to TMAX RL = 1 k TMIN to TMAX NOISE/HARMONIC PERFORMANCE Input Voltage Noise 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz Input Current Noise 0.1 Hz to 10 Hz f = 1 kHz Harmonic Distortion f = 10 kHz DYNAMIC PERFORMANCE Unity Gain Frequency Full Power Response Slew Rate Settling Time to 0.1% to 0.01% MATCHING CHARACTERISTICS Initial Offset Max Offset Over Temperature Offset Drift Input Bias Current Crosstalk @ f = 1 kHz f = 100 kHz INPUT CHARACTERISTICS Common-Mode Voltage Range2 TMIN to TMAX CMRR TMIN to TMAX Input Impedance Differential Common Mode OUTPUT CHARACTERISTICS Output Saturation Voltage3 VOL–VEE TMIN to TMAX VCC–VOH TMIN to TMAX VOL–VEE TMIN to TMAX VCC–VOH TMIN to TMAX VOL–VEE TMIN to TMAX VCC–VOH TMIN to TMAX Operating Output Current TMIN to TMAX Capacitive Load Drive POWER SUPPLY Quiescent Current TMIN to TMAX Power Supply Rejection TMIN to TMAX
2 25 21 16 13 18 0.8 RL = 1 0 k VO = ± 10 V –85 1.9 45 3 4.1 4.5 3 4 3 RL = 5 k Ω 25 –130 –93 –15.2 –15.2 70 70 14 14 80 1013||0.5 1013||2.8 –15.2 –15.2 74 74
2 25 21 16 13 18 0.8 –85 1.9 45 3 4.1 4.5 2 2.5 3 12 –130 –93 14 14 90 1013||0.5 1013||2.8 –15.2 70
2 25 21 16 13 18 0.8 –85 1.9 45 3 4.1 4.5 0.8 1.0 25 –130 –93 14 90 1013||0.5 1013||2.8
µV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz fA p-p fA/√Hz dB MHz kHz V/µs µs µs mV mV µV/°C pA dB dB V V dB dB Ω||pF Ω||pF
VO p-p = 20 V VO = 0 V to ± 10 V
VCM = –15 V to 12 V
ISINK = 20 µA ISOURCE = 20 µA ISINK = 2 mA ISOURCE = 2 mA ISINK = 15 mA ISOURCE = 15 mA 20 15
5 10 40 80 300 800
7 10 14 20 55 80 110 160 500 1000 1500 1900 20 15
5 10 40 80 300 800
7 10 14 20 55 80 110 160 500 1000 1500 1900 20
5 10 40 80 300 800
7 14 55 110 500 1500
350 1.4 80 1.8 70 70
350 1.4 80 1.8 70
350 1.4 80
mV mV mV mV mV mV mV mV mV mV mV mV mA mA pF mA dB dB
VS+ = 5 V to 15 V
70 70
–4–
REV. A
(VS = 0, 3 volts @ TA = +25 C, VCM = 0 V, VOUT = 0.2 V unless otherwise noted)
Parameter DC PERFORMANCE Initial Offset Max Offset over Temperature Offset Drift Input Bias Current at TMAX Input Offset Current at TMAX Open-Loop Gain TMIN to TMAX RL = 1 0 k TMIN to TMAX RL = 1 k TMIN to TMAX NOISE/HARMONIC PERFORMANCE Input Voltage Noise 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz Input Current Noise 0.1 Hz to 10 Hz f = 1 kHz Harmonic Distortion f = 10 kHz DYNAMIC PERFORMANCE Unity Gain Frequency Full Power Response Slew Rate Settling Time to 0.1% to 0.01% MATCHING CHARACTERISTICS Initial Offset Max Offset Over Temperature Offset Drift Input Bias Current Crosstalk @ f = 1 kHz f = 100 kHz INPUT CHARACTERISTICS Common-Mode Voltage Range2 TMIN to TMAX CMRR TMIN to TMAX Input Impedance Differential Common Mode OUTPUT CHARACTERISTICS Output Saturation Voltage3 VOL–VEE TMIN to TMAX VCC–VOH TMIN to TMAX VOL–VEE TMIN to TMAX VCC–VOH TMIN to TMAX VOL–VEE TMIN to TMAX VCC–VOH TMIN to TMAX Operating Output Current TMIN to TMAX Capacitive Load Drive POWER SUPPLY Quiescent Current TMIN to TMAX Power Supply Rejection TMIN to TMAX Conditions Min AD822A-3 V Typ 0.2 0.5 1 2 0.5 2 0.5 300 300 60 60 10 8 1000 150 30 Max 1 1.5 25 5 20
AD822
Units mV mV µV/°C pA nA pA nA V/mV V/mV V/mV V/mV V/mV V/mV
VCM = 0 V to +2 V
VO = 0.2 V to 2 V RL = 100 k
2 25 21 16 13 18 0.8 RL = 10 k to 1.5 V VO = ± 1.25 V –92 1.5 240 3 1 1.4 1 2 2 RL = 5 k Ω 10 –130 –93 –0.2 –0.2 60 60 2 2 74 1013||0.5 1013||2.8
µV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz fA p-p fA/√Hz dB MHz kHz V/µs µs µs mV mV µV/°C pA dB dB V V dB dB Ω||pF Ω||pF
VO p-p = 2.5 V VO = 0.2 V to 2.5 V
VCM = 0 V to +1 V
ISINK = 20 µA ISOURCE = 20 µA ISINK = 2 mA ISOURCE = 2 mA ISINK = 10 mA ISOURCE = 10 mA 15 12
5 10 40 80 200 500
7 10 14 20 55 80 110 160 400 400 1000 1000
350 1.24 80 1.6
mV mV mV mV mV mV mV mV mV mV mV mV mA mA pF mA dB dB
VS+ = 3 V to 15 V
70 70
REV. A
–5–
AD822–SPECIFICATIONS AD822
NOTES 1 See standard military drawing for 883B specifications. 2 This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (+V S – 1 V) to +VS. Common-mode error voltage is typically less than 5 mV with the common-mode voltage set at 1 volt below the positive supply. 3 VOL–VEE is defined as the difference between the lowest possible output voltage (V OL) and the minus voltage supply rail (V EE). VCC–VOH is defined as the difference between the highest possible output voltage (V OH) and the positive supply voltage (V CC). Specifications subject to change without notice.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD822 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Internal Power Dissipation Plastic DIP (N) . . . . . . . . . . . . . . Observe Derating Curves Cerdip (Q) . . . . . . . . . . . . . . . . . . Observe Derating Curves SOIC (R) . . . . . . . . . . . . . . . . . . . Observe Derating Curves Input Voltage . . . . . . . . . . . . . . (+VS + 0.2 V) to –(20 V + VS) Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 30 V Storage Temperature Range (N) . . . . . . . . . –65°C to +125°C Storage Temperature Range (Q) . . . . . . . . . –65°C to +150°C Storage Temperature Range (R) . . . . . . . . . –65°C to +150°C Operating Temperature Range AD822A/B . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C AD822S . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C Lead Temperature Range (Soldering 60 sec) . . . . . . . +260°C
NOTES 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 8-Pin Plastic DIP Package: θJA = 90°C/Watt 8-Pin Cerdip Package: θJA = 110°C/Watt 8-Pin SOIC Package: θJA = 160°C/Watt
ABSOLUTE MAXIMUM RATINGS 1
operation will be restored as soon as the die temperature is reduced. Leaving the device in the “overheated” condition for an extended period can result in device burnout. To ensure proper operation, it is important to observe the derating curves shown in Figure 24. While the AD822 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature is not exceeded under all conditions. With power supplies ± 12 volts (or less) at an ambient temperature of +25°C or less, if the output node is shorted to a supply rail, then the amplifier will not be destroyed, even if this condition persists for an extended period.
ORDERING GUIDE
Temperature Model1
AD822AN AD822BN AD822AR AD822BR AD822AR-3V AD822AN-3V AD822A Chips Standard Military Drawing2 Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –55°C to +125°C
Package
Description 8-Pin Plastic Mini-DIP 8-Pin Plastic Mini-DIP 8-Pin SOIC 8-Pin SOIC 8-Pin SOIC 8-Pin Plastic Mini-DIP Die
Package
Option N-8 N-8 R-8 R-8 R-8 N-8
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD822 is limited by the associated rise in junction temperature. For plastic packages, the maximum safe junction temperature is 145°C. For the cerdip packages, the maximum junction temperature is 175°C. If these maximums are exceeded momentarily, proper circuit
8-Pin Cerdip Q-8
NOTES 1 Spice model is available on ADI Model Disc. 2 Contact factory for availability.
METALIZATION PHOTOGRAPH
Contact factory for latest dimensions. Dimensions shown in inches and (mm).
– 6–
REV. A
Typical Characteristics–AD822
70 VS = 0V, 5V
INPUT BIAS CURRENT – pA
5
60 50
NUMBER OF UNITS
40 30 20
0 VS = 0V, +5V AND ±5V VS = ±5V
10
–5
0 –0.5
–0.4
–0.3
–0.2 –0.1 0 0.1 0.2 OFFSET VOLTAGE – mV
0.3
0.4
0.5
–5
–4
–3
–2 –1 0 1 2 COMMON-MODE VOLTAGE – V
3
4
5
Figure 1. Typical Distribution of Offset Voltage (390 Units)
Figure 4. Input Bias Current vs. Common-Mode Voltage; VS = +5 V, 0 V and VS = ± 5 V
16 14 12 10 % IN BIN 8 6 4 2 0 –12 VS = ±5V VS = ±15V
1k
INPUT BIAS CURRENT – pA
100
10
1
–10
–8
–6
–4
–2
0
2
4
6
8
10
0.1 –16
–12
–8
–4
0
4
8
12
16
OFFSET VOLTAGE DRIFT – µV/°C
COMMON-MODE VOLTAGE – V
Figure 2. Typical Distribution of Offset Voltage Drift (100 Units)
Figure 5. Input Bias Current vs. Common-Mode Voltage; VS = ± 15 V
50 45
100k
10k 35 30 25 20 15 10 5 0 0 1 2 3 4 5 6 7 INPUT BIAS CURRENT – pA 8 9 10 0.1 20 40 60 80 100 TEMPERATURE – °C 120 140 INPUT BIAS CURRENT – pA 40
NUMBER OF UNITS
1k
100
10
1
Figure 3. Typical Distribution of Input Bias Current (213 Units)
Figure 6. Input Bias Current vs. Temperature; VS = 5 V, VCM = 0
REV. A
–7–
AD822–Typical Characteristics
10M 40 POS RAIL OPEN-LOOP GAIN – V/V
INPUT VOLTAGE – µV
1M V S = 0V, 5V
VS = ±15V
20 RL = 20kΩ
RL = 2kΩ NEG RAIL
0
POS RAIL
POS RAIL
100k
VS = 0V, 3V
–20 RL = 100kΩ 10k 100 –40 1k 10k 100k 0 60 120 180
NEG RAIL
NEG RAIL 240 300
LOAD RESISTANCE – Ω
OUTPUT VOLTAGE FROM SUPPLY RAILS – mV
Figure 7. Open-Loop Gain vs. Load Resistance
Figure 10. Input Error Voltage with Output Voltage within 300 mV of Either Supply Rail for Various Resistive Loads; VS = ± 5 V
10M
1k
OPEN-LOOP GAIN – V/V
RL = 100kΩ 1M RL = 10kΩ
V S = ±15V V S = 0V, 5V V S = ±15V VS = 0V, 5V
INPUT VOLTAGE NOISE – nV/√Hz
100
100k RL = 600Ω V S = ±15V V S = 0V, 5V 10k –60
10
1
–40 –20 0 20 40 60 80 TEMPERATURE – °C 100 120 140
1
10
100 FREQUENCY – Hz
1k
10k
Figure 8. Open-Loop Gain vs. Temperature
Figure 11. Input Voltage Noise vs. Frequency
300
–40 RL = 10kΩ ACL = –1
200 INPUT VOLTAGE – µV
–50 –60
100
R L = 10kΩ
THD – dB
RL = 100kΩ
–70 –80
VS = 0V, 3V; V OUT = 2.5Vp-p
0
VS = ±15V; V OUT = 20Vp-p VS = ±5V; V OUT = 9V p-p
–100 –90 –200 R L = 600Ω –100 VS = 0V, 5V; V OUT = 4.5V p-p –300 –16 –12 –8 –4 0 4 OUTPUT VOLTAGE – V 8 12 16 –110 100 1k 10k FREQUENCY – Hz 100k
Figure 9. Input Error Voltage vs. Output Voltage for Resistive Loads
Figure 12. Total Harmonic Distortion vs. Frequency
–8–
REV. A
AD822
100 100
90 80
80 PHASE
OPEN-LOOP GAIN – dB
80
PHASE MARGIN IN DEGREES
COMMON-MODE REJECTION – dB
70 VS = 0V, 3V 60 50 40 30 20 10
VS = ±15V
60 GAIN 40
60
VS = 0V, 5V
40
20 RL = 2kΩ CL = 100pF
20
0
0
–20 10 100 1k 10k 100k FREQUENCY – Hz 1M
–20 10M
0 10 100 1k 10k 100k 1M 10M FREQUENCY – Hz
Figure 13. Open-Loop Gain and Phase Margin vs. Frequency
Figure 16. Common-Mode Rejection vs. Frequency
1k COMMON-MODE ERROR VOLTAGE – mV ACL = +1 VS = ±15V
5
100 OUTPUT IMPEDANCE – Ω
4
10
3
NEGATIVE RAIL +25 °C
POSITIVE RAIL
1
2
0.1
1 +125° C 0 –1
–55 °C
+125 °C –55 °C
0.01 100 1k 10k 100k FREQUENCY – Hz 1M 10M
0
1
2
3
COMMON-MODE VOLTAGE FROM SUPPLY RAILS – Volts
Figure 14. Output Impedance vs. Frequency
Figure 17. Absolute Common-Mode Error vs. CommonMode Voltage from Supply Rails (VS – VCM)
+16 +12
1000
OUTPUT SATURATION VOLTAGE – mV
OUTPUT SWING FROM 0 TO ±Volts
+8 +4 0 –4 –8
1%
100 V S – V OH V OL – V S 10
0.1%
0.01%
ERROR
1%
–12
–16 0.0 1.0 2.0 3.0 SETTLING TIME – µs 4.0 5.0
0 0.001
0.01
0.1 1 LOAD CURRENT – mA
10
100
Figure 15. Output Swing and Error vs. Settling Time
Figure 18. Output Saturation Voltage vs. Load Current
REV. A
–9–
AD822–Typical Characteristics
1000
OUTPUT SATURATION VOLTAGE – mV
100 ISOURCE = 10mA ISINK = 10mA 90
POWER SUPPLY REJECTION – dB
80 70 60 +PSRR 50 40 30 20 10 –PSRR
100 ISOURCE = 1mA ISINK = 1mA 10 ISOURCE = 10µA ISINK = 10µA
1 –60
0 –40 –20 0 20 40 60 80 100 120 140 10 100 1k TEMPERATURE – °C 10k 100k FREQUENCY – Hz 1M 10M
Figure 19. Output Saturation Voltage vs. Temperature
Figure 22. Power Supply Rejection vs. Frequency
80
30 RL = 2k VS = ±15V 25 VS = ±15V 20
SHORT CIRCUIT CURRENT LIMIT – mA
70 60 50 40 VS = 0V, 5V 30 20 10 0 –60 VS = 0V, 5V VS = 0V, 3V VS = 0V, 3V VS = ±15V + – – + + –OUT
OUTPUT VOLTAGE – V
15
10 VS = 0V, 5V VS = 0V ,3V
5
–40
–20
0
20 40 60 80 TEMPERATURE – °C
100
120
140
0 10k
100k 1M FREQUENCY – Hz
10M
Figure 20. Short Circuit Current Limit vs. Temperature
Figure 23. Large Signal Frequency Response
1600 1400 QUIESCENT CURRENT – µA 1200 1000 800 600 400 200 0 0 4 8 12 16 20
T = +125° C T = +25 °C T = –55° C
2.4 2.2
TOTAL POWER DISSIPATION – Watts
(PLASTIC) T JMAX = 145 °C (HERMETIC) T JMAX = 175 °C
2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 –60 –40 –20 8-PIN SOIC (PLASTIC) 0 20 40 60 80 100 120 140 8-PIN MINI-DIP (PLASTIC)
8-PIN CERDIP (HERMETIC)
24
28
30
36
TOTAL SUPPLY VOLTAGE – Volts
AMBIENT TEMPERATURE – °C
Figure 21. Quiescent Current vs. Supply Voltage vs. Temperature
Figure 24. Maximum Power Dissipation vs. Temperature for Plastic and Hermetic Packages
–10–
REV. A
AD822
–70
+VS VOUT 20kΩ 0.1µF 1µF 6 1 5kΩ VIN 7 5kΩ 2.2kΩ
–80
2 20V p-p 3 8
–90 CROSSTALK – dB –100 –110 –120
1/2 AD822
1/2 AD822 5
CROSSTALK = 20 LOG
VOUT 10V IN
0.1µF –VS
1µF
–130
Figure 28. Crosstalk Test Circuit
–140 300 1k 3k 10k 30k FREQUENCY – Hz 100k 300k 1M
Figure 25. Crosstalk vs. Frequency
5V
100
5µs
+VS 0.01µF 8 VIN
90
1/2 AD822
4 –V S 0.01µF RL 100pF
VOUT
10 0%
Figure 26. Unity-Gain Follower
Figure 29. Large Signal Response Unity Gain Follower; VS = ± 15 V, RL = 10 kΩ
5V
100 90
10 µs
100 90
10mV
500ns
10 0%
10 0%
Figure 27. 20 V p-p, 25 kHz Sine Wave Input; Unity Gain Follower; RL = 600 Ω, VS = ± 15 V
Figure 30. Small Signal Response Unity Gain Follower; VS = ± 15 V, RL = 10 kΩ
REV. A
–11–
AD822
1V
100 90
2µs
100 90
1V
2µs
10
10
GND
0%
GND 0%
Figure 31. VS = +5 V, 0 V; Unity Gain Follower Response to 0 V to 4 V Step
Figure 34. VS = +5 V, 0 V; Unity Gain Follower Response to 0 V to 5 V Step
10mV
100
2µs
+VS 0.01µF 8 VIN
90
1/2 AD822
4 RL 100pF
VOUT
10
GND
0%
Figure 32. Unity Gain Follower
Figure 35. VS = +5 V, 0 V; Unity Gain Follower Response, to 40 mV Step Centered 40 mV Above Ground, RL = 10 kΩ
10mV
10k VIN +VS 0.01µF 8 20k VOUT
100 90
2µs
1/2 AD822
4 RL 100pF
10
GND
0%
Figure 33. Gain of Two Inverter
Figure 36. VS = +5 V, 0 V; Gain of Two Inverter Response to 20 mV Step, Centered 20 mV Below Ground, RL = 10 kΩ
– 12–
REV. A
AD822
1V
100 90
2µs
100 90
1V
2µs
10
GND
10
0%
1V
GND
0%
a
1V
100
1V
10µs
+VS
90
Figure 37. VS = +5 V, 0 V; Gain of Two Inverter Response to 2.5 V Step Centered –1.25 V Below Ground, RL = 10 kΩ
10
GND
0%
1V
500mV
100 90
10µs
b.
+5V RP V
IN
VOUT
10
GND
0%
Figure 39. (a) Response with RP = 0; VIN from 0 to +VS (b) VIN = 0 to +VS + 200 mV VOUT = 0 to +VS RP = 49.9 kΩ Figure 38. VS = 3 V, 0 V; Gain of Two Inverter, VIN = 1.25 V, 25 kHz, Sine Wave Centered at –0.75 V, RL = 600 Ω
APPLICATION NOTES
INPUT CHARACTERISTICS
In the AD822, n-channel JFETs are used to provide a low offset, low noise, high impedance input stage. Minimum input common-mode voltage extends from 0.2 V below –VS to 1 V less than +VS. Driving the input voltage closer to the positive rail will cause a loss of amplifier bandwidth (as can be seen by comparing the large signal responses shown in Figures 31 and 34) and increased common-mode voltage error as illustrated in Figure 17. The AD822 does not exhibit phase reversal for input voltages up to and including +VS. Figure 39a shows the response of an AD822 voltage follower to a 0 V to +5 V (+VS) square wave input. The input and output arc superimposed. The output tracks the input up to +VS without phase reversal. The reduced bandwidth above a 4 V input causes the rounding of the output wave form. For input voltages greater than +VS, a resistor in series with the AD822’s noninverting input will prevent phase reversal, at the expense of greater input voltage noise. This is illustrated in Figure 39b.
Since the input stage uses n-channel JFETs, input current during normal operation is negative; the current flows out from the input terminals. If the input voltage is driven more positive than +VS – 0.4 V, the input current will reverse direction as internal device junctions become forward biased. This is illustrated in Figure 4. A current limiting resistor should be used in series with the input of the AD822 if there is a possibility of the input voltage exceeding the positive supply by more than 300 mV, or if an input voltage will be applied to the AD822 when ± VS = 0. The amplifier will be damaged if left in that condition for more than 10 seconds. A 1 kΩ resistor allows the amplifier to withstand up to 10 volts of continuous overvoltage, and increases the input voltage noise by a negligible amount. Input voltages less than –VS are a completely different story. The amplifier can safely withstand input voltages 20 volts below the minus supply voltage as long as the total voltage from the positive supply to the input terminal is less than 36 volts. In addition, the input stage typically maintains picoamp level input currents across that input voltage range.
REV. A
–13–
AD822
The AD822 is designed for 13 nV/√Hz wideband input voltage noise and maintains low noise performance to low frequencies (refer to Figure 11). This noise performance, along with the AD822’s low input current and current noise means that the AD822 contributes negligible noise for applications with source resistances greater than 10 kΩ and signal bandwidths greater than 1 kHz. This is illustrated in Figure 40.
100k WHENEVER JOHNSON NOISE IS GREATER THAN AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE CONSIDERED NEGLIGIBLE FOR APPLICATION. 1kHz 1k RESISTOR JOHNSON NOISE 100
20mV
100 90
2µ s
10 0%
INPUT VOLTAGE NOISE – µVRMS
10k
Figure 41. Small Signal Response of AD822 as Unity Gain Follower Driving 350 pF Capacitive Load
5
10 10Hz 1 AMPLIFIER GENERATED NOISE 0.1 10k 100k 1M 10M 100M SOURCE IMPEDANCE – Ω 1G 10G
4
Figure 40. Total Noise vs. Source Impedance
OUTPUT CHARACTERISTICS
The AD822 s unique bipolar rail-to-rail output stage swings within 5 mV of the minus supply and 10 mV of the positive supply with no external resistive load. The AD822’s approximate output saturation resistance is 40 Ω sourcing and 20 Ω sinking. This can be used to estimate output saturation voltage when driving heavier current loads. For instance, when sourcing 5 mA, the saturation voltage to the positive supply rail will be 200 mV, when sinking 5 mA, the saturation voltage to the minus rail will be 100 mV. The amplifier’s open-loop gain characteristic will change as a function of resistive load, as shown in Figures 7 through 10. For load resistances over 20 kΩ, the AD822’s input error voltage is virtually unchanged until the output voltage is driven to 180 mV of either supply. If the AD822’s output is overdriven so as to saturate either of the output devices, the amplifier will recover within 2 µs of its input returning to the amplifier’s linear operating region. Direct capacitive loads will interact with the amplifier’s effective output impedance to form an additional pole in the amplifier’s feedback loop, which can cause excessive peaking on the pulse response or loss of stability. Worst case is when the amplifier is used as a unity gain follower. Figure 41 shows the AD822’s pulse response as a unity gain follower driving 350 pF. This amount of overshoot indicates approximately 20 degrees of phase margin—the system is stable, but is nearing the edge. Configurations with less loop gain, and as a result less loop bandwidth, will be much less sensitive to capacitance load effects. Figure 42 is a plot of capacitive load that will result in a 20 degree phase margin versus noise gain for the AD822. Noise gain is the inverse of the feedback attenuation factor provided by the feedback network in use.
RF NOISE GAIN – 1+ ––– RI
3
2
1 300
1k 3k 10k CAPACITIVE LOAD FOR 20° PHASE MARGIN – pF
30k
RF CL RI
Figure 42. Capacitive Load Tolerance vs. Noise Gain
Figure 43 shows a method for extending capacitance load drive capability for a unity gain follower. With these component values, the circuit will drive 5,000 pF with a 10% overshoot.
+VS 8 VIN 0.01µF 100Ω 0.01µF CL 20pF 20kΩ VOUT
1/2 AD822
4 –VS
Figure 43. Extending Unity Gain Follower Capacitive Load Capability Beyond 350 pF
– 14–
REV. A
AD822
APPLICATIONS Single Supply Voltage-to-Frequency Converter Table I. AD822 In Amp Performance
The circuit shown in Figure 44 uses the AD822 to drive a low power timer, which produces a stable pulse of width t1. The positive going output pulse is integrated by R1-C1 and used as one input to the AD822, which is connected as a differential integrator. The other input (nonloading) is the unknown voltage, VIN. The AD822 output drives the timer trigger input, closing the overall feedback loop.
+10V C5 0.1µF 3 4 4 U4 REF-02 2 6 VREF = 5V 5 RSCALE ** 10k CMOS 74HCO4 U3B 3 U3A 2 1 U2 CMOS 555 R3 * 116k 4 6 2 7 C6 390pF 5% (NPO) NOTES: fOUT = V IN /(VREF*t 1 ), t 1 = 1.1*R3*C6 = 25kHz f S AS SHOWN. R THR TR DIS GND 1 CV 8 V+ OUT 3 5 OUT2 C3 0.1µF OUT1
Parameters CMRR Common-Mode Voltage Range 3 dB BW, G = 10 G = 100 tSETTLING 2 V Step (VS = 0 V, 3 V) 5 V (VS = ± 5 V) Noise @ f = 1 kHz, G = 10 G = 100 ISUPPLY (Total)
VS = 3 V, 0 V 74 dB
VS = 80 dB
5V
–0.2 V to +2 V –5.2 V to +4 V 180 kHz 180 kHz 18 kHz 18 kHz 2 µs 270 nV/√Hz 2.2 µV/√Hz 1.10 mA 5 µs 270 nV/√Hz 2.2 µV/√Hz 1.15 mA
5µ s
100 90
0.01µF, 2% R2 499k, 1% U1
1/2 AD822B
C1
R1 VIN 499k, 1% 0V TO 2.5V FULL SCALE C2 0.01µF, 2%
C4 0.01µF
10 0%
1V
* = 1% METAL FILM,
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