FEATURES
FUNCTIONAL BLOCK DIAGRAM
Fully integrated, single-lead ECG front end
Low quiescent supply current: 50 µA (typical)
Leads on/off detection while in shutdown ( 50 kΩ
RL = 50 kΩ
Max
Unit
kHz
V/µs
nV/√Hz
µV p-p
µV p-p
7.5
10
+VS − 0.1
µA
V
mA
kΩ
kHz
0.1
IOUT
VOS
IB
IOUT
Typ
15
0.01
120
7
9
11
150
20
180
1
100
12
0.1
+VS − 0.7
+VS − 0.27
125
1.5
fAC
IAC
IDC
50
+IN, SDN = low
−IN, SDN = low
Between +IN and −IN, SDN = high
10
mV
pA
mA
V
V
mV
µs
100
200
250
−300
20
100
175
kHz
nA p-p
nA
nA
MΩ
μs
10
100
12
kΩ
pA
S1 and S2
RON
tS1
Filter Recovery Switch On Time
tS2
Fast Restore Reset
tRST
8
From either rail
100
2
mV
µs
+VS = 3 V
+VS = 1.8 V
+VS = 3 V
+VS = 1.8 V
+VS = 3 V
+VS = 1.8 V
160
80
80
40
3
1.5
ms
Rev. D | Page 4 of 32
ms
µs
Data Sheet
Parameter
LOGIC INTERFACE
Input Characteristics
Input Voltage (AC/DC, FR, and
RLD SDN)
Low
High
Input Voltage (SDN)
Low
High
Output Characteristics
Output Voltage
Low
High
SYSTEM SPECIFICATIONS
Quiescent Supply Current
Wakeup Current
Shutdown Current
Peak-to-Peak Voltage Noise (RTI)
AD8233
Symbol
Test Conditions/Comments
2
Typ
Max
Unit
VIL
VIH
0.41 × +VS
0.45 × +VS
V
V
VIL
VIH
0.6 × + VS
0.3 × + VS
V
V
0.05
+VS − 0.05
V
V
LOD terminal
RL = 100 kΩ
VOL
VOH
50
60
0.65
0.75
0.5
0.6
TA = 0°C to 70°C
SDN = low, LOD = low
TA = 0°C to 70°C
SDN = low, LOD = high
TA = 0°C to 70°C
VDIFF = 0 V
f = 0.5 Hz to 40 Hz
f = 0.05 Hz to 150 Hz
VDIFF = ±0.3 V
f = 0.5 Hz to 40 Hz
f = 0.05 Hz to 150 Hz
Supply Range
Specified Temperature Range
Operational Temperature Range
1
Min
1.7
0
−40
Offset is referred to the input of the instrumentation amplifier inputs.
In ac leads off and shutdown mode, the dc leads off comparator at the +IN pin trips the LOD pin.
Rev. D | Page 5 of 32
70
1.5
1
µA
µA
µA
µA
µA
µA
9
15
µV p-p
µV p-p
11
21
µV p-p
µV p-p
V
°C
°C
3.5
70
+85
AD8233
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Parameter
Supply Voltage
Output Short-Circuit Current Duration
Maximum Voltage, Any Terminal1
Minimum Voltage, Any Terminal1
Storage Temperature Range
Operating Temperature Range
Maximum Junction Temperature
Electrostatic Discharge (ESD) Rating
Human Body Model (HBM)
Field Induced Charged Device Model
(FICDM)
1
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Rating
3.6 V
Indefinite
+VS + 0.3 V
−0.3 V
−65°C to +125°C
−40°C to +85°C
140°C
Table 4. Thermal Resistance
Package
Type
CB-20-13
PCB
1S0P1
2S2P2
8 kV
1 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
0 ms
108.5
101.1
47.9
46.8
θJA (°C/W)
1 ms 2 ms
89.0
82.3
87.3
87.3
43.4
42.1
43.3
42.1
θJC
(°C/W)
0.6
0.6
0.7
0.7
Simulated thermal numbers per JESD51-9: 1-layer PCB (1S0P), low effective
thermal conductivity test board.
2
4-layer PCB (2S2P), high effective thermal conductivity test board.
1
This level or the maximum specified supply voltage, whichever is the lesser,
indicates the superior voltage limit for any terminal. If input voltages beyond
the specified minimum or maximum voltages are expected, place resistors in
series with the inputs to limit the current to less than 5 mA.
Power (W)
0.25
1.25
0.25
1.25
ESD CAUTION
Rev. D | Page 6 of 32
Data Sheet
AD8233
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
BALL A1
INDICATOR
AD8233
1
2
GND
+VS
SDN
AC/DC
3
4
5
REFIN HPSENSE HPDRIVE
A
FR
IAOUT
+IN
LOD
RLD SDN REFOUT RLDFB
–IN
OUT
OPAMP– OPAMP+
RLD
B
C
SW
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
13737-002
D
Figure 2. 20-Ball WLCSP Pin Configuration
Table 5. 20-Ball WLCSP Pin Function Descriptions
Ball No.
A1
A2
A3
A4
Mnemonic
GND
+VS
REFIN
HPSENSE
A5
HPDRIVE
B1
B2
SDN
AC/DC
B3
B4
B5
C1
C2
C3
FR
IAOUT
+IN
LOD
RLD SDN
REFOUT
C4
C5
D1
RLDFB
−IN
OUT
D2
D3
D4
D5
OPAMP−
OPAMP+
SW
RLD
Description
Power Supply Ground.
Power Supply Terminal.
Reference Buffer Input. Use REFIN, a high impedance input terminal, to set the level of the reference buffer.
High-Pass Sense Input for Instrumentation Amplifier. Connect HPSENSE to the junction of R and C that sets the
corner frequency of the dc blocking circuit.
High-Pass Driver Output. Connect HPDRIVE to the capacitor in the first high-pass filter. The AD8233 drives this pin
to keep HPSENSE at the same level as the reference voltage.
Shutdown Control Input. Drive SDN low to enter the low power shutdown mode.
Leads Off Mode Control Input. Drive the AC/DC pin low for dc leads off mode. Drive the AC/DC pin high for ac
leads off mode.
Fast Restore Control Input. Drive FR high to enable fast recovery mode. Otherwise, drive it low.
Instrumentation Amplifier Output Terminal.
Instrumentation Amplifier, Positive Input. +IN is typically connected to the left arm (LA) electrode.
Leads Off Detection Comparator Output.
Right Leg Drive Shutdown Control Input. Drive RLD SDN low to power down the RLD amplifier.
Reference Buffer Output. The instrumentation amplifier output is referenced to this potential. Use REFOUT as a
virtual ground for any point in the circuit that requires a signal reference.
Right Leg Drive Feedback Input. RLDFB is the feedback terminal for the right leg drive circuit.
Instrumentation Amplifier, Negative Input. −IN is typically connected to the right arm (RA) electrode.
Operational Amplifier Output. The fully conditioned heart rate signal is present at this output. OUT can be
connected to the input of an ADC.
Operational Amplifier Inverting Input.
Operational Amplifier Noninverting Input.
Fast Restore Switch Terminal. Connect this terminal to the output of the second high-pass filter.
Right Leg Drive Output. Connect the driven electrode (typically right leg) to the RLD pin.
Rev. D | Page 7 of 32
AD8233
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
+VS = 3 V, VREF = 1.5 V, VCM = 1.5 V, TA = 25°C, unless otherwise noted. All typical performance characteristics are measured for the
WLCSP package.
INSTRUMENTATION AMPLIFIER PERFORMANCE CHARACTERISTICS
2100
100
80
1750
INPUT BIAS CURRENT (pA)
60
UNITS
1400
1050
700
40
20
0
–20
–40
–60
350
30
0
–30
60
90
120
CMRR (µV/V)
0
40
2500
30
GAIN (dB)
3000
1500
10
500
0
–0.5
0
0.5
1.0
1.5
2.0
GAIN ERROR (%)
2.5
3.0
3.5
NO DC OFFSET
300mV OFFSET
–10
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 4. Gain Error Distribution
Figure 7. Gain vs. Frequency
3.5
120
3.0
100
CMRR RTI (dB)
2.5
2.0
1.5
1.0
80
60
0.5
40
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT VOLTAGE (V)
Figure 5. Input Common-Mode Voltage vs. Output Voltage
20
10
100
1k
10k
FREQUENCY (Hz)
Figure 8. CMRR RTI vs. Frequency
Rev. D | Page 8 of 32
100k
13737-008
NO DC OFFSET
+300mV OFFSET
–300mV OFFSET
0
13737-005
INPUT COMMON-MODE VOLTAGE (V)
2.0
20
1000
13737-004
UNITS
50
–1.0
1.5
Figure 6. Input Bias Current vs. Input Common-Mode Voltage
3500
–1.5
1.0
INPUT COMMON-MODE VOLTAGE (V)
Figure 3. CMRR Distribution
0
–2.0
0.5
13737-007
–60
13737-003
–90
–100
13737-006
–80
0
–120
Data Sheet
AD8233
100
90
80
PSRR RTI (dB)
70
5µV/DIV
60
50
40
30
10
1
10
100
1k
10k
100k
FREQUENCY (Hz)
13737-009
200ms/DIV
0
0.1
13737-012
20
Figure 12. 0.5 Hz to 40 Hz Noise (RTI)
Figure 9. PSRR RTI vs. Frequency
1.0
10k
0.9
0.8
GAIN ERROR (%)
100
0.6
0.5
0.4
0.3
0.2
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 10. Voltage Noise Spectral Density (RTI)
0
0
50
100
150
200
250
300
DC OFFSET (mV)
Figure 13. Gain Error vs. DC Offset
22pF
470pF
1nF
5µV/DIV
1s/DIV
400µs/DIV
Figure 11. 0.1 Hz to 10 Hz Noise (RTI)
50mV/DIV
Figure 14. Small Signal Pulse Response
Rev. D | Page 9 of 32
13737-013
1
13737-014
10
0.1
13737-010
0.1
13737-011
NOISE (nV/√Hz)
0.7
1k
AD8233
Data Sheet
0.5V/DIV
70
3.0
60
2.5
50
2.0
40
1.5
30
1.0
20
0.5
10
0
0
–0.5
–10
–1.0
–40
–20
0
20
40
60
–20
100
80
13737-018
13737-015
INPUT BIAS CURRENT (IB) (nA)
3.5
400µs/DIV
80
IB
IOS
INPUT OFFSET CURRENT (IOS) (pA)
4.0
TEMPERATURE (°C)
Figure 18. Input Bias Current (IB) and Input Offset Current (IOS) vs.
Temperature
Figure 15. Large Signal Pulse Response
0.5
1.5
0.4
0.3
0.2
GAIN ERROR (%)
0.5
0
–0.5
0.1
0
–0.1
–0.2
–0.3
–40°C
+25°C
+85°C
–1.5
100
10k
1k
–0.4
1M
100k
LOAD (Ω)
–0.5
–40
0
20
40
60
80
100
80
100
TEMPERATURE (°C)
Figure 16. Output Voltage Swing vs. Load
Figure 19. Gain Error vs. Temperature
10
0.4
8
0.3
6
0.2
4
CMRR (µV/V)
0.1
0
–0.1
2
0
–2
–4
–0.2
–6
–0.3
–8
–20
0
20
40
60
80
100
TEMPERATURE (°C)
–10
–40
–20
0
20
40
60
TEMPERATURE (°C)
Figure 20. CMRR vs. Temperature
Figure 17. DC Blocking Input Offset Drift on Multiple Parts
Rev. D | Page 10 of 32
13737-020
–0.4
–40
13737-017
DC BLOCKING INPUT OFFSET (mV)
–20
13737-019
–1.0
13737-016
OUTPUT VOLTAGE SWING (V)
1.0
Data Sheet
AD8233
OPERATIONAL AMPLIFIER PERFORMANCE CHARACTERISTICS
1000
800
UNITS
600
400
400µs/DIV
–2
0
2
4
OFFSET VOLTAGE (mV)
Figure 24. Large Signal Transient Response
Figure 21. Offset Distribution
80
–40
60
–60
40
–80
20
–100
0
–120
–20
–140
–40
–160
–60
0.1
1
10
100
1k
–180
100k
10k
VOLTAGE NOISE SPECTRAL DENSITY (nV/√Hz)
–20
FREQUENCY (Hz)
Figure 22. Open-Loop Gain and Phase Margin vs. Frequency
10k
1k
100
10
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 25. Voltage Noise Spectral Density vs. Frequency
22pF
470pF
1nF
100µs/DIV
20mV/DIV
1s/DIV
Figure 26. 0.1 Hz to 10 Hz Noise
Figure 23. Small Signal Response for Various Capacitive Loads
Rev. D | Page 11 of 32
13737-026
5µV/DIV
13737-023
OPEN-LOOP GAIN (dB)
100
0
PHASE MARGIN (Degrees)
GAIN
PHASE MARGIN
13737-022
120
13737-025
–4
0.5V/DIV
13737-021
0
13737-024
200
AD8233
Data Sheet
1.5
5µV/DIV
0.5
0
–0.5
–40°C
+25°C
+85°C
200ms/DIV
13737-027
–1.0
–1.5
100
10k
1k
100k
1M
LOAD (Ω)
Figure 29. Output Voltage Swing vs. Load
Figure 27. 0.5 Hz to 40 Hz Noise
100
120
80
110
100
60
90
40
80
PSRR (dB)
20
0
–20
70
60
50
40
–40
30
–60
20
–80
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
INPUT COMMON-MODE VOLTAGE (V)
0
0.1
1
10
100
1k
10k
FREQUENCY (Hz)
Figure 30. Power Supply Rejection Ratio vs. Frequency
Figure 28. Input Bias Current vs. Input Common-Mode Voltage
Rev. D | Page 12 of 32
100k
13737-030
10
–100
13737-028
INPUT BIAS CURRENT (pA)
13737-029
OUTPUT VOLTAGE SWING (V)
1.0
Data Sheet
AD8233
INPUT BIAS CURRENT (pA)
1k
10
1
0.1
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 31. Load Transient Response (100 μA Load Change)
Figure 33. Input Bias Current vs. Temperature
0.8
0.6
0.2
0
–0.2
–0.4
–0.6
–0.8
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
100
13737-032
OFFSET (mV)
0.4
Figure 32. Offset vs. Temperature on Multiple Parts
Rev. D | Page 13 of 32
100
13737-033
13737-031
50mV/DIV
100µs/DIV
100
AD8233
Data Sheet
RLD AMPLIFIER PERFORMANCE CHARACTERISTICS
–20
–40
80
–60
60
–80
40
–100
20
–120
0
–140
–20
–160
OPEN-LOOP GAIN (dB)
100
–40
0.1
100
10
1
1k
10k
5µV/DIV
13737-037
120
0
PHASE MARGIN (Degrees)
GAIN
PHASE MARGIN
1s/DIV
–180
100k
13737-034
140
FREQUENCY (Hz)
Figure 37. 0.1 Hz to 10 Hz Noise
Figure 34. Open-Loop Gain and Phase Margin vs. Frequency
1.5
0.5
5µV/DIV
0
–40°C
+25°C
+85°C
–1.0
–1.5
100
1k
100k
10k
200ms/DIV
1M
LOAD (Ω)
Figure 38. 0.5 Hz to 40 Hz Noise
Figure 35. Output Voltage Swing vs. Load
12
10k
AC/DC = LOW, RLD SDN = HIGH
1k
100
8
6
4
2
10
0.1
1
10
100
1k
10k
FREQUENCY (Hz)
100k
0
–40
+VS = 1.8V
+VS = 3V
+VS = 3.5V
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 39. RLD Supply Current vs. Temperature
Figure 36. Voltage Spectral Noise Density vs. Frequency
Rev. D | Page 14 of 32
100
13737-039
RLD SUPPLY CURRENT (µA)
10
13737-036
VOLTAGE NOISE SPECTRAL DENSITY (nV/√Hz)
13737-038
–0.5
13737-035
OUTPUT VOLTAGE SWING (V)
1.0
Data Sheet
AD8233
REFERENCE BUFFER PERFORMANCE CHARACTERISTICS
15
100k
SOURCE
SINK
OUTPUT IMPEDANCE (Ω)
10k
5
0
–5
100
10
1
LOAD CURRENT (mA)
1
0.1
1
10
100
1k
10k
13737-042
0.1
13737-040
–15
0.01
1k
10
–10
100k
FREQUENCY (Hz)
Figure 40. Load Regulation
Figure 42. Output Impedance vs. Frequency
50mV/DIV
100µs/DIV
100
10
1
0.1
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 41. Load Transient Response (100 μA Load Change)
Figure 43. Input Bias Current vs. Temperature
Rev. D | Page 15 of 32
100
13737-043
INPUT BIAS CURRENT (pA)
1k
13737-041
OUTPUT ERROR (mV)
10
AD8233
Data Sheet
SYSTEM PERFORMANCE CHARACTERISTICS
SDN = HIGH, AC/DC = LOW, RLD SDN = LOW
60
50
40
30
20
+VS = 1.8V
+VS = 3V
+VS = 3.5V
10
0
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
13737-044
SUPPLY CURRENT (µA)
70
10k
1k
100
10
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 47. Voltage Noise Spectral Density (RTI), Measured at IAOUT
Figure 44. Supply Current vs. Temperature
900
SDN = LOW, AC/DC = LOW
RLD SDN = LOW, LOD = HIGH
700
600
5µV/DIV
500
400
300
+VS = 1.8V
+VS = 3V
+VS = 3.5V
100
0
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
200ms/DIV
13737-048
200
13737-045
SHUTDOWN CURRENT (nA)
800
Figure 48. 0.5 Hz to 40 Hz Noise (RTI), Measured at IAOUT
Figure 45. Shutdown Current vs. Temperature
1000
900
SDN = LOW, AC/DC = LOW
RLD SDN = LOW, LOD = LOW
700
10µV/DIV
600
500
400
300
+VS = 1.8V
+VS = 3V
+VS = 3.5V
100
0
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
100
2s/DIV
13737-049
200
13737-046
WAKEUP CURRENT (nA)
800
Figure 49. 0.05 Hz to 150 Hz Noise (RTI), Measured at IAOUT
Figure 46. Wakeup Current vs. Temperature
Rev. D | Page 16 of 32
13737-047
VOLTAGE NOISE SPECTRAL DENSITY (nV/√Hz)
80
Data Sheet
AD8233
THEORY OF OPERATION
The feedback of the amplifier is applied via GM2 through two
separate paths: the two resistors divide the output signal to set
an overall gain of 100, whereas the dc blocking amplifier
integrates any deviation from the reference level. Consequently,
dc offsets as large as ±300 mV across the GM1 inputs appear
inverted and with the same magnitude across the inputs of
GM2, all without saturating the signal of interest.
ARCHITECTURE OVERVIEW
The AD8233 is an integrated front end for signal conditioning
of cardiac biopotentials for heart rate monitoring. It consists of
a specialized instrumentation amplifier (IA), an operational
amplifier (A1), a right leg drive amplifier (A2), and a
midsupply reference buffer (A3). In addition, the AD8233
includes leads on or off detection circuitry and an automatic
fast restore circuit that restores the signal shortly after leads are
reconnected.
To increase the common-mode voltage range of the instrumentation amplifier, a charge pump boosts the supply voltage for
the two transconductance amplifiers. This boost in supply
voltage further prevents saturation of the amplifier in the
presence of large common-mode signals, such as line
interference. The charge pump runs from an internal oscillator,
the frequency of which is set around 500 kHz.
The AD8233 contains a specialized instrumentation amplifier
that amplifies the ECG signal while rejecting the electrode half cell
potential on the same stage. The amplification of the ECG signal
and the rejection of the electrode half cell potential are possible
with an indirect current feedback architecture, which reduces
size and power compared with traditional implementations.
OPERATIONAL AMPLIFIER
INSTRUMENTATION AMPLIFIER
The general-purpose operational amplifier (A1) is a rail-to-rail
device that can be used for low-pass filtering and to add
additional gain. The following sections provide details and
example circuits that use this amplifier.
The instrumentation amplifier shown in Figure 50 is composed
of two well matched transconductance amplifiers (GM1 and
GM2), the dc blocking amplifier (HPA), and an integrator
formed by C1 and an op amp. The transconductance amplifier,
GM1, generates a current that is proportional to the voltage
present at its inputs. When the feedback is satisfied, an equal
voltage appears across the inputs of the transconductance
amplifier, GM2, thereby matching the current generated by
GM1. The difference generates an error current that is integrated
across Capacitor C1. The resulting voltage appears at the
output of the instrumentation amplifier.
RLD AMPLIFIER
The RLD amplifier inverts the common-mode signal that is
present at the instrumentation amplifier inputs. When the right
leg drive output current is injected into the subject, it
counteracts common-mode voltage variations, thus improving
the common-mode rejection of the system.
+VS
HPDRIVE
HPSENSE
IAOUT
SW
A2
A5
A4
B4
D4
OPAMP–
D3
D2
10kΩ
CHARGE
PUMP
+VS
OPAMP+
A1
D1 OUT
S2
AC/DC
+IN B5
RFI
FILTER
–IN C5
HPA
GM1
GM2
VCM
AC/DC
S1
R
10kΩ
B3 FR
+VS – 0.1V
99R
B1 SDN
C1
0.1V
B2 AC/DC
INSTRUMENTATION AMPLIFIER (IA)
S1
S2
SYNC
RECTIFIER
RLDFB C4
SWITCH
TIMING
0.7V
RLD SDN C2
RLD D5
C1 LOD
A2
150kΩ
AC/DC
+VS – 0.27V
A1 GND
C3 REFOUT
A3
*ALL SWITCHES SHOWN IN DC LEADS OFF DETECTION POSITION AND FAST RESTORE DISABLED
= REFOUT
Figure 50. Simplified Schematic Diagram
Rev. D | Page 17 of 32
13737-050
REFIN A3
AD8233
Data Sheet
An integrator can be built by connecting a capacitor between
the RLD FB and RLD terminals. A good starting point is a 1 nF
capacitor, which places the crossover frequency at about 1 kHz
(the frequency at which the amplifier has an inverting unity
gain). This configuration results in about 26 dB of loop gain
available at a frequency range from 50 Hz to 60 Hz for
common-mode line rejection. Higher capacitor values reduce
the crossover frequency, thereby reducing the gain that is
available for rejection and, consequently, increasing the line
noise. Lower capacitor values move the crossover frequency to
higher frequencies, allowing increased gain. However, when
using higher gain, the system can become unstable and saturate
the output of the right leg amplifier.
When using this amplifier to drive an electrode, place a resistor
in series with the output to limit the current to be always less
than 10 µA, even in fault conditions. For example, if the supply
used is 3.0 V, ensure that the resistor is greater than 330 kΩ to
account for component and supply variations.
The reference voltage level is set at the REFIN pin. It can be set
with a voltage divider or by driving the REFIN pin from some
other point in the circuit (for example, from the ADC reference).
The voltage is available at the REFOUT pin for the filtering circuits
or for an ADC input.
+VS
R1
A3
R2
To limit the power consumption of the voltage divider, the use
of large resistors is recommended, such as 10 MΩ. The designer
must keep in mind that high resistor values make it easier for
interfering signals to appear at the input of the reference buffer.
To minimize noise pickup, it is recommended to place the
resistors close to each other and as near as possible to the
REFIN terminal. Furthermore, use a capacitor in parallel with
the lower resistor on the divider for additional filtering, as
shown in Figure 52. A large capacitor results in better noise
filtering but takes longer to settle the reference after power-up.
The total time the reference takes to settle within 1% can be
estimated with the formula
RLDFB
tSETTLE_REFERENCE = 5 ×
150kΩ
REFOUT
*LIMIT CURRENT TO LESS THAN 10µA.
FAST RESTORE CIRCUIT
Figure 51. Typical Configuration of Right Leg Drive Circuit
In two electrode configurations, A2 can be shut down by setting
RLD SDN low for additional power savings. If left in shutdown,
it is recommended to leave both RLD and RLDFB floating.
Alternatively, RLD can be used to bias the inputs through
10 MΩ resistors, as described in the Leads On or Off Detection
section. When the AD8233 is in shutdown and dc leads off
detection mode, RLD pulls down towards ground. This pulldown acts as an LOD wake-up function, pulling the inputs
down when the electrodes are reconnected.
REFERENCE BUFFER
Because of the low cutoff frequency used in high-pass filters in
ECG applications, signals may require several seconds to settle.
This settling time can result in a delay for the user after a step
response, such as when the electrodes are first connected.
This fast restore function is implemented internally, as shown
in Figure 53. The output of the instrumentation amplifier is
connected to a window comparator. The window comparator
detects a saturation condition at the output of the instrumentation
amplifier when its voltage approaches 0.1 V from either supply
rail.
FR B3
S1
+VS – 0.1V
+IN
SWITCH
TIMING
B5
The AD8233 operates from a single supply. To simplify the
design of single-supply applications, the AD8233 includes a
reference buffer to create a virtual ground between the supply
voltage and the system ground. The signals present at the
output of the instrumentation amplifier are referenced around
this voltage. For example, if there is zero differential input
voltage, the voltage at the output of the instrumentation
amplifier is this reference voltage.
IA
C5
–IN
Rev. D | Page 18 of 32
S2
IAOUT
0.1V
LOD C1
Figure 53. Fast Restore Circuit
13737-053
A2
VCM
13737-051
18
D5
R1 × R2 × C1
R1 + R2
Disabling the AD8233 with the shutdown terminal does not
discharge this capacitor.
1nF
TO DRIVEN R*
ELECTRODE
A3
C1
Figure 52. Setting the Internal Reference
C4
RLD
REFIN
13737-052
The common-mode signal that is present across the inputs of the
instrumentation amplifier is derived from the transconductance
amplifier, GM1. It is then connected to the inverting input of
A2 through a 150 kΩ resistor.
Data Sheet
AD8233
SATURATION DETECTED
NO SATURATION
tS1
S1
tS2
S2
13737-054
tRST
LEADS OFF
LEADS ON
Figure 54. Timing Diagram for Fast Restore Switches (Time Base Not to Scale)
If this saturation condition is present when both input
electrodes are attached to the subject, the comparator triggers a
timing circuit that automatically closes Switch S1 and Switch
S2. See Figure 54 for the fast restore switches timing diagram.
10MΩ
B5
IA
C5
Figure 55. Circuit Configuration for Two Electrode DC Leads Off Detection
For three electrode dc mode, each input must have a pull-up
resistor connected to the positive supply. During normal
operation, the potential of the subject must be inside the
common-mode range of the instrumentation amplifier, which
is only possible if a third electrode is connected to the output of
the right leg drive amplifier.
+VS
If, by the end of the timing, the saturation condition persists,
the cycle repeats. Otherwise, the AD8233 returns to its normal
operation. If either of the leads off comparator outputs
indicates that an electrode is disconnected, the timing circuit is
prevented from triggering because it is assumed that no valid
signal is present. To disable fast restore, drive the FR pin low or
tie it permanently to GND.
LEADS ON OR OFF DETECTION
The AD8233 includes leads off detection. The AD8233 features
ac and dc detection modes that both work with two and three
electrode configurations. Ultralow power comparators allow
the leads on or off detection to remain functional in shutdown
mode, creating power savings at the system level when the LOD
output is used as a wake-up signal for the microcontroller.
DC Leads On or Off Detection
The dc leads off detection mode can be used in two or three
electrode configurations. This mode works by sensing when
either instrumentation amplifier input voltage is within 0.27 V
from the positive rail. The lowest power use case for the
AD8233 is two electrode dc mode. A pull-up resistor on +IN
and a pull-down resistor on −IN create a voltage divider when
the electrodes are connected, setting the input common mode
to midsupply. When the electrodes disconnect, the comparator
monitoring +IN sets LOD high when the input pulls to +VS.
13737-055
10MΩ
10MΩ
10MΩ
B5
IA
C5
TO DRIVEN
ELECTRODE
D5
RLD
13737-056
These two switches (S1 and S2) enable two different 10 kΩ
resistor paths: one between HPSENSE and IAOUT, and
another between SW and REFOUT. During the time Switch S1
and Switch S2 are enabled, the internal resistors appear in
parallel with their corresponding external resistors, forming
high-pass filters. The result is that the equivalent lower
resistance shifts the pole to a higher frequency, delivering a
quicker settling time. The fast restore settling time depends on
how quickly the internal 10 kΩ resistors of the AD8233 can
drain the capacitors in the high-pass circuit. Smaller capacitor
values result in a shorter settling time.
+VS
Figure 56. Circuit Configuration for Three Electrode DC Leads Off Detection
The AD8233 indicates when any electrode is disconnected by
setting the LOD pin high. To use this mode, connect the
AC/DC pin to ground.
AC Leads On or Off Detection
The ac leads off detection mode is useful when using two
electrodes. A conduction path must exist between the two
electrodes, which is usually formed by two resistors, as shown
in Figure 57.
These resistors also provide a path for bias return on each
input. Connect each resistor to REFOUT or RLD to maintain the
inputs within the common-mode range of the instrumentation
amplifier.
Rev. D | Page 19 of 32
AD8233
Data Sheet
STANDBY OPERATION
+VS
A2
The AD8233 includes a shutdown pin (SDN) that further
enhances the flexibility and ease of use in portable applications
where low power consumption is critical. A logic level signal
can be applied to this pin to switch to shutdown mode.
IA
C5
10MΩ
13737-057
10MΩ
C3 REFOUT
Figure 57. Circuit Configuration for Two Electrode AC Leads Off Detection
The AD8233 detects when an electrode is disconnected by
forcing a 100 kHz current into the input terminals. This current
flows through the external resistors from IN+ to IN− and
develops a differential voltage across the inputs, which is then
synchronously detected and compared to an internal threshold.
The recommended value for these external resistors is 10 MΩ.
Low resistance values make the differential drop too low to be
detected and lower the input impedance of the amplifier. When
the electrodes are attached to the subject, the impedance of this
path must be less than 3 MΩ to maintain the drop below the
threshold of the comparator.
To use the ac leads off mode, tie the AC/DC pin to the positive
supply rail. Although REFOUT is at a constant voltage value,
using the RLD output as the input bias may be more effective in
rejecting common-mode interference at the expense of
additional power.
Driving the SDN pin low places the AD8233 in shutdown mode
and draws less than 1 µA of supply current, offering considerable
power savings. To enter normal operation, drive SDN high. When
not using this feature, permanently tie SDN to +VS.
During shutdown operation, the AD8233 cannot maintain the
REFOUT voltage, but it does not drain the REFIN voltage,
thereby maintaining this additional conduction path from the
supply to ground.
When emerging from a shutdown condition, the charge stored
in the capacitors on the high-pass filters can saturate the instrumentation amplifier and subsequent stages. The use of the fast
restore feature helps reduce the recovery time and, therefore,
minimize the amount of time powered on in power sensitive
applications.
Using leads on or off detection in shutdown mode allows
system level power saving. The microcontroller enters sleep
mode when the electrodes are disconnected, and the LOD signal
acts as an interrupt to wake up the microcontroller. An example
of this functionality is shown in Figure 59.
In three electrode ac leads off detection mode, shown in Figure 58,
pull-up resistors are not required, which improves the input
impedance of the circuit. This mode is beneficial for dry electrode
applications. The ac mode currents contribute flicker noise (1/f
noise) to the system. Depending on the application, use ac leads
off detection as a spot check and then switching to dc mode for
improved ECG acquisition.
OUT
SDN
LOD
3MCU WAKES UP
AND SETS SDN HIGH.
1AT LEAST ONE ELECTRODE IS OFF
AND THEREFORE LOD OUTPUT IS HIGH.
MCU IS OFF AND SDN IS LOW.
(AD8233 SHUTDOWN CURRENT < 1µA)
4AD8233 IS ACTIVE (~50µA)
AND MONITORING ECG.
+VS
2LOD GOES LOW WHEN BOTH
ELECTRODES ARE CONNECTED.
A FALLING EDGE AT LOD WAKES UP
THE MCU.
A2
250mV/DIV
400ms/DIV
B5
IA
C5
13737-059
B5
Figure 59. Electrode Connection and System Wakeup Sequence
D5 RLD
13737-058
INPUT PROTECTION
TO DRIVEN
ELECTRODE
Figure 58. Circuit Configuration for Three Electrode AC Leads Off Detection
The ac leads off detection mode continues to function in
shutdown mode as well. To keep the power under 1 µA, the
clock is disabled and the ac currents become dc currents. The
current source on +IN is 250 nA, while the current sink on –IN
is −300 nA. The stronger pull-down current on −IN acts as a
wake-up function, pulling LOD low when the electrodes are
reconnected.
All terminals of the AD8233 are protected against ESD. In
addition, the input structure allows dc overload conditions that
are a diode drop above the positive supply and a diode drop
below the negative supply. Voltages beyond a diode drop of the
supplies cause the ESD diodes to conduct and enable current to
flow through the diode. Use an external resistor in series with
each of the inputs to limit current for voltages beyond the
supplies. In either scenario, the AD8233 safely handles a
continuous 5 mA current at room temperature.
For applications where the AD8233 encounters extreme overload voltages, such as in cardiac defibrillators, use external
series resistors and gas discharge tubes (GDTs). Neon lamps
are commonly used as an inexpensive alternative to GDTs.
Rev. D | Page 20 of 32
Data Sheet
AD8233
These devices can handle the application of large voltages but
do not maintain the voltage below the absolute maximum
ratings for the AD8233. A complete solution includes further
clamping to either supply using additional resistors and low
leakage diode clamps, such as BAV199 or FJH1100.
As a safety measure, place a resistor between the input pin and
the electrode that is connected to the subject to ensure that the
current flow never exceeds 10 µA. Calculate the value of this
resistor to be equal to the supply voltage across the AD8233
divided by 10 µA.
In addition, excessive noise on the supply pins can adversely
affect performance. As in all linear circuits, bypass capacitors
must be used to decouple the chip power supplies. Place a
0.1 μF capacitor close to the supply pin. A 1 μF capacitor can be
used farther away from the device. In most cases, the capacitor
can be shared by other integrated circuits. Excessive decoupling
capacitance increases power dissipation during power cycling.
INPUT REFERRED OFFSETS
RADIO FREQUENCY INTERFERENCE
Because of its internal architecture, the instrumentation
amplifier must always be used with the dc blocking amplifier,
labeled HPA in Figure 50.
Radio frequency (RF) rectification is often a problem in
applications where there are large RF signals. The problem
appears as a dc offset voltage at the output. The AD8233 has a
15 pF gate capacitance and 10 kΩ resistors at each input. This
forms a low-pass filter on each input that reduces rectification
at high frequency (see Figure 60) without the addition of
external elements.
The dc blocking amplifier attenuates the input referred offsets
present at the inputs of the instrumentation amplifier, as
described in the Theory of Operation section. However, this
attenuation only occurs when the dc blocking amplifier is used
as an integrator. In this case, the input offsets from the dc
blocking amplifier are dominant and appear directly at the
output of the instrumentation amplifier.
+IN
If the dc blocking amplifier is used as a follower instead of its
intended function as an integrator, the input referred offsets of
the in-amp are amplified by a factor of 100.
10kΩ
CG
–IN
10kΩ
AD8233
IAOUT
LAYOUT RECOMMENDATIONS
13737-060
CG
Figure 60. RFI Filter Without External Capacitors
For increased filtering, additional resistors can be added in
series with each input. They must be placed as close as possible
to the instrumentation amplifier inputs. These can be the same
resistors used for overload and patient protection.
POWER SUPPLY REGULATION AND BYPASSING
The AD8233 is designed to be powered directly from a single
3 V battery, such as a CR2032. The AD8233 can also operate
from rechargeable Li-Ion batteries, but the designer must take
into account that the voltage during a charge cycle may exceed
the absolute maximum ratings of the AD8233. To avoid
damage to the device, use a power switch or a low power, low
dropout regulator, such as the ADP150 or ADP160.
It is important to follow good layout practices to optimize
system performance. In low power applications, most resistors
are of a high value to minimize additional supply current. The
challenge of using high value resistors is that high impedance
nodes become even more susceptible to noise pickup and board
parasitics, such as capacitance and surface leakages. Keep all of
the connections between high impedance nodes as short as
possible to avoid introducing additional noise and errors from
corrupting the signal.
To maintain high CMRR over frequency, keep the input traces
symmetrical and length matched. Place safety and input bias
resistors in the same position relative to each input. In addition,
the use of a ground plane significantly improves the noise
rejection of the system.
For WLCSP layout best practices, refer to the AN-617
Application Note.
Rev. D | Page 21 of 32
AD8233
Data Sheet
APPLICATION INFORMATION
ELIMINATING ELECTRODE OFFSETS
50
To achieve offset rejection, connect a resistor/capacitor (RC)
network between the output of the instrumentation amplifier
(HPSENSE) and HPDRIVE, as shown in Figure 61.
C
30
20dB PER
DECADE
20
R
A4
10
IAOUT
0
0.01
IN+
HPA
B5
GM1
GM2
S1
R
ELECTRODE
OFFSETS
99R
C1
= REFOUT
Figure 61. Eliminating Electrode Offsets
This RC network forms an integrator that feeds any dc signals
that are not filtered back into the instrumentation amplifier,
thus eliminating the offsets without saturating any node and
maintaining high signal gain.
In addition to blocking offsets present across the inputs of the
instrumentation amplifier, this integrator also works as a high-pass
filter that minimizes the effect of slow moving signals, such as
baseline wander. The cutoff frequency of the filter is given by
the following equation:
fC =
10
100
Figure 62. Frequency Response of a Single-Pole DC Blocking Circuit
13737-061
IN–
1
FREQUENCY (Hz)
C5
VCM
0.1
10kΩ
13737-062
B4
HPSENSE
100
2πRC
As with any high-pass filter with low frequency cutoff, a fast
change in dc offset requires a long time to settle. If such a change
saturates the instrumentation amplifier output, the S1 switch
briefly enables the 10 kΩ resistor path, thus moving the cutoff
frequency to
fC =
100(R + 104 )
2πRC(104 )
For values of R greater than 100 kΩ, this expression can be
approximated by
fC =
1
200 πC
This higher cutoff frequency reduces the settling time and
enables faster recovery of the ECG signal. For more
information, see the Fast Restore Circuit section.
HIGH-PASS FILTERING
where:
R is in Ω.
C is in farads.
The filter cutoff is 100 times higher than is typically expected
from a single-pole filter. Because of the feedback architecture of
the instrumentation amplifier, the typical filter cutoff equation
is modified by a gain of 100 from the instrumentation
amplifier.
The AD8233 can implement higher order high-pass filters. A
higher filter order yields better artifact rejection, but increased
signal distortion and more passive components on the PCB.
Two-Pole High-Pass Filter
A two-pole architecture can be implemented by adding a
simple ac coupling RC at the output of the instrumentation
amplifier, as shown in Figure 63.
C1
A5
HPDRIVE
D4
B4
A4
IAOUT
HPSENSE
HPA
+IN
TO NEXT
STAGE
C2
R1
S1
10kΩ
SW
10kΩ
R2
S2
B5
C5
REFOUT C3
–IN
= REFOUT
Figure 63. Schematic for a Two-Pole High-Pass Filter
Rev. D | Page 22 of 32
13737-063
A5
HPDRIVE
40
MAGNITUDE (dB)
The instrumentation amplifier in the AD8233 is designed to
apply gain and to filter out near dc signals simultaneously. This
capability allows the device to amplify a small ECG signal by a
factor of 100 while rejecting electrode offsets as large as ±300 mV.
Data Sheet
AD8233
The right side of C2 connects to the SW terminal. As with S1,
S2 reduces the recovery time for the ac coupling network by
placing 10 kΩ in parallel with R2. See the Fast Restore Circuit
section for additional details on switch timing and trigger
conditions.
If the passive network is not buffered, the network exhibits
higher output impedance at the input of a subsequent low-pass
filter, as with Sallen-Key filter topologies. Careful component
selection results in reliable performance without a buffer. See
the Low-Pass Filtering and Gain section for additional
information on component selection.
Additional High-Pass Filtering Options
In addition to the topologies explained in previous sections, an
additional pole may be added to the dc blocking circuit for the
rejection of low frequency signals. This configuration is shown
in Figure 64.
C1
R1
The cutoff frequency is located at
fC =
10
2π R1 × C1 × R2 × C2
The selection of RCOMP to be 0.14 times the value of the other
two resistors optimizes the filter for a maximally flat pass band.
Reduce the value of RCOMP to increase the Q and, consequently,
the peaking of the filter. A very low RCOMP value may result in
an unstable circuit. The selection of values based on these criteria
results in a transfer function similar to what is shown in Figure 66.
When additional low frequency rejection is desired, a highorder, high-pass filter can be implemented by adding an ac
coupling network at the output of the instrumentation amplifier,
as shown in Figure 65. The SW terminal is connected to the ac
coupling network to obtain the best settling time response
when fast restore engages.
C1
R1
TO NEXT
STAGE
C3
R2
TO NEXT
STAGE
R2
RCOMP
RCOMP
A5
HPDRIVE
A4
A5
HPDRIVE
+IN
IAOUT
HPA
10kΩ
S1
B4
D4
SW
10kΩ
IAOUT
D4
B4
HPSENSE
A4
HPSENSE
SW
10kΩ
C2
HPA
+IN
S1
10kΩ
C2
R3
S2
B5
S2
B5
C5
REFOUT C3
–IN
C5
13737-065
REFOUT C3
= REFOUT
Figure 65. Schematic for a Three-Pole, High-Pass Filter
Figure 64. Schematic for an Alternative Two-Pole, High-Pass Filter
60
With this circuit topology, the filter attenuation reverts to a
single-pole roll-off at very low frequencies. Because the initial
roll-off is 40 dB per decade, this reversion to 20 dB per decade
has little impact on the ability of the filter to reject out-of-band
low frequency signals.
The designer may choose different values to achieve the desired
filter performance. To simplify the design process, use the
following recommendations as a starting point for component
value selection.
R1 = R2 ≥ 100 kΩ
C1 = C2
RCOMP = 0.14 × R1
40dB PER
DECADE
40
MAGNITUDE (dB)
An extra benefit of this circuit topology is that it allows a lower
cutoff frequency with lower R and C values. The resistor, RCOMP,
can also be used to control the quality factor (Q) of the filter to
achieve narrow band-pass filters (for heart rate detection) or
maximum pass-band flatness (for cardiac monitoring).
20
60dB PER
DECADE
20dB PER
DECADE
0
–20
–40
–60
0.01
40dB PER
DECADE
0.1
THREE-POLE FILTER
TWO-POLE FILTER
1
FREQUENCY (Hz)
10
100
13737-066
= REFOUT
13737-064
–IN
Figure 66. Frequency Response of the Circuits Shown in Figure 64 and
Figure 65
Careful analysis and adjustment of all of the component values in
practice is recommended to optimize the filter characteristics. To
reduce the value of RCOMP, increase the peaking of the active filter to
overcome the additional roll-off introduced by the ac coupling
network. Proper adjustment yields the best pass-band flatness.
Rev. D | Page 23 of 32
AD8233
Data Sheet
Table 6. Comparison of High-Pass Filtering Options
Filter
Order
1
2
2
3
Figure to Reference
Figure 61
Figure 63
Figure 64
Figure 65
1
2
Component Count
2
4
5
7
Capacitor
Sizes/Values
Large
Large
Smaller
Smaller
Low Frequency Rejection
Good
Better
Better
Best
Signal
Distortion1
Low
Medium
Medium
Highest
Output
Impedance2
Low
Higher
Low
Higher
The signal distortion is for the equivalent corner frequency location.
Output impedance refers to the drive capability of the high-pass filter before the low-pass filter. Low output impedance is desirable to allow flexibility in the selection
of values for a low-pass filter, as explained in the Low-Pass Filtering and Gain section.
The design of the high-pass filter involves trade-offs between
signal distortion, component count, low frequency rejection,
and component size. For example, a single-pole, high-pass filter
results in the least distortion to the signal, but the associated
rejection of low frequency artifacts is the lowest of the available
filter options. Table 6 compares the recommended filtering
options.
narrow-band applications to increase peaking and the
selectivity of the band-pass filter.
A common design procedure is to set R1 = R2 = R and C1 = C2 =
C, simplifying the expressions for the cutoff frequency and Q to
fC = 1/(2πRC)
Q=
LOW-PASS FILTERING AND GAIN
The AD8233 includes an uncommitted op amp that can be
used for extra gain and filtering. For applications that do not
require a high order filter, a simple RC low-pass filter is
sufficient, and the op amp can buffer or further amplify the signal.
FROM IN-AMP
STAGE
R
FILTERED
SIGNAL
A1
C
13737-067
REFOUT
Figure 67. Schematic for a Single-Pole, Low-Pass Filter and Additional Gain
A Sallen-Key filter topology can be implemented for
applications that require a steeper roll-off or a sharper cutoff
frequency, as shown in Figure 68.
R2
FILTERED
SIGNAL
A1
R3
REFOUT
R4
13737-068
C2
Figure 68. Schematic for a Two-Pole, Low-Pass Filter
The following equations describe the low-pass cutoff frequency
(fC), gain, and Q:
fC =
These design equations only hold true in a case where the
output impedance of the previous stage is much lower than the
input impedance of the Sallen-Key filter. The design equations
do not hold true when using an ac coupling network between
the instrumentation amplifier output and the input of the lowpass filter without a buffer.
To connect these two filtering stages properly without a buffer,
make the value of R1 at least 10 times larger than the resistor of
the ac coupling network (labeled as R2 in Figure 63).
The ability of AD8233 to drive capacitive loads makes it ideal
for driving an ADC without an additional buffer. However,
depending on the input architecture of the ADC, a simple, lowpass RC network may be required to decouple the transients
from the switched capacitor input that are typical of modern
ADCs. This RC network also acts as an additional filter that can
help reduce noise and aliasing. Follow the recommended
guidelines from the ADC in use for the selection of proper R
and C values. Table 7 lists compatible ADCs by category.
Table 7. Compatible ADCs by Category
1
2π R1 × C1 × R2 × C 2
ADCs
AD7091
AD7988-1
AD7682
AD7689
Gain = 1 + R3/R4
Q=
Q can be controlled by setting the gain with R3 and R4, but this
setting limits the gain to be less than 3. The circuit becomes
unstable for gain values equal to or greater than 3. A simple
modification that allows higher gains is to make the value of C2
at least four times larger than C1.
Driving ADCs
C1
FROM IN-AMP
STAGE
R1
1
3 − Gain
R1 × C1 × R2 × C2
R1 × C2 + R2 × C2 + R1 × C1(1 − Gain)
Changing the gain has an effect on Q and vice versa. Common
values for Q are 0.5, to avoid peaking, or 0.7 for maximum
flatness and a sharp cutoff frequency. Use a high Q value in
Rev. D | Page 24 of 32
Microcontrollers
ADuCM350
ADuCM3029
ADuCM4050
Optical/
Bio-Z Sensors
ADPD1081
ADPD188GG
ADPD1080
ADPD4000
AD5940
Accelerometers
ADXL363
Data Sheet
AD8233
APPLICATION CIRCUITS
AD8233
Heart Rate Measurement (HRM) Next to the Heart
C
Figure 69. Driving an ADC
DRIVEN ELECTRODE
A driven electrode (or reference electrode) is often used to
minimize the effects of common-mode voltages induced by the
power line and other interfering sources. The AD8233 extracts
the common-mode voltage from the instrumentation amplifier
inputs and makes it available through the RLD amplifier to
drive an opposing signal into the patient. This functionality
maintains the voltage between the patient and the AD8233 at a
near constant, greatly improving the CMRR.
For wearable exercise devices, the AD8233 is typically placed in
a pod near the heart. The two sense electrodes are placed under
the pectoral muscles, and no driven electrode is used. Because
the distance from the heart to the AD8233 is small, the heart
signal is strong and there is less muscle artifact interference.
In this wearable device configuration, space is at a premium. By
using as few external components as possible, the circuit shown
in Figure 70 is optimized for size.
0.22µF
ELECTRODE
INTERFACE
10MΩ
As a safety measure, place a resistor between the RLD pin and
the electrode connected to the subject to ensure that current
flow never exceeds 10 µA. Calculate the value of this resistor to be
equal to the supply voltage across the AD8233 divided by 10 µA.
The AD8233 implements an integrator formed by an internal
150 kΩ resistor and an external capacitor to drive this
electrode. The choice of the integrator capacitor is a trade-off
between line rejection capability and stability. It is recommended
that the capacitor be small to maintain as much loop gain as
possible, around 50 Hz and 60 Hz, which is typical for line
frequencies. For stability, it is recommended that the gain of the
integrator be less than unity gain at the frequency of any other
poles in the loop, such as those formed by the capacitance and
the safety resistors of the patient. The suggested application circuits
use a 1 nF capacitor, which results in a loop gain of about 20 at
line frequencies, with a crossover frequency of about 1 kHz.
In a 2-lead configuration, the RLD pin amplifier can be shut down
or used to drive the bias current resistors on the inputs. Although
not as effective as a true driven electrode, this configuration can
provide some common-mode rejection improvement if the sense
electrode impedance is small and well matched.
MEASURING SURFACE ELECTROMYOGRAPHY
(EMG) OR ELECTROENCEPHALOGRAPHY (EEG)
HPDRIVE
180kΩ
180kΩ
10MΩ
HPSENSE
+IN
IAOUT
–IN
REFIN
+VS
RLDFB
10MΩ
+VS
10MΩ
0.1µF
1nF
GND
RLD
SW
0.1µF
10MΩ
AD8233
FR
OPAMP+
AC/DC
REFOUT
RLD SDN
OPAMP–
SDN
OUT
LOD
+VS
TO DIGITAL
INTERFACE
13737-070
ADC
SIGNAL
OUTPUT
Figure 70. Circuit for HRM Next to the Heart
A shorter distance from the AD8233 to the heart makes this
application less vulnerable to common-mode interference.
However, because RLD is not used to drive an electrode, it can
be used to improve the common-mode rejection by maintaining the midscale voltage through the 10 MΩ bias resistors.
Alternatively, tie RLD SDN low to save power, and tie the bias
resistors to REFOUT.
A single-pole, high-pass filter is set at 7 Hz, and there is no lowpass filter. No gain is used on the output op amp, which reduces
the number of resistors for a total system gain of 100, as shown in
Figure 71.
70
60
50
MAGNITUDE (dB)
Due to its flexible architecture, the AD8233 filters can be
configured to measure other biopotential signals, such as
surface EMG or nondiagnostic EEG (alpha or beta waves). The
frequency range of signals for surface EMG is typically 2 Hz to
500 Hz for skeletal muscles and 0.01 Hz to 1 Hz for smooth
muscles. When measuring wider bandwidth signals inclusive of
50 Hz or 60 Hz, consider lower gain settings. EEG signals have a
shared frequency range with ECG signals. However, the amplitude
for EEG signals is about 10 times smaller than those for ECG, and
as such, require a lower noise solution. Alpha waves (8 Hz to 13
Hz) and beta waves (14 Hz to 40 Hz) can be measured with the
AD8233 by setting the high-pass filter at 7 Hz, similar to ECG
measurement at the hands (see Figure 72). The 7 Hz cutoff
frequency helps remove additional 1/f noise, which lowers the
noise floor for the EEG measurement.
Rev. D | Page 25 of 32
40
30
20
10
0
0.1
1
10
100
1k
10k
FREQUENCY (Hz)
Figure 71. Frequency Response for HRM Next to the Heart Circuit
13737-071
R
D1
13737-069
A1
AD8233
Data Sheet
The input terminals in this configuration use two 180 kΩ
resistors to protect the user from fault conditions. Two 10 MΩ
resistors provide input bias. Use higher values for electrodes
with high output impedance, such as cloth electrodes.
The overall narrow-band nature of the two-pole, low-pass filter
combination distorts the ECG waveform significantly. Therefore,
it is only suitable to determine the heart rate, and not to analyze the
ECG signal characteristics.
Figure 70 also shows two 10 MΩ resistors to set the midscale
reference voltage. If there is already a reference voltage available,
it can be driven into the REFIN input to eliminate these two
10 MΩ resistors.
The low-pass filter stage also includes a gain of 11, bringing the
total system gain close to 1100. Because the ECG signal is
measured at the hands, it is weaker than when measured closer
to the heart.
Exercise Application, HRM at the Hands
The RLD circuit drives to the third electrode, which can also be
located at the hands, to cancel common-mode interference.
In this application, the heart rate signal is measured at the
hands with stainless steel electrodes. The arm and upper body
movement of the user create large motion artifacts, and the
long lead length makes the system susceptible to commonmode interference. A very narrow band-pass characteristic is
required to separate the heart signal from interference.
The circuit in Figure 75 is designed for monitoring the shape of
the ECG waveform.
To obtain an ECG waveform with minimal distortion, the
AD8233 is configured with a 0.5 Hz, single-pole, high-pass
filter, followed by a two-pole, 40 Hz, low-pass filter. A third
electrode is driven for optimum common-mode rejection.
0.22µF
10MΩ
HPDRIVE
10MΩ 180kΩ
180kΩ
0.22µF
360kΩ
RL
IAOUT
–IN
REFIN
60
10MΩ
0.1µF
50
AD8233
FR
OPAMP+
AC/DC
REFOUT
RLD SDN
OPAMP–
SDN
22nF
100kΩ
3.3nF
10MΩ
0.1µF
1MΩ
100kΩ
+VS
GND
RLD
SW
1MΩ
+VS
RLDFB
1nF
70
10MΩ
MAGNITUDE (dB)
RA
HPSENSE
+IN
1MΩ
OUT
+VS
LOD
SIGNAL OUTPUT
10
0
0.01
The circuit shown in Figure 72 uses a two-pole, high-pass filter
set at 7 Hz. A two-pole, low-pass filter at 24 Hz follows the
high-pass filters to eliminate any other artifacts and line noise.
70
60
MAGNITUDE (dB)
50
1k
13737-073
10
100
10
100
1k
In addition to 40 Hz filtering, the op amp stage is configured
for a gain of 2, resulting in a total system gain of 200. Keeping
the gain lower helps with any motion artifacts picked up in
band. To optimize the dynamic range of the system, the gain
level is adjustable, depending on the input signal amplitude
(which may vary with electrode placement) and ADC input range.
20
10
1
Figure 74. Frequency Response of Holter Monitor Circuit
30
FREQUENCY (Hz)
0.1
FREQUENCY (Hz)
40
1
30
20
Figure 72. Circuit for HRM at Hands
0
0.1
40
TO DIGITAL
INTERFACE
13737-072
LA
13737-075
+VS
Holter Monitor Configuration
Figure 73. Frequency Response for HRM Circuit Taken at the Hands
Rev. D | Page 26 of 32
Data Sheet
AD8233
3.3µF
+VS
ELECTRODE
INTERFACE
10MΩ
10MΩ
HPDRIVE
150kΩ
LA
300kΩ
RL
+IN
IAOUT
–IN
+VS
RLDFB
10MΩ
10MΩ
REFIN
0.1µF
GND
AD8233
SW
1MΩ
0.1µF
10MΩ
1nF
RLD
499kΩ
10MΩ
+VS (= +2.5V)
150kΩ
RA
HPSENSE
+VS
FR
OPAMP+
AC/DC
REFOUT
RLD SDN
OPAMP–
SDN
...TO MCU
OUT
LOD
...TO MCU
5.6nF
1MΩ
5.6nF
1MΩ
+VS
13737-074
...TO 11-13 ENOB ADC
0.5Hz TO 40Hz
GAIN = ×200
Figure 75. Holter Monitor Circuit
0.22µF
ADP150
+VS
ELECTRODE
INTERFACE
VOUT
1.8V TO 3.5V
HPDRIVE
150kΩ
LA
150kΩ
RA
10MΩ
10MΩ
10MΩ 1nF
0.22µF
+IN
IAOUT
–IN
+VS
100kΩ
1MΩ
RLDFB
REFIN
11nF
1MΩ
1µF
VBATT
10MΩ
10MΩ
0.1µF
0.1µF
GND
RLD
AD8233
FR
OPAMP+
AC/DC
+VS
REFOUT
RLD SDN
+VS
OPAMP–
SDN
SPI0_RDY/GPIO30
OUT
LOD
XINT0_WAKE1/GPIO16
22nF
100kΩ
1µF
10MΩ
+VS
SW
150kΩ
HPSENSE
VIN
GND
ADuCM3029
+VS
0.1µF
VBAT_ADC
7Hz TO 26Hz
GAIN = ×1100
0.1µF
VBAT_ANA1
VBAT_ANA2
VBAT_DIG1
ADC0_VIN0
SELECT VREF_ADC = 2.5V
0.1µF
0.1µF
0.1µF
VBAT_DIG2
4.7µF
ADXL362
1µF
0.1µF
VS
VDDI/O
GND
XINT0_WAKE0/GPIO15
INT2
CS
SPI1_CS0_GPIO25
MISO
SPI1_MISO_GPIO24
MOSI
SPI1_MOSI_GPIO23
SCLK
SPI1_CLK_GPIO22
TO HOST,
MEMORY
OR
DISPLAY
GND_VREFADC
GND_ANA
GND_DIG
0.47µF
CS
SPI2_CS0_GPIO21
TX
SPI2_MISO_GPIO20
RX
SPI2_MOSI_GPIO19
CLK
SPI2_CLK_GPIO18
Figure 76. Portable Heart Rate and Activity Monitor Circuit
Rev. D | Page 27 of 32
VDCDC_OUT
0.47µF
VLDO_OUT
13737-076
+VS
VREF_ADC
AD8233
Data Sheet
Portable Heart Rate and Activity Monitor System
to one of the current inputs of the ADPD1080 through a 200 kΩ
resistor to convert the voltage output of the AD8233 into a current.
The ADPD1080 is configured to alternately measure the
photodiode signal and the ECG signal from the AD8233 on
consecutive timeslots to provide fully synchronized PPG and
ECG measurements. Data can be read out of the on-chip FIFO
or straight from data registers. The ADPD1080 channel used to
process the ECG signal is set up in TIA ADC mode, and the
input bias voltage must be set to the 0.90 V setting using Bits[5:4]
of Register 0x42 if the ECG signal is on Time Slot A, or
Register 0x44 on Time Slot B. The TIA gain setting can be set to
optimize the dynamic range of the signal path. The channel used to
process the PPG signal is configured in its normal operating
mode. Figure 77 shows a plot of a synchronized ECG and PPG
measurement using the AD8233 with the ADPD1080.
The circuit in Figure 76 shows the AD8233 configured as an
HRM circuit for two electrode applications. The AD8233
implements a two-pole, low-pass filter with a cutoff frequency
of 7 Hz, and a two-pole, low-pass filter with a cutoff frequency
of 26 Hz. The total signal gain in the pass band is 1,100.
The output of this HRM circuit is sampled by the 12-bit ADC
embedded in the ADuCM3029, an ultralow power (
