Dual, 16 MHz, Rail-to-Rail
FET Input Amplifier
AD823
Data Sheet
CONNECTION DIAGRAM
An offset voltage of 800 µV maximum, an offset voltage drift of
2 µV/°C, input bias currents below 25 pA, and low input voltage
noise provide dc precision with source impedances up to a
Gigaohm. It provides 16 MHz, −3 dB bandwidth, −108 dB THD
@ 20 kHz, and a 22 V/µs slew rate with a low supply current of
2.6 mA per amplifier. The AD823 drives up to 500 pF of direct
capacitive load as a follower and provides an output current of
15 mA, 0.5 V from the supply rails. This allows the amplifier to
handle a wide range of load conditions.
+VS
7
OUT2
+IN1 3
6
–IN2
–VS 4
5
+IN2
AD823
RL = 100kΩ
CL = 50pF
+VS = +3V
G = +1
3V
500mV
00901-002
GND
200µs
Figure 2. Output Swing, +VS = +3 V, G = +1
Battery-powered precision instrumentation
Photodiode preamps
Active filters
12-bit to 16-bit data acquisition systems
Medical instrumentation
2
1
+VS = +5V
G = +1
0
–1
OUTPUT (dB)
The AD823 is a dual precision, 16 MHz, JFET input op amp
that can operate from a single supply of 3.0 V to 36 V or from
dual supplies of ±1.5 V to ±18 V. It has true single-supply
capability with an input voltage range extending below ground
in single-supply mode. Output voltage swing extends to within
50 mV of each rail for IOUT ≤ 100 µA, providing outstanding
output dynamic range.
8
–IN1 2
Figure 1. 8-Lead PDIP and SOIC
APPLICATIONS
GENERAL DESCRIPTION
OUT1 1
–2
–3
–4
–5
–6
–7
–8
1k
10k
100k
1M
FREQUENCY (Hz)
10M
00901-003
Single-supply operation
Output swings rail-to-rail
Input voltage range extends below ground
Single-supply capability from 3 V to 36 V
High load drive
Capacitive load drive of 500 pF, G = +1
Output current of 15 mA, 0.5 V from supplies
Excellent ac performance on 2.6 mA/amplifier
−3 dB bandwidth of 16 MHz, G = +1
350 ns settling time to 0.01% (2 V step)
Slew rate of 22 V/µs
Good dc performance
800 µV maximum input offset voltage
2 µV/°C offset voltage drift
25 pA maximum input bias current
Low distortion: −108 dBc worst harmonic @ 20 kHz
Low noise: 16 nV/√Hz @ 10 kHz
No phase inversion with inputs to the supply rails
00901-001
FEATURES
Figure 3. Small Signal Bandwidth, G = +1
This combination of ac and dc performance, plus the outstanding
load drive capability, results in an exceptionally versatile amplifier for applications such as A/D drivers, high speed active
filters, and other low voltage, high dynamic range systems.
The AD823 is available over the industrial temperature range of
−40°C to +85°C and is offered in both 8-lead PDIP and 8-lead
SOIC packages.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1995–2011 Analog Devices, Inc. All rights reserved.
AD823
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Applications ....................................................................................... 1
Theory of Operation ...................................................................... 13
General Description ......................................................................... 1
Output Impedance ..................................................................... 14
Connection Diagram ....................................................................... 1
Application Notes ........................................................................... 15
Revision History ............................................................................... 2
Input Characteristics .................................................................. 15
Specifications..................................................................................... 3
Output Characteristics............................................................... 15
Absolute Maximum Ratings............................................................ 6
Outline Dimensions ....................................................................... 18
Thermal Resistance ...................................................................... 6
Ordering Guide .......................................................................... 19
ESD Caution .................................................................................. 6
REVISION HISTORY
11/11—Rev. D to Rev. E
Changes to Theory of Operation Section .................................... 13
Changes to Ordering Guide .......................................................... 19
6/10—Rev. C to Rev. D
Changes to Figure 34 ...................................................................... 11
Changes to Figure 36 ...................................................................... 13
5/10—Rev. B to Rev. C
Changes to Table 4 ............................................................................ 6
2/07—Rev. A to Rev. B
Updated Format .................................................................. Universal
Changes to DC Performance .......................................................... 5
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide ......................................................... 19
5/04—Rev. 0 to Rev. A
Changes to Specifications ................................................................ 2
Changes to Ordering Guide ......................................................... 17
Updated Outline Dimensions ....................................................... 17
5/95—Revision 0: Initial Version
Rev. E | Page 2 of 20
Data Sheet
AD823
SPECIFICATIONS
At TA = 25°C, +VS = +5 V, RL = 2 kΩ to 2.5 V, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth, VO ≤ 0.2 V p-p
Full Power Response
Slew Rate
Settling Time
to 0.1%
to 0.01%
NOISE/DISTORTION PERFORMANCE
Input Voltage Noise
Input Current Noise
Harmonic Distortion
Crosstalk
f = 1 kHz
f = 1 MHz
DC PERFORMANCE
Initial Offset
Maximum Offset Over temperature
Offset Drift
Input Bias Current
at TMAX
Input Offset Current
at TMAX
Open-Loop Gain
TMIN to TMAX
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range
Input Resistance
Input Capacitance
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
IL = ±100 µA
IL = ±2 mA
IL = ±10 mA
Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
Conditions
Min
Typ
G = +1
VO = 2 V p-p
G = −1, VO = 4 V Step
12
16
3.5
22
MHz
MHz
V/µs
G = −1, VO = 2 V Step
G = −1, VO = 2 V Step
320
350
ns
ns
f = 10 kHz
f = 1 kHz
RL = 600 Ω to 2.5 V, VO = 2 V p-p, f = 20 kHz
16
1
−108
nV/√Hz
fA/√Hz
dBc
RL = 5 kΩ
RL = 5 kΩ
−105
−63
dB
dB
VCM = 0 V to 4 V
VCM = 0 V to 4 V
0.2
0.3
2
3
0.5
2
0.5
45
VO = 0.2 V to 4 V, RL = 2 kΩ
14
20
20
−0.2 to +3
VCM = 0 V to 3 V
60
VOUT = 0.5 V to 4.5 V
Sourcing to 2.5 V
Sinking to 2.5 V
G = +1
Rev. E | Page 3 of 20
70
0.8
2.0
25
5
20
Unit
mV
mV
µV/°C
pA
nA
pA
nA
V/mV
V/mV
−0.2 to +3.8
1013
1.8
76
V
Ω
pF
dB
0.025 to 4.975
0.08 to 4.92
0.25 to 4.75
16
40
30
500
V
V
V
mA
mA
mA
pF
3
TMIN to TMAX, total
VS = 5 V to 15 V, TMIN to TMAX
Max
5.2
80
36
5.6
V
mA
dB
AD823
Data Sheet
At TA = 25°C, +VS = +3.3 V, RL = 2 kΩ to 1.65 V, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth, VO ≤ 0.2 V p-p
Full Power Response
Slew Rate
Settling Time
to 0.1%
to 0.01%
NOISE/DISTORTION PERFORMANCE
Input Voltage Noise
Input Current Noise
Harmonic Distortion
Crosstalk
f = 1 kHz
f = 1 MHz
DC PERFORMANCE
Initial Offset
Maximum Offset Over temperature
Offset Drift
Input Bias Current
at TMAX
Input Offset Current
at TMAX
Open-Loop Gain
TMIN to TMAX
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range
Input Resistance
Input Capacitance
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
IL = ±100 µA
IL = ±2 mA
IL = ±10 mA
Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
Conditions
Min
Typ
G = +1
VO = 2 V p-p
G = −1, VO = 2 V Step
12
15
3.2
20
MHz
MHz
V/µs
G = −1, VO = 2 V Step
G = −1, VO = 2 V Step
250
300
ns
ns
f = 10 kHz
f = 1 kHz
RL = 100 Ω, VO = 2 V p-p, f = 20 kHz
16
1
−93
nV/√Hz
fA/√Hz
dBc
RL = 5 kΩ
RL = 5 kΩ
−105
−63
dB
dB
VCM = 0 V to 2 V
VCM = 0 V to 2 V
0.2
0.5
2
3
0.5
2
0.5
30
VO = 0.2 V to 2 V, RL = 2 kΩ
13
15
12
−0.2 to +1
VCM = 0 V to 1 V
54
VOUT = 0.5 V to 2.5 V
Sourcing to 1.5 V
Sinking to 1.5 V
G = +1
Rev. E | Page 4 of 20
70
1.5
2.5
25
5
20
Unit
mV
mV
µV/°C
pA
nA
pA
nA
V/mV
V/mV
−0.2 to +1.8
1013
1.8
70
V
Ω
pF
dB
0.025 to 3.275
0.08 to 3.22
0.25 to 3.05
15
40
30
500
V
V
V
mA
mA
mA
pF
3
TMIN to TMAX, total
VS = 3.3 V to 15 V, TMIN to TMAX
Max
5.0
80
36
5.7
V
mA
dB
Data Sheet
AD823
At TA = 25°C, VS = ±15 V, RL = 2 kΩ to 0 V, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth, VO ≤ 0.2 V p-p
Full Power Response
Slew Rate
Settling Time
to 0.1%
to 0.01%
NOISE/DISTORTION PERFORMANCE
Input Voltage Noise
Input Current Noise
Harmonic Distortion
Crosstalk
f = 1 kHz
f = 1 MHz
DC PERFORMANCE
Initial Offset
Maximum Offset Over temperature
Offset Drift
Input Bias Current
at TMAX
Input Offset Current
at TMAX
Open-Loop Gain
TMIN to TMAX
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range
Input Resistance
Input Capacitance
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
IL = ±100 µA
IL = ±2 mA
IL = ±10 mA
Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
Conditions
Min
Typ
G = +1
VO = 2 V p-p
G = −1, VO = 10 V Step
12
16
4
25
MHz
MHz
V/µs
G = −1, VO = 10 V Step
G = −1, VO = 10 V Step
550
650
ns
ns
f = 10 kHz
f = 1 kHz
RL = 600 Ω, VO = 10 V p-p, f = 20 kHz
16
1
−90
nV/√Hz
fA/√Hz
dBc
RL= 5 kΩ
RL= 5 kΩ
−105
−63
dB
dB
VCM = 0 V
VCM = −10 V
VCM = 0 V
0.7
1.0
2
5
60
0.5
2
0.5
60
VO = +10 V to −10 V, RL = 2 kΩ
17
30
30
−15.2 to +13
VCM = −15 V to +13 V
66
VOUT = −14.5 V to +14.5 V
Sourcing to 0 V
Sinking to 0 V
G = +1
Rev. E | Page 5 of 20
70
3.5
7
30
5
20
Unit
mV
mV
µV/°C
pA
pA
nA
pA
nA
V/mV
V/mV
−15.2 to +13.8
1013
1.8
82
V
Ω
pF
dB
−14.95 to +14.95
−14.92 to +14.92
−14.75 to +14.75
17
80
60
500
V
V
V
mA
mA
mA
pF
3
TMIN to TMAX, total
VS = 5 V to 15 V, TMIN to TMAX
Max
7.0
80
36
8.4
V
mA
dB
AD823
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Rating
36 V
Specification is for device in free air.
1.3 W
0.9 W
±VS
±VS
See Figure 4
−65°C to +125°C
−40°C to +85°C
300°C
Table 5. Thermal Resistance
Package Type
8-Lead PDIP
8-Lead SOIC
θJA
90
160
2.0
8-LEAD PDIP
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Unit
°C/W
°C/W
TJ = 150°C
1.5
1.0
8-LEAD SOIC
0.5
0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60
AMBIENT TEMPERATURE (°C)
70
80 90
Figure 4. Maximum Power Dissipation vs. Temperature
ESD CAUTION
Rev. E | Page 6 of 20
00901-004
MAXIMUM POWER DISSIPATION (W)
Parameter
Supply Voltage
Internal Power Dissipation
PDIP (N)
SOIC (R)
Input Voltage (Common Mode)
Differential Input Voltage
Output Short-Circuit Duration
Storage Temperature Range N, R
Operating Temperature Range
Lead Temperature Range
(Soldering, 10 sec)
Data Sheet
AD823
TYPICAL PERFORMANCE CHARACTERISTICS
80
100
+VS = +5V
314 UNITS
σ = 40µV
70
+VS = +5V
317 UNITS
σ = 0.4pA
90
80
60
70
60
UNITS
UNITS
50
40
50
40
30
30
20
20
10
–150
–100
–50
0
50
100
INPUT OFFSET VOLTAGE (µV)
150
200
0
00901-005
0
–200
0
1
Figure 5. Typical Distribution of Input Offset Voltage
18
9
10
INPUT BIAS CURRENT (pA)
1000
16
14
UNITS
8
+VS = +5V
VCM = 0V
+VS = +5V
–55°C TO +125°C
103 UNITS
20
3
4
5
6
7
INPUT BIAS CURRENT (pA)
Figure 8. Typical Distribution of Input Bias Current
10000
22
2
00901-008
10
12
10
8
6
4
100
10
1
–5
–4
1
2
–3 –2 –1 0
3
4
5
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
6
7
0.1
0
00901-006
0
–6
Figure 6. Typical Distribution of Input Offset Voltage Drift
3
25
50
75
TEMPERATURE (°C)
100
125
00901-009
2
Figure 9. Input Bias Current vs. Temperature
1000
+VS = +5V
VS = ±15V
INPUT BIAS CURRENT (pA)
1
0
–1
–2
100
10
1
–4
–5
–4
–3
–2
–1
0
1
2
3
COMMON-MODE VOLTAGE (V)
4
5
0.1
–16
Figure 7. Input Bias Current vs. Common-Mode Voltage
–12
–8
–4
0
4
8
COMMON-MODE VOLTAGE (V)
12
16
Figure 10. Input Bias Current vs. Common-Mode Voltage
Rev. E | Page 7 of 20
00901-010
–3
00901-007
INPUT BIAS CURRENT (pA)
2
AD823
Data Sheet
110
95
RL = 2kΩ
+VS = +5V
VS = ±2.5V
94
93
OPEN-LOOP GAIN (dB)
OPEN-LOOP GAIN (dB)
100
90
80
92
91
90
89
88
70
500k
86
–55
Figure 11. Open-Loop Gain vs. Load Resistance
5
35
65
TEMPERATURE (°C)
95
125
Figure 14. Open-Loop Gain vs. Temperature
1000
100
RL = 10kΩ
RL = 2kΩ
CL = 20pF
100
80
80
100
PHASE
OPEN-LOOP GAIN (dB)
RL = 1kΩ
10
RL = 100Ω
1
0.1
0
–2.5 –2.0 –1.5 –1.0 –0.5
0.5
1.0
OUTPUT VOLTAGE (V)
1.5
2.0
2.5
00901-012
OPEN-LOOP GAIN (k V )
V
–25
60
60
40
40
GAIN
20
20
0
0
–20
100
1k
10k
100k
1M
PHASE MARGIN (Degrees)
100k
10k
LOAD RESISTANCE (Ω)
–20
100M
10M
00901-015
1k
00901-011
60
100
00901-014
87
FREQUENCY (Hz)
Figure 15. Open-Loop Gain and Phase Margin vs. Frequency
Figure 12. Open-Loop Gain vs. Output Voltage, VS = ±2.5 V
100
–40
+VS = +5V
–80
–90
VS = ±15V
VOUT = 10V p-p
RL = 600Ω
ALL
OTHERS
VS = ±2.5V
VOUT = 2V p-p
RL = 1kΩ
+VS = +5V
VOUT = 2V p-p
RL = 5kΩ
–100
–110
100
+VS = +3V
VOUT = 2V p-p
RL = 5kΩ
1k
10k
100k
FREQUENCY (Hz)
1M
30
10
3
Figure 13. Total Harmonic Distortion vs. Frequency
10
100
1k
10k
FREQUENCY (Hz)
100k
Figure 16. Input Voltage Noise vs. Frequency
Rev. E | Page 8 of 20
1M
00901-016
–70
+VS = +3V
VOUT = 2V p-p
RL = 100Ω
00901-013
THD (dB)
–60
INPUT VOLTAGE NOISE (nV/√Hz)
–50
Data Sheet
AD823
90
5
CL = 20pF
RL = 2kΩ
G = +1
VS = ±15V
80
+VS = +5V
3
70
2
1
CMRR (dB)
CLOSED-LOOP GAIN (dB)
4
0
+27°C
–1
–55°C
60
50
+125°C
–2
40
–3
30
20
10
00901-017
–5
0.30 3.27 6.24 9.21 12.18 15.15 18.12 21.09 24.06 27.03 30.00
FREQUENCY (MHz)
10
OUTPUT SATURATION VOLTAGE (V)
10
1
0.1
1M
10M
VS – VOH
25°C
0.1
VOL
25°C
1
10
LOAD CURRENT (mA)
100
Figure 21. Output Saturation Voltage vs. Load Current
10
1%
0.1%
6
0.01%
QUIESCENT CURRENT (mA)
VS = ±15V
CL = 20pF
4
2
0
–2
–4
0.1%
1%
0.01%
–6
+125°C
8
+25°C
6
–55°C
4
2
–10
100
200
300
400
500
600
700
SETTLING TIME (ns)
0
0
5
10
15
SUPPLY VOLTAGE (±V)
Figure 22. Quiescent Current vs. Supply Voltage
Figure 19. Output Step Size vs. Settling Time (Inverter)
Rev. E | Page 9 of 20
20
00901-022
–8
00901-019
OUTPUT STEP SIZE FROM 0V TO VSHOWN (V)
8
10M
1
Figure 18. Output Resistance vs. Frequency, +VS = +5 V, Gain = +1
10
1M
+VS = +5V
0.01
0.1
00901-018
OUTPUT RESISTANCE (Ω)
+VS = +5V
GAIN = +1
10k
100k
FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
00901-021
100
1k
1k
Figure 20. Common-Mode Rejection Ratio vs. Frequency
Figure 17. Closed-Loop Gain vs. Frequency
0.01
100
100
00901-020
–4
AD823
Data Sheet
21
100
+VS = +5V
+VS = +5V
80
70
+PSRR
60
50
40
–PSRR
30
RS
VIN
18
SERIES RESISTANCE (Ω)
POWER SUPPLY REJECTION (dB)
90
CL
15
12
9
ФM = 45°
6
ФM = 20°
20
3
1k
10k
100k
FREQUENCY (Hz)
1M
10M
0
00901-023
0
100
1
0
3
4
5
6
7
CAPACITOR (pF × 1000)
8
9
10
Figure 26. Series Resistance vs. Capacitive Load
Figure 23. Power Supply Rejection vs. Frequency
–30
30
+VS = +5V
RL = 2kΩ
G = +1
–40
CROSSTALK (dB)
–50
20
VS = ±15V
10
–60
–70
–80
–90
–100
+VS = +5V
–110
10M
–130
1k
00901-024
100k
1M
FREQUENCY (Hz)
10k
Figure 24. Large Signal Frequency Response
100k
FREQUENCY (Hz)
VIN = 20V p-p
VS = ±15V
G = +1
5V
10µs
100kΩ
20µs
+15V
3V
VIN = 2.9V p-p
20kHz, 20V p-p
VOUT
50Ω
–15V
100kΩ
50pF
604Ω
50pF
Figure 25. Output Swing, +VS = +3 V, G = −1
Figure 28. Output Swing, VS = ±15 V, G = +1
Rev. E | Page 10 of 20
00901-028
100kΩ
10M
Figure 27. Crosstalk vs. Frequency
VIN = 2.9V p-p
+VS = +3V
G = –1
500mV
1M
00901-027
–120
+VS = +3V
0
10k
00901-025
OUTPUT VOLTAGE (V p-p)
2
00901-026
10
Data Sheet
5V
AD823
RL = 300Ω
CL = 50pF
RF = RG = 2kΩ
+VS = +5V
G = –1
RL = 100kΩ
CL = 50pF
+VS = +3V
G = +1
3V
200µs
500mV
Figure 29. Output Swing, +VS = +5 V, G = −1
00901-032
500mV
GND
00901-029
GND
200µs
Figure 32. Output Swing, +VS = +3 V, G = +1
5V
VIN = 100mV STEP
+VS = +3V
G = +1
RL = 2kΩ
CL = 50pF
+VS = +5V
G = +1
1.55V
500mV
Figure 33. Pulse Response, +VS = +5 V, G = +1
RL = 2kΩ
CL = 50pF
+VS = +5V
G = +2
RL = 2kΩ
CL = 470pF
+VS = +5V
G = +1
100ns
GND
00901-031
500mV
100ns
GND
Figure 30. Pulse Response, +VS = +3 V, G = +1
5V
00901-033
50ns
500mV
Figure 31. Pulse Response, +VS = +5 V, G = +2
200ns
00901-034
25mV
00901-030
1.45V
Figure 34. Pulse Response, +VS = +5 V, G = +1, CL = 470 pF
Rev. E | Page 11 of 20
AD823
Data Sheet
RL = 100kΩ
CL = 50pF
VS = ±15V
G = +1
+10V
5V
500ns
00901-035
–10V
Figure 35. Pulse Response, VS = ±15 V, G = +1
Rev. E | Page 12 of 20
Data Sheet
AD823
THEORY OF OPERATION
A nested integrator topology is used in the AD823 (see Figure 37).
The output stage can be modeled as an ideal op amp with a
single-pole response and a unity-gain frequency set by
transconductance gm2 and Capacitor C2. R1 is the output
impedance of the input stage; gm is the input transconductance.
C1 and C5 provide Miller compensation for the overall op amp.
The unity-gain frequency occurs at gm/C5. Solving the node
equations for this circuit yields
The AD823 is fabricated on the Analog Devices, Inc. proprietary
complementary bipolar (CB) process that enables the construction
of PNP and NPN transistors with similar fT’s in the 600 MHz to
800 MHz region. In addition, the process also features N-Channel
JFETs that are used in the input stage of the AD823. These
process features allow the construction of high frequency, low
distortion op amps with picoamp input currents. This design
uses a differential output input stage to maximize bandwidth
and headroom (see Figure 36). The smaller signal swings
required on the S1P/S1N outputs reduce the effect of the
nonlinear currents due to junction capacitances and improve
the distortion performance. With this design, harmonic
distortion of better than −91 dB @ 20 kHz into 600 Ω with
VOUT = 4 V p-p on a single 5 V supply is achieved. The
complementary common emitter design of the output stage
provides excellent load drive without the need for emitter
followers, thereby improving the output range of the device
considerably with respect to conventional op amps. The
AD823 can drive 20 mA with the outputs within 0.6 V of the
supply rails. The AD823 also offers outstanding precision for a
high speed op amp. Input offset voltages of 1 mV maximum
and offset drift of 2 µV/°C are achieved through the use of the
Analog Devices advanced thin film trimming techniques.
V OUT
Vi
A0
=
g
m2
(sR1[C1( A2 + 1)] + 1) × s C2 + 1
where:
A0 = gmgm2 R2R1 (open-loop gain of op amp).
A2 = gm2 R2 (open-loop gain of output stage).
The first pole in the denominator is the dominant pole of the
amplifier and occurs at ~18 Hz. This equals the input stage
output impedance R1 multiplied by the Miller-multiplied value
of C1. The second pole occurs at the unity-gain bandwidth of
the output stage, which is 23 MHz. This type of architecture
allows more open-loop gain and output drive to be obtained
than a standard 2-stage architecture would allow.
VCC
R42
R37
VBE + 0.3V V1
Q43
I5
Q55
Q44
A=1
I6
Q57
A = 19
Q61
Q72
Q49
Q18
Q46
J6
VINP
R44
S1P
S1N
VOUT
Q54
Q21
VINN
Q62
Q60
VCC
C1
Q48
Q53
I1
C6
R33
C2
R28
VB
Q35
I2
Q17
A = 19
R43
I3
Q56
VEE
Figure 36. Simplified Schematic
Rev. E | Page 13 of 20
Q52
I4
Q59
A=1
00901-036
J1
Q58
AD823
Data Sheet
OUTPUT IMPEDANCE
Rev. E | Page 14 of 20
S1N
gmVI
C1
R1
VOUT
S1P
C2
gmVI
R1
C5
gm2
R2
00901-037
The low frequency open-loop output impedance of the commonemitter output stage used in this design is approximately 30 kΩ.
Although this is significantly higher than a typical emitter
follower output stage, when it is connected with feedback, the
output impedance is reduced by the open-loop gain of the op
amp. With 109 dB of open-loop gain, the output impedance is
reduced to
