AD824AN

a FEATURES Single Supply Operation: 3 V to 30 V Very Low Input Bias Current: 2 pA Wide Input Voltage Range Rail-to-Rail Output Swing Low Supply Current: 500 A/Amp Wide Bandwidth: 2 MHz Slew Rate: 2 V/ s No Phase Reversal APPLICATIONS Photo Diode Preamplifier Battery Powered Instrumentation Power Supply Control and Protection Medical Instrumentation Remote Sensors Low Voltage Strain Gage Amplifiers DAC Output Amplifier GENERAL DESCRIPTION OUT A –IN A +IN A V+ +IN B –IN B OUT B Single Supply, Rail-to-Rail Low Power, FET-Input Op Amp AD824 PIN CONFIGURATIONS 14-Lead Epoxy DIP (N Suffix) 14-Lead Epoxy SO (R Suffix) 1 2 3 4 5 6 7 TOP VIEW 14 OUT D 13 –IN D 12 +IN D OUT A –IN A +IN A V+ +INB –INB OUTB 1 2 3 4 5 6 7 14 13 OUT D –IN D AD824 12 +IN D V– +IN C –IN C OUT C AD824 11 V– 10 +IN C 9 8 –IN C OUT C 11 TOP VIEW (Not to Scale) 10 9 8 16-Lead Epoxy SO (R Suffix) The AD824 is a quad, FET input, single supply amplifier, featuring rail-to-rail outputs. The combination of FET inputs and rail-to-rail outputs makes the AD824 useful in a wide variety of low voltage applications where low input current is a primary consideration. The AD824 is guaranteed to operate from a 3 V single supply up to ± 15 volt dual supplies. Fabricated on ADI’s complementary bipolar process, the AD824 has a unique input stage that allows the input voltage to safely extend beyond the negative supply and to the positive supply without any phase inversion or latchup. The output voltage swings to within 15 millivolts of the supplies. Capacitive loads to 350 pF can be handled without oscillation. The FET input combined with laser trimming provides an input that has extremely low bias currents with guaranteed offsets below 300 µV. This enables high accuracy designs even with high source impedances. Precision is combined with low noise, making the AD824 ideal for use in battery powered medical equipment. OUT A 1 –IN A 2 16 OUT D 15 –IN D 14 +IN D +IN A 3 V+ 4 +IN B 5 –IN B 6 AD824 13 V– 12 +IN C 11 –IN C 10 OUT C 9 NC OUT B 7 NC 8 NC = NO CONNECT Applications for the AD824 include portable medical equipment, photo diode preamplifiers and high impedance transducer amplifiers. The ability of the output to swing rail-to-rail enables designers to build multistage filters in single supply systems and maintain high signal-to-noise ratios. The AD824 is specified over the extended industrial (–40°C to +85°C) temperature range and is available in 14-pin DIP and narrow 14-pin and 16-pin SO packages. R EV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997 AD824–SPECIFICATIONS ELECTRICAL SPECIFICATIONS (@ V = +5.0 V, V S CM = 0 V, VOUT = 0.2 V, TA = +25 C unless otherwise noted) Min Typ 0.1 Max 1.0 1.5 300 900 12 4000 10 3.0 80 74 1013 3.3 Units mV mV µV µV pA pA pA pA V dB dB dB Ω pF V/mV V/mV V/mV V/mV µV/°C V V V V mV mV mV mV mA mA Ω dB dB µA V/µs kHz µs MHz Degrees dB µV p-p nV/√Hz fA/√Hz % Parameter INPUT CHARACTERISTICS Offset Voltage AD824A Offset Voltage AD824B Symbol VOS Conditions TMIN to TMAX VOS TMIN to TMAX Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio IB TMIN to TMAX IOS TMIN to TMAX CMRR VCM = 0 V to 2 V VCM = 0 V to 3 V TMIN to TMAX VO = 0.2 V to 4.0 V RL = 2 kΩ RL = 10 kΩ RL = 100 kΩ TMIN to TMAX, RL = 100 kΩ –0.2 66 60 60 2 300 2 300 Input Impedance Large Signal Voltage Gain AVO Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High ∆VOS/∆T VOH 20 50 250 180 40 100 1000 400 2 4.988 4.985 4.85 4.82 15 20 120 140 ± 12 ± 10 100 80 500 2 150 2.5 2 50 –123 2 16 0.8 0.005 600 Output Voltage Low VOL Short Circuit Limit Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Total Harmonic Distortion ISC ZOUT PSRR ISY SR BWP tS GBP φo CS en p-p en in THD ISOURCE = 20 µA TMIN to TMAX ISOURCE = 2.5 mA TMIN to TMAX ISINK = 20 µA TMIN to TMAX ISINK = 2.5 mA TMIN to TMAX Sink/Source TMIN to TMAX f = 1 MHz, AV = 1 VS = 2.7 V to 12 V TMIN to TMAX TMIN to TMAX R L = 1 0 kΩ , A V = 1 1% Distortion, VO = 4 V p-p VOUT = 0.2 V to 4.5 V, to 0.01% No Load f = 1 kHz, RL = 2 kΩ 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz f = 10 kHz, RL = 0, AV = +1 4.975 4.97 4.80 4.75 25 30 150 200 70 66 –2– REV. A AD824 ELECTRICAL SPECIFICATIONS (@ V = S 15.0 V, VOUT = 0 V, TA = +25 C unless otherwise noted) Conditions Min Typ 0.5 0.6 0.5 0.6 4 500 25 3 500 –15 70 66 80 1013 3.3 12 50 300 200 50 200 2000 1000 2 14.988 14.985 14.85 14.82 –14.985 –14.98 –14.88 –14.86 ± 20 100 80 560 625 675 Max 2.5 4.0 1.5 2.5 35 4000 20 13 Units mV mV mV mV pA pA pA pA pA V dB dB Ω pF V/mV V/mV V/mV V/mV µV/°C V V V V V V V V mA Ω dB dB µA µA V/µs kHz µs MHz Degrees dB µV p-p nV/√Hz fA/√Hz % Parameter INPUT CHARACTERISTICS Offset Voltage AD824A Offset Voltage AD824B Symbol VOS TMIN to TMAX VOS IB IB IOS CMRR TMIN to TMAX VCM = 0 V TMIN to TMAX VCM = –10 V TMIN to TMAX Input Voltage Range Common-Mode Rejection Ratio Input Impedance Large Signal Voltage Gain VCM = –15 V to 13 V TMIN to TMAX Vo = –10 V to +10 V; RL = 2 kΩ RL = 10 kΩ RL = 100 kΩ TMIN to TMAX, RL = 100 kΩ Input Bias Current Input Bias Current Input Offset Current AVO Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High ∆VOS/∆T VOH Output Voltage Low VOL Short Circuit Limit Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Total Harmonic Distortion ISC ZOUT PSRR ISY ISOURCE = 20 µA TMIN to TMAX ISOURCE = 2.5 mA TMIN to TMAX ISINK = 20 µA TMIN to TMAX ISINK = 2.5 mA TMIN to TMAX Sink/Source, TMIN to TMAX f = 1 MHz, AV = 1 VS = 2.7 V to 15 V TMIN to TMAX VO = 0 V TMIN to TMAX RL = 10 kΩ, AV = 1 1% Distortion, VO = 20 V p-p VOUT = 0 V to 10 V, to 0.01% f = 1 kHz, RL =2 kΩ 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz f =10 kHz, VO = 3 V rms, RL = 10 kΩ 14.975 14.970 14.80 14.75 ±8 –14.975 –14.97 –14.85 –14.8 70 68 SR BWP tS GBP φo CS en p-p en in THD 2 33 6 2 50 –123 2 16 1.1 0.005 REV. A –3– AD824–SPECIFICATIONS ELECTRICAL SPECIFICATIONS Parameter INPUT CHARACTERISTICS Offset Voltage AD824A -3 V Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Input Impedance Large Signal Voltage Gain VOS TMIN to TMAX IB TMIN to TMAX IOS TMIN to TMAX CMRR VCM = 0 V to 1 V TMIN to TMAX VO = 0.2 V to 2.0 V RL = 2 kΩ RL = 10 kΩ RL = 100 kΩ TMIN to TMAX, RL = 100 kΩ 0 58 56 2 250 2 250 74 1013 3.3 AVO 10 30 180 90 20 65 500 250 2 2.988 2.985 2.85 2.82 15 20 120 140 ±8 ±6 100 (@ VS = +3.0 V, VCM = 0 V, VOUT = 0.2 V, TA = +25 C unless otherwise noted) Conditions Min Typ 0.2 Max 1.0 1.5 12 4000 10 1 Units mV mV pA pA pA pA V dB dB Ω pF V/mV V/mV V/mV V/mV µV/°C V V V V mV mV mV mV mA mA Ω dB dB µA V/µs kHz µs MHz Degrees dB µV p-p nV/√Hz fA/√Hz % Symbol Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High ∆VOS/∆T VOH Output Voltage Low VOL Short Circuit Limit Short Circuit Limit Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Total Harmonic Distortion ISC ISC ZOUT PSRR ISY SR BWP tS GBP φo CS en p-p en in THD ISOURCE = 20 µA TMIN to TMAX ISOURCE = 2.5 mA TMIN to TMAX ISINK = 20 µA TMIN to TMAX ISINK = 2.5 mA TMIN to TMAX Sink/Source Sink/Source, TMIN to TMAX f = 1 MHz, AV = 1 VS = 2.7 V to 12 V, TMIN to TMAX VO = 0.2 V, TMIN to TMAX RL =10 kΩ, AV = 1 1% Distortion, VO = 2 V p-p VOUT = 0.2 V to 2.5 V, to 0.01% f = 1 kHz, RL = 2 kΩ 0.1 Hz to 10 Hz f = 1 kHz f = 10 kHz, RL = 0, AV = +1 2.975 2.97 2.8 2.75 25 30 150 200 70 66 500 2 300 2 2 50 –123 2 16 0.8 0.01 600 –4– REV. A AD824 WAFER TEST LIMITS (@ V = +5.0 V, V S CM = 0 V, TA = +25 C unless otherwise noted) Conditions Limit 1.0 12 20 –0.2 to 3.0 66 70 15 4.975 25 600 Units mV max pA max pA V min dB min µV/V V/mV min V min mV max µA max Parameter Offset Voltage Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage High Output Voltage Low Supply Current/Amplifier Symbol VOS IB IOS VCM CMRR PSRR AVO VOH VOL ISY VCM = 0 V to 2 V V = + 2.7 V to +12 V RL = 2 kΩ ISOURCE = 20 µA ISINK = 20 µA VO = 0 V, RL = ∞ NOTE Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. DICE CHARACTERISTICS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . –VS – 0.2 V to +VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 30 V Output Short Circuit Duration to GND . . . . . . . . . Indefinite Storage Temperature Range N, R Package . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Operating Temperature Range AD824A, B . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Junction Temperature Range N, R Package . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C Package Type 14-Pin Plastic DIP (N) 14-Pin SOIC (R) 16-Pin SOIC (R) θJA2 76 120 92 θJC 33 36 27 Units °C/W °C/W °C/W ABSOLUTE MAXIMUM RATINGS 1 AD824 Die Size 0.70 X 0.130 inch, 9,100 sq. mils. Substrate (Die Backside) Is Connected to V+. Transistor Count, 143. VCC I5 R1 R2 R9 I6 Q18 Q29 NOTES 1 Absolute maximum ratings apply to both DICE and packaged parts unless otherwise noted. 2 θJA is specified for the worst case conditions, i.e., θJA is specified for device in socket for P-DIP packages; θJA is specified for device soldered in circuit board for SOIC package. Q21 Q27 Q4 +IN J1 J2 Q5 Q19 Q7 R13 Q22 R7 Q23 C4 VOUT Q20 Q6 C3 ORDERING GUIDE Model AD824AN AD824BN AD824AR AD824AR-3V AD824AN-3V AD824AR-14 AD824AR-14-3V AD824AR-16 AD824AChips Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C +25°C Package Option 14-Pin Plastic DIP 14-Pin Plastic DIP 14-Pin SOIC 14-Pin SOIC 14-Pin Plastic DIP 14-Pin SOIC 14-Pin SOIC 16-Pin SOIC DICE –IN R15 C2 Q24 Q25 Q8 C1 Q2 R12 I1 R14 Q28 I2 I3 VEE I4 R17 Q26 Q3 Q31 Figure 1. Simplified Schematic of 1/4 AD824 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD824 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. A –5– AD824–Typical Characteristics 80 VS = ±15V NO LOAD 60 80 VS = +5V NO LOAD 60 GAIN – dB GAIN – dB 40 40 45 20 90 135 0 100 1k 10k 100k 1M 180 PHASE – Degrees PHASE – Degrees 45 20 90 135 0 100 1k 10k 100k 1M 180 10M PHASE – Degrees 10M 100 90 100 90 10 0% 10 0% 50mV 1µs 50mV 1µs Figure 2. Open-Loop Gain/Phase and Small Signal Response, VS = ± 15 V, No Load Figure 4. Open-Loop Gain/Phase and Small Signal Response, VS = +5 V, No Load 80 VS = ±15V CL = 100pF 60 VS = +5V CL = 220pF 60 GAIN – dB 40 GAIN – dB 45 20 90 135 0 180 40 45 20 90 135 0 100 1k 10k 100k 1M 180 PHASE – Degrees –20 10M 1k 10k 100k 1M 10M 100 90 100 90 10 0% 10 0% 50mV 1µs 50mV 1µs Figure 3. Open-Loop Gain/Phase and Small Signal Response, VS = ± 15 V, CL = 100 pF Figure 5. Open-Loop Gain/Phase and Small Signal Response, VS = +5 V, CL = 220 pF –6– REV. A AD824 60 VS = +3V NO LOAD 100 90 t 9.950 µs 40 GAIN – dB 45 20 90 135 0 180 PHASE – Degrees 10 0% 5V 2µs –20 t 10.810 µs 1k 10k 100k 1M 10M 100 90 100 90 10 0% 5V 2µs 10 0% Figure 8. Slew Rate, RL = 10k 50mV 1µs Figure 6. Open-Loop Gain/Phase and Small Signal Response, VS = +3 V, No Load VOUT 100 90 60 VS = +3V CL = 220pF 10 0% 5V 40 GAIN – dB 100µs 45 20 90 135 0 180 PHASE – Degrees Figure 9. Phase Reversal with Inputs Exceeding Supply by 1 Volt 0.8 –20 0.7 OUTPUT TO RAIL – Volts 1k 10k 100k 1M 10M 0.6 0.5 SOURCE 0.4 0.3 0.2 0.1 SINK 100 90 10 0% 0 1µ 5µ 10µ 50mV 1µs 50µ 100µ 500µ LOAD CURRENT – A 1m 5m 10m Figure 7. Open-Loop Gain/Phase and Small Signal Response, VS = +3 V, CL = 220 pF Figure 10. Output Voltage to Supply Rail vs. Sink and Source Load Currents REV. A –7– AD824–Typical Characteristics 14 COUNT = 60 12 NOISE DENSITY – nV/√Hz +3V ≤ VS ≤ ± 15V 10 NUMBER OF UNITS 60 8 6 4 40 20 2 5 10 15 FREQUENCY – kHz 20 0 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 OFFSET VOLTAGE DRIFT 1.5 2.0 2.5 Figure 11. Voltage Noise Density Figure 14. TC VOS Distribution, –55°C to +125°C, VS = 5, 0 150 0.1 VS = 5, 0 125 RL = 0 AV = +1 INPUT OFFSET CURRENT – pA 10k 20k 100 0.010 VS = +3 THD+N – % 75 50 25 VS = +5 0.001 VS = ±15 0 –25 –60 0.0001 20 100 1k FREQUENCY – Hz –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE – °C Figure 12. Total Harmonic Distortion Figure 15. Input Offset Current vs. Temperature 280 COUNT = 860 240 200 100k VS = 5, 0 10k INPUT BIAS CURRENT – pA NUMBER OF UNITS 1k 160 120 80 100 10 40 0 –0.5 1 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 OFFSET VOLTAGE – mV 0.3 0.4 0.5 20 40 60 80 100 120 140 TEMPERATURE – °C Figure 13. Input Offset Distribution, VS = 5, 0 Figure 16. Input Bias Current vs. Temperature –8– REV. A AD824 120 . .. 1k 100 COMMON-MODE REJECTION – dB 80 INPUT VOLTAGE NOISE – nV/√Hz 100 1k 10k 100k FREQUENCY – Hz 1M 10M 100 60 40 10 20 0 10 1 1 10 100 1k FREQUENCY – Hz 10k 100k Figure 17. Common-Mode Rejection vs. Frequency Figure 20. Input Voltage Noise Spectral Density vs. Frequency –40 120 –60 POWER SUPPLY REJECTION – dB 100 80 THD – dB –80 60 40 –100 20 –120 100 1k 10k FREQUENCY – Hz 100k 0 10 100 1k 10k 100k FREQUENCY – Hz 1M 10M Figure 18. THD vs. Frequency, 3 V rms Figure 21. Power Supply Rejection vs. Frequency 100 100 30 80 OPEN-LOOP GAIN – dB 80 PHASE MARGIN – Degrees 25 OUTPUT VOLTAGE – Volts 60 ±15V 40 +3, 0V 20 60 20 40 15 20 10 0 0 5 –20 10 100 1k 10k 100k FREQUENCY – Hz 1M –20 10M 0 1k 3k 10k 30k 100k INPUT FREQUENCY – Hz 300k 1M Figure 19. Open-Loop Gain and Phase vs. Frequency Figure 22. Large Signal Frequency Response REV. A –9– AD824 –80 5V –90 100 90 5µs CROSSTALK – dB –100 –110 1 TO 4 –120 1 TO 2 –130 1 TO 3 10 0% –140 10 100 1k FREQUENCY – Hz 10k 100k Figure 23. Crosstalk vs. Frequency Figure 26. Large Signal Response 10k 2750 2500 VS = ±15V 1k OUTPUT IMPEDANCE – Ω SUPPLY CURRENT – µA 2250 100 2000 1750 1500 VS = 3, 0 10 1 .1 1250 1000 –60 .01 10 100 1k 10k 100k FREQUENCY – Hz 1M 10M –40 –20 0 20 40 60 80 TEMPERATURE – °C 100 120 140 Figure 24. Output Impedance vs. Frequency, Gain = +1 Figure 27. Supply Current vs. Temperature 1000 VS = ±15V OUTPUT SATURATION VOLTAGE – mV 20mV 100 90 500ns VS = 3, 0 100 VOL – VS 10 VS – VOH 10 0% 0 0.01 0.10 1.0 LOAD CURRENT – mA 10.0 Figure 25. Small Signal Response, Unity Gain Follower, 10k 100 pF Load Figure 28. Output Saturation Voltage –10– REV. A AD824 APPLICATION NOTES INPUT CHARACTERISTICS In the AD824, n-channel JFETs are used to provide a low offset, low noise, high impedance input stage. Minimum input common-mode voltage extends from 0.2 V below –VS to 1 V less than +VS. Driving the input voltage closer to the positive rail will cause a loss of amplifier bandwidth. The AD824 does not exhibit phase reversal for input voltages up to and including +VS. Figure 29a shows the response of an AD824 voltage follower to a 0 V to +5 V (+VS) square wave input. The input and output are superimposed. The output tracks the input up to +VS without phase reversal. The reduced bandwidth above a 4 V input causes the rounding of the output wave form. For input voltages greater than +VS, a resistor in series with the AD824’s noninverting input will prevent phase reversal at the expense of greater input voltage noise. This is illustrated in Figure 29b. A current-limiting resistor should be used in series with the input of the AD824 if there is a possibility of the input voltage exceeding the positive supply by more than 300 mV or if an input voltage will be applied to the AD824 when ± VS = 0. The amplifier will be damaged if left in that condition for more than 10 seconds. A 1 kΩ resistor allows the amplifier to withstand up to 10 volts of continuous overvoltage and increases the input voltage noise by a negligible amount. Input voltages less than –VS are a completely different story. The amplifier can safely withstand input voltages 20 volts below the minus supply voltage as long as the total voltage from the positive supply to the input terminal is less than 36 volts. In addition, the input stage typically maintains picoamp level input currents across that input voltage range. OUTPUT CHARACTERISTICS 1V 100 90 2µs The AD824’s unique bipolar rail-to-rail output stage swings within 15 mV of the positive and negative supply voltages. The AD824’s approximate output saturation resistance is 100 Ω for both sourcing and sinking. This can be used to estimate output saturation voltage when driving heavier current loads. For instance, the saturation voltage will be 0.5 volts from either supply with a 5 mA current load. For load resistances over 20 kΩ, the AD824’s input error voltage is virtually unchanged until the output voltage is driven to 180 mV of either supply. 10 GND 0% 1V (a) 1V +VS 100 90 If the AD824’s output is overdriven so as to saturate either of the output devices, the amplifier will recover within 2 µs of its input returning to the amplifier’s linear operating region. 10µs 1V 10 GND 0% 1V Direct capacitive loads will interact with the amplifier’s effective output impedance to form an additional pole in the amplifier’s feedback loop, which can cause excessive peaking on the pulse response or loss of stability. Worst case is when the amplifier is used as a unity gain follower. Figures 5 and 7 show the AD824’s pulse response as a unity gain follower driving 220 pF. Configurations with less loop gain, and as a result less loop bandwidth, will be much less sensitive to capacitance load effects. Noise gain is the inverse of the feedback attenuation factor provided by the feedback network in use. Figure 30 shows a method for extending capacitance load drive capability for a unity gain follower. With these component values, the circuit will drive 5,000 pF with a 10% overshoot. +V S VOUT (b) +5V RP VIN 0.01µF 100Ω 0.01µF CL 20pF VOUT 8 VIN 1/4 AD824 4 Figure 29. (a) Response with RP = 0; VIN from 0 to +VS (b) VIN = 0 to + VS + 200 m V VOUT = 0 to + VS RP = 49.9 kΩ –VS 20kΩ Since the input stage uses n-channel JFETs, input current during normal operation is positive; the current flows out from the input terminals. If the input voltage is driven more positive than +VS – 0.4 V, the input current will reverse direction as internal device junctions become forward biased. This is illustrated in Figure 9. Figure 30. Extending Unity Gain Follower Capacitive Load Capability Beyond 350 pF REV. A –11– AD824 APPLICATIONS Single Supply Voltage-to-Frequency Converter Table I. AD824 In Amp Performance The circuit shown in Figure 31 uses the AD824 to drive a low power timer, which produces a stable pulse of width t1. The positive going output pulse is integrated by R1-C1 and used as one input to the AD824, which is connected as a differential integrator. The other input (nonloading) is the unknown voltage, VIN. The AD824 output drives the timer trigger input, closing the overall feedback loop. +10V C5 0.1µF 3 4 4 U4 REF02 2 VREF = 5V 6 5 RSCALE ** 10k CMOS 74HCO4 U3B 3 U3A 2 1 U2 CMOS 555 R3* 116k 4 6 2 7 C6 390pF 5% (NPO) R THR TR DIS GND 1 CV 8 V+ OUT 3 5 OUT2 C3 0.1µF Parameters CMRR Common-Mode Voltage Range 3 dB BW, G = 10 G = 100 tSETTLING 2 V Step (VS = 0 V, 3 V) 5 V (VS = ± 5 V) Noise @ f = 1 kHz, G = 10 G = 100 VS = 3 V, 0 V 74 dB VS = 80 dB 5V –0.2 V to +2 V –5.2 V to +4 V 180 kHz 180 kHz 18 kHz 18 kHz 2 µs 270 nV/√Hz 2.2 µV/√Hz 5 µs 270 nV/√Hz 2.2 µV/√Hz 5µs OUT1 100 90 0.01µF, 2% R2 499k, 1% U1 C1 R1 VI N 499k, 1% 0V TO 2.5V FULL SCALE C2 0.01µF, 2% 1/4 AD824B 10 0% 1V C4 0.01µF NOTES: fOUT = VIN /(VREF*t1), t1 = 1.1*R3*C6 = 25kHz fS AS SHOWN. Figure 32a. Pulse Response of In Amp to a 500 mV p-p Input Signal; VS = +5 V, 0 V; Gain = 10 * = 1% METAL FILM,