AD824ARZ-14-REEL7

Single Supply, Rail-to-Rail Low Power, FET-Input Op Amp AD824 Data Sheet PIN CONFIGURATION Single supply operation: 3 V to 30 V Very low input bias current: 2 pA Wide input voltage range Rail-to-rail output swing Low supply current per amplifier: 500 µA Wide bandwidth: 2 MHz Slew rate: 2 V/µs No phase reversal OUT A 1 14 OUT D 13 –IN D –IN A 2 +IN A 3 V+ 4 +IN B 5 10 –IN B 6 9 –IN C 8 OUT C OUT B 7 AD824 12 +IN D TOP VIEW (Not to Scale) 11 V– +IN C 00875-001 FEATURES Figure 1. 14-Lead SOIC (R Suffix) APPLICATIONS Photo diode preamplifier Battery powered instrumentation Power supply control and protection Medical instrumentation Remote sensors Low voltage strain gage amplifiers DAC output amplifier GENERAL DESCRIPTION The AD824 is a quad, FET input, single supply amplifier, featuring rail-to-rail outputs. The combination of FET inputs and rail-to-rail outputs makes the AD824 useful in a wide variety of low voltage applications where low input current is a primary consideration. The AD824 is guaranteed to operate from a 3 V single supply up to ±15 V dual supplies. AD824AR-3V parametric performance at 3 V is fully guaranteed. Fabricated on Analog Devices, Inc., complementary bipolar process, the AD824 has a unique input stage that allows the input voltage to safely extend beyond the negative supply and to the positive supply without any phase inversion or latch-up. The output voltage swings to within 15 mV of the supplies. Capacitive loads to 350 pF can be handled without oscillation. Rev. E The FET input combined with laser trimming provides an input that has extremely low bias currents with guaranteed offsets below 1 mV. This enables high accuracy designs even with high source impedances. Precision is combined with low noise, making the AD824 ideal for use in battery powered medical equipment. Applications for the AD824 include portable medical equipment, photo diode preamplifiers, and high impedance transducer amplifiers. The ability of the output to swing rail-to-rail enables designers to build multistage filters in single supply systems and maintain high signal-to-noise ratios. The AD824 is specified over the extended industrial (−40°C to +85°C) temperature range and is available in narrow 14-lead SOIC package. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD824 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Input Characteristics .................................................................. 12 Applications ....................................................................................... 1 Output Characteristics............................................................... 12 Pin Configuration ............................................................................. 1 Applications Information .............................................................. 13 General Description ......................................................................... 1 Single Supply Voltage-to-Frequency Converter ..................... 13 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Single Supply Programmable Gain Instrumentation Amplifier ..................................................................................... 13 Electrical Specifications ............................................................... 3 3 V, Single Supply Stereo Headphone Driver ......................... 14 Absolute Maximum Ratings ............................................................ 6 Low Dropout Bipolar Bridge Driver ........................................ 14 Thermal Resistance ...................................................................... 6 A 3.3 V/5 V Precision Sample-and-Hold Amplifier .............. 15 ESD Caution .................................................................................. 6 Outline Dimensions ....................................................................... 16 Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 16 Theory of Operation ...................................................................... 12 REVISION HISTORY 4/15—Rev. D to Rev. E Change to Figure 1 Caption ............................................................ 1 5/14—Rev. C to Rev. D Updated Format .................................................................. Universal Removed 16-Lead SOIC Package (Throughout) .......................... 1 Deleted Wafer Test Limits Section ................................................. 5 Deleted AD824 SPICE Macro-model Section ............................ 15 Changes to Ordering Guide .......................................................... 16 2/03—Rev. B to Rev. C Deleted N Package .............................................................. Universal Edits to General Description........................................................... 1 Edits to Absolute Maximum Ratings ............................................. 5 Edits to Ordering Guide .................................................................. 5 Edits to Figure 4 .............................................................................. 12 Edits to Figure 8 .............................................................................. 13 Updated Outline Dimensions ....................................................... 16 1/02—Rev. A to Rev. B Edits to Electrical Specifications................................................. 2, 3 Edits to Absolute Maximum Ratings ............................................. 5 Edits to Ordering Guide .................................................................. 5 Deleted Dice Characteristics ........................................................... 5 Rev. E | Page 2 of 16 Data Sheet AD824 SPECIFICATIONS ELECTRICAL SPECIFICATIONS At VS = 5.0 V, VCM = 0 V, VOUT = 0.2 V, TA = 25°C; unless otherwise noted. Table 1. Parameter INPUT CHARACTERISTICS Offset Voltage (AD824A) Symbol Test Conditions/Comments Min Typ Max Unit 0.1 1.0 1.5 12 4000 10 1013||3.3 mV mV pA pA pA pA V dB dB dB Ω||pF 20 50 250 180 40 100 1000 400 2 V/mV V/mV V/mV V/mV µV/°C ISOURCE = 20 µA TMIN to TMAX ISOURCE = 2.5 mA TMIN to TMAX ISINK = 20 µA TMIN to TMAX ISINK = 2.5 mA TMIN to TMAX Sink/source TMIN to TMAX f = 1 MHz, AV = 1 4.975 4.97 4.80 4.75 4.988 4.985 4.85 4.82 15 20 120 140 ±12 ±10 100 V V V V mV mV mV mV mA mA Ω VS = 2.7 V to 12 V TMIN to TMAX TMIN to TMAX 70 66 VOS TMIN to TMAX Input Bias Current IB 2 300 2 300 TMIN to TMAX Input Offset Current IOS TMIN to TMAX Input Voltage Range Common-Mode Rejection Ratio Input Impedance Large Signal Voltage Gain Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High CMRR VCM = 0 V to 2 V VCM = 0 V to 3 V TMIN to TMAX AVO VO = 0.2 V to 4.0 V RL = 2 kΩ RL = 10 kΩ RL = 100 kΩ TMIN to TMAX, RL = 100 kΩ −0.2 66 60 60 ΔVOS/ΔT VOH Output Voltage Low VOL Short Circuit Limit ISC Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio ZOUT Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Total Harmonic Distortion ISY PSRR SR BWP tS GBP φo CS RL = 10 kΩ, AV = 1 1% distortion, VO = 4 V p-p VOUT = 0.2 V to 4.5 V, to 0.01% en p-p en in THD +3.0 80 74 25 30 150 200 80 500 600 dB dB µA No load f = 1 kHz, RL = 2 kΩ 2 150 2.5 2 50 –123 V/µs kHz µs MHz Degrees dB 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz f = 10 kHz, RL = ∞, AV = +1 2 16 0.8 0.005 µV p-p nV/√Hz fA/√Hz % Rev. E | Page 3 of 16 AD824 Data Sheet At VS = ±15.0 V, VOUT = 0 V, TA = 25°C; unless otherwise noted. Table 2. Parameter INPUT CHARACTERISTICS Offset Voltage (AD824A) Symbol Test Conditions/Comments Min VOS Input Bias Current IB Input Offset Current IB IOS TMIN to TMAX VCM = 0 V TMIN to TMAX VCM = −10 V TMIN to TMAX Max Unit 0.5 0.6 4 500 25 3 500 2.5 4.0 35 4000 1013||3.3 mV mV pA pA pA pA pA V dB dB Ω||pF 20 Input Voltage Range Common-Mode Rejection Ratio CMRR VCM = −15 V to 13 V TMIN to TMAX Input Impedance Large Signal Voltage Gain AVO VO = −10 V to +10 V; RL = 2 kΩ RL = 10 kΩ RL = 100 kΩ 12 50 300 50 200 2000 V/mV V/mV V/mV TMIN to TMAX, RL = 100 kΩ 200 1000 2 V/mV µV/°C ISOURCE = 20 µA TMIN to TMAX ISOURCE = 2.5 mA TMIN to TMAX ISINK = 20 µA TMIN to TMAX ISINK = 2.5 mA TMIN to TMAX Sink/source, TMIN to TMAX f = 1 MHz, AV = 1 14.975 14.970 14.80 14.75 14.988 14.985 14.85 14.82 –14.985 –14.98 –14.88 –14.86 ±20 100 V V V V V V V V mA Ω VS = 2.7 V to 15 V TMIN to TMAX VO = 0 V TMIN to TMAX 70 68 Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Short Circuit Limit Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Total Harmonic Distortion −15 70 66 Typ ΔVOS/ΔT VOH VOL ISC ZOUT PSRR ISY SR BWP tS GBP φo CS en p-p en in THD RL = 10 kΩ, AV = 1 1% distortion, VO = 20 V p-p VOUT = 0 V to 10 V, to 0.01% ±8 +13 80 –14.975 –14.97 –14.85 –14.8 80 560 625 675 dB dB µA µA f = 1 kHz, RL = 2 kΩ 2 33 6 2 50 –123 V/µs kHz µs MHz Degrees dB 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz f =10 kHz, VO = 3 V rms, RL = 10 kΩ 2 16 1.1 0.005 µV p-p nV/√Hz fA/√Hz % Rev. E | Page 4 of 16 Data Sheet AD824 At VS = 3.0 V, VCM = 0 V, VOUT = 0.2 V, TA = 25°C; unless otherwise noted. Table 3. Parameter INPUT CHARACTERISTICS Offset Voltage (AD824A−3 V) Symbol Test Conditions/Comments Min VOS Typ Max Unit 0.2 1.0 1.5 12 4000 10 1013||3.3 mV mV pA pA pA pA V dB dB Ω||pF 20 65 500 250 V/mV V/mV V/mV V/mV 2 µV/°C 2.988 2.985 2.85 2.82 15 20 120 140 ±8 ±6 100 V V V V mV mV mV mV mA mA Ω TMIN to TMAX Input Bias Current IB 2 250 2 250 TMIN to TMAX Input Offset Current IOS TMIN to TMAX Input Voltage Range Common-Mode Rejection Ratio CMRR VCM = 0 V to 1 V TMIN to TMAX Input Impedance Large Signal Voltage Gain AVO VO = 0.2 V to 2.0 V; RL = 2 kΩ RL = 10 kΩ RL = 100 kΩ TMIN to TMAX, RL = 100 kΩ Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High VOH VOL Short Circuit Limit ISC ISC ZOUT Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Total Harmonic Distortion 10 30 180 90 ΔVOS/ΔT Output Voltage Low Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio 0 58 56 PSRR ISY ISOURCE = 20 µA TMIN to TMAX ISOURCE = 2.5 mA TMIN to TMAX ISINK = 20 µA TMIN to TMAX ISINK = 2.5 mA TMIN to TMAX Sink/source Sink/source, TMIN to TMAX f = 1 MHz, AV = 1 2.975 2.97 2.8 2.75 VS = 2.7 V to 12 V, TMIN to TMAX VO = 0.2 V, TMIN to TMAX 70 66 SR BWP tS GBP φo CS RL =10 kΩ, AV = 1 1% distortion, VO = 2 V p-p VOUT = 0.2 V to 2.5 V, to 0.01% en p-p en in THD 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz, RL = 2 kΩ f = 10 kHz, RL = ∞, AV = +1 Rev. E | Page 5 of 16 1 74 500 25 30 150 200 600 dB dB µA 2 300 2 2 50 –123 V/µs kHz µs MHz Degrees dB 2 16 0.8 0.01 µV p-p nV/√Hz fA/√Hz % AD824 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter1 Supply Voltage Input Voltage Differential Input Voltage Output Short Circuit Duration to GND Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature Range (Soldering 60 sec) 1 Table 5. Thermal Resistance Rating ±18 V −VS − 0.2 V to +VS ±30 V Indefinite −65°C to +150°C −40°C to +85°C −65°C to +150°C 300°C Package Type 14-Lead SOIC (R) 1 θJA1 120 ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. VCC I5 I6 Q18 R2 Q29 R9 Q21 Q27 Q4 J1 Q6 C3 Q5 J2 Q20 Q19 +IN R7 Q7 R13 R15 –IN Q23 Q22 C2 C4 VOUT Q24 Q25 Q8 C1 Q2 Q3 Q31 I1 R14 I2 R17 I3 Q28 Q26 I4 VEE Figure 2. Simplified Schematic of 1/4 AD824 Rev. E | Page 6 of 16 00875-002 R12 Unit °C/W θJA is specified for the worst case conditions, that is, θJA is specified for device soldered in circuit board for SOIC package. Absolute maximum ratings apply to packaged parts unless otherwise noted. R1 θJC 36 Data Sheet AD824 TYPICAL PERFORMANCE CHARACTERISTICS VS = ±15V NO LOAD 80 60 GAIN (dB) 60 45 90 20 135 0 180 1k 10k 100k 1M 45 90 20 135 0 180 100 10M 1k 10k 100 90 1M 10M 100 90 10 0% 00875-003 10 0% 50mV 1µs 50mV Figure 3. Open-Loop Gain/Phase and Small Signal Response, VS = ±15 V, No Load 1µs Figure 5. Open-Loop Gain/Phase and Small Signal Response, VS = 5 V, No Load VS = ±15V CL = 100pF 80 VS = 5V CL = 220pF 60 60 GAIN (dB) 40 45 90 20 135 0 180 1k 10k 100k 1M 90 20 135 180 0 –20 10M 1k 10k FREQUENCY (Hz) 100k 1M 10M FREQUENCY (Hz) 100 90 100 90 10 0% 50mV 00875-004 10 0% 1µs Figure 4. Open-Loop Gain/Phase and Small Signal Response, VS = ±15 V, CL = 100 pF 50mV 1µs Figure 6. Open-Loop Gain/Phase and Small Signal Response, VS = 5 V, CL = 220 pF Rev. E | Page 7 of 16 00875-006 100 45 PHASE (Degrees) 40 PHASE (Degrees) GAIN (dB) 100k FREQUENCY (Hz) FREQUENCY (Hz) 00875-005 100 40 PHASE (Degrees) 40 PHASE (Degrees) GAIN (dB) VS = 5V NO LOAD 80 AD824 Data Sheet VS = 3V NO LOAD 60 45 90 20 135 t PHASE (Degrees) GAIN (dB) 40 9.950µs 100 90 180 0 10 0% –20 5V 1k 10k 100k 1M 2µs 10M FREQUENCY (Hz) t 100 90 10.810µs 10 0% 00875-007 10 0% 1µs 50mV 5V Figure 7. Open-Loop Gain/Phase and Small Signal Response, VS = 3 V, No Load 2µs Figure 9. Slew Rate, RL = 10 kΩ 100 90 VS = 3V CL = 220pF 60 00875-009 100 90 VOUT 135 10 0% 100µs 5V Figure 10. Phase Reversal with Inputs Exceeding Supply by 1 V 180 0 00875-010 90 20 PHASE (Degrees) 45 0.8 –20 0.7 1k 10k 100k 1M 10M FREQUENCY (Hz) OUTPUT TO RAIL (V) 0.6 100 90 0.5 0.4 SOURCE 0.3 0.2 SINK 0.1 0% 50mV 1µs 0 1µ Figure 8. Open-Loop Gain/Phase and Small Signal Response, VS = 3 V, CL = 220 pF 5µ 10µ 50µ 100µ 500µ LOAD CURRENT (A) 1m 5m 10m 00875-011 10 00875-008 GAIN (dB) 40 Figure 11. Output Voltage to Supply Rail vs. Sink and Source Load Currents Rev. E | Page 8 of 16 Data Sheet AD824 14 COUNT = 60 NUMBER OF UNITS 12 60 40 8 6 10 15 FREQUENCY (kHz) 0 –2.5 20 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 OFFSET VOLTAGE DRIFT (µV/°C) 00875-015 2 20 5 Figure 15. TC VOS Distribution, −55°C to +125°C, VS = 5 V, 0 V Figure 12. Voltage Noise Density 0.1 10 4 00875-012 NOISE DENSITY (nV/√Hz) 3V ≤ VS ≤ ±15V 150 RL = ∞ AV = +1 VS = 5V, 0V INPUT OFFSET CURRENT (pA) 125 VS = +3V THD + N (%) 0.01 VS = +5V VS = ±15V 0.001 100 75 50 25 20 100 1k 10k 20k FREQUENCY (Hz) –25 –60 00875-013 0.0001 0 20 40 60 80 100 120 140 Figure 16. Input Offset Current vs. Temperature 280 100k COUNT = 860 240 VS = 5V, 0V INPUT BIAS CURRENT (pA) 10k 200 160 120 80 1k 100 10 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 OFFSET VOLTAGE (mV) 0.5 Figure 14. Input Offset Distribution, VS = 5 V, 0 V 0.1 20 40 60 80 100 120 TEMPERATURE (°C) Figure 17. Input Bias Current vs. Temperature Rev. E | Page 9 of 16 140 00875-017 1 40 00875-014 NUMBER OF UNITS –20 TEMPERATURE (°C) Figure 13. Total Harmonic Distortion 0 –0.5 –40 00875-016 0 AD824 Data Sheet 120 1k INPUT VOLTAGE NOISE (nV/√Hz) 80 60 40 20 1k 10k 100k 1M 10M FREQUENCY (Hz) 1 1 1k 10k 100k –80 –100 1k 10k 100k FREQUENCY (Hz) 80 60 40 20 0 10 00875-019 –120 100 100 30 80 80 25 40 40 3V, 0V 20 20 0 0 10k 100k 1M –20 10M FREQUENCY (Hz) OUTPUT VOLTAGE (V) 60 ±15V 100k 1M 10M 20 15 10 5 00875-020 60 PHASE MARGIN (Degrees) 100 1k 10k Figure 22. Power Supply Rejection vs. Frequency 100 100 1k FREQUENCY (Hz) Figure 19. THD vs. Frequency, 3 V rms –20 100 00875-022 POWER SUPPLY REJECTION (dB) 120 –60 OPEN-LOOP GAIN (dB) 100 Figure 21. Input Voltage Noise Spectral Density vs. Frequency –40 10 10 FREQUENCY (Hz) Figure 18. Common-Mode Rejection vs. Frequency THD (dB) 10 00875-021 100 00875-018 0 10 100 Figure 20. Open-Loop Gain and Phase vs. Frequency 0 1k 3k 10k 30k 100k 300k INPUT FREQUENCY (Hz) Figure 23. Large Signal Frequency Response Rev. E | Page 10 of 16 1M 00875-023 COMMON-MODE REJECTION (dB) 100 Data Sheet AD824 –80 –90 CROSSTALK (dB) –100 5V –110 5µs 100 90 1 TO 4 –120 1 TO 3 1 TO 2 –130 10 100 1k 10k 100k FREQUENCY (Hz) 00875-027 10 0% 00875-024 –140 Figure 24. Crosstalk vs. Frequency Figure 27. Large Signal Response 2750 10k VS = ±15V 2500 SUPPLY CURRENT (µA) 100 10 1 0.1 2250 2000 VS = +3V, 0V 1750 1500 1250 100 1k 10k 100k 10M 1M FREQUENCY (Hz) 1000 –60 00875-025 0.01 10 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) Figure 25. Output Impedance vs. Frequency, Gain = +1 Figure 28. Supply Current vs. Temperature OUTPUT SATURATION VOLTAGE (mV) 1k 20mV –40 00875-028 OUTPUT IMPEDANCE (Ω) 1k 500ns 100 90 VS = ±15V VS = 3V, 0V 100 VOL – VS 10 VS – VOH 1 0.01 00875-026 0.1 1 LOAD CURRENT (mA) Figure 26. Small Signal Response, Unity Gain Follower, 10 kΩ||100 pF Load Rev. E | Page 11 of 16 Figure 29. Output Saturation Voltage 10 00875-029 10 0% AD824 Data Sheet THEORY OF OPERATION INPUT CHARACTERISTICS In the AD824, n-channel JFETs are used to provide a low offset, low noise, high impedance input stage. Minimum input common-mode voltage extends from 0.2 V below −VS to 1 V less than +VS. Driving the input voltage closer to the positive rail causes a loss of amplifier bandwidth. The AD824 does not exhibit phase reversal for input voltages up to and including +VS. Figure 30a shows the response of an AD824 voltage follower to a 0 V to 5 V (+VS) square wave input. The input and output are superimposed. The output tracks the input up to +VS without phase reversal. The reduced bandwidth above a 4 V input causes the rounding of the output waveform. For input voltages greater than +VS, a resistor in series with the noninverting input prevents phase reversal at the expense of greater input voltage noise. This is illustrated in Figure 30b. 1V 2µs 100 90 Input voltages less than −VS are a completely different story. The amplifier can safely withstand input voltages 20 V below the −VS as long as the total voltage from the +VS to the input terminal is less than 36 V. In addition, the input stage typically maintains picoamp level input currents across that input voltage range. OUTPUT CHARACTERISTICS The unique bipolar rail-to-rail output stage of the AD824 swings within 15 mV of the positive and negative supply voltages. The approximate output saturation resistance of the AD824 is 100 Ω for both sourcing and sinking. This can be used to estimate output saturation voltage when driving heavier current loads. For instance, the saturation voltage is 0.5 V from either supply with a 5 mA current load. For load resistances over 20 kΩ, the input error voltage of the AD824 is virtually unchanged until the output voltage is driven to 180 mV of either supply. 10 0% If the output of the AD824 is overdriven to saturate either of the output devices, the amplifier will recover within 2 μs of its input returning to the amplifier’s linear operating region. 1V (a) 1V +VS 100 90 GND 0% Direct capacitive loads will interact with the amplifier’s effective output impedance to form an additional pole in the amplifier’s feedback loop, which can cause excessive peaking on the pulse response or loss of stability. Worst case is when the amplifier is used as a unity gain follower. Figure 6 and Figure 8 show the pulse response of the AD824 as a unity gain follower driving 220 pF. Configurations with less loop gain, and as a result less loop bandwidth, will be much less sensitive to capacitance load effects. Noise gain is the inverse of the feedback attenuation factor provided by the feedback network in use. 10µs 1V 10 1V (b) Figure 31 shows a method for extending capacitance load drive capability for a unity gain follower. With these component values, the circuit drives 5,000 pF with a 10% overshoot. 5V RP VOUT 00875-030 VIN +VS 0.01µF 8 Figure 30. (a) Response with RP = 0; VIN from 0 V to +VS; (b) VIN = −200 V to + VS + 200 mV; VOUT = 0 V to + VS; RP = 49.9 kΩ 100Ω 1/4 VIN Because the input stage uses n-channel JFETs, input current during normal operation is positive; the current flows out from the input terminals. If the input voltage is driven more positive than +VS − 0.4 V, the input current reverses direction as internal device junctions become forward biased. This is illustrated in Figure 10. Use a current-limiting resistor in series with the input of the AD824 if there is a possibility of the input voltage exceeding the AD824 VOUT 0.01µF 4 CL –VS 20pF 20kΩ 00875-031 GND positive supply by more than 300 mV or if an input voltage will be applied to the AD824 when ±VS = 0 V. The amplifier will be damaged if left in that condition for more than 10 seconds. A 1 kΩ resistor allows the amplifier to withstand up to 10 V of continuous overvoltage and increases the input voltage noise by a negligible amount. Figure 31. Extending Unity Gain Follower Capacitive Load Capability Beyond 350 pF Rev. E | Page 12 of 16 Data Sheet AD824 APPLICATIONS INFORMATION SINGLE SUPPLY VOLTAGE-TO-FREQUENCY CONVERTER Table 6. AD824 In Amp Performance The circuit shown in Figure 32 uses the AD824 to drive a low power timer, which produces a stable pulse of width, t1. The positive going output pulse is integrated by R1 and C1 and used as one input to the AD824, which is connected as a differential integrator. The other input (nonloading) is the unknown voltage, VIN. The AD824 output drives the timer trigger input, closing the overall feedback loop. 10V 2 6 VREF = 5V 5 3 CMOS 74HCO4 RSCALE ** 10kΩ 4 U3B 4 C3 0.1µF 3 U3A 2 1 R1 499kΩ 1% 0V TO 2.5V FULL SCALE U1 C1 0.01µF 2% R3* 116kΩ AD824 C2 0.01µF 2% C6 390pF 5% (NPO) 180 kHz 18 kHz 180 kHz 18 kHz 2 μs 5 μs 270 nV/√Hz 2.2 μV/√Hz 270 nV/√Hz 2.2 μV/√Hz 5µs OUT1 4 100 90 8 V+ R 6 THR 2 TR 1/4 VS = ±5 V 80 dB −5.2 V to +4 V OUT2 U2 CMOS 555 R2 499kΩ 1% VS = 3 V, 0 V 74 dB −0.2 V to +2 V OUT CV 7 DIS 3 5 10 0% GND 1 00875-033 C5 0.1µF U4 REF02 Parameter CMRR Common-Mode Voltage Range 3 dB BW G = 10 G = 100 tSETTLING 2 V Step (VS = 0 V, 3 V) 5 V (VS = ± 5 V) Noise @ f = 1 kHz G = 10 G = 100 1V C4 0.1µF Figure 33. Pulse Response of In Amp to a 500 mV p-p Input Signal; VS = 5 V, 0 V; Gain = 10 NOTES fOUT = VIN/(VREF × t1), t1 = 1.1 × R3 × C6 = 25kHz fS AS SHOWN. 00875-032 * = 1% METAL FILM,