AD8295BCPZ-RL

Precision Instrumentation Amplifier with Signal Processing Amplifiers AD8295 FEATURES Saves board space Includes precision in-amp, 2 op amps, and 2 matched resistors 4 mm × 4 mm LFCSP No heat slug for more routing room Differential output fully specified In-amp specifications Gain set with 1 external resistor (gain range: 1 to 1000) 8 nV/√Hz @ 1 kHz, maximum input voltage noise 90 dB minimum CMRR (G = 1) 0.8 nA maximum input bias current 1.2 MHz, −3 dB bandwidth (G = 1) 2 V/μs slew rate Wide power supply range: ±2.3 V to ±18 V 1 ppm/°C, 0.03% resistor matching CONNECTION DIAGRAM +VS 16 OUT 15 A2 +IN 14 A2 –IN 13 12 A2 OUT –IN 1 AD8295 A2 RG 2 IA RG 3 A1 +IN 4 5 6 7 11 A1 +IN 10 A1 R1 R1 20kΩ R2 20kΩ 8 9 A1 –IN 07343-001 –VS REF A1 OUT A1 R2 Figure 1. APPLICATIONS Industrial process controls Wheatstone bridges Precision data acquisition systems Medical instrumentation Strain gages Transducer interfaces Differential output Table 1. Instrumentation Amplifiers by Category General Purpose AD82201 AD8221 AD8222 AD82241 AD8228 AD8295 1 Zero Drift AD82311 AD85531 AD85551 AD85561 AD85571 AD82931 Military Grade AD620 AD621 AD524 AD526 AD624 Low Power AD6271 AD6231 AD82231 High Speed PGA AD8250 AD8251 AD8253 Rail-to-rail output. GENERAL DESCRIPTION The AD8295 contains all the components necessary for a precision instrumentation amplifier front end in one small 4 mm × 4 mm package. It contains a high performance instrumentation amplifier, two general-purpose operational amplifiers, and two precisely matched 10 kΩ resistors. The AD8295 is designed to make PCB routing easy and efficient. The AD8295 components are arranged in a logical way so that typical application circuits have short routes and few vias. Unlike most chip scale packages, the AD8295 does not have an exposed metal pad on the back of the part, which frees additional space for routing and vias. The AD8295 comes in a 4 mm × 4 mm LFCSP that requires half the board space of an 8-pin SOIC package. The AD8295 includes a high performance, programmable gain instrumentation amplifier. Gain is set from 1 to 1000 with a single resistor. The low noise and excellent common-mode rejection of the AD8295 enable the part to easily detect small signals even in the presence of large common-mode interference. For a similar instrumentation amplifier without the associated signal conditioning circuitry, see the AD8221 or AD8222 data sheet. The AD8295 operates on both single and dual supplies and is well suited for applications where ±10 V input voltages are encountered. Performance is specified over the entire industrial temperature range of −40°C to +85°C for all grades. The AD8295 is operational from −40°C to +125°C; see the Typical Performance Characteristics section for expected operation up to 125°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. AD8295 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  Connection Diagram ....................................................................... 1  General Description ......................................................................... 1  Revision History ............................................................................... 2  Specifications..................................................................................... 3  Instrumentation Amplifier Specifications, Single-Ended and Differential Output Configurations ........................................... 3  Op Amp Specifications ................................................................ 5  Internal Resistor Network ........................................................... 6  Power and Temperature Specifications ..................................... 6  Absolute Maximum Ratings............................................................ 7  Thermal Characteristics .............................................................. 7  ESD Caution .................................................................................. 7  Pin Configuration and Function Descriptions ............................. 8  Typical Performance Characteristics ............................................. 9  In-Amp .......................................................................................... 9  Op Amps...................................................................................... 16  System .......................................................................................... 18  Theory of Operation ...................................................................... 19  Uncommitted Op Amps ............................................................ 19  Instrumentation Amplifier........................................................ 19  Layout .......................................................................................... 20  Input Protection ......................................................................... 21  Input Bias Current Return Path ............................................... 21  RF Interference ........................................................................... 21  Differential Output .................................................................... 22  Applications Information .............................................................. 23  Creating a Reference Voltage at Midscale ............................... 23  High Accuracy G = −1 Configuration with Low-Pass Filter .. 23  2-Pole Sallen-Key Filter ............................................................. 24  AC-Coupled Instrumentation Amplifier ................................ 24  Driving Differential ADCs ........................................................ 25  Outline Dimensions ....................................................................... 26  Ordering Guide .......................................................................... 26  REVISION HISTORY 10/08—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD8295 SPECIFICATIONS INSTRUMENTATION AMPLIFIER SPECIFICATIONS, SINGLE-ENDED AND DIFFERENTIAL OUTPUT CONFIGURATIONS VS = ±15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted. The differential configuration is shown in Figure 59. Table 2. Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR, DC to 60 Hz G=1 G = 10 G = 100 G = 1000 CMRR at 8 kHz G=1 G = 10 G = 100 G = 1000 NOISE Voltage Noise, 1 kHz Input Voltage Noise, eNI Output Voltage Noise, eNO RTI G=1 G = 10 G = 100 to 1000 Current Noise VOLTAGE OFFSET Input Offset, VOSI Over Temperature Average TC Output Offset, VOSO Over Temperature Average TC Offset RTI vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Over Temperature Average TC Input Offset Current Over Temperature Average TC Test Conditions VCM = −10 V to +10 V 1 kΩ source imbalance 80 100 120 130 80 90 100 110 RTI noise = √(eNI2 + (eNO/G)2) VIN+, VIN−, VREF = 0 V VIN+, VIN−, VREF = 0 V f = 0.1 Hz to 10 Hz 2 0.5 0.25 40 6 120 150 0.4 500 0.8 9 90 110 124 130 110 120 130 140 0.5 TA = −40°C to +85°C 1 0.2 TA = −40°C to +85°C 1 2.0 3.0 1 1.5 94 114 130 140 110 130 140 150 0.2 1 0.1 0.5 0.8 1.5 0.5 0.6 2 90 110 130 140 80 100 120 120 dB dB dB dB dB dB dB dB Min A Grade Typ Max Min B Grade Typ Max Unit 8 75 2 0.5 0.25 40 6 8 75 nV/√Hz nV/√Hz μV p-p μV p-p μV p-p fA/√Hz pA p-p f = 1 kHz f = 0.1 Hz to 10 Hz RTI VOS = ( VOSI) + (VOSO/G) VS = ±5 V to ±15 V TA = −40°C to +85°C VS = ±5 V to ±15 V TA = −40°C to +85°C VS = ±2.3 V to ±18 V 60 80 0.3 350 0.5 5 μV μV μV/°C μV mV μV/°C dB dB dB dB nA nA pA/°C nA nA pA/°C Rev. 0 | Page 3 of 28 AD8295 Parameter GAIN Gain Range Gain Error G=1 G = 10 G = 100 G = 1000 Gain Nonlinearity G=1 G = 10 G = 100 Gain vs. Temperature G=1 G>1 DYNAMIC RESPONSE (SINGLEENDED CONFIGURATION) Small Signal −3 dB Bandwidth G=1 G = 10 G = 100 G = 1000 Settling Time 0.01% G = 1 to 100 G = 1000 Settling Time 0.001% G = 1 to 100 G = 1000 Slew Rate G=1 G = 5 to 1000 DYNAMIC RESPONSE (DIFFERENTIAL OUTPUT CONFIGURATION) Small Signal −3 dB Bandwidth G=1 G = 10 G = 100 G = 1000 Settling Time 0.01% G = 1 to 100 G = 1000 Settling Time 0.001% G = 1 to 100 G = 1000 Slew Rate G=1 G = 5 to 1000 REFERENCE INPUT RIN IIN Voltage Range Gain to Output Test Conditions G = 1 + (49.4 kΩ/RG) VOUT ± 10 V 0.05 0.3 0.3 0.3 VOUT = −10 V to +10 V 3 7 7 10 20 20 5 −50 1 7 7 5 20 20 1 −50 ppm ppm ppm ppm/°C ppm/°C 0.02 0.1 0.1 0.1 % % % % Min 1 A Grade Typ Max 1000 Min 1 B Grade Typ Max 1000 Unit V/V 1200 750 140 15 10 V step 10 80 10 V step 13 110 1.5 2 2 2.5 1.5 2 1200 750 140 15 10 80 13 110 2 2.5 kHz kHz kHz kHz μs μs μs μs V/μs V/μs 1200 1000 140 15 10 V step 10 80 10 V step 13 110 1.5 2 2 2.5 20 50 −VS 1 ± 0.0001 1.5 2 1200 1000 140 15 10 80 13 110 2 2.5 20 50 −VS 1 ± 0.0001 kHz kHz kHz kHz μs μs μs μs V/μs V/μs kΩ μA V V/V VIN+, VIN−, VREF = 0 V 60 +VS 60 +VS Rev. 0 | Page 4 of 28 AD8295 Parameter INPUT Input Impedance Differential Common Mode Input Operating Voltage Range 1 Over Temperature Input Operating Voltage Range1 Over Temperature OUTPUT Output Swing Over Temperature Output Swing Over Temperature Short-Circuit Current 1 Test Conditions Min A Grade Typ Max Min B Grade Typ Max Unit 100||2 100||2 VS = ±2.3 V to ±5 V TA = −40°C to +85°C VS = ±5 V to ±18 V TA = −40°C to +85°C RL = 10 kΩ VS = ±2.3 V to ±5 V TA = −40°C to +85°C VS = ±5 V to ±18 V TA = −40°C to +85°C −VS + 1.9 −VS + 2.0 −VS + 1.9 −VS + 2.0 −VS + 1.1 −VS + 1.4 −VS + 1.2 −VS + 1.6 18 +VS − 1.1 +VS − 1.2 +VS − 1.2 +VS − 1.2 +VS − 1.2 +VS − 1.3 +VS − 1.4 +VS − 1.5 −VS + 1.9 −VS + 2.0 −VS + 1.9 −VS + 2.0 −VS + 1.1 −VS + 1.4 −VS + 1.2 −VS + 1.6 100||2 100||2 +VS − 1.1 +VS − 1.2 +VS − 1.2 +VS − 1.2 +VS − 1.2 +VS − 1.3 +VS − 1.4 +VS − 1.5 18 GΩ||pF GΩ||pF V V V V V V V V mA One input grounded; G = 1. OP AMP SPECIFICATIONS VS = ±15 V, TA = 25°C, RL = 2 kΩ, unless otherwise noted. Table 3. Parameter INPUT CHARACTERISTICS Offset Voltage, VOS Average TC Input Bias Current 1 Test Conditions Min A Grade Typ Max 40 4 10 20 10 2 2 −VS + 1.2 100 100 90 f = 0.1 Hz to 10 Hz +VS − 1.2 125 110 40 2.2 1 2.6 VS = ±2.3 V to ±5 V TA = −40°C to +85°C VS = ±5 V to ±18 V TA = −40°C to +85°C −VS + 1.1 −VS + 1.4 −VS + 1.2 −VS + 1.6 18 +VS − 1.2 +VS − 1.3 +VS − 1.4 +VS − 1.5 −VS + 1.1 −VS + 1.4 −VS + 1.2 −VS + 1.6 18 −VS + 1.2 116 100 94 Min B Grade Typ Max 20 2 8 16 8 0.5 0.5 +VS − 1.2 125 110 40 2.2 1 2.6 +VS − 1.2 +VS − 1.3 +VS − 1.4 +VS − 1.5 Unit μV μV/°C nA nA nA nA nA V dB dB dB nV/√Hz μV p-p MHz V/μs V V V V mA TA = −40°C to +85°C TA = −40°C TA = +85°C Input Offset Current Over Temperature Input Voltage Range Open-Loop Gain Common-Mode Rejection Ratio Power Supply Rejection Ratio Voltage Noise Density Voltage Noise DYNAMIC PERFORMANCE Gain Bandwidth Product Slew Rate OUTPUT CHARACTERISTICS Output Swing Over Temperature Output Swing Over Temperature Short-Circuit Current 1 TA = −40°C to +85°C Op amp uses an npn input stage, so input bias current always flows into the inputs. Rev. 0 | Page 5 of 28 AD8295 INTERNAL RESISTOR NETWORK When used with internal Op Amp A1, TA = 25°C, unless otherwise noted. Use in external op amp feedback loops is not recommended. Table 4. Parameter Nominal Resistor Value Resistor Matching Matching Temperature Coefficient Absolute Resistor Accuracy Absolute Temperature Coefficient Test Conditions Min A Grade Typ 20 Max 0.1 5 0.2 −50 Min B Grade Typ 20 Max 0.03 1 0.1 −50 Unit kΩ % ppm/°C % ppm/°C TA = −40°C to +85°C TA = −40°C to +85°C POWER AND TEMPERATURE SPECIFICATIONS VS = ±15 V, VREF = 0 V, TA = 25°C, unless otherwise noted. Table 5. Parameter POWER SUPPLY Operating Range Quiescent Current Over Temperature TEMPERATURE RANGE Specified Performance Operational Performance 1 1 Test Conditions Min ±2.3 A Grade Typ Max ±18 2.3 2.5 +85 +125 Min ±2.3 B Grade Typ Max ±18 2.3 2.5 +85 +125 Unit V mA mA °C °C In-amp + two op amps TA = −40°C to +85°C −40 −40 2 2 −40 −40 See the Typical Performance Characteristics section for expected operation from 85°C to 125°C. Rev. 0 | Page 6 of 28 AD8295 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Supply Voltage Output Short-Circuit Current Input Voltage Common-Mode Differential Storage Temperature Range Operating Temperature Range1 Lead Temperature (Soldering, 10 sec) Junction Temperature ESD (Human Body Model) ESD (Charge Device Model) ESD (Machine Model) 1 THERMAL CHARACTERISTICS Rating ±18 V Indefinite ±VS ±VS −65°C to +130°C −40°C to +125°C 300°C 130°C 2000 V 500 V 200 V Specifications are provided for a device in free air. Table 7. Package 16-Lead LFCSP_VQ θJA 86 Unit °C/W ESD CAUTION Temperature range for specified performance is −40°C to +85°C. See the Typical Performance Characteristics section for expected operation from 85°C to 125°C. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 7 of 28 AD8295 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 14 A2 +IN 16 +VS 15 OUT 13 A2 –IN –IN 1 RG 2 RG 3 +IN 4 PIN 1 INDICATOR 12 A2 OUT 11 A1 +IN 10 A1 R1 9 A1 –IN AD8295 TOP VIEW (Not to Scale) A1 OUT 7 A1 R2 8 –VS 5 REF 6 Figure 2. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 2, 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic −IN RG +IN −VS REF A1 OUT A1 R2 A1 −IN A1 R1 A1 +IN A2 OUT A2 −IN A2 +IN OUT +VS Description In-Amp Negative Input. In-Amp Gain-Setting Resistor Terminals. In-Amp Positive Input. Negative Supply. In-Amp Reference Terminal. Drive with a low impedance source. Output is referred to this pin. Op Amp A1 Output. Resistor R2 Terminal. Connected internally to Op Amp A1 inverting input. Op Amp A1 Inverting Input. Midpoint of resistor divider. Resistor R1 Terminal. Connected internally to Op Amp A1 inverting input. Op Amp A1 Noninverting Input. Op Amp A2 Output. Op Amp A2 Inverting Input. Op Amp A2 Noninverting Input. In-Amp Output. Positive Supply. Rev. 0 | Page 8 of 28 07343-017 AD8295 TYPICAL PERFORMANCE CHARACTERISTICS IN-AMP VS = ±15 V, REF = 0 V, TA = 25°C, RL = 10 kΩ, unless otherwise noted. 800 800 600 HITS 400 200 07343-057 600 HITS 400 200 –100 –50 0 CMRR (µV/V) 50 100 –1.0 –0.5 0 0.5 1.0 INPUT OFFSET CURRENT (nA) Figure 3. Typical Distribution for CMRR, G = 1 5 Figure 6. Typical Distribution of Input Offset Current 800 INPUT COMMON-MODE VOLTAGE (V) 700 600 500 4 3 2 1 0 –1 –2 –3 –5 –4 –3 –2 –1 0 1 2 G=1 VS = ±2.5V, ±5V HITS 400 300 200 100 0 3 4 5 VOSI (µV) OUTPUT VOLTAGE (V) Figure 4. Typical Distribution of Input Offset Voltage 700 600 500 400 HITS Figure 7. Input Common-Mode Range vs. Output Voltage, G = 1, VS = ±2.5 V, ±5 V, REF = 0 V 15 G=1 VS = ±15V INPUT COMMON-MODE VOLTAGE (V) 10 5 0 300 200 100 0 –2 –1 0 INPUT BIAS CURRENT (nA) 1 2 –5 –10 07343-059 –10 –5 0 5 10 15 OUTPUT VOLTAGE (V) Figure 5. Typical Distribution of Input Bias Current Figure 8. Input Common-Mode Range vs. Output Voltage, G = 1, VS = ±15 V, REF = 0 V Rev. 0 | Page 9 of 28 07343-046 –15 –15 07343-045 –100 –50 0 50 100 07343-058 –4 07343-060 0 0 AD8295 5 INPUT COMMON-MODE VOLTAGE (V) CHANGE IN INPUT OFFSET VOLTAGE (µV) 4 3 2 1 0 –1 –2 –3 –5 –4 –3 –2 –1 0 1 2 G = 100 VS = ±2.5V, ±5V 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 2 4 6 8 10 07343-062 3 4 5 07343-047 –4 0 OUTPUT VOLTAGE (V) WARM-UP TIME (Min) Figure 9. Input Common-Mode Range vs. Output Voltage, G = 100, VS = ±2.5 V, ±5 V, REF = 0 V 15 INPUT COMMON-MODE VOLTAGE (V) Figure 12. Change in Input Offset Voltage vs. Warm-Up Time 5 4 3 2 CURRENT (nA) G = 100 VS = ±15V 10 NEGATIVE BIAS POSITIVE BIAS 5 1 0 –1 –2 –3 –4 0 –5 OFFSET –10 –10 –5 0 5 10 15 07343-048 –20 0 20 40 60 80 100 120 140 OUTPUT VOLTAGE (V) TEMPERATURE (°C) Figure 10. Input Common-Mode Range vs. Output Voltage, G = 100, VS = ±15 V, REF = 0 V 0 –0.050 INPUT BIAS CURRENT (nA) Figure 13. Input Bias Current and Offset Current vs. Temperature 180 160 ±15V POSITIVE PSRR (dB) GAIN = 1000 140 GAIN = 100 120 GAIN = 10 100 80 60 40 20 0.1 GAIN = 1 –0.100 –0.150 –0.200 ±5V –0.250 –0.300 –0.350 –15 07343-061 –10 –5 0 5 10 15 1 10 100 1k 10k 100k 1M COMMON-MODE VOLTAGE (V) FREQUENCY (Hz) Figure 11. Input Bias Current vs. Common-Mode Voltage Figure 14. Positive PSRR vs. Frequency, RTI, G = 1 to 1000 Rev. 0 | Page 10 of 28 07343-049 07343-063 –15 –15 –5 –40 AD8295 180 160 GAIN = 1000 140 GAIN = 100 180 170 160 150 130 CMRR (dB) GAIN = 1000 NEGATIVE PSRR (dB) 140 GAIN = 100 120 GAIN = 10 110 100 GAIN = 1 90 80 70 60 50 07343-051 07343-020 120 GAIN = 10 100 GAIN = 1 80 60 40 20 0.1 1 10 100 1k 10k 100k 1M 07343-050 40 0.1 1 10 100 FREQUENCY (Hz) 1k 10k 100k FREQUENCY (Hz) Figure 15. Negative PSRR vs. Frequency, RTI, G = 1 to 1000 200 150 100 Figure 18. CMRR vs. Frequency, RTI 180 170 160 150 GAIN = 1000 140 130 CMRR (dB) GAIN ERROR (ppm) 50 0 –50 –100 –150 –200 –40 GAIN = 100 120 GAIN = 10 110 100 GAIN = 1 90 80 70 60 50 40 0.1 07343-064 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) FREQUENCY (Hz) Figure 16. Gain Error vs. Temperature, G = 1 70 60 50 40 30 GAIN = 100 GAIN = 1000 INPUT VOLTAGE LIMIT (V) REFERRED TO SUPPLY VOLTAGES Figure 19. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance +VS–0 –0.4 –0.8 –1.2 –1.6 –2.0 FROM +V GAIN (dB) 20 10 0 –10 –20 –30 GAIN = 10 GAIN = 1 +2.0 +1.6 +1.2 +0.8 +0.4 FROM –V 07343-044 –40 100 1k 10k 100k 1M 10M –VS+0 2 6 10 SUPPLY VOLTAGE (V) 14 18 FREQUENCY (Hz) Figure 17. Gain vs. Frequency Figure 20. Input Voltage Limit vs. Supply Voltage, G = 1 Rev. 0 | Page 11 of 28 07343-052 1 10 100 1k 10k 100k AD8295 +VS–0 –0.4 4 3 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES –0.8 –1.2 –1.6 RL = 10kΩ NONLINEARITY (1ppm/DIV) 2 1 0 2kΩ LOAD –1 –2 –3 –4 –10 600Ω LOAD 10kΩ LOAD RL = 2kΩ +1.6 +1.2 +0.8 +0.4 RL = 10kΩ RL = 2kΩ 07343-021 2 6 10 SUPPLY VOLTAGE (V) 14 18 –8 –6 –4 –2 0 VOUT (V) 2 4 6 8 10 Figure 21. Output Voltage Swing vs. Supply Voltage, G = 1 30 40 30 Figure 24. Gain Nonlinearity, G = 1 OUTPUT VOLTAGE SWING (V p-p) NONLINEARITY (10ppm/DIV) 20 10 0 –10 –20 –30 2kΩ LOAD 20 600Ω LOAD 10 10kΩ LOAD 07343-022 1 10 100 LOAD RESISTANCE (Ω) 1k 10k –8 –6 –4 –2 0 VOUT (V) 2 4 6 8 10 Figure 22. Output Voltage Swing vs. Load Resistance +VS–0 –1 –2 –3 SOURCING 1k Figure 25. Gain Nonlinearity, G = 100 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES VOLTAGE NOISE RTI (nV/ Hz) GAIN = 1 100 GAIN = 10 GAIN = 100 GAIN = 1000 +3 +2 SINKING +1 10 07343-023 0 1 2 3 4 5 6 7 8 9 10 11 12 1 10 100 1k 10k 100k OUTPUT CURRENT (mA) FREQUENCY (Hz) Figure 23. Output Voltage Swing vs. Output Current, G = 1 Figure 26. Voltage Noise Spectral Density vs. Frequency, G = 1 to 1000 Rev. 0 | Page 12 of 28 07343-027 –VS+0 1 GAIN = 1000 BW LIMIT 07343-025 0 –40 –10 07343-024 –VS+0 AD8295 07343-028 2µV/DIV 1s/DIV 5pA/DIV 1s/DIV Figure 27. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1 30 Figure 30. 0.1 Hz to 10 Hz Current Noise GAIN = 10, 100, 1000 MAX OUTPUT VOLTAGE (V p-p) 25 GAIN = 1 20 15 10 5 07343-029 10k 100k FREQUENCY (Hz) 1M Figure 28. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1000 1k Figure 31. Large Signal Frequency Response 5V/DIV CURRENT NOISE (fA/ Hz) 100 7.4µs TO 0.01% 8.3µs TO 0.001% 0.002%/DIV 20µs/DIV 07343-033 1 10 100 1k 10k 100k FREQUENCY (Hz) 07343-030 10 Figure 29. Current Noise Spectral Density vs. Frequency Figure 32. Large Signal Pulse Response and Settling Time, G = 1 Rev. 0 | Page 13 of 28 07343-032 0.1µV/DIV 1s/DIV 0 1k 07343-031 AD8295 5V/DIV 4.8µs TO 0.01% 6.6µs TO 0.001% 0.002%/DIV 20µs/DIV 07343-034 20mV/DIV 4µs/DIV Figure 33. Large Signal Pulse Response and Settling Time, G = 10 Figure 36. Small Signal Pulse Response, G = 1, RL = 2 kΩ, CL = 100 pF 5V/DIV 9.2µs TO 0.01% 16.2µs TO 0.001% 0.002%/DIV 07343-035 20µs/DIV 20mV/DIV 4µs/DIV Figure 34. Large Signal Pulse Response and Settling Time, G = 100 Figure 37. Small Signal Pulse Response, G = 10, RL = 2 kΩ, CL = 100 pF 5V/DIV 83µs TO 0.01% 112µs TO 0.001% 0.002%/DIV 07343-036 200µs/DIV 20mV/DIV 10µs/DIV Figure 35. Large Signal Pulse Response and Settling Time, G = 1000 Figure 38. Small Signal Pulse Response, G = 100, RL = 2 kΩ, CL = 100 pF Rev. 0 | Page 14 of 28 07343-039 07343-038 07343-037 AD8295 1k SETTLING TIME (µs) 100 SETTLED TO 0.001% 10 SETTLED TO 0.01% 20mV/DIV 100µs/DIV 07343-040 1 10 GAIN 100 1k Figure 39. Small Signal Pulse Response, G = 1000, RL = 2 kΩ, CL = 100 pF 15 Figure 41. Settling Time vs. Gain for a 10 V Step SETTLING TIME (µs) 10 SETTLED TO 0.001% 5 SETTLED TO 0.01% 0 5 10 15 20 OUTPUT VOLTAGE STEP SIZE (V) Figure 40. Settling Time vs. Step Size, G = 1 07343-041 0 Rev. 0 | Page 15 of 28 07343-042 1 AD8295 OP AMPS VS = ±15 V, TA = 25°C, RL = 10 kΩ, Op Amp A1 and Op Amp A2, unless otherwise noted. 80 70 GAIN = 1000 60 4 GAIN = 100 GAIN (dB) VOLTAGE NOISE (µV) 07343-065 8 6 50 40 30 20 10 0 –10 –20 0.1 1 10 100 1k 10k 100k 1M 10M 100M GAIN = 1 GAIN = 10 2 0 –2 –4 –6 –8 0 1 2 3 4 5 TIME (Sec) 6 7 8 9 10 FREQUENCY (Hz) Figure 42. Closed-Loop Gain vs. Frequency, G = 1 to 1000 140 14 12 Figure 45. 0.1 Hz to 10 Hz Noise 120 +PSRR CURRENT (nA) 10 8 6 +BIAS CURRENT 4 2 0 –2 –4 07343-066 –BIAS CURRENT 100 PSRR (dB) 80 –PSRR 60 40 OFFSET CURRENT –40 –30 –20 –10 100 110 120 FREQUENCY (Hz) TEMPERATURE (°C) Figure 43. PSRR vs. Frequency 1k Figure 46. Input Bias Current and Input Offset Current vs. Temperature 40 30 20 GAIN ERROR (ppm) 10 0 –10 –20 –30 –40 –50 NOISE (nV/ Hz) 100 07343-067 1 10 100 1k 10k 100k –20 0 20 40 60 80 100 120 140 FREQUENCY (Hz) TEMPERATURE (°C) Figure 44. Voltage Noise Density vs. Frequency Figure 47. Gain Drift Using On-Chip Resistor Divider, G = 1 Rev. 0 | Page 16 of 28 07343-070 10 –60 –40 07343-069 1 10 100 1k 10k 100k 1M 130 20 0.1 –6 0 10 20 30 40 50 60 70 80 90 07343-068 AD8295 40 30 20 GAIN ERROR (ppm) 10 0 –10 –20 –30 –40 –50 –20 0 20 40 60 80 100 120 140 07343-071 –60 –40 TEMPERATURE (°C) Figure 48. Gain Drift Using On-Chip Resistor Divider, G = 2 Rev. 0 | Page 17 of 28 AD8295 SYSTEM VS = ±15 V, VREF = 0 V, TA = 25°C, unless otherwise noted. 80 GAIN = 1000 3.0 60 2.5 +125°C +85°C +25°C –40°C 40 GAIN = 100 SUPPLY CURRENT (mA) 2.0 GAIN (dB) 20 GAIN = 10 1.5 0 GAIN = 1 1.0 –20 0.5 100 1k 10k 100k 1M 10M 07343-054 2 4 6 8 10 12 14 16 FREQUENCY (Hz) SUPPLY VOLTAGE (±V) Figure 49. Differential Output Configuration, Gain vs. Frequency 80 70 Figure 51. Supply Current vs. Supply Voltage COMMON-MODE OUTPUT (dB) 60 50 40 30 20 10 0 FREQUENCY (Hz) Figure 50. Differential Output Configuration, Common-Mode Output vs. Frequency 07343-055 1 10 100 1k 10k 100k 1M Rev. 0 | Page 18 of 28 07343-072 –40 10 0 AD8295 THEORY OF OPERATION As shown in Figure 52, the AD8295 contains a precision instrumentation amplifier, two uncommitted op amps, and a precision resistor array. These components allow many common applications to be wired using simple pin-strapping, directly at the IC. This not only saves printed circuit board (PCB) space but also improves circuit performance because both temperature drift and resistor tolerance errors are reduced. +VS 16 Resistor values can be obtained by referring to Table 9 or by using the following gain equation: RG = 49.4 kΩ G −1 Calculated Gain 1.990 4.984 9.998 19.93 50.40 100 199.4 495 991 Table 9. Gains Achieved Using 1% Resistors 1% Standard Table Value of RG 49.9 kΩ 12.4 kΩ 5.49 kΩ 2.61 kΩ 1.00 kΩ 499 Ω 249 Ω 100 Ω 49.9 Ω OUT 15 A2 +IN 14 A2 –IN 13 12 –IN 1 AD8295 A2 A2 OUT RG 2 IA RG 3 A1 +IN 4 5 6 7 11 A1 +IN 10 A1 R1 R1 20kΩ R2 20kΩ 8 9 A1 –IN –VS REF A1 OUT A1 R2 Figure 52. Functional Block Diagram UNCOMMITTED OP AMPS The AD8295 has two uncommitted op amps that can be used independently. These op amps allow simple pin-strapping for many common applications circuits. Op Amp A1 has its inverting input connected to a precision 2:1 voltage divider resistor network. Because this network is internal to the IC, these resistors are closely matched and also track each other, with temperature variations. Op Amp A1 and the associated resistor network can be used to create either a noninverting gain stage of 2 or an inverting gain stage of −1 with excellent gain accuracy and gain drift. Op Amp A2 is a more conventional op amp, with standard inverting and noninverting inputs and an output. The AD8295 defaults to G = 1 when no gain resistor is used. Gain accuracy is a combination of both the RG accuracy and the accuracy listed in the specifications in Table 2, including accuracy over temperature. Gain error and gain drift are kept to a minimum when the gain resistor is not used. 07343-004 Common-Mode Input Voltage Range The AD8295 in-amp architecture applies gain internally and then removes the common-mode voltage. Therefore, internal nodes in the AD8295 experience a combination of both the gained signal and the common-mode signal. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not. Figure 7 through Figure 10 show the allowable common-mode input voltage ranges for various output voltages and supply voltages. If Figure 7 through Figure 10 indicate that internal voltage limiting may be an issue, the common-mode range can be improved by lowering the gain in the instrumentation amplifier by one half and applying a second G = 2 stage. Figure 53 shows how to do this amplification with the internal circuitry of the AD8295, requiring no additional external components. A1 TOTAL GAIN = IN-AMP × 2 +IN RG –IN + IN-AMP – REF INSTRUMENTATION AMPLIFIER Gain Selection The transfer function of the AD8295 is VOUT = G × (VIN+ − VIN−) + VREF where placing a resistor across the RG terminals sets the gain of the AD8295 according to the following equation: + A1 – R2 20kΩ R1 20kΩ A1 OUT G =1+ 49.4 kΩ RG Figure 53. Applying Gain in a Later Stage Allows Wider Input Common-Mode Range Rev. 0 | Page 19 of 28 07343-019 AD8295 Reference Terminal The output voltage of the AD8295 instrumentation amplifier is developed with respect to the potential on the reference terminal. This is useful when the output signal needs to be offset to a precise dc level. The reference pin input can be driven slightly beyond the rails. The REF pin is protected with ESD diodes, and the REF voltage should not exceed either +VS or −VS by more than 0.3 V. For best performance, the source impedance to the REF terminal should be kept below 1 Ω. Additional impedance at the REF terminal can significantly degrade the CMRR of the amplifier. When the reference source has significant output impedance (for example, a resistive voltage divider), buffer the signal before driving the REF pin. Internal Op Amp A1 or A2 can be used for this purpose, as shown in Figure 54. INCORRECT CORRECT Common-Mode Rejection over Frequency The AD8295 has a higher CMRR over frequency than typical in-amps, which gives it greater immunity to disturbances such as line noise and its associated harmonics. The AD8295 pinout and hidden paddle package were designed so that the board designer can take full advantage of this performance with a well-implemented layout. Poor layout can cause some of the common-mode signal to be converted to a differential signal before it reaches the in-amp. Such conversions occur when one input path has a frequency response that is different from the other. To keep CMRR across frequency high, the input source impedance and capacitance of each path should be closely matched. Additional source resistance in the input path (for example, for input protection) should be placed close to the in-amp inputs to minimize their interaction with parasitic capacitance from the PCB traces. Parasitic capacitance at the gain setting pins can also affect CMRR over frequency. The traces to the RG resistor should be kept as short as possible. If the board design has a component at the gain setting pins (for example, a switch or jumper), the part should be chosen so that the parasitic capacitance is as small as possible. AD8295 +VS +VS RA RB REF RA C + RB AD8295 REF OP AMP BUFFER 07343-010 Unused Op Amps When not in use, the internal op amps should be connected in a unity-gain configuration, with the noninverting input connected to a bias point in the input range of the op amp. These connections ensure that the AD8295 op amp uses minimum power and does not disturb the internal power supplies of the AD8295. These connections are shown as dotted lines in several of the applications figures. Figure 54. Driving the Reference Pin Noise at the reference feeds directly to the output. Therefore, in Figure 54, Capacitor C is added to filter out any high frequency noise on the positive power supply line. For very clean supplies, the capacitor may not be needed. The filter frequency is a tradeoff between noise rejection and start-up time, and is given by the following equation: Reference The output voltage of the instrumentation amplifier section of the AD8295 is developed with respect to the potential on the reference terminal (REF); care should be taken to tie the REF pin to the appropriate local ground. f LOWPASS = 1 RR 2π C A B RA + RB LAYOUT The AD8295 is a high precision device. To ensure optimum performance at the PCB level, care must be taken in the board layout. The AD8295 pins are arranged in a logical manner to aid in this task. Unlike most LFCSP packages, the AD8295 package was designed without the thermal pad to allow routes and vias directly beneath the chip. Careful board layout maximizes system performance. Traces from the gain setting resistor to the RG pins should be kept as short as possible to minimize parasitic inductance. To ensure the most accurate output, the trace from the REF pin should either be connected to the local ground of the AD8295 or to a voltage that is referenced to the local ground of the AD8295. Rev. 0 | Page 20 of 28 AD8295 Power Supplies A stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. See the PSRR performance curves in Figure 14 and Figure 15 for more information. A 0.1 μF capacitor should be placed as close as possible to each supply pin. An additional capacitor, a 10 μF tantalum for the lower frequencies, can be used farther away from the IC. In most cases, the 10 μF bypass capacitor can be shared by other integrated circuits on the same PCB. +VS INCORRECT +VS CORRECT +VS AD8295 IN-AMP REF AD8295 IN-AMP REF –VS TRANSFORMER +VS –VS TRANSFORMER +VS 0.1µF +IN RG 10µF AD8295 IN-AMP REF AD8295 IN-AMP REF 10MΩ AD8295 IN-AMP –IN REF VOUT LOAD –VS THERMOCOUPLE +VS 07343-005 –VS THERMOCOUPLE +VS C 0.1µF –VS 10µF C Figure 55. Supply Decoupling, REF, and Output Referred to Local Ground AD8295 C IN-AMP REF fHIGH-PASS = 2π1 RC C R AD8295 IN-AMP REF INPUT PROTECTION All terminals of the AD8295 are protected against ESD by diodes at the inputs. If voltages beyond the supplies are anticipated, resistors should be placed in series with the inputs to limit the current. Resistors should be chosen so that current does not exceed 6 mA into the internal ESD diodes in the overload condition. These resistors can be the same as those used for RFI protection. (See the RF Interference section for more information.) For applications where the AD8295 encounters extreme overload voltages, as in cardiac defibrillators, external series resistors and low leakage diode clamps, such as BAV199Ls, FJH1100s, or SP720s can be used. R 07343-006 –VS CAPACITIVELY COUPLED –VS CAPACITIVELY COUPLED Figure 56. Creating an Input Bias Current Return Path RF INTERFERENCE RF interference is often a problem when amplifiers are used in applications where there are strong RF signals. The precision circuits in the AD8295 can rectify the RF signals so that they appear as a dc offset voltage error. To avoid this rectification, place a low-pass filter before the input. Figure 57 shows such a network in front of the instrumentation amplifier. The filter limits both the differential and common-mode bandwidth, as shown in the following equations: INPUT BIAS CURRENT RETURN PATH The input bias currents of the AD8295 must have a return path to common. When the source, such as a thermocouple, cannot provide a return current path, one should be created, as shown in Figure 56. Otherwise, the input currents charge up the input capacitance until the in-amp is turned off or saturated. f FILTER (Diff ) = f FILTER (CM ) = where CD ≥ 10CC. 1 2πR(2C D + C C ) 1 2πRC C Rev. 0 | Page 21 of 28 AD8295 +VS 0.1µF CC R 4.02kΩ CD R 4.02kΩ CC 1nF 0.1µF –VS 10µF –IN 10nF RG 1nF +IN 10µF +VS 0.1µF +VS 16 15 OUT 14 A2 +IN 13 A2 –IN 12 –INPUT –IN 1 AD8295 A2 A2 OUT AD8295 IN-AMP REF VOUT RG 2 11 A1 +IN VREF INPUT A1 R1 +OUT A1 –IN IA RG 3 10 A1 07343-007 R1 20kΩ R2 20kΩ 9 +INPUT +IN 4 5 6 7 8 Figure 57. RFI Suppression –VS 0.1µF –VS REF A1 OUT A1 R2 –OUT Lower cutoff frequencies improve RFI robustness. Accuracy of the CC capacitors is important, because any mismatch between the R × CC at the positive input and the R × CC at the negative input degrades the CMRR of the AD8295. Keeping CD at least 10 times larger than CC is recommended. NOTES 1. CONNECT AS SHOWN IF A2 IS NOT BEING USED. Figure 59. Minimum Component Connections for Differential Output DIFFERENTIAL OUTPUT The AD8295 can be pin-strapped to provide a differential output; the simplified schematic is shown in Figure 58 and the full pin connection is shown in Figure 59. This configuration uses the instrumentation amplifier to maintain the differential voltage, while the op amp maintains the common-mode voltage. Because the in-amp precisely controls the output relative to its reference pin, this circuit has the same excellent dc performance as the single-ended output configuration. The transfer function for the differential and common-mode outputs are as follows: VDIFF_OUT = VOUT+ − VOUT− = G × (VIN+ − VIN−) VCM_OUT = (VOUT+ + VOUT−)/2 = VREF where: G =1+ 49.4 kΩ RG An alternative differential output configuration, which also requires no external components, is shown in Figure 60. Unlike the previous circuit, this configuration uses an inverting op amp configuration to double the gain from the instrumentation amplifier. Because this configuration requires less gain from the instrumentation amplifier, it can have a wider frequency response and a wider input common-mode range vs. output voltage. However, because it does not take advantage of feedback at the reference pin of the instrumentation amplifier, dc performance includes the errors from the op amp and the resistor network. When using the internal precision components of the AD8295, these errors have a minimal effect on overall accuracy. This configuration is not specified in this data sheet. +IN RG –IN + IN-AMP – REF R1 20kΩ R2 20kΩ +OUT – A1 + –OUT 07343-043 This configuration is fully specified (see Table 2, Figure 49, and Figure 50). DC performance is the same as for the single-ended configuration; ac performance is slightly different. +IN + IN-AMP –IN – REF 20kΩ VREF INPUT +OUT VREF INPUT Figure 60. Alternative Differential Output Configuration – 20kΩ A1 + –OUT Figure 58. Differential Output Using an Op Amp 07343-018 Rev. 0 | Page 22 of 28 07343-008 AD8295 APPLICATIONS INFORMATION CREATING A REFERENCE VOLTAGE AT MIDSCALE A reference voltage other than ground is often useful, for example, when driving a single-supply ADC. Creating a reference voltage derived from a voltage divider is straightforward with the AD8295 (see Figure 61). In this configuration, Op Amp A2 is used to provide a buffered VS/2 reference for the in-amp section. This configuration is very similar to the one described in the Reference Terminal section. Note that the internal resistors of Op Amp A1 are not used to provide VS/2. Instead, external 1% (or better) resistors are used. Because the negative input of Op Amp A1 is permanently connected to the junction of internal resistors R1 and R2, Op Amp A1 operates as a low voltage clamp, preventing the resistor string from providing a convenient VS/2 voltage. Noise at the reference feeds directly to the output, so if the reference voltage is derived from a noisy source, filtering is required. In Figure 61, Capacitor C1 has been added to filter out high frequency noise on the positive power supply line. The 10 uF capacitor and the 100 kΩ resistors shown in Figure 61 roll off noise starting at 0.3 Hz. The filter frequency is a tradeoff between noise rejection and start-up time. +VS 100kΩ OUTPUT +VS 0.1µF +VS 16 15 HIGH ACCURACY G = −1 CONFIGURATION WITH LOW-PASS FILTER The circuit in Figure 62 uses Op Amp A1 and the resistor string to provide a precise G = −1 configuration. Because no external resistors are used to set the gain, gain accuracy and gain drift depend only on the internally matched resistors, yielding excellent performance. Adding a capacitor across Resistor R2 is a simple way to provide a single-pole low-pass filter that rolls off at 20 dB per decade. This capacitor is shown as C1 in Figure 62. A2 +IN A2 –IN 12 +VS 16 15 OUT 14 13 –INPUT –IN 1 AD8295 A2 A2 OUT VREF BUFFERED RG 2 IA RG 3 A1 +INPUT +IN 4 5 6 7 11 VREF INPUT A1 R1 10 R1 20kΩ R2 20k Ω 8 9 A1 –IN –VS VREF INPUT A1 OUT A1 R2 C1 07343-011 100k Ω C1 10µF NOTES 1. fLOW PASS = 1/(2π 20kΩ C1). LP FILTERED OUTPUT OUT 14 A2 +IN 13 A2 –IN A2 OUT A1 +IN Figure 62. Single-Pole Output Filter Using a Single External Capacitor –INPUT –IN 1 AD8295 A2 12 RG 2 11 IA RG 3 10 VS/2 BUFFERED A1 R1 A1 –IN If the connections to Pin 10 and Pin 11 in Figure 62 are changed so that Pin 10 connects to ground and Pin 11 connects to the in-amp output, the result is a G = 2 circuit, also with excellent gain accuracy and drift. In the G = 2 configuration, Capacitor C1 lowers the gain from 2 to 1 at higher frequencies. A1 +INPUT +IN 4 5 6 7 R1 20kΩ R2 20kΩ 8 9 Figure 61. Single-Supply Connection with Buffered Reference 07343-009 REF A1 OUT A1 R2 Rev. 0 | Page 23 of 28 AD8295 2-POLE SALLEN-KEY FILTER Figure 63 shows the in-amp output section of the AD8295 being low-pass filtered using a 2-pole Sallen-Key filter. The filter section consists of Op Amp A2, External Resistors R1 and R2, as well as Capacitors C1 and C2. Resistor R3 compensates for input offset current errors and is equal to the parallel combination of R1 and R2. The ratio of capacitance between C1 and C2 sets the filter quality factor, Q. For most applications, a filter Q of 0.5 to 0.7 provides a good trade-off between performance and stability. High Q, non-polarized capacitors, such as NPO ceramic, should be used. The exact pole frequencies are dependent on the tolerance of the resistors and capacitors used. The design equations for a Sallen-Key filter can be greatly simplified if the resistors and capacitors are made equal. When C1 = C2 and R1 = R2, Q is 0.5 and the design equation simplifies to f = 1/(2πRC) where R is in ohms and C is in farads. For example, with R1 = R2 = 10 kΩ, and C1 = C2 = 2.2 nF, f = 7.2 kHz When C1 is not equal to C2 and R1 is not equal to R2, the values of Q and the cutoff frequency are calculated as follows: Q= f= R1 R2 C1 C 2 C 2(R1 + R2) 1 2π R1 R2 C1 C2 +VS 0.1µF +VS 16 15 AC-COUPLED INSTRUMENTATION AMPLIFIER The circuit in Figure 64 provides a one-pole high-pass filter, using only one external capacitor. At low frequencies, Capacitor C1 has a high impedance, thus operating Op Amp A1 at high gain (G = XC/20 kΩ). Because of its high gain, Op Amp A1 is able to drive the in-amp reference pin until it forces the output of the in-amp to 0 V. Therefore, no signal appears at the circuit output. At higher frequencies, the gain of Op Amp A1 drops and the op amp is no longer able to maintain the in-amp output at 0 V. Therefore, at frequencies above the RC filter bandwidth, the in-amp operates in a normal manner, and the signal appears at the output. The 3 dB corner frequency is set by Internal Resistor R1 and External Capacitor C1 as follows: f = 1/((2π × 20 kΩ) × C1) The precision of R1 (better than 0.2%) means that the filter bandwidth depends mainly on the tolerance of Capacitor C1. At low frequencies, Op Amp A1 drives the appropriate voltage on the reference pin to null out the original signal. Voltage supplies should be chosen so that Op Amp A1 has enough output headroom to produce the nulling voltage. OUTPUT +VS 16 OUT 15 14 A2 +IN 13 A2 –IN –INPUT –IN 1 AD8295 A2 12 A2 OUT A1 +IN R2 R1 OUT C2 A2 +IN RG C1 R3 A2 –IN 12 2 11 IA RG A1 R1 3 10 14 13 –INPUT –IN 1 AD8295 A2 A2 OUT LP FILTERED OUTPUT +INPUT A1 +IN 4 5 6 7 R1 20kΩ R2 20kΩ 8 A1 –IN 9 2 11 –VS REF A1 OUT A1 R2 C1 IA RG 3 10 A1 +IN +INPUT 4 5 6 7 R1 20kΩ R2 20kΩ 8 9 A1 R1 A1 –IN Figure 64. AC-Coupled Connection –VS 0.1µF –VS REF Figure 63. 2-Pole Sallen-Key Filter Rev. 0 | Page 24 of 28 07343-012 A1 OUT A1 R2 07343-015 RG A1 +IN AD8295 DRIVING DIFFERENTIAL ADCs Figure 65 shows how to configure the AD8295 to drive a differential ADC. The circuit shown uses very little board space and consumes little power. With the AD7690, this configuration gives excellent dc performance and a THD of 83 dB (10 kHz input). For applications that need better distortion performance, a dedicated ADC driver, such as the ADA4941-1 or ADA4922-1 is recommended. The 500 Ω resistors and the 2.2 nF capacitors form a low-pass, antialiasing filter at 144 kHz. The four elements of the filter also prevent the switching transients produced by a typical SAR converter from destabilizing the AD8295. The capacitors provide charge to the switched capacitor front end of the ADC, and the resistors shield the AD8295 from driving any sharp current changes. If the application requires a lower frequency antialiasing filter than the one shown, increasing the capacitor values produces much better distortion results than increasing the resistor values. The 500 Ω resistors also give the ADC protection against overvoltage. Because the AD8295 runs on wider supply voltages than a typical ADC, there is a possibility of overdriving some converters. This is not an issue with a PulSAR® ADC, such as the AD7690, because its input can handle a 130 mA overdrive, which is much higher than the short-circuit limit of the AD8295. However, other converters have less robust inputs and may benefit from the resistive protection. +7V +7V 0.1µF +VS 16 15 0.1µF A2 +IN A2 –IN 12 OUT 14 13 ADR435 A2 OUT +5V A1 +IN +2.5V A1 R1 +OUT A1 –IN 2.2nF 10kΩ 10kΩ 500Ω 0.1µF +5V 0.1µF –INPUT –IN 1 AD8295 A2 RG 2 11 IA RG 3 10 IN+ VDD A1 +IN +INPUT 4 5 6 7 R1 20kΩ R2 20k Ω 8 9 AD7690 2.2nF –OUT 500Ω REF IN– GND +5V + 10µF 07343-014 –VS 0.1µF –7V REF A1 OUT A1 R2 Figure 65. Driving a Differential ADC Rev. 0 | Page 25 of 28 AD8295 OUTLINE DIMENSIONS 4.00 BSC SQ 0.60 MAX 13 12 16 1 0.60 MAX PIN 1 INDICATOR 3.75 BCS SQ 0.65 BSC 1.95 REF SQ 9 8 5 4 TOP VIEW 0.80 MAX 0.65 TYP 0.75 0.60 0.50 BOTTOM VIEW 1.00 0.85 0.80 SEATING PLANE 12° MAX 0.35 0.30 0.25 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 040908-A COMPLIANT TO JEDEC STANDARDS MO-263-VBBC Figure 66. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad, with Hidden Paddle CP-16-19 Dimensions shown in millimeters ORDERING GUIDE Model AD8295ACPZ-R7 1 AD8295ACPZ-RL1 AD8295ACPZ-WP1 AD8295BCPZ-R71 AD8295BCPZ-RL1 AD8295BCPZ-WP1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 16-Lead LFCSP_VQ, 7-Inch Tape and Reel 16-Lead LFCSP_VQ, 13-Inch Tape and Reel 16-Lead LFCSP_VQ, Waffle Pack 16-Lead LFCSP_VQ, 7-Inch Tape and Reel 16-Lead LFCSP_VQ, 13-Inch Tape and Reel 16-Lead LFCSP_VQ, Waffle Pack Package Option CP-16-19 CP-16-19 CP-16-19 CP-16-19 CP-16-19 CP-16-19 Z = RoHS Compliant Part. Rev. 0 | Page 26 of 28 AD8295 NOTES Rev. 0 | Page 27 of 28 AD8295 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07343-0-10/08(0) Rev. 0 | Page 28 of 28