AD8307ARZ-REEL

Low Cost, DC to 500 MHz, 92 dB Logarithmic Amplifier AD8307 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM Complete multistage logarithmic amplifier 92 dB dynamic range: −75 dBm to +17 dBm to −90 dBm using matching network Single supply of 2.7 V minimum at 7.5 mA typical DC to 500 MHz operation, ±1 dB linearity Slope of 25 mV/dB, intercept of −84 dBm Highly stable scaling over temperature Fully differential dc-coupled signal path 100 ns power-up time, 150 μA sleep current AD8307 7.5mA VPS 7 INP 8 INM 1 BAND GAP REFERENCE AND BIASING SIX 14.3dB 900MHz AMPLIFIER STAGES +INP 3 NINE DETECTOR CELLS SPACED 14.3dB COM 2 5 INT 2 2µA /dB 4 OUT 3 OFS 12.5kΩ COM INPUT-OFFSET COMPENSATION LOOP 01082-001 APPLICATIONS ENB MIRROR 1.1kΩ –INP 6 Conversion of signal level to decibel form Transmitter antenna power measurement Receiver signal strength indication (RSSI) Low cost radar and sonar signal processing Network and spectrum analyzers (to 120 dB) Signal level determination down to 20 Hz True decibel ac mode for multimeters Figure 1. GENERAL DESCRIPTION The AD8307 is the first logarithmic amplifier made available in an 8-lead SOIC_N package. It is a complete 500 MHz monolithic demodulating logarithmic amplifier based on the progressive compression (successive detection) technique, providing a dynamic range of 92 dB to ±3 dB law conformance and 88 dB to a tight ±1 dB error bound at all frequencies up to 100 MHz. The AD8307 is extremely stable and easy to use, requiring no significant external components. A single-supply voltage of 2.7 V to 5.5 V at 7.5 mA is needed. A fast acting CMOScompatible control pin can disable the AD8307 to a standby current of 150 μA. Table 1. Next Generation Upgrades for the AD8307 Device No. AD8310 ADL5513 AD8309 Product Description 15 ns Response Time, Buffered Output Lower Input Range (80 dB), Operation to 4 GHz, Higher Power Consumption Higher Input Range (100 dB), Limiter Output The AD8307 operates over the industrial temperature range of −40°C to +85°C and is available in an 8-lead SOIC package and an 8-lead PDIP. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©1997–2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8307 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Enable Interface .......................................................................... 14  Applications ....................................................................................... 1  Input Interface ............................................................................ 14  Functional Block Diagram .............................................................. 1  Offset Interface ........................................................................... 15  General Description ......................................................................... 1  Output Interface ......................................................................... 15  Revision History ............................................................................... 2  Theory of Operation ...................................................................... 17  Specifications..................................................................................... 3  Basic Connections ...................................................................... 17  Absolute Maximum Ratings............................................................ 4  Input Matching ........................................................................... 18  ESD Caution .................................................................................. 4  Narrow-Band Matching ............................................................ 18  Pin Configuration and Function Descriptions ............................. 5  Slope and Intercept Adjustments ............................................. 19  Typical Performance Characteristics ............................................. 6  Applications Information .............................................................. 20  Log Amp Theory .............................................................................. 9  Buffered Output.......................................................................... 20  Progressive Compression .......................................................... 10  Four-Pole Filter ........................................................................... 20  Demodulating Log Amps .......................................................... 11  1 μW to 1 kW 50 Ω Power Meter ............................................. 21  Intercept Calibration .................................................................. 12  Measurement System with 120 dB Dynamic Range .............. 21  Offset Control ............................................................................. 12  Operation at Low Frequencies.................................................. 22  Extension of Range ..................................................................... 13  Outline Dimensions ....................................................................... 23  Interfaces .......................................................................................... 14  Ordering Guide .......................................................................... 24  REVISION HISTORY 12/2019—Rev. E to Rev. F Changes to Ordering Guide .......................................................... 24 9/2015—Rev. D to Rev. E Changes to General Description Section ...................................... 1 Added Table 1; Renumbered Sequentially .................................... 1 6/2003—Rev. A to Rev. B Renumbered TPCs and Figures ........................................ Universal Changes to Ordering Guide .............................................................3 Changes to Figure 24...................................................................... 17 Deleted Evaluation Board Information ....................................... 18 Updated Outline Dimensions ....................................................... 19 7/2008—Rev. C to Rev. D Deleted DC-Coupled Applications Section ................................ 22 Deleted Operation Above 500 MHz Section .............................. 23 Updated Outline Dimensions ....................................................... 23 10/2006—Rev. B to Rev. C Updated Format .................................................................. Universal Changes to Table 1 ............................................................................ 3 Changes to Table 3 ............................................................................ 5 Changes to Offset Interface ........................................................... 15 Changes to Output Interface ......................................................... 15 Updated captions to Outline Dimensions ................................... 24 Changes to Ordering Guide .......................................................... 24 Rev. F | Page 2 of 24 Data Sheet AD8307 SPECIFICATIONS VS = 5 V, TA = 25°C, RL ≥ 1 MΩ, unless otherwise noted. Table 2. Parameter GENERAL CHARACTERISTICS Input Range (±3 dB Error) Input Range (±1 dB Error) Logarithmic Conformance Logarithmic Slope vs. Temperature Logarithmic Intercept vs. Temperature Input Noise Spectral Density Operating Noise Floor Output Resistance Internal Load Capacitance Response Time Upper Usable Frequency Lower Usable Frequency AMPLIFIER CELL CHARACTERISTICS Cell Bandwidth Cell Gain INPUT CHARACTERISTICS DC Common-Mode Voltage Common-Mode Range DC Input Offset Voltage3 Incremental Input Resistance Input Capacitance Bias Current POWER INTERFACES Supply Voltage Supply Current Disabled Conditions Min From noise floor to maximum input From noise floor to maximum input f ≤ 100 MHz, central 80 dB f = 500 MHz, central 75 dB Unadjusted1 Sine amplitude, unadjusted2 Equivalent sine power in 50 Ω Inputs shorted RSOURCE = 50 Ω/2 Pin 4 to ground 23 23 −87 −88 10 Small signal, 10% to 90%, 0 mV to 100 mV, CL = 2 pF Large signal, 10% to 90%, 0 V to 2.4 V, CL = 2 pF AC-coupled input −3 dB Typ 92 88 ±0.3 ±0.5 25 20 −84 1.5 −78 12.5 3.5 400 500 500 10 Max ±1 27 27 −77 −76 15 900 14.3 AC-coupled input Either input (small signal) RSOURCE ≤ 50 Ω Drift Differential Either pin to ground Either input −0.3 3.2 +1.6 50 0.8 1.1 1.4 10 2.7 VENB ≥ 2 V VENB ≤ 1 V 8 150 1 Unit dB dB dB dB mV/dB mV/dB μV dBm dBm nV/√Hz dBm kΩ pF ns ns MHz Hz MHz dB 25 V V μV μV/°C kΩ pF μA 5.5 10 750 V mA μA VS − 1 500 This can be adjusted downward by adding a shunt resistor from the output to ground. A 50 kΩ resistor reduces the nominal slope to 20 mV/dB. This can be adjusted in either direction by a voltage applied to Pin 5, with a scale factor of 8 dB/V. 3 Normally nulled automatically by internal offset correction loop and can be manually nulled by a voltage applied between Pin 3 and ground; see the Applications Information section. 2 Rev. F | Page 3 of 24 AD8307 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Input Voltage (Pin 1 and Pin 8) Storage Temperature Range (N, R) Ambient Temperature Range, Rated Performance Industrial, AD8307AN, AD8307AR Lead Temperature Range (Soldering, 10 sec) Ratings 7.5 V VSUPPLY −65°C to +125°C −40°C to +85°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION 300°C Rev. F | Page 4 of 24 Data Sheet AD8307 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INM 1 8 INP COM 2 7 VPS AD8307 6 ENB TOP VIEW OUT 4 (Not to Scale) 5 INT 01082-002 OFS 3 Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic INM COM OFS OUT INT ENB VPS INP Description Signal Input Minus Polarity. Normally at VPOS/2. Common Pin (Usually Grounded). Offset Adjustment. External capacitor connection. Logarithmic (RSSI) Output Voltage. ROUT = 12.5 kΩ. Intercept Adjustment, ±3 dB. (See the Slope and Intercept Adjustments section.) CMOS-Compatible Chip Enable. Active when high. Positive Supply: 2.7 V to 5.5 V. Signal Input Plus Polarity. Normally at VPOS/2. Due to the symmetrical nature of the response, there is no special significance to the sign of the two input pins. DC resistance from INP to INM = 1.1 kΩ. Rev. F | Page 5 of 24 AD8307 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 8 3 7 1 5 ERROR (dB) 4 3 TEMPERATURE ERROR @ +85°C 0 TEMPERATURE ERROR @ +25°C –1 TEMPERATURE ERROR @ –40°C 2 –2 0 1.0 01082-003 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 –3 –80 2.0 01082-006 SUPPLY CURRENT (mA) 2 6 –60 VENB (V) –40 –20 0 20 INPUT LEVEL (dBm) Figure 3. Supply Current vs. VENB (5 V) Figure 6. Log Conformance vs. Input Level (dBm) at −40°C, +25°C, and +85°C 3 8 INPUT FREQUENCY 10MHz 6 2 5 INPUT FREQUENCY 100MHz VOUT (V) 4 3 1 INPUT FREQUENCY 300MHz 2 INPUT FREQUENCY 500MHz 0 1.0 01082-004 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 0 –80 2.0 01082-007 SUPPLY CURRENT (mA) 7 –60 3 1.5 2 1.0 0 20 0.5 ERROR (dB) CFO VALUE = 0.01µF 0 –0.5 –1 INPUT FREQUENCY = 100MHz CFO VALUE = 1µF CFO VALUE = 0.1µF –1.0 01082-005 –2 –60 –40 –20 0 –1.5 –80 20 01082-008 ERROR (dB) INPUT FREQUENCY = 300MHz 0 –3 –80 –20 Figure 7. VOUT vs. Input Level (dBm) at Various Frequencies Figure 4. Supply Current vs. VENB (3 V) 1 –40 INPUT LEVEL (dBm) VENB (V) –60 –40 –20 0 20 INPUT LEVEL (dBm) INPUT LEVEL (dBm) Figure 5. Log Conformance vs. Input Level (dBm), 100 MHz and 300 MHz Rev. F | Page 6 of 24 Figure 8. Log Conformance vs. CFO Values at 1 kHz Input Frequency Data Sheet AD8307 3.0 3 100MHz INT PIN = 3.0V 10MHz, INT = –96.52dBm 2.5 2 1 ERROR (dB) INT PIN = 4.0V 10MHz, INT = –87.71dBm 1.5 NO CONNECT ON INT 10MHz, INT = –82.90dBm 1.0 +INPUT 0 –1 0.5 –INPUT 01082-009 –2 0 –80 –70 –60 –50 –40 –30 –20 –10 0 10 01082-012 VOUT (V) 2.0 –3 –80 20 –60 INPUT LEVEL (dBm) 3.0 0 20 3 2 INT VOLTAGE INT = 1.0V, INT = –86dBm 500MHz 1 ERROR (dB) INT VOLTAGE INT NO CONNECT, INT = –71dBm 1.5 1.0 0 –1 0 –80 –70 –60 –50 –40 –30 –20 –10 0 –2 01082-010 INT VOLTAGE INT = 2.0V, INT = –78dBm 0.5 100MHz 01082-013 2.5 VOUT (V) –20 Figure 12. Log Conformance vs. Input Level at 100 MHz Showing Response to Alternative Inputs Figure 9. VOUT vs. Input Level at 5 V Supply; Showing Intercept Adjustment 2.0 –40 INPUT LEVEL (dBm) –3 –90 10 –70 INPUT LEVEL (dBm) –50 –30 –10 10 INPUT LEVEL (dBm) Figure 10. VOUT vs. Input Level at 3 V Supply Using AD820 as Buffer, Gain = +2; Showing Intercept Adjustment Figure 13. Log Conformance vs. Input Level at 100 MHz and 500 MHz; Input Driven Differentially Using Transformer 3 2.5 2 2.0 500MHz 1.0 ERROR (dB) VOUT (V) 1 1.5 100MHz @ –40°C 100MHz @ +25°C 0 100MHz –1 0.5 –60 –40 –20 01082-011 0 –3 –70 20 01082-014 –2 100MHz @ +85°C 0 –80 10MHz –60 –50 –40 –30 –20 –10 0 10 INPUT LEVEL (dBm) INPUT LEVEL (dBm) Figure 11. VOUT vs. Input Level at Three Temperatures (−40°C, +25°C, +85°C) Rev. F | Page 7 of 24 Figure 14. Log Conformance vs. Input Level at 3 V Supply Using AD820 as Buffer, Gain = +2 20 AD8307 Data Sheet 2V VOUT CH 1 CH1 200mV VOUT CH1 CH1 500mV CH1 GND 500ns CH2 2.00V CH2 GND 01082-015 GND INPUT SIGNAL CH2 200ns CH2 1.00V Figure 18. VOUT Rise Time Figure 15. Power-Up Response Time VOUT CH 1 01082-018 VENB CH 2 CH1 500mV CH1 200mV 2.5V INPUT SIGNAL CH2 VENB CH 2 CH2 GND VOUT CH1 01082-016 GND 500ns Figure 19. Large Signal Response Time Figure 16. Power-Down Response Time HP8648B 10MHz REF CLK SIGNAL GENERATOR PULSE MODE IN PULSE VPS = 5.0V MODULATION MODE 0.1µF 1nF RF OUT VPS = 5.0V HP8648B SIGNAL GENERATOR HP8112A PULSE GENERATOR OUT 0.1µF 1nF RF OUT SYNCH OUT NC 8 7 6 8 5 52.3Ω AD8307 3 1nF NC = NO CONNECT TEK P6139A 10x PROBE TRIG HP8112A OUT PULSE GENERATOR NC 5 AD8307 1 4 NC TEK744A SCOPE 2 3 4 NC TRIG 1nF 01082-017 2 6 OUT INM COM OFS OUT INM COM OFS OUT 1 7 EXT TRIG INP VPS ENB INT INP VPS ENB INT 52.3Ω 200ns CH2 1.00V TEK P6204 FET PROBE TEK744A SCOPE NC = NO CONNECT Figure 20. Test Setup for VOUT Pulse Response Figure 17. Test Setup for Power-Up/Power-Down Response Time Rev. F | Page 8 of 24 TRIG 01082-020 CH2 2.00V 01082-019 CH1 GND Data Sheet AD8307 LOG AMP THEORY Logarithmic amplifiers perform a more complex operation than that of classical linear amplifiers, and their circuitry is significantly different. A good grasp of what log amps do and how they work can prevent many pitfalls in their application. The essential purpose of a log amp is not to amplify, though amplification is utilized to achieve the function. Rather, it is to compress a signal of wide dynamic range to its decibel equivalent. It is thus a measurement device. A better term may be logarithmic converter, because its basic function is the conversion of a signal from one domain of representation to another via a precise nonlinear transformation. describing VOUT for all values of VIN continues indefinitely in both directions. The dotted line shows that the effect of adding an offset voltage, VSHIFT, to the output is to lower the effective intercept voltage, VX. Exactly the same alteration can be achieved by raising the gain (or signal level) ahead of the log amp by the factor, VSHIFT/VY. For example, if VY is 500 mV per decade (25 mV/dB), an offset of 150 mV added to the output appears to lower the intercept by two-tenths of a decade, or 6 dB. Adding an offset to the output is thus indistinguishable from applying an input level that is 6 dB higher. Logarithmic compression leads to situations that can be confusing or paradoxical. For example, a voltage offset added to the output of a log amp is equivalent to a gain increase ahead of its input. In the usual case where all the variables are voltages, and regardless of the particular structure, the relationship between the variables can be expressed as The log amp function described by Equation 1 differs from that of a linear amplifier in that the incremental gain δVOUT/δVIN is a very strong function of the instantaneous value of VIN, as is apparent by calculating the derivative. For the case where the logarithmic base is δ, VOUT  VY log (VIN /VX ) where: VOUT is the output voltage. VY is the slope voltage; the logarithm is usually taken to base 10 (in which case VY is also the volts per decade). VIN is the input voltage. VX is the intercept voltage. All log amps implicitly require two references, in this example, VX and VY, which determine the scaling of the circuit. The absolute accuracy of a log amp cannot be any better than the accuracy of its scaling references. Equation 1 is mathematically incomplete in representing the behavior of a demodulating log amp, such as the AD8307, where VIN has an alternating sign. However, the basic principles are unaffected, and this can be safely used as the starting point in the analyses of log amp scaling. VOUT 5VY 4VY 3VY VOUT V  Y VIN VIN (1) VSHIFT That is, the incremental gain is inversely proportional to the instantaneous value of the input voltage. This remains true for any logarithmic base, which is chosen as 10 for all decibel related purposes. It follows that a perfect log amp is required to have infinite gain under classical small signal (zero amplitude) conditions. Less ideally, this result indicates that whatever means are used to implement a log amp, accurate response under small signal conditions (that is, at the lower end of the dynamic range) demands the provision of a very high gain bandwidth product. A further consequence of this high gain is that in the absence of an input signal, even very small amounts of thermal noise at the input of a log amp cause a finite output for zero input. This results in the response line curving away from the ideal shown in Figure 21 toward a finite baseline, which can be either above or below the intercept. Note that the value given for this intercept can be an extrapolated value, in which case the output cannot cross zero, or even reach it, as is the case for the AD8307. While Equation 1 is fundamentally correct, a simpler formula is appropriate for specifying the calibration attributes of a log amp like the AD8307, which demodulates a sine wave input. LOWER INTERCEPT 2VY VY VOUT = VSLOPE (PIN – P0) VIN = VX 0dBc VIN = 102VX +40dBc VIN = 104VX +80dBc 01082-021 LOG VIN VOUT = 0 VIN = 10–2VX –40dBc (2) –2VY Figure 21. Ideal Log Amp Function Figure 21 shows the input/output relationship of an ideal log amp, conforming to Equation 1. The horizontal scale is logarithmic and spans a wide dynamic range, shown in Figure 21 as over 120 dB, or six decades. The output passes through zero (the log intercept) at the unique value VIN = VX and ideally becomes negative for inputs below the intercept. In the ideal case, the straight line (3) where: VOUT is the demodulated and filtered baseband (video or RSSI) output. VSLOPE is the logarithmic slope, now expressed in V/dB (typically between 15 mV/dB and 30 mV/dB). PIN is the input power, expressed in decibels relative to some reference power level. P0 is the logarithmic intercept, expressed in decibels relative to the same reference level. The most widely used reference in RF systems is decibels above 1 mW in 50 Ω, written dBm. Note that the quantity (PIN – P0) is Rev. F | Page 9 of 24 Data Sheet just dB. The logarithmic function disappears from the formula because the conversion has already been implicitly performed in stating the input in decibels. This is strictly a concession to popular convention; log amps manifestly do not respond to power (tacitly, power absorbed at the input), but rather to input voltage. The use of dBV (decibels with respect to 1 V rms) is more precise, though still incomplete, because waveform is involved as well. Because most users think about and specify RF signals in terms of power, more specifically, in dBm re: 50 Ω, this convention is used in specifying the performance of the AD8307. PROGRESSIVE COMPRESSION Most high speed, high dynamic range log amps use a cascade of nonlinear amplifier cells (see Figure 22) to generate the logarithmic function from a series of contiguous segments, a type of piecewise linear technique. This basic topology immediately opens up the possibility of enormous gain bandwidth products. For example, the AD8307 employs six cells in its main signal path, each having a small signal gain of 14.3 dB (×5.2) and a −3 dB bandwidth of about 900 MHz. The overall gain is about 20,000 (86 dB) and the overall bandwidth of the chain is some 500 MHz, resulting in the incredible gain bandwidth product (GBW) of 10,000 GHz, about a million times that of a typical op amp. This very high GBW is an essential prerequisite for accurate operation under small signal conditions and at high frequencies. In Equation 2, however, the incremental gain decreases rapidly as VIN increases. The AD8307 continues to exhibit an essentially logarithmic response down to inputs as small as 50 μV at 500 MHz. A A STAGE N–1 A STAGE N A VW 01082-022 VX STAGE 2 A/1 AEK SLOPE = 1 0 EK INPUT 01082-023 SLOPE = A Figure 23. A/1 Amplifier Function Let the input of an N-cell cascade be VIN, and the final output be VOUT. For small signals, the overall gain is simply AN. A six-stage system in which A = 5 (14 dB) has an overall gain of 15,625 (84 dB). The importance of a very high small signal gain in implementing the logarithmic function has been noted; however, this parameter is only of incidental interest in the design of log amps. From this point forward, rather than considering gain, analyze the overall nonlinear behavior of the cascade in response to a simple dc input, corresponding to the VIN of Equation 1. For very small inputs, the output from the first cell is V1 = AVIN. The output from the second cell is V2 = A2 VIN, and so on, up to VN = AN VIN. At a certain value of VIN, the input to the Nth cell, VN − 1, is exactly equal to the knee voltage EK. Thus, VOUT = AEK and because there are N − 1 cells of Gain A ahead of this node, calculate VIN = EK /AN − 1. This unique situation corresponds to the lin-log transition (labeled 1 in Figure 24). Below this input, the cascade of gain cells acts as a simple linear amplifier, whereas for higher values of VIN, it enters into a series of segments that lie on a logarithmic approximation (dotted line). VOUT Figure 22. Cascade of Nonlinear Gain Cells To develop the theory, first consider a scheme slightly different from that employed in the AD8307, but simpler to explain and mathematically more straightforward to analyze. This approach is based on a nonlinear amplifier unit, called an A/1 cell, with the transfer characteristic shown in Figure 23. The local small signal gain δVOUT/δVIN is A, maintained for all inputs up to the knee voltage EK, above which the incremental gain drops to unity. The function is symmetrical: the same drop in gain occurs for instantaneous values of VIN less than –EK. The large signal gain has a value of A for inputs in the range −EK ≤ VIN ≤ +EK, but falls asymptotically toward unity for very large inputs. In logarithmic amplifiers based on this amplifier function, both the slope voltage and the intercept voltage must be traceable to the one reference voltage, EK. Therefore, in this fundamental analysis, the calibration accuracy of the log amp is dependent solely on this voltage. In practice, it is possible to separate the basic references used to determine VY and VX and, in the case of the AD8307, VY is traceable to an on-chip band gap reference, whereas VX is derived from the thermal voltage kT/q and is later temperature corrected. (4A–3) E K 2 3 (3A–2) E K 3 (A–1) E K (2A–1) E K AEK 2 1 RATIO OF A LOG VIN 0 EK/AN–1 EK/AN–2 EK/AN–3 EK/AN–4 01082-024 STAGE 1 OUTPUT AD8307 Figure 24. First Three Transitions Continuing this analysis, the next transition occurs when the input to the N − 1 stage just reaches EK, that is, when VIN = EK/AN − 2. The output of this stage is then exactly AEK, and it is easily demonstrated (from the function shown in Figure 23) that the output of the final stage is (2A − 1)EK (labeled 2 in Figure 24). Thus, the output has changed by an amount (A − 1)EK for a change in VIN from EK/AN − 1 to EK/AN − 2, that is, a ratio change of A. At the next critical point (labeled 3 in Figure 24), the input is again A times larger and VOUT has increased to (3A − 2)EK, that is, by another linear increment of (A − 1)EK. Rev. F | Page 10 of 24 Data Sheet AD8307 Further analysis shows that right up to the point where the input to the first cell is above the knee voltage, VOUT changes by (A − 1)EK for a ratio change of A in VIN. This can be expressed as a certain fraction of a decade, which is simply log10(A). For example, when A = 5, a transition in the piecewise linear output function occurs at regular intervals of 0.7 decade (log10(A), or 14 dB divided by 20 dB). This insight immediately allows the user to write the volts per decade scaling parameter, which is also the scaling voltage, VY, when using base 10 logarithms, as VY  Decades Change in VIN   A  1EK log10 ( A) The intercept voltage can be determined by using two pairs of transition points on the output function (consider Figure 24). The result is A EK ( N  1 / A  1) (5) For the case under consideration, using N = 6, calculate VZ = 4.28 μV. However, be careful about the interpretation of this parameter, because it was earlier defined as the input voltage at which the output passes through zero (see Figure 21). Clearly, in the absence of noise and offsets, the output of the amplifier chain shown in Figure 23 can be zero when, and only when, VIN = 0. This anomaly is due to the finite gain of the cascaded amplifier, which results in a failure to maintain the logarithmic approximation below the lin-log transition (labeled 1 in Figure 24). Closer analysis shows that the voltage given by Equation 5 represents the extrapolated, rather than actual, intercept. DEMODULATING LOG AMPS Log amps based on a cascade of A/1 cells are useful in baseband applications because they do not demodulate their input signal. However, baseband and demodulating log amps alike can be made using a different type of amplifier stage, called an A/0 cell. Its function differs from that of the A/1 cell in that the gain above the knee voltage EK falls to zero, as shown by the solid line in Figure 25. This is also known as the limiter function, and a chain of N such cells are often used to generate hard-limited output in recovering the signal in FM and PM modes. OUTPUT tanh SLOPE = A 0 EK INPUT Figure 25. A/0 Amplifier Functions (Ideal and Tanh) (4) Note that only two design parameters are involved in determining VY, namely, the cell gain A and the knee voltage, EK, while N, the number of stages, is unimportant in setting the slope of the overall function. For A = 5 and EK = 100 mV, the slope would be a rather awkward 572.3 mV per decade (28.6 mV/dB). A well designed log amp has rational scaling parameters. VX  A/0 01082-025 Linear Change in VOUT SLOPE = 0 AEK The AD640, AD606, AD608, AD8307, and various other Analog Devices, Inc., communications products incorporating a logarithmic intermediate frequency (IF) amplifier all use this technique. It becomes apparent that the output of the last stage can no longer provide the logarithmic output because this remains unchanged for all inputs above the limiting threshold, which occurs at VIN = EK/AN − 1. Instead, the logarithmic output is now generated by summing the outputs of all the stages. The full analysis for this type of log amp is only slightly more complicated than that of the previous case. It is readily shown that, for practical purposes, the intercept voltage, VX, is identical to that given in Equation 5, while the slope voltage is VY  AEK log10  A  (6) Preference for the A/0 style of log amp over one using A/1 cells stems from several considerations. The first is that an A/0 cell can be very simple. In the AD8307, it is based on a bipolar transistor differential pair, having resistive loads, RL, and an emitter current source, IE. This exhibits an equivalent knee voltage of EK = 2 kT/q and a small signal gain of A = IERL/EK. The large signal transfer function is the hyperbolic tangent (see the dashed line in Figure 25). This function is very precise, and the deviation from an ideal A/0 form is not detrimental. In fact, the rounded shoulders of the tanh function result in a lower ripple in the logarithmic conformance than that obtained using an ideal A/0 function. An amplifier composed of these cells is entirely differential in structure and can thus be rendered very insensitive to disturbances on the supply lines and, with careful design, to temperature variations. The output of each gain cell has an associated transconductance (gm) cell that converts the differential output voltage of the cell to a pair of differential currents, which are summed simply by connecting the outputs of all the gm (detector) stages in parallel. The total current is then converted back to a voltage by a transresistance stage to generate the logarithmic output. This scheme is depicted in single-sided form in Figure 26. Rev. F | Page 11 of 24 AD8307 Data Sheet A/0 gm A/0 gm A3VIN A/0 gm A4VIN gm variation of EK. Do this by adding an offset with the required temperature behavior. VLIM A/0 gm IOUT 01082-026 A2VIN AVIN VIN Figure 26. Log Amp Using A/0 Stages and Auxiliary Summing Cells The chief advantage of this approach is that the slope voltage can now be decoupled from the knee voltage, EK = 2 kT/q, which is inherently PTAT. By contrast, the simple summation of the cell outputs results in a very high temperature coefficient of the slope voltage given in Equation 6. To do this, the detector stages are biased with currents (not shown), which are rendered stable with temperature. These are derived either from the supply voltage (as in the AD606 and AD608) or from an internal band gap reference (as in the AD640 and AD8307). This topology affords complete control over the magnitude and temperature behavior of the logarithmic slope, decoupling it completely from EK. A further step is needed to achieve the demodulation response, required when the log amp converts an alternating input into a quasi-dc baseband output. This is achieved by altering the gm cells used for summation purposes to also implement the rectification function. Early discrete log amps based on the progressive compression technique used half-wave rectifiers. This made postdetection filtering difficult. The AD640 was the first commercial monolithic log amp to use a full-wave rectifier, a practice followed in all subsequent Analog Devices types. These detectors can be modeled as essentially linear gm cells, but produce an output current independent of the sign of the voltage applied to the input of each cell; that is, they implement the absolute value function. Because the output from the later A/0 stages closely approximates an amplitude symmetric square wave for even moderate input levels (most stages of the amplifier chain operate in a limiting mode), the current output from each detector is almost constant over each period of the input. Somewhat earlier detector stages produce a waveform having only very brief dropouts, whereas the detectors nearest the input produce a low level, almost sinusoidal waveform at twice the input frequency. These aspects of the detector system result in a signal that is easily filtered, resulting in low residual ripple on the output. INTERCEPT CALIBRATION All monolithic log amps from Analog Devices include accurate means to position the intercept voltage, VX (or equivalent power for a demodulating log amp). Using the scheme shown in Figure 26, the basic value of the intercept level departs considerably from that predicted by the simpler analyses given earlier. However, the intrinsic intercept voltage is still proportional to EK, which is PTAT (see Equation 5). Recalling that the addition of an offset to the output produces an effect that is indistinguishable from a change in the position of the intercept, it is possible to cancel the left-right motion of VX resulting from the temperature The precise temperature shaping of the intercept positioning offset results in a log amp having stable scaling parameters, making it a true measurement device, for example, as a calibrated received signal strength indicator (RSSI). In this application, the user is more interested in the value of the output for an input waveform that is invariably sinusoidal. Although the input level can alternatively be stated as an equivalent power, in dBm, be sure to work carefully. It is essential to know the load impedance in which this power is presumed to be measured. In radio frequency (RF) practice, it is generally safe to assume a reference impedance of 50 Ω in which 0 dBm (1 mW) corresponds to a sinusoidal amplitude of 316.2 mV (223.6 mV rms). The intercept can likewise be specified in dBm. For the AD8307, it is positioned at −84 dBm, corresponding to a sine amplitude of 20 μV. It is important to bear in mind that log amps do not respond to power, but to the voltage applied to their input. The AD8307 presents a nominal input impedance much higher than 50 Ω (typically 1.1 kΩ low frequencies). A simple input matching network can considerably improve the sensitivity of this type of log amp. This increases the voltage applied to the input and thus alters the intercept. For a 50 Ω match, the voltage gain is 4.8 and the entire dynamic range moves down by 13.6 dB (see Figure 35). Note that the effective intercept is a function of waveform. For example, a square wave input reads 6 dB higher than a sine wave of the same amplitude and a Gaussian noise input 0.5 dB higher than a sine wave of the same rms value. OFFSET CONTROL In a monolithic log amp, direct coupling between the stages is used for several reasons. First, this avoids the use of coupling capacitors, which typically have a chip area equal to that of a basic gain cell, thus considerably increasing die size. Second, the capacitor values predetermine the lowest frequency at which the log amp can operate; for moderate values, this can be as high as 30 MHz, limiting the application range. Third, the parasitic (backplate) capacitance lowers the bandwidth of the cell, further limiting the applications. However, the very high dc gain of a direct-coupled amplifier raises a practical issue. An offset voltage in the early stages of the chain is indistinguishable from a real signal. For example, if it were as high as 400 μV, it would be 18 dB larger than the smallest ac signal (50 μV), potentially reducing the dynamic range by this amount. This problem is averted by using a global feedback path from the last stage to the first, which corrects this offset in a similar fashion to the dc negative feedback applied around an op amp. The high frequency components of the signal must be removed to prevent a reduction of the HF gain in the forward path. Rev. F | Page 12 of 24 Data Sheet AD8307 In the AD8307, this is achieved by an on-chip filter, providing sufficient suppression of HF feedback to allow operation above 1 MHz. To extend the range below this frequency, an external capacitor can be added. This permits the high-pass corner to be lowered to audio frequencies using a capacitor of modest value. Note that this capacitor has no effect on the minimum signal frequency for input levels above the offset voltage; this extends down to dc (for a signal applied directly to the input pins). The offset voltage varies from part to part; some exhibit essentially stable offsets of under 100 μV without the benefit of an offset adjustment. EXTENSION OF RANGE The theoretical dynamic range for the basic log amp shown in Figure 26 is AN. For A = 5.2 (14.3 dB) and N = 6, it is 20,000 or 86 dB. The actual lower end of the dynamic range is largely determined by the thermal noise floor, measured at the input of the chain of amplifiers. The upper end of the range is extended upward by the addition of top-end detectors. The input signal is applied to a tapped attenuator, and progressively smaller signals are applied to three passive rectifying gm cells whose outputs are summed with those of the main detectors. With care in design, the extension to the dynamic range can be seamless over the full frequency range. For the AD8307, it amounts to a further 27 dB. Therefore, the total dynamic range is theoretically 113 dB. The specified range of 90 dB (−74 dBm to +16 dBm) is for high accuracy and calibrated operation, and includes the low end degradation due to thermal noise and the top end reduction due to voltage limitations. The additional stages are not redundant, but are needed to maintain accurate logarithmic conformance over the central region of the dynamic range, and in extending the usable range considerably beyond the specified range. In applications where log conformance is less demanding, the AD8307 can provide over 95 dB of range. Rev. F | Page 13 of 24 AD8307 Data Sheet INTERFACES The differential current-mode outputs of the nine detectors are summed and then converted to single-sided form in the output stage, nominally scaled 2 μA/dB. The logarithmic output voltage is developed by applying this current to an on-chip 12.5 kΩ resistor, resulting in a logarithmic slope of 25 mV/dB (that is, 500 mV/decade) at the OUT pin. This voltage is not buffered, allowing the use of a variety of special output interfaces, including the addition of postdemodulation filtering. The last detector stage includes a modification to temperature stabilize the log intercept, which is accurately positioned to make optimal use of the full output voltage range available. The intercept can be adjusted using the INT pin, which adds or subtracts a small current to the signal current. tolerance is typically within ±20%. Similarly, the capacitors have a typical tolerance of ±15% and essentially zero temperature or voltage sensitivity. Most interfaces have additional small junction capacitances associated with them due to active devices or ESD protection; these can be neither accurate nor stable. Component numbering in each of these interface diagrams is local. ENABLE INTERFACE The chip enable interface is shown in Figure 28. The currents in the diode-connected transistors control the turn-on and turnoff states of the band gap reference and the bias generator, and are a maximum of 100 μA when Pin 6 is taken to 5 V, under worst-case conditions. Left unconnected, or at a voltage below 1 V, the AD8307 is disabled and consumes a sleep current of under 50 μA; tied to the supply, or at a voltage above 2 V, it is fully enabled. The internal bias circuitry is very fast, typically