High Speed, Video
Difference Amplifier
AD830
Data Sheet
FEATURES
CONNECTION DIAGRAM
1
X2
2
Y1
3
AD830
GM
8
VP
7
OUT
4
GM
6
NC
C
5
VN
NC = NO CONNECT
00881-001
Y2
Figure 1. 8-Lead Plastic PDIP (N), CERDIP (Q), and SOIC (RN) Packages
110
100
90
80
VS = ±15V
70
60
VS = ±5V
50
30
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Differential line receiver
High speed level shifter
High speed in-amp
Differential to single-ended conversion
Resistorless summation and subtraction
High speed analog-to-digital converter
00881-002
40
APPLICATIONS
Figure 2. Common-Mode Rejection Ratio vs. Frequency
Good gain flatness and excellent differential gain of 0.06% and
phase of 0.08° make the AD830 suitable for many video system
applications. Furthermore, the AD830 is suited for general-purpose
signal processing from dc to 10 MHz.
GENERAL DESCRIPTION
9
The AD830 is a wideband, differencing amplifier designed for use
at video frequencies but also useful in many other applications. It
accurately amplifies a fully differential signal at the input and
produces an output voltage referred to a user-chosen level. The
undesired common-mode signal is rejected, even at high
frequencies. High impedance inputs ease interfacing to finite
source impedances and, thus, preserve the excellent commonmode rejection. In many respects, it offers significant
improvements over discrete difference amplifier approaches, in
particular in high frequency common-mode rejection.
6
VS = ±5V
RL = 150Ω
3
CL = 33pF
GAIN (dB)
0
–3
CL = 4.7pF
–6
–9
–12
CL = 15pF
–15
–18
–21
10k
100k
1M
10M
100M
FREQUENCY (Hz)
1G
00881-003
The wide common-mode and differential voltage range of the
AD830 make it particularly useful and flexible in level shifting
applications but at lower power dissipation than discrete solutions.
Low distortion is preserved over the many possible differential and
common-mode voltages at the input and output.
Rev. D
X1
A=1
CMRR (dB)
Differential amplification
Wide common-mode voltage range: +12.8 V to −12 V
Differential voltage: ±2 V
High CMRR: 60 dB at 4 MHz
Built-in differential clipping level: ±2.3 V
Fast dynamic performance
85 MHz unity gain bandwidth
35 ns settling time to 0.1%
360 V/μs slew rate
Symmetrical dynamic response
Excellent video specifications
Differential gain error: 0.06%
Differential phase error: 0.08°
15 MHz (0.1 dB) bandwidth
Flexible operation
High output drive of ±50 mA min
Specified with both ±5 V and ±15 V supplies
Low distortion: THD = −72 dB @ 4 MHz
Excellent DC performance: 3 mV max input
Offset voltage
Figure 3. Closed-Loop Gain vs. Frequency, Gain = +1
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Technical Support
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AD830
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 11
Applications ....................................................................................... 1
Traditional Differential Amplification .................................... 11
Connection Diagram ....................................................................... 1
Problems With the Op Amp Based Approach ....................... 11
General Description ......................................................................... 1
AD830 for Differential Amplification ..................................... 11
Revision History ............................................................................... 2
Advantageous Properties of the AD830 .................................. 11
Specifications..................................................................................... 3
Understanding the AD830 Topology ...................................... 11
Absolute Maximum Ratings ............................................................ 7
Interfacing the Input .................................................................. 12
Maximum Power Dissipation ..................................................... 7
Supplies, Bypassing, and Grounding (Figure 34) ................... 14
Thermal Resistance ...................................................................... 7
AC-Coupled Line Receiver ....................................................... 17
ESD Caution .................................................................................. 7
Outline Dimensions ....................................................................... 19
Typical Performance Characteristics ............................................. 8
Ordering Guide .......................................................................... 20
REVISION HISTORY
1/2018—Rev. C to Rev. D
Change to Table 4 ............................................................................. 7
Changes to Ordering Guide .......................................................... 20
3/2010—Rev. B to Rev. C
Updated Format .................................................................. Universal
Changes to Ordering Guide .......................................................... 20
1/2003—Rev. A to Rev. B.
Updated Ordering Guide ................................................................ 4
Change to Figure 30 ...................................................................... 14
Updated Outline Dimensions ..................................................... 15
Rev. D | Page 2 of 20
Data Sheet
AD830
SPECIFICATIONS
VS = ±15 V, RLOAD = 150 Ω, CLOAD = 5 pF, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
DYNAMIC CHARACTERISTICS
3 dB Small Signal Bandwidth
0.1 dB Gain Flatness
Frequency
Differential Gain Error
Differential Phase Error
Slew Rate
3 dB Large Signal Bandwidth
Settling Time, Gain = +1
Harmonic Distortion
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Offset Voltage
Open-Loop Gain
Gain Error
Peak Nonlinearity, RL = 1 kΩ,
Gain = +1
Input Bias Current
Input Offset Current
INPUT CHARACTERISTICS
Differential Voltage Range
Differential Clipping Level 2
Common-Mode Voltage
Range
CMRR
Input Resistance
Input Capacitance
OUTPUT CHARACTERISTICS
Output Voltage Swing
Short-Circuit Current
Output Current
Conditions
AD830J/AD830A
Min
Typ
Max
Min
AD830S 1
Typ
Gain = +1, VOUT = 100 mV rms
Gain = +1, VOUT = 100 mV rms
75
11
75
11
85
15
0 V to 0.7 V, frequency =
4.5 MHz
0 V to 0.7 V, frequency =
4.5 MHz
2 V step, RL = 500 Ω
4 V step, RL = 500 Ω
Gain = +1, VOUT = 1 V rms
VOUT = 2 V step, to 0.1%
VOUT = 4 V step, to 0.1%
2 V p-p, frequency = 1 MHz
2 V p-p, frequency = 4 MHz
frequency = 10 kHz
Gain = +1
Gain = +1, TMIN − TMAX
DC
RL = 1 kΩ, G = ±1
−1 V ≤ X ≤ +1 V
−1.5 V ≤ X ≤ +1.5 V
−2 V ≤ X ≤ +2 V
VIN = 0 V, 25°C to TMAX
VIN = 0 V, TMIN
VIN = 0 V, TMIN − TMAX
VCM = 0
Pin 1 and Pin 2 inputs only
VDM = ±1 V
DC, Pin 1/Pin 2, ±10 V
DC, Pin 1/Pin 2, ±10 V,
TMIN − TMAX
Frequency = 4 MHz
RL ≥ 1 kΩ
RL ≥ 1 kΩ, ±16.5 VS
Short to ground
RL = 150 Ω
38
85
15
±2.1
−12.0
90
88
55
±12
±13
Unit
MHz
MHz
0.06
0.09
0.06
0.09
%
0.08
0.12
0.08
0.12
Degrees
360
350
45
25
35
−82
−72
27
1.4
±1.5
64
Max
69
±0.1
0.01
0.035
0.15
5
7
0.1
38
±3
±5
64
+12.8
100
60
370
2
+13.8/−13.8
+15.3/−14.7
±80
±50
Rev. D | Page 3 of 20
±1.5
±0.6
0.03
0.07
0.4
10
13
1
±2.0
±2.3
360
350
45
25
35
−82
−72
27
1.4
±2.1
−12.0
90
86
55
±12
±13
±50
69
±0.1
0.01
0.035
0.15
5
8
0.1
V/μs
V/μs
MHz
ns
ns
dBc
dBc
nV/√Hz
pA/√Hz
±3
±7
±0.6
0.03
0.07
0.4
10
17
1
mV
mV
dB
%
% FS
% FS
% FS
μA
μA
μA
+12.8
V
V
V
±2.0
±2.3
100
dB
60
370
2
dB
dB
kΩ
pF
+13.8/−13.8
+15.3/−14.7
±80
V
V
mA
mA
AD830
Parameter
POWER SUPPLIES
Operating Range
Quiescent Current
+PSRR (to VP)
−PSRR (to VN)
PSRR
PSRR
1
2
Data Sheet
Conditions
TMIN – TMAX
DC, G = +1
DC, G = +1
DC, G = +1, ±5 to ±15 VS
DC, G = +1, ±5 to ±15 VS
TMIN − TMAX
AD830J/AD830A
Min
Typ
Max
Min
±4
±4
66
14.5
86
68
71
62
68
See the Standard Military Drawing 5962-9313001MPA for specifications.
Clipping level function on X channel only.
Rev. D | Page 4 of 20
±16.5
17
AD830S 1
Typ
66
14.5
86
68
71
60
68
Max
Unit
±16.5
17
V
mA
dB
dB
dB
dB
Data Sheet
AD830
VS = ±5 V, RLOAD = 150 Ω, CLOAD = 5 pF, TA = +25°C, unless otherwise noted.
Table 2.
AD830J/AD830A
Parameter
DYNAMIC CHARACTERISTICS
3 dB Small Signal Bandwidth
0.1 dB Gain Flatness Frequency
Differential Gain Error
Differential Phase Error
Slew Rate, Gain = +1
3 dB Large Signal Bandwidth
Settling Time
Harmonic Distortion
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Offset Voltage
Open-Loop Gain
Unity Gain Accuracy
Peak Nonlinearity, RL= 1 kΩ
Input Bias Current
Input Offset Current
INPUT CHARACTERISTICS
Differential Voltage Range
Differential Clipping Level 2
Common-Mode Voltage Range
CMRR
Input Resistance
Input Capacitance
OUTPUT CHARACTERISTICS
Output Voltage Swing
Short-Circuit Current
Output Current
Conditions
Min
Gain = +1, VOUT = 100 mV rms
Gain = +1, VOUT = 100 mV rms
0 V to 0.7 V, frequency = 4.5 MHz,
Gain = +2
0 V to 0.7 V, frequency = 4.5 MHz,
Gain = +2
2 V step, RL = 500 Ω
4 V step, RL = 500 Ω
Gain = +1, VOUT = 1 V rms
VOUT = 2 V step, to 0.1%
VOUT = 4 V step, to 0.1%
2 V p-p, frequency = 1 MHz
2 V p-p, frequency = 4 MHz
Frequency = 10 kHz
35
5
Gain = +1
Gain = +1, TMIN − TMAX
DC
RL = 1 kΩ
−1 V ≤ X ≤ +1 V
−1.5 V ≤ X ≤ +1.5 V
−2 V ≤ X ≤ +2 V
VIN = 0 V, 25°C to TMAX
VIN = 0 V, TMIN
VIN = 0 V, TMIN − TMAX
60
VCM = 0
Pin 1 and Pin 2 inputs only
VDM = ±1 V
DC, Pin 1/Pin 2, +4 V to −2 V
DC, Pin 1/Pin 2, +4 V to −2 V,
TMIN − TMAX
Frequency = 4 MHz
RL ≥ 150 Ω
RL ≥ 150 Ω, ±4 VS
Short to ground
30
±2.0
−2.0
90
88
55
±3.2
±2.2
±40
Rev. D | Page 5 of 20
Typ
Max
40
6.5
AD830S 1
Min
35
5
Typ
Max
40
6.5
Units
MHz
MHz
0.14
0.18
0.14
0.18
%
0.32
210
240
36
35
48
−69
−56
27
1.4
0.4
0.32
210
240
36
35
48
−69
−56
27
1.4
0.4
Degrees
V/μs
V/μs
MHz
ns
ns
dBc
dBc
nV/√Hz
pA/√Hz
±1.5
±3
±4
±1.5
±3
±5
mV
mV
dB
%
% FS
% FS
% FS
μA
μA
μA
65
±0.1
0.01
0.045
0.23
5
7
0.1
30
60
±0.6
0.03
0.07
0.4
10
13
1
±2.0
±2.2
+2.9
100
60
370
2
±3.5
−2.4/+2.7
−55/+70
±2.0
−2.0
90
86
55
±3.2
±2.2
±40
65
±0.1
0.01
0.045
0.23
5
8
0.1
±0.6
0.03
0.07
0.4
10
17
1
±2.0
±2.2
100
V
V
V
dB
60
370
2
dB
dB
kΩ
pF
+2.9
±3.5
−2.4/+2.7
−55/+70
V
V
mA
mA
AD830
Data Sheet
AD830J/AD830A
Parameter
POWER SUPPLIES
Operating Range
Quiescent Current
+PSRR (to VP)
−PSRR (to VN)
PSRR (Dual Supply)
PSRR (Dual Supply)
1
2
Conditions
Min
Typ
±4
TMIN − TMAX
DC, G = +1, offset
DC, G = +1, Offset
DC, G = +1, ±5 to ±15 VS
DC, G = +1, ±5 to ±15 VS
TMIN − TMAX
66
13.5
86
68
71
62
68
See Standard Military Drawing 5962-9313001MPA for specifications.
Clipping level function on X channel only.
Rev. D | Page 6 of 20
AD830S 1
Max
Min
±16.5
16
±4
Typ
66
13.5
86
68
71
60
68
Max
Units
±16.5
16
V
mA
dB
dB
dB
dB
Data Sheet
AD830
MAXIMUM POWER DISSIPATION
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
Internal Power Dissipation
Rating
±18 V
Observe derating
curves
Observe derating
curves
±VS
±VS
−65°C to +150°C
−65°C to +125°C
−65°C to +125°C
Output Short-Circuit Duration
Common-Mode Input Voltage
Differential Input Voltage
Storage Temperature Range (Q)
Storage Temperature Range (N)
Storage Temperature Range (RN)
Operating Temperature Range
AD830J
AD830A
AD830S
Lead Temperature Range (Soldering 60 sec)
0°C to +70°C
−40°C to +85°C
−55°C to +125°C
300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
The maximum power that can be safely dissipated by the
AD830 is limited by the associated rise in junction temperature.
For the plastic packages, the maximum safe junction
temperature is 145°C. For the CERDIP, the maximum junction
temperature is 175°C. If these maximums are exceeded
momentarily, proper circuit operation will be restored as soon
as the die temperature is reduced. Leaving the AD830 in the
overheated condition for an extended period can result in
permanent damage to the device. To ensure proper operation, it
is important to observe the recommended derating curves.
While the AD830 output is internally short-circuit protected,
this may not be sufficient to guarantee that the maximum
junction temperature is not exceeded under all conditions. If
the output is shorted to a supply rail for an extended period,
then the amplifier may be permanently destroyed.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
28-Lead PDIP Package
8-Lead SOIC Package
8-Lead CERDIP Package
θJA
90
155
110
Unit
°C/W
°C/W
°C/W
ESD CAUTION
2.8
TJ MAX = 145°C
TJ MAX = 175°C
2.6
TOTAL POWER DISSIPATION (W)
TOTAL POWER DISSIPATION (W)
2.5
2.0
1.5
8-LEAD PDIP
1.0
0.5
8-LEAD SOIC
2.4
2.2
2.0
1.8
1.6
1.4
1.2
8-LEAD CERDIP
1.0
0.8
0.6
–10
10
30
50
AMBIENT TEMPERATURE (°C)
70
90
0.2
–60
00881-004
–30
Figure 4. Maximum Power Dissipation vs. Temperature, PDIP and SOIC Packages
–40
–20
0
20
40
60
80
AMBIENT TEMPERATURE (°C)
100
120
140
00881-005
0.4
0
–50
Figure 5. Maximum Power Dissipation vs. Temperature, CERDIP Package
Rev. D | Page 7 of 20
AD830
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
110
100
±
TO VP @ ±15V
90
90
80
80
70
VS = ±15V
PSRR (dB)
CMRR (dB)
100
70
60
VS =±±5V
±
TO VP @ ±5V
±
TO VN @ ±15V
60
TO VN @ ±5V
50
40
50
30
40
10k
100k
1M
10M
FREQUENCY (Hz)
10
00881-006
1k
1k
Figure 6. Common-Mode Rejection Ratio vs. Frequency
0
–60
± ±15V
–3
±5V SUPPLIES
SECOND HARMONIC
THIRD HARMONIC
±10V
–6
–70
±15V SUPPLIES
SECOND HARMONIC
THIRD HARMONIC
–9
–12
–15
±5V
–18
–21
–24
1M
10M
1M
10M
100M
1G
140
FREQUENCY (Hz)
Figure 7. Harmonic Distortion vs. Frequency
Figure 10. Closed-Loop Gain vs. Frequency G = +1
3
9
±5V
± S
2
INPUT OFFSET VOLTAGE (mV)
8
7
6
5
4
–40
–20
0
20
40
60
80
100
120
JUNCTION TEMPERATURE (°C)
140
1
±±10V S
0
–1
±±15V S
–2
–3
–4
–60
00881-008
3
–60
100k
00881-010
100k
FREQUENCY (Hz)
00881-011
10k
RL = 150Ω
CL = 4.7pF
–27
10k
00881-007
–90
1k
INPUT CURRENT (µA)
10M
1M
3
VOUT = 2V p-p
RL = 150Ω
GAIN = +1
–80
100k
FREQUENCY (Hz)
Figure 9. Power Supply Rejection Ratio vs. Frequency
GAIN (dB)
HARMONIC DISTORTION (dBc)
–50
10k
00881-009
20
30
–40
–20
0
20
40
60
80
100
120
JUNCTION TEMPERATURE (°C)
Figure 11. Input Offset Voltage vs. Temperature
Figure 8. Input Bias Current vs. Temperature
Rev. D | Page 8 of 20
Data Sheet
AD830
0.40
GAIN = +2
RL = 150Ω
FREQ = 4.5MHz
0.18
0.08
0.08
0.16
0.32
0.07
0.07
0.14
0.28
0.06
0.06
0.12
0.24
0.05
0.05
0.10
0.20
0.03
0.03
0.02
0.02
0.01
0.01
0
5
6
7
8
9
10
11
12
SUPPLY VOLTAGE (±V)
13
14
0
15
0.08
0.08
0.02
0.04
0
–50
–50
–60
–70
HD3 ±15V
100kHz
0.75
1.00
1.25
1.50
PEAK AMPLITUDE (V)
1.75
2.00
9
10
11
12
SUPPLY VOLTAGE (±V)
13
0
15
14
–60
HD3 ±5V
–70 4MHz
HD2 ±15V
4MHz
–80
HD3 ±15V
4MHz
HD2 ±15V
100kHz
–100
0.25
00881-013
0.50
8
HD2 ±5V
4MHz
–90
–90
–100
0.25
7
6
Figure 15. Differential Gain and Phase vs. Supply Voltage, RL = 150 Ω
HARMONIC DISTORTION (dB)
HARMONIC DISTORTION (dB)
5
–40
HD2 ±5V
100kHz
0.12
PHASE
0.04
–40
–80
0.16
GAIN
0.06
Figure 12. Differential Gain and Phase vs. Supply Voltage, RL = 500 Ω
HD3 ±5V
100kHz
0.36
DIFFERENTIAL PHASE (Degrees)
0.04
GAIN
DIFFERENTIAL GAIN (%)
0.04
00881-012
PHASE
DIFFERENTIAL PHASE (Degrees)
0.09
00881-015
0.09
Figure 13. Harmonic Distortion vs. Peak Amplitude, Frequency = 100 kHz
0.50
0.75
1.00
1.25
1.50
2.00
1.75
PEAK AMPLITUDE (V)
Figure 16. Harmonic Distortion vs. Peak Amplitude, Frequency = 4 MHz
15.00
50
QUIESCENT SUPPLY CURRENT (mA)
40
30
20
14.50
14.25
±16.5V S
14.00
13.75
13.50
13.25
±5VS
13.00
12.75
12.50
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
12.25
–60
00881-014
INPUT VOLTAGE NOISE (nV/√Hz)
14.75
–40
–20
0
20
40
60
80
100
120
JUNCTION TEMPERATURE (°C)
Figure 17. Supply Current vs. Junction Temperature
Figure 14. Noise Spectral Density
Rev. D | Page 9 of 20
140
00881-017
DIFFERENTIAL GAIN (%)
0.20
0.10
GAIN = +2
RL = 500Ω
FREQ = 4.5MHz
00881-016
0.10
AD830
Data Sheet
RL = 150Ω
CL = 0pF
0
±15V
V1
6
1
GM
2
–3
–9
±5V
–12
–6
–15
–9
–18
–12
–21
–15
GAIN OF 2 CONNECTION
0
–6
1M
10M
FREQUENCY (Hz)
GM
C
5
1
GM
AD830
2
V1
–21
1G
100M
OUT
6
VN
VOUT = 2V1
RESISTORLESS GAIN OF 2
3
00881-018
–27
100k
VP
8
7
A=1
4
–18
–24
AD830
3
3
(a)
VP
8
OUT
7
A=1
GM
C
4
Figure 18. Closed-Loop Gain vs. Frequency for the Three Common
Connections of Figure 16
6
5
VN
VOUT = V1
OP AMP CONNECTION
100mV
VS = ±5V
V1
1
100
GM
AD830
2
3
(b)
VP
8
OUT
7
90
A=1
GM
C
4
6
5
VN
VOUT = V1
GAIN OF 1
VS = ±15V
(c)
Figure 21. Connection Diagrams
10
00881-019
0%
20ns
1V
VS = ±5V
100
Figure 19. Small Signal Pulse Response, RL = 150 Ω, CL = 4.7 pF, G = +1
6
90
VS = ±5V
RL = 150Ω
3
CL = 33pF
VS = ±15V
0
CL = 15pF
–3
10
0%
CL = 4.7pF
–6
00881-022
9
GAIN (dB)
20ns
–9
Figure 22. Large Signal Pulse Response, RL = 150 Ω, CL = 4.7 pF, G = +1
–12
9
–15
6
–18
VS = ±15V
RL = 150Ω
CL = 33pF
3
1M
10M
FREQUENCY (Hz)
100M
1G
Figure 20. Closed-Loop Gain vs. Frequency vs. CL, G = +1, VS = ±5 V
CL = 15pF
0
–3
CL = 4.7pF
–6
–9
–12
–15
–18
–21
10k
100k
1M
10M
FREQUENCY (Hz)
100M
1G
00881-023
100k
GAIN (dB)
–21
10k
00881-020
UNITY GAIN CONNECTION
–3
9
00881-021
3
Figure 23. Closed-Loop Gain vs. Frequency vs. CL, G = +1, VS = ±15 V
Rev. D | Page 10 of 20
Data Sheet
AD830
THEORY OF OPERATION
TRADITIONAL DIFFERENTIAL AMPLIFICATION
ADVANTAGEOUS PROPERTIES OF THE AD830
In the past, when differential amplification was needed to reject
common-mode signals superimposed with a desired signal,
most often the solution used was the classic op amp based
difference amplifier shown in Figure 24. The basic function
VO = V1 − V2 is simply achieved, but the overall performance is
poor and the circuit possesses many serious problems that make
it difficult to realize a robust design with moderate to high
levels of performance.
•
•
•
•
•
•
•
•
•
R1
V2
R2
UNDERSTANDING THE AD830 TOPOLOGY
R3
VOUT
R4
ONLY IF R1 = R2 = R3 = R4
DOES VOUT = V1 – V2
00881-024
V1
Figure 24. Op Amp Based Difference Amplifier
PROBLEMS WITH THE OP AMP BASED APPROACH
•
•
•
•
•
•
•
•
High common-mode rejection ratio (CMRR)
High impedance inputs
Symmetrical dynamic response for +1 and −1 Gain
Low sensitivity to the value of source R
Equal input impedance for the + and − input
Excellent high frequency CMRR
No halving of the bandwidth
Constant power distortion versus common-mode voltage
Highly matched resistors not needed
Low common-mode rejection ratio (CMRR)
Low impedance inputs
CMRR highly sensitive to the value of source R
Different input impedance for the + and − input
Poor high frequency CMRR
Requires very highly matched resistors, R1 to R4, to achieve
high CMRR
Halves the bandwidth of the op amp
High power dissipation in the resistors for large commonmode voltage
AD830 FOR DIFFERENTIAL AMPLIFICATION
The AD830 amplifier was specifically developed to solve the
listed problems with the discrete difference amplifier approach.
Its topology, discussed in detail in the Understanding the AD830
Topology section, by design acts as a difference amplifier. The
circuit of Figure 25 shows how simply the AD830 is configured
to produce the difference of the two signals, V1 and V2, in which
the applied differential signal is exactly reproduced at the
output relative to a separate output common. Any commonmode voltage present at the input is removed by the AD830.
V1
V2
V→ I
IX
A=1
VOUT
The AD830 represents Analog Devices first amplifier product to
embody a powerful alternative amplifier topology. Referred to
as active feedback, the topology used in the AD830 provides
inherent advantages in the handling of differential signals,
differing system commons, level shifting, and low distortion,
high frequency amplification. In addition, it makes possible the
implementation of many functions not realizable with single op
amp circuits or superior to op amp based equivalent circuits.
With this in mind, it is important to understand the internal
structure of the AD830.
The topology, reduced to its elemental form, is shown in Figure 26.
Nonideal effects, such as nonlinearity, bias currents, and limited
full scale, are omitted from this model for simplicity but are
discussed later. The key feature of this topology is the use of
two, identical voltage-to-current converters, GM, that make up
input and feedback signal interfaces. They are labeled with
inputs VX and VY, respectively. These voltage-to-current
converters possess fully differential inputs, high linearity, high
input impedance, and wide voltage range operation. This
enables the part to handle large amplitude differential signals; it
also provides high common-mode rejection, low distortion, and
negligible loading on the source. The label, GM, is meant to
convey that the transconductance is a large signal quantity,
unlike in the front end of most op amps. The two GM stage
current outputs, IX and IY, sum together at a high impedance
node, which is characterized by an equivalent resistance and
capacitance connected to an ac common. A unity voltage gain
stage follows the high impedance node to provide buffering
from loads. Relative to either input, the open-loop gain, AOL, is
set by the transconductance, GM, working into the resistance,
RP; AOL = GM × RP. The unity gain frequency, ω0 dB, for the openloop gain is established by the transconductance, GM, working
into the capacitance, CC; ω0 dB = GM/CC. The open-loop
description of the AD830 is shown below for completeness.
V→ I
VOUT = V1 – V2
00881-025
IY
Figure 25. AD830 as a Difference Amplifier
Rev. D | Page 11 of 20
AD830
Data Sheet
INTERFACING THE INPUT
GM
Common-Mode Voltage Range
IX
A=1
IY
VY1
GM
VY2
CC
RP
The common-mode range of the AD830 is defined by the
amplitude of the differential input signal and the supply voltage.
The general definition of common-mode voltage, VCM, is
usually applied to a symmetrical differential signal centered
around a particular voltage, as illustrated in Figure 28. This is
the meaning implied here for common-mode voltage. The
internal circuitry establishes the maximum allowable voltage on
the input or feedback pins for a given supply voltage. This
constraint and the differential input voltage sets the commonmode voltage limit. Figure 29 shows a curve of the commonmode voltage range versus the differential voltage for three
supply voltage settings.
VOUT
IX = (VX1 – VX2) GM
IY = (VY1 – VY2) GM
IZ = IX + IY
AOLS =
GMRP
1 + S (CCRP)
00881-026
IZ
Figure 26. Topology Diagram
VX2
GM
IX
A=1
IY
VY1
VY2
VOUT
VMAX
CC
GM
VCM
VPEAK
VX1 – VX2 = VY2 – VY1
FOR VY2 = VOUT
VOUT = (VX1 – VX2 + VY1)
1
1 + S(CC/GM)
00881-027
VX1
00881-028
VX1
VX2
Figure 28. Common-Mode Definition
Figure 27. Closed-Loop Connection
The bandwidth of the circuit is defined by the GM and the
capacitor, CC. The highly linear GM stages give the amplifier a
single-pole response, excluding the output amplifier and
loading effects. It is important to note that the bandwidth and
general dynamic behavior is symmetrical (identical) for the
noninverting and the inverting connections of the AD830. In
addition, the input impedance and CMRR are the same for
either connection. This is very advantageous and unlike in a
voltage or current feedback amplifier where there is a distinct
difference in performance between the inverting and
noninverting gain. The practical importance of this cannot be
overemphasized and is a key feature offered by the AD830
amplifier topology.
15
COMMON-MODE VOLTAGE (±V)
+VCM
±15V = VS
12
–VCM
+VCM
9
±10V = VS
–VCM
6
+VCM
3
±5V = VS
–VCM
0
0
0.8
1.2
1.6
0.4
DIFFERENTIAL INPUT VOLTAGE (VPEAK )
2.0
00881-029
Precise amplification is accomplished through closed-loop
operation of this topology. Voltage feedback is implemented via
the Y GM stage where the output is connected to the −Y input
for negative feedback, as shown in Figure 27. An input signal is
applied across the X GM stage, either fully differential or singleended referred to common. It produces a current signal that is
summed at the high impedance node with the output current
from the Y GM stage. Negative feedback nulls this sum to a small
error current necessary to develop the output voltage at the high
impedance node. The error current is usually negligible, so the
null condition essentially forces the Y GM output stage current
to equal the exact X GM output current. Because the two
transconductances are identical, the differential voltage across
the Y inputs equals the negative of the differential voltage across
the X input; VY = −VX or, more precisely, VY2 − VY1 = VX1 − VX2.
This simple relation provides the basis to easily analyze any
function possible to synthesize with the AD830, including any
feedback situation.
Figure 29. Input Common-Mode Voltage Range vs. Differential Input Voltage
Differential Voltage Range
The maximum applied differential voltage is limited by the
clipping range of the input stages. This is nominally set at a
2.4 V magnitude and depicted in the cross plot (X-Y) in Figure 30.
The useful linear range of the input stages is set at 2 V but is
actually a function of the distortion required for a particular
application. The distortion increases for larger differential input
voltages. A plot of relative distortion versus the input differential
voltage is shown in Figure 13 and Figure 16. The distortion
characteristics impose a secondary limit to the differential input
voltage for high accuracy applications.
Rev. D | Page 12 of 20
Data Sheet
AD830
1V
mismatches in the resistances, a residual offset remains and is
likely to be greater than the bias current (offset current)
mismatches.
1V
100
90
Applying Feedback
Choice of Polarity
The sign of the gain is easily selected by choosing the polarity
of the connections to the + and − inputs of the X GM stage.
Swapping between inverting and noninverting gain is possible
simply by reversing the input connections. The response of the
amplifier is identical in either connection, except for the sign
change.
The bandwidth, high impedance, and transient behavior of the
AD830 is symmetrical for both polarities of gain. This is very
advantageous and unlike an op amp.
Input Impedance
The relatively high input impedance of the AD830, for a
differential receiver amplifier, permits connections to modest
impedance sources without much loading or loss of commonmode rejection. The nominal input resistance is 300 kΩ. The
real limit to the upper value of the source resistance is in its
effect on common-mode rejection and bandwidth. If the source
resistance is in only one input, then the low frequency
common-mode rejection is lowered to ≈ RIN/RS. The source
resistance/input capacitance pole limits the bandwidth. Refer to
the following equation:
f = 1 × R ×C
IN
S
2π
Furthermore, the high frequency common-mode rejection is
additionally lowered by the difference in the frequency response
caused by the RS × CIN pole. Therefore, to maintain good low
and high frequency common-mode rejection, it is recommended
that the source resistances of the + and − inputs be matched and
of modest value (≤10 kΩ).
Handling Bias Currents
The bias currents are typically 4 μA flowing into each pin of the
GM stages of the AD830. Because all applications possess some
finite source resistance, the bias current through this resistor
creates a voltage drop (IBIAS × RS). The relatively high input
impedance of the AD830 permits modest values of RS, typically
≤10 kΩ. If the source resistance is in only one terminal, then an
objectionable offset voltage may result, for example, 4 μA × 5
kΩ = 20 mV. Placement of an equal value resistor in series with
the other input cancels the offset to first order. However, due to
Output Common Mode
The output swing of the AD830 is defined by the differential
input voltage, the gain, and the output common. Depending on
the anticipated signal span, the output common (or ground)
may be set anywhere between the allowable peak output voltage
in a manner similar to that described for input voltage common
mode. A plot of the peak output voltage versus the supply is
shown in Figure 31. A prediction of the common-mode range
versus the peak output differential voltage can be easily derived
from the maximum output swing as VOCM = VMAX − VPEAK.
15
12
VP
VN
9
6
3
0
0
4
8
12
SUPPLY VOLTAGE (V)
16
20
00881-031
00881-030
Figure 30. Clipping Behavior
MAXIMUM OUTPUT SWING (±V)
10
0%
The AD830 is intended for use with gains from 1 to 100. Gains
greater than one are simply set by a pair of resistors connected
as shown in the difference amplifier (Figure 40) with gain >1.
The value of the bottom resistor, R2, should be kept less than
1 kΩ to ensure that the pole formed by CIN and the parallel
connection of R1 and R2 is sufficiently high in frequency so that
it does not introduce excessive phase shift around the loop and
destabilize the amplifier. A compensating resistor, equal to the
parallel combination of R1 and R2, should be placed in series
with the other Y GM stage input to preserve the high frequency
common-mode rejection and to lower the offset voltage
induced by the input bias current.
Figure 31. Maximum Output Swing vs. Supply
Output Current
The absolute peak output current is set by the short-circuit
current limiting, typically greater than 60 mA. The maximum
drive capability is rated at 50 mA but without a guarantee of
distortion performance. Best distortion performance is obtained
by keeping the output current ≤20 mA. Attempting to drive
large voltages into low valued resistances, for example, 10 V into
150 Ω causes an apparent lowering of the limit for output signal
swing but is just the current limiting behavior.
Rev. D | Page 13 of 20
AD830
Data Sheet
The AD830 is capable of driving modest sized capacitive loads
while maintaining its rated performance. Several curves of
bandwidth versus capacitive load are given in Figure 34 and
Figure 37. The AD830 was designed primarily as a low
distortion video speed amplifier but with a trade-off, for
example, giving up very large capacitive load driving capability.
If very large capacitive loads must be driven, the network shown
in Figure 32 should be used to ensure stable operation. If the
loss of gain caused by the resistor, RS, in series with the load is
objectionable, the optional feedback network shown may be
added to restore the lost gain.
Inclusion of power supply bypassing capacitors is necessary to
achieve stable behavior and the specified performance. It is
especially important when driving low resistance loads. At
minimum, connect a 0.1 μF ceramic capacitor at the supply lead
of the AD830 package. In addition, for the best bypassing, it is
best to connect a 0.01 μF ceramic capacitor and 4.7 μF tantalum
capacitor to the supply lead going to the AD830.
VP
AND
VN
0.1µF
LOAD
GND
LEAD
+VS
VCM
INPUT
SIGNAL
RS
36.5Ω
GM
2
7
ZCM
3
6
GM
4
C
VOUT
R1
1kΩ
C1
100pF
A=1
0.1µF
*OPTIONAL
FEEDBACK
NETWORK
RS
5
–VS
R2
Figure 32. Circuit for Driving Large Capacitive Loads
±5V
–6
LOAD
GND
LEAD
The AD830 is designed to be capable of rejecting noise and
dissimilar potentials in the ground lines. Therefore, proper
care is necessary to realize the benefits of the differential
amplification of the part. Separation of the input and output
grounds is crucial in rejection of the common-mode noise at
the inputs and eliminating any ground drops on the input signal
line. For example, connecting the ground of a coaxial cable to
the AD830 output common (board ground) could degrade the
CMR and also introduce power-down loading on cable grounds.
Single-Supply Operation
–9
–12
–15
–18
–21
–24
100k
1M
FREQUENCY (Hz)
10M
100M
00881-033
CLOSED-LOOP AMPLITUDE RESPONSE (dB)
±15V
0
–27
10k
4.7µF
However, it is also necessary as in any electronic system to
provide a return path for bias currents back to their original
power supply. This is accomplished by providing a connection
between the differing grounds through a modest impedance
labeled ZCM, for example, 100 Ω.
3
–3
0.01µF
Figure 34. Supply Decoupling Options
0.1µF
8
00881-032
AD830
1
VP
AND
VN
00881-034
Driving Cap Loads
Figure 33. Closed-Loop Response vs. Frequency with 100 pF Load and Series
Resistor Compensation
SUPPLIES, BYPASSING, AND GROUNDING
(FIGURE 34)
The AD830 is capable of operating over a wide range of supply
voltages, both single and dual supplies. The coupling may be dc
or ac, provided the input and output voltages stay within the
specified common-mode voltage limits. For dual supplies, the
device works from ±4 V to ±16.5 V. Single-supply operation is
possible over 8 V to 33 V. It is also possible to operate the part
with split-supply voltages, for example, +24 V or −5 V for
special applications such as level shifting. The primary
constraint is that the total potential between the two supplies
does not exceed 33 V.
The AD830 is capable of operating in single power supply
applications down to a voltage of 8 V, with the generalized
connection shown in Figure 35. There is a constraint on the
common-mode voltage at the input and output that establishes
the range for these voltages. Direct coupling may be used for
input and output voltages that lie in these ranges. Any gain
network applied needs to be referred to the output common
connection or have an appropriate offset voltage. In situations
where the signal lies at a common voltage outside the commonmode range of the AD830, direct coupling does not work, so ac
coupling should be used. Figure 47 shows how to easily
accomplish coupling to the AD830. For single-supply operation
where direct coupling is desired, the input and output commonmode curves (Figure 36 and Figure 37) should be used.
Rev. D | Page 14 of 20
Data Sheet
AD830
VP
AD830
1
VIN
8
GM
2
VOUT
7
A=1
3
VP
6
GM
C
4
5
VCM
VOUT = (VIN – VICM) + VOCM
VOCM
00881-035
VICM
are very good, as shown in Figure 12 for 500 Ω and Figure 15
for 150 Ω. The input and output common should be separated
to achieve the full CMR performance of the AD830 as a
differential amplifier. However, a common return path is
necessary between System A and System B.
V1
1
INPUT
SIGNAL
V2
2
COMMON IN
SYSTEM A
3
ZCM
AD830
GM
A=1
6
C
0.1µF
4
5
30
Figure 38. Differential Line Receiver
20
Wide Range Level Shifter
16
VP = +15V
12
VP = +10V
8
TO GND
0
0
0.4
0.8
1.2
1.6
DIFFERENTIAL INPUT VOLTAGE (VPEAK )
2.0
Figure 36. Input Common-Mode Range for Single Supply
28
24
The wide common-mode range and accuracy of the AD830
allows easy level shifting of differential signals referred to an
input common-mode voltage to any new voltage defined at the
output. The inputs may be referenced to levels as high as 10 V at
the inputs with a ±2 V swing around 10 V. In the circuit in
Figure 39, the output voltage, VOUT, is defined by the simple
equation shown below. The excellent linearity and low distortion
are preserved over the full input and output common-mode
range. The voltage sources need not be of low impedance, since
the high input resistance and modest input bias current of the
AD830 V-to-I converters permit the use of resistive voltage
dividers as reference voltages.
VP
TO VP
20
V1
INPUT
SIGNAL
V2
INPUT
COMMON
16
12
8
A=1
6
3
C
TO GND
26
30
0.1µF
5
VN
00881-037
18
22
SUPPLY VOLTAGE (V)
VOUT
7
4
14
0.1µF
8
GM
2
GM
4
0
10
AD830
1
VOUT = V1 – V2 + V3
Figure 37. Output Swing Limit for Single Supply
Differential Line Receiver
OUTPUT
COMMON
V3
00881-039
4
00881-036
COMMON-MODE VOLTAGE LIMITS (±V)
COMMON IN
SYSTEM B
VOUT = V1 – V2
VP = +30V
24
00881-038
VN
28
MAXIMUM OUTPUT SWING (±V)
VOUT
7
GM
Figure 35. General Single-Supply Connection
0.1µF
8
Figure 39. Differential Amplification with Level Shifting
The AD830 is specifically designed to perform as a differential
line receiver. The circuit in Figure 38 shows how simple it is to
configure the AD830 for this function. The signal from System A is
received differentially relative to the common of System A, and
that voltage is exactly reproduced relative to the common in
System B. The common-mode rejection versus frequency, shown
in Figure 6, is excellent, typically 100 dB at low frequencies.
The high input impedance permits the AD830 to operate as a
bridging amplifier across low impedance terminations with
negligible loading. The differential gain and phase specifications
Difference Amplifier with Gain > 1
The AD830 can provide instrumentation amplifier style and
differential amplification at gains greater than 1. The input
signal is connected differentially and the gain is set via feedback
resistors, as shown in Figure 40. The gain is G = (R2 + R1)/R2.
The AD830 can provide either inverting or noninverting
differential amplification. The polarity of the gain is established
by the polarity of the connection at the input. Feedback resistor,
R2, should generally be R2 ≤ 1 kΩ to maintain closed-loop
Rev. D | Page 15 of 20
AD830
Data Sheet
VP
2
R1 R2
ZCM
7
GM
C
0.1µF
5
6
GM
OPTIONAL CC
C
4
499Ω
0.1µF
5
Figure 42. Cable Tap Amplifier
R1
VN
R2
VOUT = (V1 – V2)(1 + R1/R2)
Resistorless Summing
Figure 40. Gain of G Differential Amplifier, G>1
Offsetting the Output With Gain
Some applications, such as ADCs, require that the signal be
amplified and also offset, typically to accommodate the input
range of the device. The AD830 can offset the output signal
very simply through Pin 3 even with gain > 1. The voltage
applied to Pin 3 must be attenuated by an appropriate factor so
that V3 × G = desired offset. In Figure 41, a resistive divider
from a voltage reference is used to produce the attenuated offset
voltage.
Direct, two input, resistorless summing is easily realized from
the general unity gain mode. By grounding VX2 and applying the
two inputs to VX1 and VY1, the output is the exact sum of the
applied voltages, V1 and V3, relative to common; VOUT = V1 + V3.
A diagram of this simple but potent application is shown below
in Figure 43. The AD830 summing circuit possesses several
virtues not present in the classic op amp based summing circuits.
It has high impedance inputs, no resistors, very precise summing,
high reverse isolation, and noninverting gain. Achieving this
function and performance with op amps requires significantly
more components.
VP
VP
VCM
R1 R2
ZCM
AD830
1
V1
GM
2
VOUT
7
GM
2
C
6
GM
V3
C
4
0.1µF
5
5
VN
R1 VREF
VN
R2
VOUT = (V1 – V2)(1 + R1/R2)
OUT
7
A=1
6
4
8
GM
3
A=1
3
AD830
1
0.1µF
8
VOUT = V1 +V3
Figure 43. Resistorless Summing Amplifier
R3
2× Gain Bandwidth Line Driver
V3
R4
00881-041
V1
INPUT
SIGNAL
V2
499Ω
VN
A=1
3
75Ω
6
4
VOUT
75Ω
A=1
3
8
GM
VOUT
7
00881-043
1
00881-040
V1
INPUT
SIGNAL
V2
VCM
AD830
2
249Ω
0.1µF
8
GM
RG
VP
0.1µF
AD830
1
00881-042
stability and also keep bias current induced offsets low. Highest
CMRR and lowest dc offsets are preserved by including a
compensating resistor in series with Pin 3. The gain may be as
high as 100.
Figure 41. Offsetting the Output with Differential Gain >1
Loop Through or Line Bridging Amplifier (Figure 42)
The AD830 is ideally suited for use as a video line bridging
amplifier. The video signal is tapped from the conductor of the
cable relative to its shield. The high input impedance of the
AD830 provides negligible loading on the cable. More significantly,
the benign loading is maintained while the AD830 is powered
down. Coupled with its good video load driving performance,
the AD830 is well suited for video cable monitoring applications.
A gain of two, without the use of resistors, is possible with the
AD830. This is accomplished by grounding VX2, tying the VX1
and VY1 inputs together, and applying the input, VIN, to this
wired connection. The output is exactly twice the applied
voltage, VIN; VOUT = 2 × VIN. Figure 44 shows the connections
for this highly useful application. The most notable characteristic of
this alternative gain of +2 is that there is no loss of bandwidth as
in a voltage feedback op amp based gain of +2 where the
bandwidth is halved; therefore, the gain bandwidth is doubled.
In addition, this circuit is accurate without the need for any
precise valued resistors, as in the op amp equivalents, and it
possesses excellent differential gain and phase performance, as
shown in Figure 45 and Figure 46.
Rev. D | Page 16 of 20
Data Sheet
AD830
VP
0.1µF
GM
2
VOUT 75Ω
7
A=1
3
75Ω
6
GM
C
AMPLITUDE RESPONSE (dB)
0.1µF
5
00881-044
4
VN
Figure 44. Full Bandwidth Line Driver (G = +2)
0.08
0.20
GAIN = +2
RL = 150Ω
0.18
FREQ = 3.58MHz
0 TO 0.7V
0.16
0.07
0.14
0.06
0.12
0.05
0.10
PHASE
0.08
0.06
0.03
0.02
0.04
GAIN
0.01
6
7
8
9
10
11
12
SUPPLY VOLTAGE (±V)
13
14
VS = ±10V
–0.3
–0.4
VS = ±5V
–0.5
–0.6
15
100k
1M
FREQUENCY (Hz)
The AD830 is configurable as an ac-coupled differential
amplifier on a single- or bipolar-supply voltage. All that is
needed is inclusion of a few noncritical passive components, as
illustrated in Figure 47. A simple resistive network at the X GM
input establishes a common-mode bias. Here, the common
mode is centered at 6 V, but in principle can be any voltage
within the common-mode limits of the AD830. The 10 kΩ
resistors to each input bias the X GM stage with sufficiently high
impedance to keep the input coupling corner frequency low, but
not too large so that residual bias current induced offset voltage
becomes troublesome. For dual-supply operation, the 10 kΩ
resistors may go directly to ground. The output common is
conveniently set by a Zener diode for a low impedance
reference to preserve the high frequency CMR. However, a
simple resistive divider works fine, and good high frequency
CMR can be maintained by placing a compensating resistor in
series with the +Y input. The excellent CMRR response of the
circuit is shown in Figure 48. A plot of the 0.1 dB flatness from
10 Hz is also shown. With the use of 10 μF capacitors, the CMR
is >90 dB down to a few tens of hertz. This level of performance
is almost impossible to achieve with discrete solutions.
+12V
10µF
AD830
1
0.1µF
8
75Ω
COAX
VOUT 75Ω CABLE
GM
RT
ZCM
2
7
10µF
10kΩ
+VS
2kΩ*
10kΩ
1000µF
A=1
10kΩ
100M
AC-COUPLED LINE RECEIVER
Figure 45. Differential Gain and Phase for the Circuit of Figure 44
INPUT
SIGNAL
10M
Figure 46. 0.1 dB Gain Flatness for the Circuit of Figure 44
0.02
5
RL = 150Ω
GAIN = +2
–0.2
–0.8
10k
00881-045
DIFFERENTIAL GAIN (%)
0.09
–0.1
–0.7
DIFFERENTIAL PHASE (Degrees)
0.10
0.04
VS = ±15V
0
3
75Ω
6
GM
+12V
C
4
5
4.7kΩ
10kΩ
*OPTIONAL TUNING FOR IMPROVING
VERY LOW FREQUENCY CMR.
1N4736
Figure 47. AC-Coupled Line Receiver
Rev. D | Page 17 of 20
6.8V
00881-047
VIN
0.1
8
00881-046
AD830
1
0.2
AD830
Data Sheet
0.1
120
0
100
80
AMPLITUDE RESPONSE (dB)
COMMON-MODE REJECTION (dB)
WITH CIRCUIT TRIMMED USING
EXTERNAL 2kΩ POTENTIOMETER
WITHOUT EXTERNAL
2kΩ POTENTIOMETER
60
40
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100M
Figure 48. Common-Mode Rejection vs. Frequency for Line Receiver
Rev. D | Page 18 of 20
–0.9
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 49. Amplitude Response vs. Frequency for Line Receiver
00881-049
100
00881-048
–0.8
20
10
Data Sheet
AD830
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
5
1
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.100 (2.54)
BSC
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
070606-A
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 50. 8-Lead Plastic Dual-in-Line Package [PDIP]
(N-8)
Dimensions shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 51. 8-Lead Standard Small Outline Package [SOIC_N]
(R-8)
Dimensions shown in millimeters and (inches)
Rev. D | Page 19 of 20
012407-A
4.00 (0.1574)
3.80 (0.1497)
AD830
Data Sheet
0.005 (0.13)
MIN
8
0.055 (1.40)
MAX
5
0.310 (7.87)
0.220 (5.59)
1
4
0.100 (2.54) BSC
0.320 (8.13)
0.290 (7.37)
0.405 (10.29) MAX
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.070 (1.78)
0.030 (0.76)
SEATING
PLANE
15°
0°
0.015 (0.38)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 52. 8-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-8)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model 1, 2
AD830ANZ
AD830ARZ
AD830ARZ-REEL7
AD830JRZ
AD830JRZ-R7
5962-9313001MPA
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
0°C to +70°C
0°C to +70°C
−55°C to +125°C
Package Description
8-Lead PDIP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead CERDIP
Z = RoHS Compliant Part.
See Standard Military Drawing 5962-9313001 MPA for specifications.
©2005–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00881-0-1/18(D)
Rev. D | Page 20 of 20
Package Option
N-8
R-8
R-8
R-8
R-8
Q-8
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