AD8317-EVALZ

1 MHz to 10 GHz, 55 dB Log Detector/Controller AD8317 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS VPOS GAIN BIAS DET DET DET TADJ SLOPE I V VSET I V VOUT DET CLPF INHI INLO COMM RF transmitter PA setpoint control and level monitoring Power monitoring in radio link transmitters RSSI measurement in base stations, WLANs, WiMAX, and radars 05541-001 Wide bandwidth: 1 MHz to 10 GHz High accuracy: ±1.0 dB over temperature 55 dB dynamic range up to 8 GHz ± 3 dB error Stability over temperature: ±0.5 dB Low noise measurement/controller output, VOUT Pulse response time: 6 ns/10 ns (fall/rise) Small footprint, 2 mm × 3 mm LFCSP Supply operation: 3.0 V to 5.5 V at 22 mA Fabricated using high speed SiGe process Figure 1. GENERAL DESCRIPTION The AD8317 is a demodulating logarithmic amplifier, capable of accurately converting an RF input signal to a corresponding decibel-scaled output. It employs the progressive compression technique over a cascaded amplifier chain, each stage of which is equipped with a detector cell. The device can be used in either measurement or controller modes. The AD8317 maintains accurate log conformance for signals of 1 MHz to 8 GHz and provides useful operation to 10 GHz. The input dynamic range is typically 55 dB (referenced to 50 Ω) with less than ±3 dB error. The AD8317 has 6 ns/10 ns response time (fall time/rise time) that enables RF burst detection to a pulse rate of beyond 50 MHz. The device provides unprecedented logarithmic intercept stability vs. ambient temperature conditions. A supply of 3.0 V to 5.5 V is required to power the device. Current consumption is typically 22 mA, and it decreases to 200 μA when the device is disabled. The feedback loop through an RF amplifier is closed via VOUT, the output of which regulates the output of the amplifier to a magnitude corresponding to VSET. The AD8317 provides 0 V to (VPOS − 0.1 V) output capability at the VOUT pin, suitable for controller applications. As a measurement device, VOUT is externally connected to VSET to produce an output voltage, VOUT, that is a decreasing linear-in-dB function of the RF input signal amplitude. The logarithmic slope is 22 mV/dB, determined by the VSET interface. The intercept is 15 dBm (referenced to 50 Ω, CW input) using the INHI input. These parameters are very stable against supply and temperature variations. The AD8317 is fabricated on a SiGe bipolar IC process and is available in a 2 mm × 3 mm, 8-lead LFCSP with an operating temperature range of −40°C to +85°C. The AD8317 can be configured to provide a control voltage to a power amplifier or a measurement output from the VOUT pin. Because the output can be used for controller applications, special attention has been paid to minimize wideband noise. In this mode, the setpoint control voltage is applied to the VSET pin. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2005–2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8317 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Input Signal Coupling ................................................................ 11 Applications ....................................................................................... 1 Output Interface ......................................................................... 11 Functional Block Diagram .............................................................. 1 Setpoint Interface ....................................................................... 11 General Description ......................................................................... 1 Temperature Compensation of Output Voltage ..................... 12 Revision History ............................................................................... 2 Measurement Mode ................................................................... 12 Specifications..................................................................................... 3 Setting the Output Slope in Measurement Mode .................. 13 Absolute Maximum Ratings............................................................ 5 Controller Mode ......................................................................... 13 ESD Caution .................................................................................. 5 Output Filtering .......................................................................... 15 Pin Configuration and Function Descriptions ............................. 6 Operation Beyond 8 GHz ......................................................... 15 Typical Performance Characteristics ............................................. 7 Evaluation Board ............................................................................ 16 Theory of Operation ...................................................................... 10 Die Information .............................................................................. 18 Using the AD8317 .......................................................................... 11 Outline Dimensions ....................................................................... 19 Basic Connections ...................................................................... 11 Ordering Guide .......................................................................... 19 REVISION HISTORY 9/2019—Rev. C to Rev. D Changes to Table 6 .......................................................................... 18 Updated Outline Dimensions ....................................................... 19 8/2017—Rev. B to Rev. C Change to Figure 2 and Table 3 ...................................................... 6 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide ......................................................... 19 3/2008—Rev. A to Rev. B Changes to Features.......................................................................... 1 Changes to General Description .................................................... 1 Changes to Measurement Mode Section ..................................... 12 Changes to Equation 12 ................................................................. 15 8/2007—Rev. 0 to Rev. A Changes to f = 8.0 GHz, ±1 dB Dynamic Range Parameter ........4 Changes to Table 2.............................................................................6 Changes to Figure 20...................................................................... 10 Changes to Setpoint Interface Section and Figure 22 ................ 12 Changes Figure 27 .......................................................................... 13 Changes to Table 5.......................................................................... 17 Added Die Information Section ................................................... 19 Changes to Ordering Guide .......................................................... 21 10/2005—Revision 0: Initial Version Rev. D | Page 2 of 19 Data Sheet AD8317 SPECIFICATIONS VPOS = 3 V, CLPF = 1000 pF, TA = 25°C, 52.3 Ω termination resistor at INHI, unless otherwise noted. Table 1. Parameter SIGNAL INPUT INTERFACE Specified Frequency Range DC Common-Mode Voltage MEASUREMENT MODE f = 900 MHz Input Impedance ±1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope1 Intercept1 Output Voltage, High Power In Output Voltage, Low Power In f = 1.9 GHz Input Impedance ±1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope1 Intercept1 Output Voltage, High Power In Output Voltage, Low Power In f = 2.2 GHz Input Impedance ±1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope1 Intercept1 Output Voltage, High Power In Output Voltage, Low Power In f = 3.6 GHz Input Impedance ±1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope1 Intercept1 Output Voltage, High Power In Output Voltage, Low Power In Conditions INHI (Pin 1) Min Typ Max Unit 10 VPOS − 0.6 GHz V −25 12 0.42 1.00 1500||0.33 50 46 −3 −53 −22 15 0.58 1.27 −19.5 21 0.78 1.40 Ω||pF dB dB dBm dBm mV/dB dBm V V −25 10 0.35 0.75 950||0.38 50 48 −4.00 −54 −22 14 0.54 1.21 −19.5 20 0.80 1.35 Ω||pF dB dB dBm dBm mV/dB dBm V V 0.001 VOUT (Pin 5) shorted to VSET (Pin 4), sinusoidal input signal RTADJ = 18 kΩ TA = 25°C −40°C < TA < +85°C ±1 dB error ±1 dB error PIN = −10 dBm PIN = −40 dBm RTADJ = 8 kΩ TA = 25°C −40°C < TA < +85°C ±1 dB error ±1 dB error PIN = −10 dBm PIN = −35 dBm RTADJ = 8 kΩ TA = 25°C −40°C < TA < +85°C ±1 dB error ±1 dB error PIN = −10 dBm PIN = −40 dBm RTADJ = 8 kΩ TA = 25°C −40°C < TA < +85°C ±1 dB error ±1 dB error PIN = −10 dBm PIN = −40 dBm Rev. D | Page 3 of 19 810||0.39 50 47 −5 −55 −22 14 0.53 1.20 Ω||pF dB dB dBm dBm mV/dB dBm V V 300||0.33 42 40 −6 −48 −22 11 0.47 1.16 Ω||pF dB dB dBm dBm mV/dB dBm V V AD8317 Parameter f = 5.8 GHz Input Impedance ±1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope1 Intercept1 Output Voltage, High Power In Output Voltage, Low Power In f = 8.0 GHz Input Impedance ±1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope2 Intercept2 Output Voltage, High Power In Output Voltage, Low Power In OUTPUT INTERFACE Voltage Swing Output Current Drive Small Signal Bandwidth Output Noise Fall Time Rise Time Video Bandwidth (or Envelope Bandwidth) VSET INTERFACE Nominal Input Range Data Sheet Conditions RTADJ = 500 Ω Min TA = 25°C −40°C < TA < +85°C ±1 dB error ±1 dB error PIN = −10 dBm PIN = −40 dBm RTADJ = open TA = 25°C −40°C < TA < +85°C ±1 dB error ±1 dB error PIN = −10 dBm PIN = −40 dBm VOUT (Pin 5) VSET = 0 V, RFIN = open VSET = 1.7 V, RFIN = open VSET = 0 V, RFIN = open RFIN = −10 dBm, from CLPF to VOUT RFIN = 2.2 GHz, −10 dBm, fNOISE = 100 kHz, CLPF = open Input level = no signal to −10 dBm, 90% to 10%, CLPF = 8 pF Input level = no signal to −10 dBm, 90% to 10%, CLPF = open, ROUT = 150 Ω Input level = −10 dBm to no signal, 10% to 90%, CLPF = 8 pF Input level = −10 dBm to no signal, 10% to 90%, CLPF = open, ROUT = 150 Ω VSET (Pin 4) RFIN = 0 dBm, measurement mode RFIN = −50 dBm, measurement mode Typ Ω||pF dB dB dBm dBm mV/dB dBm V V 28||0.79 44 35 −2 −46 −22 21 0.70 1.39 Ω||pF dB dB dBm dBm mV/dB dBm V V VPOS − 0.1 10 10 140 90 V mV mA MHz nV/√Hz 18 ns 6 ns 20 ns 10 ns 50 MHz V V dB/V kΩ kΩ V RFIN = −20 dBm, controller mode, VSET = 1 V TADJ INTERFACE Input Resistance Disable Threshold Voltage TADJ (Pin 6) TADJ = 0.9 V, sourcing 50 μA TADJ = open 13 VPOS − 0.4 POWER INTERFACE Supply Voltage Quiescent Current vs. Temperature Disable Current VPOS (Pin 7) 1 2 3.0 18 −40°C ≤ TA ≤ +85°C TADJ = VPOS 22 60 200 5.5 30 Slope and intercept are determined by calculating the best-fit line between the power levels of −40 dBm and −10 dBm at the specified input frequency. Slope and intercept are determined by calculating the best-fit line between the power levels of −34 dBm and −16 dBm at 8.0 GHz. Rev. D | Page 4 of 19 Unit 110||0.05 50 48 −4 −54 −22 16 0.59 1.27 0.35 1.40 −45 40 Logarithmic Scale Factor Input Resistance Max V mA μA/°C μA Data Sheet AD8317 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage, VPOS VSET Voltage Input Power (Single-Ended, Referenced to 50 Ω) Internal Power Dissipation θJA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 60 sec) Rating 5.7 V 0 V to VPOS 12 dBm 0.73 W 55°C/W 125°C −40°C to +85°C −65°C to +150°C 260°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Rev. D | Page 5 of 19 AD8317 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 8 INLO AD8317 7 VPOS CLPF 3 TOP VIEW (Not to Scale) 6 TADJ VSET 4 5 VOUT NOTES 1. EXPOSED PAD MUST BE CONNECTED TO GROUND VIA A LOW IMPEDANCE PATH. 05541-002 INHI 1 COMM 2 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 3 Mnemonic INHI COMM CLPF 4 5 VSET VOUT 6 TADJ 7 8 VPOS INLO EPAD Description RF Input. Nominal input range of −50 dBm to 0 dBm, referenced to 50 Ω; ac-coupled RF input. Device Common. Connect to a low impedance ground plane. Loop Filter Capacitor. In measurement mode, this capacitor sets the pulse response time and video bandwidth. In controller mode, the capacitance on this node sets the response time of the error amplifier/integrator. Setpoint Control Input for Controller Mode or Feedback Input for Measurement Mode. Measurement and Controller Output. In measurement mode, VOUT provides a decreasing linear-in-dB representation of the RF input signal amplitude. In controller mode, VOUT is used to control the gain of a VGA or VVA with a positive gain sense (increasing voltage increases gain). Temperature Compensation Adjustment. Frequency-dependent temperature compensation is set by connecting a ground-referenced resistor to this pin. Positive Supply Voltage: 3.0 V to 5.5 V. RF Common for INHI. AC-coupled RF common. Exposed Pad. Exposed pad must be connected to ground via a low impedance path. Rev. D | Page 6 of 19 Data Sheet AD8317 TYPICAL PERFORMANCE CHARACTERISTICS 1.75 1.5 1.75 1.5 1.50 1.0 1.50 1.0 1.25 0.5 1.25 0.5 1.00 0 1.00 0 0.75 –0.5 0.75 –0.5 0.50 –1.0 0.50 –1.0 0.25 –1.5 0.25 –1.5 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 PIN (dBm) –2.0 Figure 6. VOUT and Log Conformance vs. Input Amplitude at 3.6 GHz, RTADJ = 8 kΩ 2.00 2.0 1.75 1.5 1.75 1.5 1.50 1.0 1.50 1.0 1.25 0.5 1.25 0.5 1.00 0 1.00 0 0.75 –0.5 0.75 –0.5 0.50 –1.0 0.50 –1.0 0.25 –1.5 0.25 –1.5 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 –2.0 PIN (dBm) VOUT (V) 2.0 ERROR (dB) 2.00 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 05541-004 VOUT (V) 5 PIN (dBm) Figure 3. VOUT and Log Conformance vs. Input Amplitude at 900 MHz, RTADJ = 18 kΩ 0 5 –2.0 PIN (dBm) Figure 4. VOUT and Log Conformance vs. Input Amplitude at 1.9 GHz, RTADJ = 8 kΩ Figure 7. VOUT and Log Conformance vs. Input Amplitude at 5.8 GHz, RTADJ = 500 Ω 2.00 2.0 1.75 1.5 1.75 1.5 1.50 1.0 1.50 1.0 1.25 0.5 1.25 0.5 1.00 0 1.00 0 0.75 –0.5 0.75 –0.5 0.50 –1.0 0.50 –1.0 0.25 –1.5 0.25 –1.5 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 –2.0 0 5 VOUT (V) 2.0 ERROR (dB) 2.00 05541-005 VOUT (V) 0 ERROR (dB) –2.0 05541-007 5 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 –2.0 PIN (dBm) PIN (dBm) Figure 5. VOUT and Log Conformance vs. Input Amplitude at 2.2 GHz, RTADJ = 8 kΩ Figure 8. VOUT and Log Conformance vs. Input Amplitude at 8.0 GHz, RTADJ = Open, Error Calculated from PIN = −34 dBm to PIN = −16 dBm Rev. D | Page 7 of 19 ERROR (dB) 0 05541-008 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 ERROR (dB) 2.0 05541-006 2.00 VOUT (V) 2.0 ERROR (dB) 2.00 05541-003 VOUT (V) VPOS = 3 V; TA = +25°C, −40°C, +85°C; CLPF = 1000 pF, unless otherwise noted. Black: +25°C; Blue: −40°C; Red: +85°C. Error is calculated by using the best-fit line between PIN = −40 dBm and PIN = −10 dBm at the specified input frequency, unless otherwise noted 2.00 2.0 1.75 1.5 1.75 1.5 1.50 1.0 1.50 1.0 1.25 0.5 1.25 0.5 1.00 0 1.00 0 0.75 –0.5 0.75 –0.5 0.50 –1.0 0.50 –1.0 0.25 –1.5 0.25 –1.5 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 PIN (dBm) 10 –2.0 Figure 12. VOUT and Log Conformance vs. Input Amplitude at 3.6 GHz, Multiple Devices, RTADJ = 8 kΩ 2.00 2.0 1.75 1.5 1.75 1.5 1.50 1.0 1.50 1.0 1.25 0.5 1.25 0.5 1.00 0 1.00 0 0.75 –0.5 0.75 –0.5 0.50 –1.0 0.50 –1.0 0.25 –1.5 0.25 –1.5 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 –2.0 0 5 VOUT (V) 2.0 ERROR (dB) 2.00 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 05541-010 VOUT (V) 5 PIN (dBm) Figure 9. VOUT and Log Conformance vs. Input Amplitude at 900 MHz, Multiple Devices, RTADJ = 18 kΩ 10 PIN (dBm) –2.0 0 5 10 PIN (dBm) Figure 10. VOUT and Log Conformance vs. Input Amplitude at 1.9 GHz, Multiple Devices, RTADJ = 8 kΩ Figure 13. VOUT and Log Conformance vs. Input Amplitude at 5.8 GHz, Multiple Devices, RTADJ = 500 Ω 2.00 2.0 1.75 1.5 1.75 1.5 1.50 1.0 1.50 1.0 1.25 0.5 1.25 0.5 1.00 0 1.00 0 0.75 –0.5 0.75 –0.5 0.50 –1.0 0.50 –1.0 0.25 –1.5 0.25 –1.5 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 –2.0 VOUT (V) 2.0 ERROR (dB) 2.00 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 05541-011 VOUT (V) 0 05541-012 –2.0 PIN (dBm) Figure 11. VOUT and Log Conformance vs. Input Amplitude at 2.2 GHz, Multiple Devices, RTADJ = 8 kΩ ERROR (dB) 10 05541-013 5 0 5 ERROR (dB) 0 –2.0 10 PIN (dBm) Figure 14. VOUT and Log Conformance vs. Input Amplitude at 8.0 GHz, Multiple Devices, RTADJ = Open, Error Calculated from PIN = −34 dBm to PIN = −16 dBm Rev. D | Page 8 of 19 05541-014 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 VOUT (V) 2.0 ERROR (dB) 2.00 ERROR (dB) Data Sheet 05541-009 VOUT (V) AD8317 Data Sheet AD8317 j1 10000 j0.2 1 2 100MHz –j0.2 900MHz 1900MHz 8000MHz –j2 –j0.5 –20dBm –10dBm 100 0dBm 2200MHz 10 1k 3600MHz 5800MHz 10000 NOISE SPECTRAL DENSITY (nV/ Hz) Δ : 1.86V @ : 1.69V 05541-017 3 Ch3 500mV Ch4 200mV M4.00µs A Ch3 T 12.7560µs 1000 100 10 1k 620mV 10k 100k 10M 1M FREQUENCY (Hz) Figure 19. Noise Spectral Density of Output Buffer (from CLPF to VOUT); CLPF = 0.1 μF Figure 16. Power-On/Power-Off Response Time; VPOS = 3.0 V; Input AC-Coupling Capacitors = 10 pF; CLPF = Open VOUT (V) CH1 RISE 10.44ns 05541-016 CH1 FALL 6.113ns M20.0ns A CH1 T 943.600ns 10M 1M Figure 18. Noise Spectral Density of Output; CLPF = Open Figure 15. Input Impedance vs. Frequency; No Termination Resistor on INHI (Impedance De-Embedded to Input Pins), Z0 = 50 Ω CH1 200mV 100k FREQUENCY (Hz) 05541-015 10000MHz 4 10k –j1 START FREQUENCY = 0.05GHz STOP FREQUENCY = 10GHz RF OFF 2.00 2.0 1.75 1.5 1.50 1.0 1.25 0.5 1.00 0 0.75 –0.5 0.50 –1.0 0.25 1.40V 0 –65 Figure 17. VOUT Pulse Response Time; Pulsed RF Input 0.1 GHz, −10 dBm; CLPF = Open; RLOAD = 150 Ω Rev. D | Page 9 of 19 3.3V 3.0V 3.6V –55 ERROR (dB) 0.5 –40dBm –1.5 –45 –35 –25 –15 PIN (dBm) –5 5 15 –2.0 Figure 20. Output Voltage Stability vs. Supply Voltage at 1.9 GHz When VPOS Varies by 10% 05541-020 0.2 1000 05541-019 0 –60dBm 05541-018 NOISE SPECTRAL DENSITY (nV/ Hz) j2 j0.5 AD8317 Data Sheet THEORY OF OPERATION The AD8317 is a 6-stage demodulating logarithmic amplifier, specifically designed for use in RF measurement and power control applications at frequencies up to 10 GHz. A block diagram is shown in Figure 21. Sharing much of its design with the AD8318 logarithmic detector/controller, the AD8317 maintains tight intercept variability vs. temperature over a 50 dB range. Additional enhancements over the AD8318, such as a reduced RF burst response time of 6 ns to 10 ns, 22 mA supply current, and board space requirements of only 2 mm × 3 mm, add to the low cost and high performance benefits of the AD8317. VPOS GAIN BIAS DET DET DET TADJ SLOPE V I VSET I V VOUT DET CLPF INHI COMM 05541-021 INLO Figure 21. Block Diagram A fully differential design, using a proprietary, high speed SiGe process, extends high frequency performance. Input INHI receives the signal with a low frequency impedance of nominally 500 Ω in parallel with 0.7 pF. The maximum input with ±1 dB logconformance error is typically 0 dBm (referenced to 50 Ω). The noise spectral density referred to the input is 1.15 nV/Hz, which is equivalent to a voltage of 118 μV rms in a 10.5 GHz bandwidth or a noise power of −66 dBm (referenced to 50 Ω). This noise spectral density sets the lower limit of the dynamic range. However, the low end accuracy of the AD8317 is enhanced by specially shaping the demodulating transfer characteristic to partially compensate for errors due to internal noise. The common pin, COMM, provides a quality low impedance connection to the printed circuit board (PCB) ground. The package paddle, which is internally connected to the COMM pin, must also be grounded to the PCB to reduce thermal impedance from the die to the PCB. The logarithmic function is approximated in a piecewise fashion by six cascaded gain stages. (For a more comprehensive explanation of the logarithm approximation, see the AD8307 data sheet.) The cells have a nominal voltage gain of 9 dB each and a 3 dB bandwidth of 10.5 GHz. Using precision biasing, the gain is stabilized over temperature and supply variations. The overall dc gain is high, due to the cascaded nature of the gain stages. An offset compensation loop is included to correct for offsets within the cascaded cells. At the output of each of the gain stages, a square-law detector cell is used to rectify the signal. The RF signal voltages are converted to a fluctuating differential current having an average value that increases with signal level. Along with the six gain stages and detector cells, an additional detector is included at the input of the AD8317, providing a 50 dB dynamic range in total. After the detector currents are summed and filtered, the following function is formed at the summing node: ID × log10(VIN/VINTERCEPT) (1) where: ID is the internally set detector current. VIN is the input signal voltage. VINTERCEPT is the intercept voltage (that is, when VIN = VINTERCEPT, the output voltage would be 0 V, if it were capable of going to 0 V). Rev. D | Page 10 of 19 Data Sheet AD8317 USING THE AD8317 The AD8317 is specified for operation up to 10 GHz; as a result, low impedance supply pins with adequate isolation between functions are essential. A power supply voltage of between 3.0 V and 5.5 V must be applied to VPOS. Power supply decoupling capacitors of 100 pF and 0.1 μF must be connected close to this power supply pin. VS (3.0V TO 5.5V) C5 0.1µF R2 0Ω C4 100pF C2 VOUT 8 INLO 7 VPOS R1 52.3Ω 6 TADJ 5 VOUT R4 0Ω AD8317 INHI 1 C1 SIGNAL INPUT COMM 2 CLPF 3 47nF VSET 4 2 1SEE THE TEMPERATURE COMPENSATION OF OUTPUT VOLTAGE SECTION. 2SEE THE OUTPUT FILTERING SECTION. 05541-022 47nF 1 Figure 22. Basic Connections Figure 22) combines with the relatively high input impedance to give an adequate broadband 50 Ω match. The coupling time constant, 50 × CC/2, forms a high-pass corner with a 3 dB attenuation at fHP = 1/(2π × 50 × CC ), where C1 = C2 = CC. Using the typical value of 47 nF, this high-pass corner is ~68 kHz. In high frequency applications, fHP must be as large as possible to minimize the coupling of unwanted low frequency signals. In low frequency applications, add a simple RC network forming a low-pass filter at the input for similar reasons. This low-pass filter network must generally be placed at the generator side of the coupling capacitors, thereby lowering the required capacitance value for a given high-pass corner frequency. OUTPUT INTERFACE The VOUT pin is driven by a PNP output stage. An internal 10 Ω resistor is placed in series with the output and the VOUT pin. The rise time of the output is limited mainly by the slew on CLPF. The fall time is an RC-limited slew given by the load capacitance and the pull-down resistance at VOUT. There is an internal pull-down resistor of 1.6 kΩ. A resistive load at VOUT is placed in parallel with the internal pull-down resistor to provide additional discharge current. The paddle of the LFCSP package is internally connected to COMM. For optimum thermal and electrical performance, the paddle must be soldered to a low impedance ground plane. VPOS CLPF 10Ω + 0.8V – INPUT SIGNAL COUPLING The RF input (INHI) is single-ended and must be ac-coupled. The INLO (input common) must be ac-coupled to ground. Suggested coupling capacitors are 47 nF ceramic 0402-style capacitors for input frequencies of 1 MHz to 10 GHz. The coupling capacitors must be mounted close to the INHI and INLO pins. The coupling capacitor values can be increased to lower the high-pass cutoff frequency of the input stage. The high-pass corner is set by the input coupling capacitors and the internal 10 pF high-pass capacitor. The dc voltage on INHI and INLO is approximately one diode voltage drop below VPOS. CURRENT VPOS 5pF 18.7kΩ VOUT 1200Ω 05541-024 BASIC CONNECTIONS 400Ω COMM Figure 24. Output Interface To reduce the fall time, load VOUT with a resistive load of