AD8319-EVAL

1 MHz to 10 GHz, 40 dB Log Detector/Controller AD8319 FEATURES Wide bandwidth: 1 MHz to 10 GHz High accuracy: ±1.0 dB over temperature >40 dB dynamic range up to 8 GHz Stability over temperature ±0.5 dB Low noise measurement/controller output VOUT Pulse response time: 8/10 ns (fall/rise) Small footprint 2 mm x 3 mm CSP package Supply operation: 3.0V to 5.5V @ 22 mA Fabricated using high speed SiGe process FUNCTIONAL BLOCK DIAGRAM VPOS TADJ GAIN BIAS SLOPE I V VSET I DET INHI INLO DET DET DET V VOUT CLPF COMM APPLICATIONS RF transmitter PA setpoint control and level monitoring Power monitoring in radiolink transmitters RSSI measurement in base stations, WLAN, WiMAX, radar Figure 1. GENERAL DESCRIPTION The AD8319 is a demodulating logarithmic amplifier, capable of accurately converting an RF input signal to a corresponding decibel-scaled output. It employs the progressive compression technique over a cascaded amplifier chain, each stage of which is equipped with a detector cell. The device can be used in either measurement or controller modes. The AD8319 maintains accurate log conformance for signals of 1 MHz to 8 GHz and provides useful operation to 10 GHz. The input dynamic range is typically 40 dB (re: 50 Ω) with error less than ±1 dB. The AD8319 has 8/10 ns response time (fall time/rise time) that enables RF burst detection to a pulse rate of beyond 50 MHz. The device provides unprecedented logarithmic intercept stability vs. ambient temperature conditions. A supply of 3.0 V to 5.5 V is required to power the device. Current consumption is typically 22 mA, and it decreases to 200 μA when the device is disabled. The AD8319 can be configured to provide a control voltage to a power amplifier or a measurement output from the VOUT pin. Because the output can be used for controller applications, special attention has been paid to minimize wideband noise. In this mode, the setpoint control voltage is applied to the VSET pin. The feedback loop through an RF amplifier is closed via VOUT, the output of which regulates the amplifier’s output to a magnitude corresponding to VSET. The AD8319 provides 0 V to (VPOS − 0.1 V) output capability at the VOUT pin, suitable for controller applications. As a measurement device, VOUT is externally connected to VSET to produce an output voltage VOUT that is a decreasing linear-in-dB function of the RF input signal amplitude. The logarithmic slope is −22 mV/dB, determined by the VSET interface. The intercept is +15 dBm (re: 50 Ω, CW input) using the INHI input. These parameters are very stable against supply and temperature variations. The AD8319 is fabricated on a SiGe bipolar IC process and is available in a 2 mm × 3 mm, 8-lead LFCSP_VD package for an operating temperature range of –40oC to +85oC. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved. 05705-001 AD8319 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 10 Using the AD8319 .......................................................................... 11 Basic Connections ...................................................................... 11 Input Signal Coupling................................................................ 11 Output Interface ......................................................................... 11 Setpoint Interface ....................................................................... 11 Temperature Compensation of Output Voltage..................... 12 Measurement Mode ................................................................... 12 Setting the Output Slope in Measurement Mode .................. 13 Controller Mode......................................................................... 13 Output Filtering.......................................................................... 15 Operation Beyond 8 GHz ......................................................... 15 Evaluation Board ............................................................................ 16 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 18 REVISION HISTORY 10/05—Revision 0: Initial Version Rev. 0 | Page 2 of 20 AD8319 SPECIFICATIONS VPOS = 3 V, CLPF = 1000 pF, TA = 25°C, 52.3 Ω termination resistor at INHI, unless otherwise noted. Table 1. Parameter SIGNAL INPUT INTERFACE Specified Frequency Range DC Common-Mode Voltage MEASUREMENT MODE f = 900 MHz Input Impedance ±1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope 1 Intercept1 Output Voltage: High Power In Output Voltage: Low Power In f = 1.9 GHz Input Impedance ±1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope1 Intercept1 Output Voltage: High Power In Output Voltage: Low Power In f = 2.2 GHz Input Impedance ±1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope1 Intercept1 Output Voltage: High Power In Output Voltage: Low Power In f = 3.6 GHz Input Impedance ±1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope1 Intercept1 Output Voltage: High Power In Output Voltage: Low Power In Conditions INHI (Pin 1) Min 0.001 VPOS – 0.6 VOUT (Pin 5) shorted to VSET (Pin 4), sinusoidal input signal RTADJ = 18 kΩ TA = +25°C −40°C < TA < +85°C ±1 dB error ±1 dB error −25 12 PIN = –10 dBm PIN = –40 dBm RTADJ = 8 kΩ TA = +25°C −40°C < TA < +85°C ±1 dB error ±1 dB error −25 10 PIN = –10 dBm PIN = –35 dBm RTADJ = 8 kΩ TA = +25°C −40°C < TA < +85°C ±1 dB error ±1 dB error 1500||0.33 40 40 −3 −43 −22 15 0.57 1.25 950||0.38 40 40 −4 −44 −22 13 0.53 1.19 810||0.39 40 40 −5 −45 −22 13 0.5 1.18 300||0.33 40 36 −6 −46 −22 10 0.46 1.14 Ω||pF dB dB dBm dBm mV/dB dBm V V Ω||pF dB dB dBm dBm mV/dB dBm V V Ω||pF dB dB dBm dBm mV/dB dBm V V Ω||pF dB dB dBm dBm mV/dB dBm V V Typ Max 10 Unit GHz V −19.5 21 −19.5 20 PIN = –10 dBm PIN = –35 dBm RTADJ = 8 kΩ TA = +25°C −40°C < TA < +85°C ±1 dB error ±1 dB error PIN = –10 dBm PIN = –40 dBm Rev. 0 | Page 3 of 20 AD8319 Parameter f = 5.8 GHz Input Impedance ±1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope1 Intercept1 Output Voltage: High Power In Output Voltage: Low Power In f = 8.0 GHz Input Impedance ±1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope 2 Intercept2 Output Voltage: High Power In Output Voltage: Low Power In OUTPUT INTERFACE Voltage Swing Output Current Drive Small Signal Bandwidth Output Noise Fall Time Fall Time Rise Time Rise Time Video Bandwidth (or Envelope Bandwidth) VSET INTERFACE Nominal Input Range Logarithmic Scale Factor Input Resistance TADJ INTERFACE Input Resistance Disable Threshold Voltage POWER INTERFACE Supply Voltage Quiescent Current vs. Temperature Disable Current 1 2 Conditions RTADJ = 500 Ω TA = +25°C −40°C < TA < +85°C ±1 dB error ±1 dB error Min Typ 110||0.05 40 40 −3 −43 −22 15 0.57 1.25 28||0.79 40 31 −1 −41 −22 20 0.67 1.34 VPOS – 0.1 10 10 140 90 18 6 20 10 50 Max Unit Ω||pF dB dB dBm dBm mV/dB dBm V V Ω||pF dB dB dBm dBm mV/dB dBm V V V mV mA MHz nV/√Hz ns ns ns ns MHz PIN = –10 dBm PIN = –40 dBm RTADJ = open TA = +25°C −40°C < TA < +85°C ± 1 dB error ± 1 dB error PIN = –10 dBm PIN = –40 dBm VOUT (Pin 5) VSET = 0 V; RFIN = open VSET = 1.5 V; RFIN = open VSET = 0 V; RFIN = open RFIN = −10 dBm; from CLPF to VOUT RF Input = 2.2 GHz, –10 dBm, fNOISE = 100 kHz, CLPF = open Input level = no signal to −10 dBm, 90% to 10%; CLPF = 8 pF Input level = no signal to −10 dBm, 90% to 10%; CLPF = open; ROUT = 150 Ω Input level = –10 dBm to no signal, 10% to 90%; CLPF = 8 pF Input level = –10 dBm to no signal, 10% to 90%; CLPF = open; ROUT = 150 Ω VSET (Pin 4) RFIN = 0 dBm; measurement mode RFIN = –40 dBm; measurement mode RFIN = −20 dBm; controller mode; VSET = 1 V TADJ (Pin 6) TADJ = 0.9 V, sourcing 50 μA TADJ = Open VPOS (Pin 7) 3.0 18 −40°C ≤ TA ≤ +85°C TADJ = VPOS 0.35 1.23 −45 40 40 VPOS – 0.4 5.5 30 V dB/V kΩ kΩ 22 60 200 V mA μA/°C μA Slope and intercept are determined by calculating the best-fit line between the power levels of −40 dBm and −10 dBm at the specified input frequency. Slope and intercept are determined by calculating the best-fit line between the power levels of −34 dBm and −16 dBm at 8.0 GHz. Rev. 0 | Page 4 of 20 AD8319 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage: VPOS VSET Voltage Input Power (Single-Ended, Re: 50 Ω) Internal Power Dissipation θJA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering 60 sec) Rating 5.7 V 0 to VPOS 12 dBm 0.73 55°C/W 125°C −40°C to +85°C −65°C to +150°C 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 5 of 20 AD8319 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INHI 1 COMM 2 CLPF 3 VSET 4 8 INLO AD8319 TOP VIEW (Not to Scale) 7 VPOS 6 TADJ 5 VOUT 05705-002 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 3 4 5 Mnemonic INHI COMM CLPF VSET VOUT Description RF Input. Nominal input range of −50 dBm to 0 dBm, re: 50 Ω; ac-coupled RF input. Device Common. Connect to a low impedance ground plane. Loop Filter Capacitor. In measurement mode, this capacitor sets the pulse response time and video bandwidth. In controller mode, the capacitance on this node sets the response time of the error amplifier/integrator. Setpoint Control Input for Controller Mode or Feedback Input for Measurement Mode. Measurement and Controller Output. In measurement mode, VOUT provides a decreasing linear-in dB representation of the RF input signal amplitude. In controller mode, VOUT is used to control the gain of a VGA or VVA with a positive gain sense (increasing voltage increases gain). Temperature Compensation Adjustment. Frequency-dependent temperature compensation is set by connecting a ground-referenced resistor to this pin. Positive Supply Voltage: 3.0 V to 5.5 V. RF Common for INHI. AC-coupled RF common. Internally connected to COMM; solder to a low impedance ground plane. 6 7 8 TADJ VPOS INLO Paddle Rev. 0 | Page 6 of 20 AD8319 TYPICAL PERFORMANCE CHARACTERISTICS VPOS = 3 V; T = 25°C, –40°C, +85°C; CLPF = 1000 pF; unless otherwise noted. Colors: 25°C Black; -40°C Blue; 85°C Red Error is calculated by using the best-fit line between PIN = −40 dBm and PIN = −10 dBm at the specified input frequency, unless otherwise noted. 2.00 1.75 1.50 1.25 VOUT (V) 2.0 1.5 1.0 ERROR (dB) 2.00 1.75 1.50 1.25 VOUT (V) 2.0 1.5 1.0 ERROR (dB) 05705-008 0.5 0 –0.5 –1.0 –1.5 –2.0 –50 –40 –30 –20 –10 0 10 PIN (dBm) 0.5 0 –0.5 –1.0 –1.5 –2.0 –50 –40 –30 –20 –10 0 10 PIN (dBm) 1.00 0.75 0.50 0.25 0 –60 1.00 0.75 0.50 0.25 0 –60 05705-003 Figure 3. VOUT and Log Conformance vs. Input Amplitude at 900 MHz, RTADJ = 18 kΩ 2.00 1.75 1.50 1.25 VOUT (V) Figure 6. VOUT and Log Conformance vs. Input Amplitude at 3.6 GHz, RTADJ = 8 kΩ 2.00 1.75 1.50 ERROR (dB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –50 –40 –30 –20 –10 0 10 PIN (dBm) 2.0 1.5 1.0 ERROR (dB) ERROR (dB) 05705-007 1.25 VOUT (V) 0.5 0 –0.5 –1.0 –1.5 –2.0 –50 –40 –30 –20 –10 0 10 PIN (dBm) 1.00 0.75 0.50 0.25 0 –60 1.00 0.75 0.50 0.25 0 –60 Figure 4. VOUT and Log Conformance vs. Input Amplitude at 1.9 GHz, RTADJ = 8 kΩ 2.00 1.75 1.50 1.25 VOUT (V) 05705-004 Figure 7. VOUT and Log Conformance vs. Input Amplitude at 5.8 GHz, RTADJ = 500 Ω 2.00 1.75 1.50 ERROR (dB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –50 –40 –30 –20 –10 0 10 PIN (dBm) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –50 –40 –30 –20 –10 0 10 PIN (dBm) 1.25 VOUT (V) 1.00 0.75 0.50 0.25 0 –60 1.00 0.75 0.50 0.25 0 –60 Figure 5. VOUT and Log Conformance vs. Input Amplitude at 2.2 GHz, RTADJ = 8 kΩ Rev. 0 | Page 7 of 20 05705-005 Figure 8. VOUT and Log Conformance vs. Input Amplitude at 8.0 GHz, RTADJ = Open, Error Calculated from PIN = −34 dBm to PIN = -16 dBm 05705-006 AD8319 2.00 1.75 1.50 1.25 VOUT (V) 2.00 1.75 1.50 ERROR (dB) 2.00 1.75 1.50 1.25 VOUT (V) 2.0 1.5 1.0 ERROR (dB) 05705-014 1.25 1.00 0.75 0.50 0.25 0 –50 –40 –30 –20 –10 0 10 PIN (dBm) 0.5 0 –0.5 –1.0 –1.5 –2.0 –50 –40 –30 –20 –10 0 10 PIN (dBm) 1.00 0.75 0.50 0.25 0 –60 1.00 0.75 0.50 0.25 0 –60 Figure 9. VOUT and Log Conformance vs. Input Amplitude at 900 MHz, Multiple Devices, RTADJ = 18 kΩ 2.00 1.75 1.50 1.25 VOUT (V) 05705-009 Figure 12. VOUT and Log Conformance vs. Input Amplitude at 3.6 GHz, Multiple Devices, RTADJ = 8 kΩ 2.00 1.75 1.50 ERROR (dB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –50 –40 –30 –20 –10 0 10 PIN (dBm) 2.0 1.5 1.0 ERROR (dB) ERROR (dB) 05705-013 1.25 VOUT (V) 0.5 0 –0.5 –1.0 –1.5 –2.0 –50 –40 –30 –20 –10 0 10 PIN (dBm) 1.00 0.75 0.50 0.25 0 –60 1.00 0.75 0.50 0.25 Figure 10. VOUT and Log Conformance vs. Input Amplitude at 1.9 GHz, Multiple Devices, RTADJ = 8 kΩ 2.00 1.75 1.50 1.25 VOUT (V) 05705-010 0 –60 Figure 13. VOUT and Log Conformance vs. Input Amplitude at 5.8 GHz, Multiple Devices, RTADJ = 500 Ω 2.00 1.75 1.50 ERROR (dB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –50 –40 –30 –20 –10 0 10 PIN (dBm) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –50 –40 –30 –20 –10 0 10 PIN (dBm) 1.25 VOUT (V) 1.00 0.75 0.50 0.25 0 –60 1.00 0.75 0.50 0.25 Figure 11. VOUT and Log Conformance vs. Input Amplitude at 2.2 GHz, Multiple Devices, RTADJ = 8 kΩ 05705-011 0 –60 Figure 14. VOUT and Log Conformance vs. Input Amplitude at 8.0 GHz, Multiple Devices, RTADJ =Open, Error Calculated from PIN = −34 dBm to PIN = −16 dBm Rev. 0 | Page 8 of 20 05705-012 AD8319 j1 j0.5 j2 10000 j0.2 NOISE SPECTRAL DENSITY (nV/ Hz) –60dBm 1000 RF OFF –20dBm 100 –40dBm –10dBm 0 0.2 0.5 1 2 100MHz –j0.2 900MHz 1900MHz 8000MHz –j0.5 –j2 –j1 05705-015 3600MHz START FREQUENCY = 0.05GHz STOP FREQUENCY = 10GHz 10000MHz 10 1k 10k 100k FREQUENCY (Hz) 1M 10M 5800MHz Figure 15. Input Impedance vs. Frequency; No Termination Resistor on INHI (Impedance De-Embedded to Input Pins), Z0 = 50 Ω Δ : 1.53V @ : 1.53V Figure 18. Noise Spectral Density of Output; CLPF = Open 10000 NOISE SPECTRAL DENSITY (nV/ Hz) 1000 100 1 05705-016 Ch1 500mV M2.00μs T 29.60% A CH1 420V 10 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 16. Power On/Off Response Time; VP = 3.0 V; Input AC-Coupling Caps = 10 pF; CLPF = Open Figure 19. Noise Spectral Density of Output Buffer (from CLPF to VOUT); CLPF = 0.1 μF 2.00 2.0 3.3V 1.75 1.50 1.25 3.0V 3.6V 1.5 1.0 CH1 RISE 9.949ns CH1 FALL 6.032ns 1.00 0.75 0.50 0.25 0 –0.5 –1.0 –1.5 –2.0 0 5 10 05705-017 Ch1 200mV M20.0ns T 72.40% A CH1 1.04V PIN (dBm) Figure 17. VOUT Pulse Response Time; Pulsed RF Input 0.1 GHz, −10 dBm; CLPF = Open; RLOAD = 150 Ω Figure 20. Output Voltage Stability vs. Supply Voltage at 1.9 GHz When VPOS Varies by 10% Rev. 0 | Page 9 of 20 05705-020 1 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 ERROR (dB) 0.5 VOUT (V) 05705-019 05705-018 2200MHz 0dBm AD8319 THEORY OF OPERATION The AD8319 is a 5-stage demodulating logarithmic amplifier, specifically designed for use in RF measurement and power control applications at frequencies up to 10 GHz. A block diagram is shown in Figure 21. Sharing much of its design with the AD8318 logarithmic detector/controller, the AD8319 maintains tight intercept variability vs. temperature over a 40 dB range. Additional enhancements over the AD8318, such as reduced RF burst response time of 8 ns to 10 ns, 22 mA supply current, and board space requirements of only 2 mm x 3 mm add to the low cost and high performance benefits found in the AD8319. VPSO TADJ The logarithmic function is approximated in a piecewise fashion by five cascaded gain stages. (For a more comprehensive explanation of the logarithm approximation, please refer to the AD8307 data sheet, available at www.analog.com.) The cells have a nominal voltage gain of 9 dB each and a 3 dB bandwidth of 10.5 GHz. Using precision biasing, the gain is stabilized over temperature and supply variations. The overall dc gain is high due to the cascaded nature of the gain stages. An offset compensation loop is included to correct for offsets within the cascaded cells. At the output of each of the gain stages, a squarelaw detector cell is used to rectify the signal. The RF signal voltages are converted to a fluctuating differential current having an average value that increases with signal level. Along with the five gain stages and detector cells, an additional detector is included at the input of the AD8319, providing a 40 dB dynamic range in total. After the detector currents are summed and filtered, the following function is formed at the summing node: ID × log10(VIN/VINTERCEPT) where: ID is the internally set detector current. VIN is the input signal voltage. VINTERCEPT is the intercept voltage (that is, when VIN = VINTERCEPT, the output voltage would be 0 V, if it were capable of going to 0 V). GAIN BIAS SLOPE V I VSET I DET INHI INLO DET DET DET V VOUT CLPF COMM Figure 21. Block Diagram A fully differential design, using a proprietary, high speed SiGe process, extends high frequency performance. Input INHI receives the signal with a low frequency impedance of nominally 500 Ω in parallel with 0.7 pF. The maximum input with ±1 dB log-conformance error is typically 0 dBm (re: 50 Ω). The noise spectral density referred to the input is 1.15 nV/√Hz, which is equivalent to a voltage of 118 μV rms in a 10.5 GHz bandwidth or a noise power of −66 dBm (re: 50 Ω). This noise spectral density sets the lower limit of the dynamic range. However, the low end accuracy of the AD8319 is enhanced by specially shaping the demodulating transfer characteristic to partially compensate for errors due to internal noise. The common pin, COMM, provides a quality low impedance connection to the printed circuit board (PCB) ground. The package paddle, which is internally connected to the COMM pin, should also be grounded to the PCB to reduce thermal impedance from the die to the PCB. Rev. 0 | Page 10 of 20 05705-021 AD8319 USING THE AD8319 BASIC CONNECTIONS The AD8319 is specified for operation up to 10 GHz, as a result, low impedance supply pins with adequate isolation between functions are essential. A power supply voltage of between 3.0 V and 5.5 V should be applied to VPOS. Power supply decoupling capacitors of 100 pF and 0.1 μF should be connected close to this power supply pin. VS(2.7V–5.5V) C5 0.1μF C4 100pF R2 0Ω SEE TEXT VOUT 47nF 8 INLO R1 52.3Ω INHI 1 7 VPOS 6 TADJ 5 VOUT R4 0Ω VSET 4 05705-022 combines with the relatively high input impedance to give an adequate broadband 50 Ω match. The coupling time constant, 50 × CC/2, forms a high-pass corner with a 3 dB attenuation at fHP = 1/(2π × 50 × CC ), where C1 = C2 = CC. Using the typical value of 47 nF, this high-pass corner will be ~68 kHz. In high frequency applications, fHP should be as large as possible to minimize the coupling of unwanted low frequency signals. In low frequency applications, a simple RC network forming a low-pass filter should be added at the input for similar reasons. This should generally be placed at the generator side of the coupling capacitors, thereby lowering the required capacitance value for a given high-pass corner frequency. C2 OUTPUT INTERFACE The VOUT pin is driven by a PNP output stage. An internal 10 Ω resistor is placed in series with the output and the VOUT pin. The rise time of the output is limited mainly by the slew on CLPF. The fall time is an RC-limited slew given by the load capacitance and the pull-down resistance at VOUT. There is an internal pull-down resistor of 1.6 kΩ. A resistive load at VOUT is placed in parallel with the internal pull-down resistor to provide additional discharge current. VPOS CLPF 10Ω + 0.8V – 1200Ω 400Ω COMM 05705-024 AD8319 C1 47nF COMM 2 CLPF 3 SIGNAL INPUT SEE TEXT Figure 22. Basic Connections The paddle of the LFCSP package is internally connected to COMM. For optimum thermal and electrical performance, the paddle should be soldered to a low impedance ground plane. INPUT SIGNAL COUPLING The RF input (INHI) is single-ended and must be ac-coupled. INLO (input common) should be ac-coupled to ground. Suggested coupling capacitors are 47 nF ceramic 0402-style capacitors for input frequencies of 1 MHz to 10 GHz. The coupling capacitors should be mounted close to the INHI and INLO pins. The coupling capacitor values can be increased to lower the input stage’s high-pass cutoff frequency. The highpass corner is set by the input coupling capacitors and the internal 10 pF high-pass capacitor. The dc voltage on INHI and INLO is about one diode voltage drop below VPOS. VPOS 5pF 5pF FIRST GAIN STAGE 2kΩ INLO Gm STAGE OFFSET COMP 05705-023 VOUT Figure 24. Output Interface To reduce the fall time, VOUT should be loaded with a resistive load of