1 MHz to 10 GHz, 45 dB
Log Detector/Controller
AD8319
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VPOS
GAIN
BIAS
DET
DET
DET
TADJ
SLOPE
I
V
VSET
I
V
VOUT
DET
CLPF
INHI
INLO
COMM
APPLICATIONS
05705-001
Wide bandwidth: 1 MHz to 10 GHz
High accuracy: ±1.0 dB over temperature
45 dB dynamic range up to 8 GHz
Stability over temperature: ±0.5 dB
Low noise measurement/controller output VOUT
Pulse response time (fall/rise): 6 ns/10 ns
Small footprint: 2 mm × 3 mm LFCSP
Supply operation: 3.0 V to 5.5 V @ 22 mA
Fabricated using high speed SiGe process
Figure 1.
RF transmitter PA setpoint controls and level monitoring
Power monitoring in radiolink transmitters
RSSI measurement in base stations, WLANs, WiMAX,
and radars
GENERAL DESCRIPTION
The AD8319 is a demodulating logarithmic amplifier, capable
of accurately converting an RF input signal to a corresponding
decibel-scaled output. It employs the progressive compression
technique over a cascaded amplifier chain, each stage of which
is equipped with a detector cell. The device can be used in either
measurement or controller modes. The AD8319 maintains
accurate log conformance for signals of 1 MHz to 8 GHz and
provides useful operation to 10 GHz. The input dynamic range
is typically 45 dB (re: 50 Ω) with error less than ±3 dB. The
AD8319 has 6 ns/10 ns (fall time/rise time) response time that
enables RF burst detection to a pulse rate of beyond 50 MHz.
The device provides unprecedented logarithmic intercept stability
vs. ambient temperature conditions. A supply of 3.0 V to 5.5 V
is required to power the device. Current consumption is typically
22 mA, and it decreases to 200 µA when the device is disabled.
The AD8319 can be configured to provide a control voltage to
a power amplifier or a measurement output from the VOUT
pin. Because the output can be used for controller applications,
special attention was paid to minimize wideband noise. In this
mode, the setpoint control voltage is applied to the VSET pin.
Rev. D
The feedback loop through an RF amplifier is closed via VOUT,
the output of which regulates the output of the amplifier to a
magnitude corresponding to VSET. The AD8319 provides 0 V to
(VPOS − 0.1 V) output capability at the VOUT pin, suitable for
controller applications. As a measurement device, VOUT is
externally connected to VSET to produce an output voltage,
VOUT, that is a decreasing linear-in-dB function of the RF input
signal amplitude.
The logarithmic slope is −22 mV/dB, determined by the VSET
interface. The intercept is 15 dBm (re: 50 Ω, CW input) using
the INHI input. These parameters are very stable against supply
and temperature variations.
The AD8319 is fabricated on a SiGe bipolar IC process and is
available in a 2 mm × 3 mm, 8-lead LFCSP for an operating
temperature range of −40°C to +85°C.
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Tel: 781.329.4700 ©2005–2017 Analog Devices, Inc. All rights reserved.
Technical Support
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AD8319
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Signal Coupling ................................................................ 11
Applications ....................................................................................... 1
Output Interface ......................................................................... 11
Functional Block Diagram .............................................................. 1
Setpoint Interface ....................................................................... 11
General Description ......................................................................... 1
Temperature Compensation of Output Voltage ..................... 12
Revision History ............................................................................... 2
Measurement Mode ................................................................... 12
Specifications..................................................................................... 3
Setting the Output Slope in Measurement Mode .................. 13
Absolute Maximum Ratings ............................................................ 5
Controller Mode ......................................................................... 13
ESD Caution .................................................................................. 5
Output Filtering .......................................................................... 15
Pin Configuration and Function Descriptions ............................. 6
Operation Beyond 8 GHz.......................................................... 16
Typical Performance Characteristics ............................................. 7
Evaluation Board ............................................................................ 17
Theory of Operation ...................................................................... 10
Outline Dimensions ....................................................................... 19
Using the AD8319 .......................................................................... 11
Ordering Guide .......................................................................... 19
Basic Connections ...................................................................... 11
REVISION HISTORY
9/2017—Rev. C to Rev. D
Changed CP-8-1 to CP-8-23 ........................................ Throughout
Changes to Figure 2 .......................................................................... 6
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 19
3/2013—Rev. B to Rev. C
Updated Outline Dimensions ....................................................... 18
4/2008—Rev. A to Rev. B
Changes to Features Section and General Description Section . 1
Changes to Theory of Operation Section .................................... 10
Changes to Figure 22 and Setpoint Interface Section ................ 11
3/2007—Rev. 0 to Rev. A
Changes to Figure 9 .......................................................................... 8
Changes to Figure 22 and Setpoint Interface Section ................ 11
Changes to Measurement Mode Section ..................................... 12
Changes to Layout .......................................................................... 16
Changes to Layout .......................................................................... 17
Updated Outline Dimensions ....................................................... 18
10/2005—Revision 0: Initial Version
Rev. D | Page 2 of 19
Data Sheet
AD8319
SPECIFICATIONS
VPOS = 3 V, CLPF = 1000 pF, TA = 25°C, 52.3 Ω termination resistor at INHI, unless otherwise noted.
Table 1.
Parameter
SIGNAL INPUT INTERFACE
Specified Frequency Range
DC Common-Mode Voltage
MEASUREMENT MODE
f = 900 MHz
Input Impedance
±1 dB Dynamic Range
Maximum Input Level
Minimum Input Level
Slope 1
Intercept1
Output Voltage: High Power In
Output Voltage: Low Power In
f = 1.9 GHz
Input Impedance
±1 dB Dynamic Range
Maximum Input Level
Minimum Input Level
Slope1
Intercept1
Output Voltage: High Power In
Output Voltage: Low Power In
f = 2.2 GHz
Input Impedance
±1 dB Dynamic Range
Maximum Input Level
Minimum Input Level
Slope1
Intercept1
Output Voltage: High Power In
Output Voltage: Low Power In
f = 3.6 GHz
Input Impedance
±1 dB Dynamic Range
Maximum Input Level
Minimum Input Level
Slope1
Intercept1
Output Voltage: High Power In
Output Voltage: Low Power In
Conditions
INHI (Pin 1)
Min
Typ
Max
Unit
10
VPOS − 0.6
GHz
V
1500||0.33
40
40
−3
−43
−22
15
0.57
1.25
Ω||pF
dB
dB
dBm
dBm
mV/dB
dBm
V
V
0.001
VOUT (Pin 5) shorted to VSET (Pin 4),
sinusoidal input signal
RTADJ = 18 kΩ
TA = 25°C
−40°C < TA < +85°C
±1 dB error
±1 dB error
−25
12
PIN = −10 dBm
PIN = −40 dBm
RTADJ = 8 kΩ
TA = 25°C
−40°C < TA < +85°C
±1 dB error
±1 dB error
−25
10
PIN = −10 dBm
PIN = −35 dBm
RTADJ = 8 kΩ
TA = 25°C
−40°C < TA < +85°C
±1 dB error
±1 dB error
PIN = −10 dBm
PIN = −35 dBm
RTADJ = 8 kΩ
TA = 25°C
−40°C < TA < +85°C
±1 dB error
±1 dB error
PIN = −10 dBm
PIN = −40 dBm
Rev. D | Page 3 of 19
950||0.38
40
40
−4
−44
−22
13
0.53
1.19
−19.5
21
−19.5
20
Ω||pF
dB
dB
dBm
dBm
mV/dB
dBm
V
V
810||0.39
40
40
−5
−45
−22
13
0.5
1.18
Ω||pF
dB
dB
dBm
dBm
mV/dB
dBm
V
V
300||0.33
40
36
−6
−46
−22
10
0.46
1.14
Ω||pF
dB
dB
dBm
dBm
mV/dB
dBm
V
V
AD8319
Parameter
f = 5.8 GHz
Input Impedance
±1 dB Dynamic Range
Data Sheet
Conditions
RTADJ = 500 Ω
Min
Typ
Max
Unit
110||0.05
40
40
−3
−43
−22
15
0.57
1.25
Ω||pF
dB
dB
dBm
dBm
mV/dB
dBm
V
V
28||0.79
40
31
−1
−41
−22
20
0.67
1.34
Ω||pF
dB
dB
dBm
dBm
mV/dB
dBm
V
V
VPOS − 0.1
10
10
140
90
V
mV
mA
MHz
nV/√Hz
18
ns
6
ns
20
ns
10
ns
50
MHz
RFIN = −20 dBm; controller mode; VSET = 1 V
0.35
1.23
−45
40
V
V
dB/V
kΩ
TADJ INTERFACE
Input Resistance
Disable Threshold Voltage
TADJ (Pin 6)
TADJ = 0.9 V, sourcing 50 µA
TADJ = open
40
VPOS − 0.4
kΩ
V
POWER INTERFACE
Supply Voltage
Quiescent Current
vs. Temperature
VPOS (Pin 7)
Maximum Input Level
Minimum Input Level
Slope1
Intercept1
Output Voltage: High Power In
Output Voltage: Low Power In
f = 8.0 GHz
Input Impedance
±1 dB Dynamic Range
Maximum Input Level
Minimum Input Level
Slope 2
Intercept2
Output Voltage: High Power In
Output Voltage: Low Power In
OUTPUT INTERFACE
Voltage Swing
Output Current Drive
Small Signal Bandwidth
Output Noise
Fall Time
Rise Time
TA = 25°C
−40°C < TA < +85°C
±1 dB error
±1 dB error
PIN = −10 dBm
PIN = −40 dBm
RTADJ = open
TA = 25°C
−40°C < TA < +85°C
±1 dB error
±1 dB error
PIN = −10 dBm
PIN = −40 dBm
VOUT (Pin 5)
VSET = 0 V; RFIN = open
VSET = 1.5 V; RFIN = open
VSET = 0 V; RFIN = open
RFIN = −10 dBm; from CLPF to VOUT
RFIN = 2.2 GHz, −10 dBm, fNOISE = 100 kHz,
CLPF = open
Input level = no signal to −10 dBm, 90% to 10%;
CLPF = 8 pF
Input level = no signal to −10 dBm, 90% to 10%;
CLPF = open; ROUT = 150 Ω
Input level = −10 dBm to no signal, 10% to 90%;
CLPF = 8 pF
Input level = −10 dBm to no signal, 10% to 90%;
CLPF = open; ROUT = 150 Ω
Video Bandwidth (or Envelope Bandwidth)
VSET INTERFACE
Nominal Input Range
Logarithmic Scale Factor
Input Resistance
Disable Current
1
2
VSET (Pin 4)
RFIN = 0 dBm; measurement mode
RFIN = −40 dBm; measurement mode
3.0
18
−40°C ≤ TA ≤ +85°C
TADJ = VPOS
22
60
5.5
30
200
Slope and intercept are determined by calculating the best fit line between the power levels of −40 dBm and −10 dBm at the specified input frequency.
Slope and intercept are determined by calculating the best fit line between the power levels of −34 dBm and −16 dBm at 8.0 GHz.
Rev. D | Page 4 of 19
V
mA
µA/°C
µA
Data Sheet
AD8319
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage: VPOS
VSET Voltage
Input Power (Single-Ended, re: 50 Ω)
Internal Power Dissipation
θJA
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec)
Rating
5.7 V
0 to VPOS
12 dBm
0.73 W
55°C/W
125°C
−40°C to +85°C
−65°C to +150°C
260°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. D | Page 5 of 19
AD8319
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
8 INLO
COMM 2
CLPF 3
VSET 4
AD8319
TOP VIEW
(Not to Scale)
7 VPOS
6 TADJ
5 VOUT
NOTES
1. THE PAD IS INTERNALLY CONNECTED TO
COMM; SOLDER TO A LOW IMPEDANCE
GROUND PLANE.
05705-002
INHI 1
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
2
3
Mnemonic
INHI
COMM
CLPF
4
5
VSET
VOUT
6
TADJ
7
8
VPOS
INLO
EPAD
Description
RF Input. Nominal input range of −50 dBm to 0 dBm, re: 50 Ω; ac-coupled RF input.
Device Common. Connect this pin to a low impedance ground plane.
Loop Filter Capacitor. In measurement mode, this capacitor sets the pulse response time and video bandwidth.
In controller mode, the capacitance on this node sets the response time of the error amplifier/integrator.
Setpoint Control Input for Controller Mode or Feedback Input for Measurement Mode.
Measurement and Controller Output. In measurement mode, VOUT provides a decreasing linear-in-dB
representation of the RF input signal amplitude. In controller mode, VOUT is used to control the gain of a VGA or
VVA with a positive gain sense (increasing voltage increases gain).
Temperature Compensation Adjustment. Frequency dependent temperature compensation is set by connecting
a ground referenced resistor to this pin.
Positive Supply Voltage, 3.0 V to 5.5 V.
RF Common for INHI. AC-coupled RF common.
The pad is internally connected to COMM; solder to a low impedance ground plane.
Rev. D | Page 6 of 19
Data Sheet
AD8319
TYPICAL PERFORMANCE CHARACTERISTICS
1.75
1.5
1.75
1.5
1.50
1.0
1.50
1.0
1.25
0.5
1.25
0.5
1.00
0
1.00
0
0.75
–0.5
0.75
–0.5
0.50
–1.0
0.50
–1.0
0.25
–1.5
0.25
–1.5
–20
–10
0
–2.0
10
PIN (dBm)
0
–60
–30
–20
–10
0
–2.0
10
Figure 6. VOUT and Log Conformance Error vs.
Input Amplitude at 3.6 GHz, RTADJ = 8 kΩ
2.00
2.0
1.75
1.5
1.75
1.5
1.50
1.0
1.50
1.0
1.25
0.5
1.25
0.5
1.00
0
1.00
0
0.75
–0.5
0.75
–0.5
0.50
–1.0
0.50
–1.0
0.25
–1.5
0.25
–1.5
0
–60
–2.0
–50
–40
–30
–20
–10
0
10
PIN (dBm)
VOUT (V)
2.0
ERROR (dB)
2.00
0
–60
05705-004
VOUT (V)
–40
PIN (dBm)
Figure 3. VOUT and Log Conformance Error vs.
Input Amplitude at 900 MHz, RTADJ = 18 kΩ
–50
–40
–30
–20
–10
0
–2.0
10
PIN (dBm)
Figure 4. VOUT and Log Conformance Error vs.
Input Amplitude at 1.9 GHz, RTADJ = 8 kΩ
Figure 7. VOUT and Log Conformance Error vs.
Input Amplitude at 5.8 GHz, RTADJ = 500 Ω
2.00
2.0
1.75
1.5
1.75
1.5
1.50
1.0
1.50
1.0
1.25
0.5
1.25
0.5
1.00
0
1.00
0
0.75
–0.5
0.75
–0.5
0.50
–1.0
0.50
–1.0
0.25
–1.5
0.25
–1.5
0
–60
–2.0
–50
–40
–30
–20
–10
0
PIN (dBm)
Figure 5. VOUT and Log Conformance Error vs.
Input Amplitude at 2.2 GHz, RTADJ = 8 kΩ
10
VOUT (V)
2.0
ERROR (dB)
2.00
0
–60
05705-005
VOUT (V)
–50
ERROR (dB)
–30
05705-007
–40
–50
–40
–30
–20
PIN (dBm)
–10
0
–2.0
10
ERROR (dB)
–50
05705-008
0
–60
ERROR (dB)
2.0
05705-006
2.00
VOUT (V)
2.0
ERROR (dB)
2.00
05705-003
VOUT (V)
VPOS = 3 V; T = 25°C, −40°C, +85°C; CLPF = 1000 pF; unless otherwise noted. Black: 25°C; Blue: −40°C; Red: +85°C. Error is calculated by
using the best fit line between PIN = −40 dBm and PIN = −10 dBm at the specified input frequency, unless otherwise noted.
Figure 8. VOUT and Log Conformance Error vs. Input Amplitude at 8.0 GHz,
RTADJ = Open, Error Calculated from PIN = −34 dBm to PIN = −16 dBm
Rev. D | Page 7 of 19
2.0
1.75
1.5
1.75
1.5
1.50
1.0
1.50
1.0
1.25
0.5
1.25
0.5
1.00
0
1.00
0
0.75
–0.5
0.75
–0.5
0.50
–1.0
0.50
–1.0
0.25
–1.5
0.25
–1.5
–10
0
10
–40
–30
–20
–10
0
–2.0
10
PIN (dBm)
Figure 12. VOUT and Log Conformance Error vs. Input Amplitude at 3.6 GHz,
Multiple Devices, RTADJ = 8 kΩ
2.00
2.0
1.75
1.5
1.75
1.5
1.50
1.0
1.50
1.0
1.25
0.5
1.25
0.5
1.00
0
1.00
0
0.75
–0.5
0.75
–0.5
0.50
–1.0
0.50
–1.0
0.25
–1.5
0.25
–1.5
0
–60
–50
–40
–30
–20
–10
0
–2.0
10
PIN (dBm)
VOUT (V)
2.0
ERROR (dB)
2.00
0
–60
05705-010
Figure 10. VOUT and Log Conformance Error vs. Input Amplitude at 1.9 GHz,
Multiple Devices, RTADJ = 8 kΩ
–50
–40
–30
–20
–10
0
–2.0
10
PIN (dBm)
Figure 13. VOUT and Log Conformance Error vs. Input Amplitude at 5.8 GHz,
Multiple Devices, RTADJ = 500 Ω
2.0
2.00
2.0
1.75
1.5
1.75
1.5
1.50
1.0
1.50
1.0
1.25
0.5
1.25
0.5
1.00
0
1.00
0
0.75
–0.5
0.75
–0.5
0.50
–1.0
0.50
–1.0
0.25
–1.5
0.25
–1.5
–50
–40
–30
–20
PIN (dBm)
–10
0
–2.0
10
0
–60
05705-011
0
–60
ERROR (dB)
2.00
VOUT (V)
VOUT (V)
Figure 9. VOUT and Log Conformance Error vs. Input Amplitude at 900 MHz,
Multiple Devices, RTADJ = 18 kΩ
–50
Figure 11. VOUT and Log Conformance Error vs. Input Amplitude at 2.2 GHz,
Multiple Devices, RTADJ = 8 kΩ
ERROR (dB)
–20
05705-013
–30
–50
–40
–30
–20
PIN (dBm)
–10
0
–2.0
10
ERROR (dB)
–40
PIN (dBm)
VOUT (V)
0
–60
–2.0
–50
05705-014
0
–60
05705-012
2.00
VOUT (V)
2.0
ERROR (dB)
2.00
ERROR (dB)
Data Sheet
05705-009
VOUT (V)
AD8319
Figure 14. VOUT and Log Conformance Error vs. Input Amplitude at 8.0 GHz,
Multiple Devices, RTADJ = Open, Error Calculated from
PIN = −34 dBm to PIN = −16 dBm
Rev. D | Page 8 of 19
Data Sheet
AD8319
j1
j2
j0.5
NOISE SPECTRAL DENSITY (nV/ Hz)
10k
1
2
100MHz
–j0.2
900MHz
1900MHz
2200MHz
–j0.5
0dBm
–j2
3600MHz
START FREQUENCY = 0.05GHz
STOP FREQUENCY = 10GHz
–j1
10000MHz
5800MHz
Figure 15. Input Impedance vs. Frequency; No Termination Resistor on INHI
(Impedance De-Embedded to Input Pins), Z0 = 50 Ω
10
1k
10M
1M
10k
NOISE SPECTRAL DENSITY (nV/ Hz)
05705-016
A CH1
100k
Figure 18. Noise Spectral Density of Output vs. Frequency; CLPF = Open
1
M2.00µs
T 29.60%
10k
FREQUENCY (Hz)
∆ : 1.53V
@ : 1.53V
Ch1 500mV
–10dBm
–40dBm
100
05705-015
8000MHz
RF OFF
–20dBm
1k
100
10
1k
420V
05705-019
0.5
10k
100k
10M
1M
FREQUENCY (Hz)
Figure 16. Power On/Off Response Time; VP = 3.0 V;
Input AC-Coupling Capacitors = 10 pF; CLPF = Open
Figure 19. Noise Spectral Density of Output Buffer vs. Frequency (from CLPF
to VOUT); CLPF = 0.1 μF
2.0
2.00
1.75
CH1 FALL
6.032ns
1.50
05705-017
VOUT (V)
CH1 RISE
9.949ns
1
Ch1 200mV
M20.0ns
T 72.40%
A CH1
3.3V
3.6V
1.0
1.25
0.5
1.00
0
0.75
–0.5
0.50
–1.0
0.25
–1.5
0
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
1.04V
1.5
3.0V
0
5
10
–2.0
PIN (dBm)
Figure 17. VOUT Pulse Response Time; Pulsed RF Input 0.1 GHz, −10 dBm;
CLPF = Open; RLOAD = 150 Ω
Rev. D | Page 9 of 19
Figure 20. VOUT Stability and Error vs. Supply Voltage at 1.9 GHz
When VPOS Varies by 10%
ERROR (dB)
0.2
05705-020
0
–60dBm
1k
05705-018
j0.2
AD8319
Data Sheet
THEORY OF OPERATION
The AD8319 is a five-stage demodulating logarithmic amplifier,
specifically designed for use in RF measurement and power control
applications at frequencies up to 10 GHz. A block diagram is
shown in Figure 21. Sharing much of its design with the AD8318
logarithmic detector/controller, the AD8319 maintains tight
intercept variability vs. temperature over a 40 dB range. Additional
enhancements over the AD8318, such as reduced RF burst
response time of 6 ns to 10 ns, 22 mA supply current, and
board space requirements of only 2 mm × 3 mm add to the low
cost and high performance benefits found in the AD8319.
VPSO
GAIN
BIAS
DET
DET
DET
TADJ
SLOPE
V
I
VSET
I
V
VOUT
DET
CLPF
INHI
The logarithmic function is approximated in a piecewise fashion
by five cascaded gain stages. (For a detailed explanation of the
logarithm approximation, refer to the AD8307 data sheet.) The
cells have a nominal voltage gain of 9 dB each and a 3 dB
bandwidth of 10.5 GHz. Using precision biasing, the gain is
stabilized over temperature and supply variations. The overall
dc gain is high due to the cascaded nature of the gain stages.
An offset compensation loop is included to correct for offsets
within the cascaded cells. At the output of each of the gain
stages, a square-law detector cell is used to rectify the signal.
The RF signal voltages are converted to a fluctuating differential
current having an average value that increases with signal level.
Along with the five gain stages and detector cells, an additional
detector is included at the input of the AD8319, providing a
40 dB dynamic range in total. After the detector currents are
summed and filtered, the following function is formed at the
summing node:
ID × log10(VIN/VINTERCEPT)
COMM
05705-021
INLO
Figure 21. Block Diagram
A fully differential design, using a proprietary, high speed
SiGe process, extends high frequency performance. Input INHI
receives the signal with a low frequency impedance of nominally
500 Ω in parallel with 0.7 pF. The maximum input with ±1 dB
log conformance error is typically 0 dBm (re: 50 Ω). The noise
spectral density referred to the input is 1.15 nV/√Hz, which is
equivalent to a voltage of 118 μV rms in a 10.5 GHz bandwidth
or a noise power of −66 dBm (re: 50 Ω). This noise spectral
density sets the lower limit of the dynamic range. However, the
low end accuracy of the AD8319 is enhanced by specially shaping
the demodulating transfer characteristic to partially compensate
for errors due to internal noise. The common pin, COMM,
provides a quality low impedance connection to the PCB
ground. The package paddle, which is internally connected
to the COMM pin, should also be grounded to the PCB to
reduce thermal impedance from the die to the PCB.
(1)
where:
ID is the internally set detector current.
VIN is the input signal voltage.
VINTERCEPT is the intercept voltage (that is, when VIN = VINTERCEPT,
the output voltage would be 0 V, if it were capable of going to 0 V).
Rev. D | Page 10 of 19
Data Sheet
AD8319
USING THE AD8319
BASIC CONNECTIONS
The AD8319 is specified for operation up to 10 GHz, as a result,
low impedance supply pins with adequate isolation between
functions are essential. A power supply voltage of between 3.0 V
and 5.5 V should be applied to VPOS. Power supply decoupling
capacitors of 100 pF and 0.1 µF should be connected close to
this power supply pin.
VS (3.0V TO 5.5V)
R2
0Ω
C4
100pF
SEE
NOTE 1
VOUT
8
INLO
7
VPOS
R1
52.3Ω
6
TADJ
5
VOUT
R4
0Ω
AD8319
C1
47nF
SIGNAL
INPUT
INHI
1
COMM
2
CLPF
3
VSET
4
SEE
NOTE 2
05705-022
NOTES
1. SEE THE TEMPERATURE COMPENSATION OF THE OUTPUT VOLTAGE
SECTION.
2. SEE THE OUTPUT FILTERING SECTION.
OUTPUT INTERFACE
The VOUT pin is driven by a PNP output stage. An internal 10 Ω
resistor is placed in series with the output and the VOUT pin.
The rise time of the output is limited mainly by the slew on
CLPF. The fall time is an RC-limited slew given by the load
capacitance and the pull-down resistance at VOUT. There is
an internal pull-down resistor of 1.6 kΩ. A resistive load at
VOUT is placed in parallel with the internal pull-down resistor
to provide additional discharge current.
Figure 22. Basic Connections
VPOS
CLPF
The paddle of the LFCSP is internally connected to COMM.
For optimum thermal and electrical performance, the paddle
should be soldered to a low impedance ground plane.
10Ω
+
0.8V
–
1200Ω
INPUT SIGNAL COUPLING
400Ω
The RF input (INHI) is single-ended and must be ac-coupled.
INLO (input common) should be ac-coupled to ground.
Suggested coupling capacitors are 47 nF ceramic 0402-style
capacitors for input frequencies of 1 MHz to 10 GHz. The
coupling capacitors should be mounted close to the INHI and
INLO pins. The coupling capacitor values can be increased to
lower the high-pass cutoff frequency of the input stage. The
high-pass corner is set by the input coupling capacitors and the
internal 10 pF high-pass capacitor. The dc voltage on INHI and
INLO is approximately one diode voltage drop below VPOS.
5pF
18.7kΩ
COMM
Figure 24. Output Interface
To reduce the fall time, VOUT should be loaded with a resistive
load of
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